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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 369:4b4223e7d720
prev367:9c52dcbad3fb
next374:8f80a795513e
author nkeynes
date Sat Sep 08 03:12:21 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Move the store queue operation to a function in sh4mem.c
file annotate diff log raw
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/**
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 * $Id: sh4core.in,v 1.3 2007-09-08 03:12:21 nkeynes Exp $
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <math.h>
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#include "dream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/intc.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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#define SH4_CALLTRACE 1
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#define MAX_INT 0x7FFFFFFF
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#define MIN_INT 0x80000000
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#define MAX_INTF 2147483647.0
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#define MIN_INTF -2147483648.0
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#define EXV_EXCEPTION    0x100  /* General exception vector */
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#define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
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#define EXV_INTERRUPT    0x600  /* External interrupt vector */
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/********************** SH4 Module Definition ****************************/
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void sh4_init( void );
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void sh4_reset( void );
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uint32_t sh4_run_slice( uint32_t );
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void sh4_start( void );
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void sh4_stop( void );
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void sh4_save_state( FILE *f );
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int sh4_load_state( FILE *f );
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void sh4_accept_interrupt( void );
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struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
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				       NULL, sh4_run_slice, sh4_stop,
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				       sh4_save_state, sh4_load_state };
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struct sh4_registers sh4r;
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void sh4_init(void)
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{
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    register_io_regions( mmio_list_sh4mmio );
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    MMU_init();
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    sh4_reset();
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}
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void sh4_reset(void)
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{
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    /* zero everything out, for the sake of having a consistent state. */
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    memset( &sh4r, 0, sizeof(sh4r) );
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    /* Resume running if we were halted */
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    sh4r.sh4_state = SH4_STATE_RUNNING;
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    sh4r.pc    = 0xA0000000;
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    sh4r.new_pc= 0xA0000002;
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    sh4r.vbr   = 0x00000000;
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    sh4r.fpscr = 0x00040001;
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    sh4r.sr    = 0x700000F0;
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    /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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    /* Peripheral modules */
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    CPG_reset();
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    INTC_reset();
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    MMU_reset();
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    TMU_reset();
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    SCIF_reset();
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}
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static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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static int sh4_breakpoint_count = 0;
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static uint16_t *sh4_icache = NULL;
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static uint32_t sh4_icache_addr = 0;
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void sh4_set_breakpoint( uint32_t pc, int type )
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{
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    sh4_breakpoints[sh4_breakpoint_count].address = pc;
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    sh4_breakpoints[sh4_breakpoint_count].type = type;
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    sh4_breakpoint_count++;
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}
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gboolean sh4_clear_breakpoint( uint32_t pc, int type )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc && 
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	    sh4_breakpoints[i].type == type ) {
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	    while( ++i < sh4_breakpoint_count ) {
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		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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	    }
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	    sh4_breakpoint_count--;
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	    return TRUE;
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	}
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    }
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    return FALSE;
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}
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int sh4_get_breakpoint( uint32_t pc )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc )
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	    return sh4_breakpoints[i].type;
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    }
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    return 0;
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}
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uint32_t sh4_run_slice( uint32_t nanosecs ) 
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{
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    int i;
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    sh4r.slice_cycle = 0;
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    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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	if( sh4r.event_pending < nanosecs ) {
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	    sh4r.sh4_state = SH4_STATE_RUNNING;
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	    sh4r.slice_cycle = sh4r.event_pending;
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	}
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    }
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    if( sh4_breakpoint_count == 0 ) {
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	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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		if( sh4r.event_types & PENDING_EVENT ) {
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		    event_execute();
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		}
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		/* Eventq execute may (quite likely) deliver an immediate IRQ */
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		if( sh4r.event_types & PENDING_IRQ ) {
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		    sh4_accept_interrupt();
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		}
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	    }
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	    if( !sh4_execute_instruction() ) {
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		break;
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	    }
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	}
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    } else {
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	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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		if( sh4r.event_types & PENDING_EVENT ) {
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		    event_execute();
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		}
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		/* Eventq execute may (quite likely) deliver an immediate IRQ */
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		if( sh4r.event_types & PENDING_IRQ ) {
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		    sh4_accept_interrupt();
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		}
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	    }
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	    if( !sh4_execute_instruction() )
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		break;
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#ifdef ENABLE_DEBUG_MODE
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	    for( i=0; i<sh4_breakpoint_count; i++ ) {
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		if( sh4_breakpoints[i].address == sh4r.pc ) {
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		    break;
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		}
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	    }
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	    if( i != sh4_breakpoint_count ) {
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		dreamcast_stop();
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		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
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		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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		break;
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	    }
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#endif	
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	}
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    return nanosecs;
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}
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void sh4_stop(void)
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{
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}
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void sh4_save_state( FILE *f )
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{
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    fwrite( &sh4r, sizeof(sh4r), 1, f );
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    MMU_save_state( f );
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    INTC_save_state( f );
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    TMU_save_state( f );
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    SCIF_save_state( f );
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}
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int sh4_load_state( FILE * f )
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{
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    fread( &sh4r, sizeof(sh4r), 1, f );
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    MMU_load_state( f );
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    INTC_load_state( f );
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    TMU_load_state( f );
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    return SCIF_load_state( f );
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}
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/********************** SH4 emulation core  ****************************/
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void sh4_set_pc( int pc )
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{
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    sh4r.pc = pc;
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    sh4r.new_pc = pc+2;
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}
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#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
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#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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#if(SH4_CALLTRACE == 1)
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#define MAX_CALLSTACK 32
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static struct call_stack {
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    sh4addr_t call_addr;
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    sh4addr_t target_addr;
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    sh4addr_t stack_pointer;
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} call_stack[MAX_CALLSTACK];
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static int call_stack_depth = 0;
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int sh4_call_trace_on = 0;
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static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
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{
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    if( call_stack_depth < MAX_CALLSTACK ) {
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	call_stack[call_stack_depth].call_addr = source;
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	call_stack[call_stack_depth].target_addr = dest;
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	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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    }
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    call_stack_depth++;
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}
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static inline trace_return( sh4addr_t source, sh4addr_t dest )
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{
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    if( call_stack_depth > 0 ) {
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	call_stack_depth--;
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    }
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}
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void fprint_stack_trace( FILE *f )
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{
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    int i = call_stack_depth -1;
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    if( i >= MAX_CALLSTACK )
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	i = MAX_CALLSTACK - 1;
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    for( ; i >= 0; i-- ) {
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	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
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		 (call_stack_depth - i), call_stack[i].call_addr,
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		 call_stack[i].target_addr, call_stack[i].stack_pointer );
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    }
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}
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#define TRACE_CALL( source, dest ) trace_call(source, dest)
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#define TRACE_RETURN( source, dest ) trace_return(source, dest)
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#else
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#define TRACE_CALL( dest, rts ) 
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#define TRACE_RETURN( source, dest )
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#endif
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#define RAISE( x, v ) do{			\
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    if( sh4r.vbr == 0 ) { \
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        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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        dreamcast_stop(); return FALSE;	\
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    } else { \
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        sh4r.spc = sh4r.pc;	\
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        sh4r.ssr = sh4_read_sr(); \
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        sh4r.sgr = sh4r.r[15]; \
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        MMIO_WRITE(MMU,EXPEVT,x); \
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        sh4r.pc = sh4r.vbr + v; \
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        sh4r.new_pc = sh4r.pc + 2; \
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        sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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	if( sh4r.in_delay_slot ) { \
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	    sh4r.in_delay_slot = 0; \
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	    sh4r.spc -= 2; \
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	} \
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    } \
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    return TRUE; } while(0)
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#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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#define MEM_READ_WORD( addr ) sh4_read_word(addr)
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#define MEM_READ_LONG( addr ) sh4_read_long(addr)
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#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
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#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
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#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
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#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
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#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
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#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
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#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
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#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
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static void sh4_switch_banks( )
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{
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    uint32_t tmp[8];
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    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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}
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static void sh4_load_sr( uint32_t newval )
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{
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    if( (newval ^ sh4r.sr) & SR_RB )
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        sh4_switch_banks();
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    sh4r.sr = newval;
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    sh4r.t = (newval&SR_T) ? 1 : 0;
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    sh4r.s = (newval&SR_S) ? 1 : 0;
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    sh4r.m = (newval&SR_M) ? 1 : 0;
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    sh4r.q = (newval&SR_Q) ? 1 : 0;
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    intc_mask_changed();
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}
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static void sh4_write_float( uint32_t addr, int reg )
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{
nkeynes@359
   346
    if( IS_FPU_DOUBLESIZE() ) {
nkeynes@359
   347
	if( reg & 1 ) {
nkeynes@359
   348
	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
nkeynes@359
   349
	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
nkeynes@359
   350
	} else {
nkeynes@359
   351
	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
nkeynes@359
   352
	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
nkeynes@359
   353
	}
nkeynes@359
   354
    } else {
nkeynes@359
   355
	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
nkeynes@359
   356
    }
nkeynes@359
   357
}
nkeynes@359
   358
nkeynes@359
   359
static void sh4_read_float( uint32_t addr, int reg )
nkeynes@359
   360
{
nkeynes@359
   361
    if( IS_FPU_DOUBLESIZE() ) {
nkeynes@359
   362
	if( reg & 1 ) {
nkeynes@359
   363
	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
nkeynes@359
   364
	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
nkeynes@359
   365
	} else {
nkeynes@359
   366
	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@359
   367
	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
nkeynes@359
   368
	}
nkeynes@359
   369
    } else {
nkeynes@359
   370
	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@359
   371
    }
nkeynes@359
   372
}
nkeynes@359
   373
nkeynes@359
   374
static uint32_t sh4_read_sr( void )
nkeynes@359
   375
{
nkeynes@359
   376
    /* synchronize sh4r.sr with the various bitflags */
nkeynes@359
   377
    sh4r.sr &= SR_MQSTMASK;
nkeynes@359
   378
    if( sh4r.t ) sh4r.sr |= SR_T;
nkeynes@359
   379
    if( sh4r.s ) sh4r.sr |= SR_S;
nkeynes@359
   380
    if( sh4r.m ) sh4r.sr |= SR_M;
nkeynes@359
   381
    if( sh4r.q ) sh4r.sr |= SR_Q;
nkeynes@359
   382
    return sh4r.sr;
nkeynes@359
   383
}
nkeynes@359
   384
nkeynes@359
   385
/**
nkeynes@359
   386
 * Raise a general CPU exception for the specified exception code.
nkeynes@359
   387
 * (NOT for TRAPA or TLB exceptions)
nkeynes@359
   388
 */
nkeynes@359
   389
gboolean sh4_raise_exception( int code )
nkeynes@359
   390
{
nkeynes@359
   391
    RAISE( code, EXV_EXCEPTION );
nkeynes@359
   392
}
nkeynes@359
   393
nkeynes@359
   394
gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
nkeynes@359
   395
    if( sh4r.in_delay_slot ) {
nkeynes@359
   396
	return sh4_raise_exception(slot_code);
nkeynes@359
   397
    } else {
nkeynes@359
   398
	return sh4_raise_exception(normal_code);
nkeynes@359
   399
    }
nkeynes@359
   400
}
nkeynes@359
   401
nkeynes@359
   402
gboolean sh4_raise_tlb_exception( int code )
nkeynes@359
   403
{
nkeynes@359
   404
    RAISE( code, EXV_TLBMISS );
nkeynes@359
   405
}
nkeynes@359
   406
nkeynes@359
   407
void sh4_accept_interrupt( void )
nkeynes@359
   408
{
nkeynes@359
   409
    uint32_t code = intc_accept_interrupt();
nkeynes@359
   410
    sh4r.ssr = sh4_read_sr();
nkeynes@359
   411
    sh4r.spc = sh4r.pc;
nkeynes@359
   412
    sh4r.sgr = sh4r.r[15];
nkeynes@359
   413
    sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
nkeynes@359
   414
    MMIO_WRITE( MMU, INTEVT, code );
nkeynes@359
   415
    sh4r.pc = sh4r.vbr + 0x600;
nkeynes@359
   416
    sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   417
    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
nkeynes@359
   418
}
nkeynes@359
   419
nkeynes@359
   420
gboolean sh4_execute_instruction( void )
nkeynes@359
   421
{
nkeynes@359
   422
    uint32_t pc;
nkeynes@359
   423
    unsigned short ir;
nkeynes@359
   424
    uint32_t tmp;
nkeynes@359
   425
    float ftmp;
nkeynes@359
   426
    double dtmp;
nkeynes@359
   427
    
nkeynes@359
   428
#define R0 sh4r.r[0]
nkeynes@359
   429
    pc = sh4r.pc;
nkeynes@359
   430
    if( pc > 0xFFFFFF00 ) {
nkeynes@359
   431
	/* SYSCALL Magic */
nkeynes@359
   432
	syscall_invoke( pc );
nkeynes@359
   433
	sh4r.in_delay_slot = 0;
nkeynes@359
   434
	pc = sh4r.pc = sh4r.pr;
nkeynes@359
   435
	sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   436
    }
nkeynes@359
   437
    CHECKRALIGN16(pc);
nkeynes@359
   438
nkeynes@359
   439
    /* Read instruction */
nkeynes@359
   440
    uint32_t pageaddr = pc >> 12;
nkeynes@359
   441
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@359
   442
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@359
   443
    } else {
nkeynes@359
   444
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@359
   445
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@359
   446
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@359
   447
	     * region, fallback on the full-blown memory read
nkeynes@359
   448
	     */
nkeynes@359
   449
	    sh4_icache = NULL;
nkeynes@359
   450
	    ir = MEM_READ_WORD(pc);
nkeynes@359
   451
	} else {
nkeynes@359
   452
	    sh4_icache_addr = pageaddr;
nkeynes@359
   453
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@359
   454
	}
nkeynes@359
   455
    }
nkeynes@359
   456
%%
nkeynes@359
   457
AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
nkeynes@359
   458
AND #imm, R0 {: R0 &= imm; :}
nkeynes@359
   459
AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
nkeynes@359
   460
NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
nkeynes@359
   461
OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
nkeynes@359
   462
OR #imm, R0  {: R0 |= imm; :}
nkeynes@359
   463
OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
nkeynes@359
   464
TAS.B @Rn {:
nkeynes@359
   465
    tmp = MEM_READ_BYTE( sh4r.r[Rn] );
nkeynes@359
   466
    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@359
   467
    MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
nkeynes@359
   468
:}
nkeynes@359
   469
TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
nkeynes@359
   470
TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
nkeynes@359
   471
TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
nkeynes@359
   472
XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
nkeynes@359
   473
XOR #imm, R0 {: R0 ^= imm; :}
nkeynes@359
   474
XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
nkeynes@359
   475
XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   476
nkeynes@359
   477
ROTL Rn {:
nkeynes@359
   478
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   479
    sh4r.r[Rn] <<= 1;
nkeynes@359
   480
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   481
:}
nkeynes@359
   482
ROTR Rn {:
nkeynes@359
   483
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   484
    sh4r.r[Rn] >>= 1;
nkeynes@359
   485
    sh4r.r[Rn] |= (sh4r.t << 31);
nkeynes@359
   486
:}
nkeynes@359
   487
ROTCL Rn {:
nkeynes@359
   488
    tmp = sh4r.r[Rn] >> 31;
nkeynes@359
   489
    sh4r.r[Rn] <<= 1;
nkeynes@359
   490
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   491
    sh4r.t = tmp;
nkeynes@359
   492
:}
nkeynes@359
   493
ROTCR Rn {:
nkeynes@359
   494
    tmp = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   495
    sh4r.r[Rn] >>= 1;
nkeynes@359
   496
    sh4r.r[Rn] |= (sh4r.t << 31 );
nkeynes@359
   497
    sh4r.t = tmp;
nkeynes@359
   498
:}
nkeynes@359
   499
SHAD Rm, Rn {:
nkeynes@359
   500
    tmp = sh4r.r[Rm];
nkeynes@359
   501
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   502
    else if( (tmp & 0x1F) == 0 )  
nkeynes@359
   503
        sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
nkeynes@359
   504
    else 
nkeynes@359
   505
	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
nkeynes@359
   506
:}
nkeynes@359
   507
SHLD Rm, Rn {:
nkeynes@359
   508
    tmp = sh4r.r[Rm];
nkeynes@359
   509
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   510
    else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
nkeynes@359
   511
    else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
nkeynes@359
   512
:}
nkeynes@359
   513
SHAL Rn {:
nkeynes@359
   514
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   515
    sh4r.r[Rn] <<= 1;
nkeynes@359
   516
:}
nkeynes@359
   517
SHAR Rn {:
nkeynes@359
   518
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   519
    sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
nkeynes@359
   520
:}
nkeynes@359
   521
SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
nkeynes@359
   522
SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
nkeynes@359
   523
SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
nkeynes@359
   524
SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
nkeynes@359
   525
SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
nkeynes@359
   526
SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
nkeynes@359
   527
SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
nkeynes@359
   528
SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
nkeynes@359
   529
nkeynes@359
   530
EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
nkeynes@359
   531
EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
nkeynes@359
   532
EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
nkeynes@359
   533
EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
nkeynes@359
   534
SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
nkeynes@359
   535
SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   536
nkeynes@359
   537
CLRT {: sh4r.t = 0; :}
nkeynes@359
   538
SETT {: sh4r.t = 1; :}
nkeynes@359
   539
CLRMAC {: sh4r.mac = 0; :}
nkeynes@359
   540
LDTLB {: /* TODO */ :}
nkeynes@359
   541
CLRS {: sh4r.s = 0; :}
nkeynes@359
   542
SETS {: sh4r.s = 1; :}
nkeynes@359
   543
MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
nkeynes@359
   544
NOP {: /* NOP */ :}
nkeynes@359
   545
nkeynes@359
   546
PREF @Rn {:
nkeynes@359
   547
     tmp = sh4r.r[Rn];
nkeynes@359
   548
     if( (tmp & 0xFC000000) == 0xE0000000 ) {
nkeynes@369
   549
	 sh4_flush_store_queue(tmp);
nkeynes@359
   550
     }
nkeynes@359
   551
:}
nkeynes@359
   552
OCBI @Rn {: :}
nkeynes@359
   553
OCBP @Rn {: :}
nkeynes@359
   554
OCBWB @Rn {: :}
nkeynes@359
   555
MOVCA.L R0, @Rn {:
nkeynes@359
   556
    tmp = sh4r.r[Rn];
nkeynes@359
   557
    CHECKWALIGN32(tmp);
nkeynes@359
   558
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   559
:}
nkeynes@359
   560
MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   561
MOV.W Rm, @(R0, Rn) {: 
nkeynes@359
   562
    CHECKWALIGN16( R0 + sh4r.r[Rn] );
nkeynes@359
   563
    MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   564
:}
nkeynes@359
   565
MOV.L Rm, @(R0, Rn) {:
nkeynes@359
   566
    CHECKWALIGN32( R0 + sh4r.r[Rn] );
nkeynes@359
   567
    MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   568
:}
nkeynes@359
   569
MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
nkeynes@359
   570
MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
nkeynes@359
   571
                    sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
nkeynes@359
   572
:}
nkeynes@359
   573
MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
nkeynes@359
   574
                    sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
nkeynes@359
   575
:}
nkeynes@359
   576
MOV.L Rm, @(disp, Rn) {:
nkeynes@359
   577
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   578
    CHECKWALIGN32( tmp );
nkeynes@359
   579
    MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
nkeynes@359
   580
:}
nkeynes@359
   581
MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   582
MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   583
MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   584
MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   585
MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   586
MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   587
MOV.L @(disp, Rm), Rn {:
nkeynes@359
   588
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   589
    CHECKRALIGN32( tmp );
nkeynes@359
   590
    sh4r.r[Rn] = MEM_READ_LONG( tmp );
nkeynes@359
   591
:}
nkeynes@359
   592
MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
nkeynes@359
   593
MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
nkeynes@359
   594
MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
nkeynes@359
   595
MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
nkeynes@359
   596
MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
nkeynes@359
   597
MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
nkeynes@359
   598
MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
nkeynes@359
   599
MOV.L @(disp, PC), Rn {:
nkeynes@359
   600
    CHECKSLOTILLEGAL();
nkeynes@359
   601
    tmp = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@359
   602
    sh4r.r[Rn] = MEM_READ_LONG( tmp );
nkeynes@359
   603
:}
nkeynes@359
   604
MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   605
MOV.W R0, @(disp, GBR) {:
nkeynes@359
   606
    tmp = sh4r.gbr + disp;
nkeynes@359
   607
    CHECKWALIGN16( tmp );
nkeynes@359
   608
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   609
:}
nkeynes@359
   610
MOV.L R0, @(disp, GBR) {:
nkeynes@359
   611
    tmp = sh4r.gbr + disp;
nkeynes@359
   612
    CHECKWALIGN32( tmp );
nkeynes@359
   613
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   614
:}
nkeynes@359
   615
MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
nkeynes@359
   616
MOV.W @(disp, GBR), R0 {: 
nkeynes@359
   617
    tmp = sh4r.gbr + disp;
nkeynes@359
   618
    CHECKRALIGN16( tmp );
nkeynes@359
   619
    R0 = MEM_READ_WORD( tmp );
nkeynes@359
   620
:}
nkeynes@359
   621
MOV.L @(disp, GBR), R0 {:
nkeynes@359
   622
    tmp = sh4r.gbr + disp;
nkeynes@359
   623
    CHECKRALIGN32( tmp );
nkeynes@359
   624
    R0 = MEM_READ_LONG( tmp );
nkeynes@359
   625
:}
nkeynes@359
   626
MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
nkeynes@359
   627
MOV.W R0, @(disp, Rn) {: 
nkeynes@359
   628
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   629
    CHECKWALIGN16( tmp );
nkeynes@359
   630
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   631
:}
nkeynes@359
   632
MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
nkeynes@359
   633
MOV.W @(disp, Rm), R0 {: 
nkeynes@359
   634
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   635
    CHECKRALIGN16( tmp );
nkeynes@359
   636
    R0 = MEM_READ_WORD( tmp );
nkeynes@359
   637
:}
nkeynes@359
   638
MOV.W @(disp, PC), Rn {:
nkeynes@359
   639
    CHECKSLOTILLEGAL();
nkeynes@359
   640
    tmp = pc + 4 + disp;
nkeynes@359
   641
    sh4r.r[Rn] = MEM_READ_WORD( tmp );
nkeynes@359
   642
:}
nkeynes@359
   643
MOVA @(disp, PC), R0 {:
nkeynes@359
   644
    CHECKSLOTILLEGAL();
nkeynes@359
   645
    R0 = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@359
   646
:}
nkeynes@359
   647
MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
nkeynes@359
   648
nkeynes@359
   649
CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
nkeynes@359
   650
CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
nkeynes@359
   651
CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   652
CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   653
CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   654
CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   655
CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
nkeynes@359
   656
CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
nkeynes@359
   657
CMP/STR Rm, Rn {: 
nkeynes@359
   658
    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@359
   659
    tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
nkeynes@359
   660
    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@359
   661
             (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@359
   662
:}
nkeynes@359
   663
nkeynes@359
   664
ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
nkeynes@359
   665
ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
nkeynes@359
   666
ADDC Rm, Rn {:
nkeynes@359
   667
    tmp = sh4r.r[Rn];
nkeynes@359
   668
    sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
nkeynes@359
   669
    sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@359
   670
:}
nkeynes@359
   671
ADDV Rm, Rn {:
nkeynes@359
   672
    tmp = sh4r.r[Rn] + sh4r.r[Rm];
nkeynes@359
   673
    sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@359
   674
    sh4r.r[Rn] = tmp;
nkeynes@359
   675
:}
nkeynes@359
   676
DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
nkeynes@359
   677
DIV0S Rm, Rn {: 
nkeynes@359
   678
    sh4r.q = sh4r.r[Rn]>>31;
nkeynes@359
   679
    sh4r.m = sh4r.r[Rm]>>31;
nkeynes@359
   680
    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@359
   681
:}
nkeynes@359
   682
DIV1 Rm, Rn {:
nkeynes@359
   683
    /* This is just from the sh4p manual with some
nkeynes@359
   684
     * simplifications (someone want to check it's correct? :)
nkeynes@359
   685
     * Why they couldn't just provide a real DIV instruction...
nkeynes@359
   686
     */
nkeynes@359
   687
    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@359
   688
nkeynes@359
   689
    dir = sh4r.q ^ sh4r.m;
nkeynes@359
   690
    sh4r.q = (sh4r.r[Rn] >> 31);
nkeynes@359
   691
    tmp2 = sh4r.r[Rm];
nkeynes@359
   692
    sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
nkeynes@359
   693
    tmp0 = sh4r.r[Rn];
nkeynes@359
   694
    if( dir ) {
nkeynes@359
   695
         sh4r.r[Rn] += tmp2;
nkeynes@359
   696
         tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
nkeynes@359
   697
    } else {
nkeynes@359
   698
         sh4r.r[Rn] -= tmp2;
nkeynes@359
   699
         tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
nkeynes@359
   700
    }
nkeynes@359
   701
    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@359
   702
    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@359
   703
:}
nkeynes@359
   704
DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
nkeynes@359
   705
DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
nkeynes@359
   706
DT Rn {:
nkeynes@359
   707
    sh4r.r[Rn] --;
nkeynes@359
   708
    sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
nkeynes@359
   709
:}
nkeynes@359
   710
MAC.W @Rm+, @Rn+ {:
nkeynes@359
   711
    CHECKRALIGN16( sh4r.r[Rn] );
nkeynes@359
   712
    CHECKRALIGN16( sh4r.r[Rm] );
nkeynes@359
   713
    int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
nkeynes@359
   714
    sh4r.r[Rn] += 2;
nkeynes@359
   715
    stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
nkeynes@359
   716
    sh4r.r[Rm] += 2;
nkeynes@359
   717
    if( sh4r.s ) {
nkeynes@359
   718
	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
nkeynes@359
   719
	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
nkeynes@359
   720
	    sh4r.mac = 0x000000017FFFFFFFLL;
nkeynes@359
   721
	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
nkeynes@359
   722
	    sh4r.mac = 0x0000000180000000LL;
nkeynes@359
   723
	} else {
nkeynes@359
   724
	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   725
		((uint32_t)(sh4r.mac + stmp));
nkeynes@359
   726
	}
nkeynes@359
   727
    } else {
nkeynes@359
   728
	sh4r.mac += SIGNEXT32(stmp);
nkeynes@359
   729
    }
nkeynes@359
   730
:}
nkeynes@359
   731
MAC.L @Rm+, @Rn+ {:
nkeynes@359
   732
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   733
    CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@359
   734
    int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
nkeynes@359
   735
    sh4r.r[Rn] += 4;
nkeynes@359
   736
    tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
nkeynes@359
   737
    sh4r.r[Rm] += 4;
nkeynes@359
   738
    if( sh4r.s ) {
nkeynes@359
   739
        /* 48-bit Saturation. Yuch */
nkeynes@359
   740
        if( tmpl < (int64_t)0xFFFF800000000000LL )
nkeynes@359
   741
            tmpl = 0xFFFF800000000000LL;
nkeynes@359
   742
        else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@359
   743
            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@359
   744
    }
nkeynes@359
   745
    sh4r.mac = tmpl;
nkeynes@359
   746
:}
nkeynes@359
   747
MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   748
                        (sh4r.r[Rm] * sh4r.r[Rn]); :}
nkeynes@359
   749
MULU.W Rm, Rn {:
nkeynes@359
   750
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   751
               (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
nkeynes@359
   752
:}
nkeynes@359
   753
MULS.W Rm, Rn {:
nkeynes@359
   754
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   755
               (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
nkeynes@359
   756
:}
nkeynes@359
   757
NEGC Rm, Rn {:
nkeynes@359
   758
    tmp = 0 - sh4r.r[Rm];
nkeynes@359
   759
    sh4r.r[Rn] = tmp - sh4r.t;
nkeynes@359
   760
    sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
nkeynes@359
   761
:}
nkeynes@359
   762
NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
nkeynes@359
   763
SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
nkeynes@359
   764
SUBC Rm, Rn {: 
nkeynes@359
   765
    tmp = sh4r.r[Rn];
nkeynes@359
   766
    sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
nkeynes@359
   767
    sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
nkeynes@359
   768
:}
nkeynes@359
   769
nkeynes@359
   770
BRAF Rn {:
nkeynes@359
   771
     CHECKSLOTILLEGAL();
nkeynes@359
   772
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   773
     sh4r.in_delay_slot = 1;
nkeynes@359
   774
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   775
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   776
     return TRUE;
nkeynes@359
   777
:}
nkeynes@359
   778
BSRF Rn {:
nkeynes@359
   779
     CHECKSLOTILLEGAL();
nkeynes@359
   780
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   781
     sh4r.in_delay_slot = 1;
nkeynes@359
   782
     sh4r.pr = sh4r.pc + 4;
nkeynes@359
   783
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   784
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   785
     TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   786
     return TRUE;
nkeynes@359
   787
:}
nkeynes@359
   788
BT disp {:
nkeynes@359
   789
    CHECKSLOTILLEGAL();
nkeynes@359
   790
    if( sh4r.t ) {
nkeynes@359
   791
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   792
        sh4r.pc += disp + 4;
nkeynes@359
   793
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   794
        return TRUE;
nkeynes@359
   795
    }
nkeynes@359
   796
:}
nkeynes@359
   797
BF disp {:
nkeynes@359
   798
    CHECKSLOTILLEGAL();
nkeynes@359
   799
    if( !sh4r.t ) {
nkeynes@359
   800
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   801
        sh4r.pc += disp + 4;
nkeynes@359
   802
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   803
        return TRUE;
nkeynes@359
   804
    }
nkeynes@359
   805
:}
nkeynes@359
   806
BT/S disp {:
nkeynes@359
   807
    CHECKSLOTILLEGAL();
nkeynes@359
   808
    if( sh4r.t ) {
nkeynes@359
   809
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   810
        sh4r.in_delay_slot = 1;
nkeynes@359
   811
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   812
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   813
        sh4r.in_delay_slot = 1;
nkeynes@359
   814
        return TRUE;
nkeynes@359
   815
    }
nkeynes@359
   816
:}
nkeynes@359
   817
BF/S disp {:
nkeynes@359
   818
    CHECKSLOTILLEGAL();
nkeynes@359
   819
    if( !sh4r.t ) {
nkeynes@359
   820
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   821
        sh4r.in_delay_slot = 1;
nkeynes@359
   822
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   823
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   824
        return TRUE;
nkeynes@359
   825
    }
nkeynes@359
   826
:}
nkeynes@359
   827
BRA disp {:
nkeynes@359
   828
    CHECKSLOTILLEGAL();
nkeynes@359
   829
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   830
    sh4r.in_delay_slot = 1;
nkeynes@359
   831
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   832
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   833
    return TRUE;
nkeynes@359
   834
:}
nkeynes@359
   835
BSR disp {:
nkeynes@359
   836
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   837
    CHECKSLOTILLEGAL();
nkeynes@359
   838
    sh4r.in_delay_slot = 1;
nkeynes@359
   839
    sh4r.pr = pc + 4;
nkeynes@359
   840
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   841
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   842
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   843
    return TRUE;
nkeynes@359
   844
:}
nkeynes@359
   845
TRAPA #imm {:
nkeynes@359
   846
    CHECKSLOTILLEGAL();
nkeynes@359
   847
    MMIO_WRITE( MMU, TRA, imm<<2 );
nkeynes@359
   848
    sh4r.pc += 2;
nkeynes@359
   849
    sh4_raise_exception( EXC_TRAP );
nkeynes@359
   850
:}
nkeynes@359
   851
RTS {: 
nkeynes@359
   852
    CHECKSLOTILLEGAL();
nkeynes@359
   853
    CHECKDEST( sh4r.pr );
nkeynes@359
   854
    sh4r.in_delay_slot = 1;
nkeynes@359
   855
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   856
    sh4r.new_pc = sh4r.pr;
nkeynes@359
   857
    TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@359
   858
    return TRUE;
nkeynes@359
   859
:}
nkeynes@359
   860
SLEEP {:
nkeynes@359
   861
    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@359
   862
	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@359
   863
    } else {
nkeynes@359
   864
	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@359
   865
    }
nkeynes@359
   866
    return FALSE; /* Halt CPU */
nkeynes@359
   867
:}
nkeynes@359
   868
RTE {:
nkeynes@359
   869
    CHECKPRIV();
nkeynes@359
   870
    CHECKDEST( sh4r.spc );
nkeynes@359
   871
    CHECKSLOTILLEGAL();
nkeynes@359
   872
    sh4r.in_delay_slot = 1;
nkeynes@359
   873
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   874
    sh4r.new_pc = sh4r.spc;
nkeynes@359
   875
    sh4_load_sr( sh4r.ssr );
nkeynes@359
   876
    return TRUE;
nkeynes@359
   877
:}
nkeynes@359
   878
JMP @Rn {:
nkeynes@359
   879
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   880
    CHECKSLOTILLEGAL();
nkeynes@359
   881
    sh4r.in_delay_slot = 1;
nkeynes@359
   882
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   883
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   884
    return TRUE;
nkeynes@359
   885
:}
nkeynes@359
   886
JSR @Rn {:
nkeynes@359
   887
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   888
    CHECKSLOTILLEGAL();
nkeynes@359
   889
    sh4r.in_delay_slot = 1;
nkeynes@359
   890
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   891
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   892
    sh4r.pr = pc + 4;
nkeynes@359
   893
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   894
    return TRUE;
nkeynes@359
   895
:}
nkeynes@359
   896
STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
nkeynes@359
   897
STS.L MACH, @-Rn {:
nkeynes@359
   898
    sh4r.r[Rn] -= 4;
nkeynes@359
   899
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   900
    MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
nkeynes@359
   901
:}
nkeynes@359
   902
STC.L SR, @-Rn {:
nkeynes@359
   903
    CHECKPRIV();
nkeynes@359
   904
    sh4r.r[Rn] -= 4;
nkeynes@359
   905
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   906
    MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
nkeynes@359
   907
:}
nkeynes@359
   908
LDS.L @Rm+, MACH {:
nkeynes@359
   909
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   910
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@359
   911
               (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
nkeynes@359
   912
    sh4r.r[Rm] += 4;
nkeynes@359
   913
:}
nkeynes@359
   914
LDC.L @Rm+, SR {:
nkeynes@359
   915
    CHECKSLOTILLEGAL();
nkeynes@359
   916
    CHECKPRIV();
nkeynes@359
   917
    CHECKWALIGN32( sh4r.r[Rm] );
nkeynes@359
   918
    sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
nkeynes@359
   919
    sh4r.r[Rm] +=4;
nkeynes@359
   920
:}
nkeynes@359
   921
LDS Rm, MACH {:
nkeynes@359
   922
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@359
   923
               (((uint64_t)sh4r.r[Rm])<<32);
nkeynes@359
   924
:}
nkeynes@359
   925
LDC Rm, SR {:
nkeynes@359
   926
    CHECKSLOTILLEGAL();
nkeynes@359
   927
    CHECKPRIV();
nkeynes@359
   928
    sh4_load_sr( sh4r.r[Rm] );
nkeynes@359
   929
:}
nkeynes@359
   930
LDC Rm, SGR {:
nkeynes@359
   931
    CHECKPRIV();
nkeynes@359
   932
    sh4r.sgr = sh4r.r[Rm];
nkeynes@359
   933
:}
nkeynes@359
   934
LDC.L @Rm+, SGR {:
nkeynes@359
   935
    CHECKPRIV();
nkeynes@359
   936
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   937
    sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
   938
    sh4r.r[Rm] +=4;
nkeynes@359
   939
:}
nkeynes@359
   940
STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
nkeynes@359
   941
STS.L MACL, @-Rn {:
nkeynes@359
   942
    sh4r.r[Rn] -= 4;
nkeynes@359
   943
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   944
    MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
nkeynes@359
   945
:}
nkeynes@359
   946
STC.L GBR, @-Rn {:
nkeynes@359
   947
    sh4r.r[Rn] -= 4;
nkeynes@359
   948
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   949
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
nkeynes@359
   950
:}
nkeynes@359
   951
LDS.L @Rm+, MACL {:
nkeynes@359
   952
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   953
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   954
               (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
nkeynes@359
   955
    sh4r.r[Rm] += 4;
nkeynes@359
   956
:}
nkeynes@359
   957
LDC.L @Rm+, GBR {:
nkeynes@359
   958
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   959
    sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
   960
    sh4r.r[Rm] +=4;
nkeynes@359
   961
:}
nkeynes@359
   962
LDS Rm, MACL {:
nkeynes@359
   963
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   964
               (uint64_t)((uint32_t)(sh4r.r[Rm]));
nkeynes@359
   965
:}
nkeynes@359
   966
LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
nkeynes@359
   967
STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
nkeynes@359
   968
STS.L PR, @-Rn {:
nkeynes@359
   969
    sh4r.r[Rn] -= 4;
nkeynes@359
   970
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   971
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
nkeynes@359
   972
:}
nkeynes@359
   973
STC.L VBR, @-Rn {:
nkeynes@359
   974
    CHECKPRIV();
nkeynes@359
   975
    sh4r.r[Rn] -= 4;
nkeynes@359
   976
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
   977
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
nkeynes@359
   978
:}
nkeynes@359
   979
LDS.L @Rm+, PR {:
nkeynes@359
   980
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   981
    sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
nkeynes@359
   982
    sh4r.r[Rm] += 4;
nkeynes@359
   983
:}
nkeynes@359
   984
LDC.L @Rm+, VBR {:
nkeynes@359
   985
    CHECKPRIV();
nkeynes@359
   986
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
   987
    sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
   988
    sh4r.r[Rm] +=4;
nkeynes@359
   989
:}
nkeynes@359
   990
LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
nkeynes@359
   991
LDC Rm, VBR {:
nkeynes@359
   992
    CHECKPRIV();
nkeynes@359
   993
    sh4r.vbr = sh4r.r[Rm];
nkeynes@359
   994
:}
nkeynes@359
   995
STC SGR, Rn {:
nkeynes@359
   996
    CHECKPRIV();
nkeynes@359
   997
    sh4r.r[Rn] = sh4r.sgr;
nkeynes@359
   998
:}
nkeynes@359
   999
STC.L SGR, @-Rn {:
nkeynes@359
  1000
    CHECKPRIV();
nkeynes@359
  1001
    sh4r.r[Rn] -= 4;
nkeynes@359
  1002
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1003
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
nkeynes@359
  1004
:}
nkeynes@359
  1005
STC.L SSR, @-Rn {:
nkeynes@359
  1006
    CHECKPRIV();
nkeynes@359
  1007
    sh4r.r[Rn] -= 4;
nkeynes@359
  1008
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1009
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
nkeynes@359
  1010
:}
nkeynes@359
  1011
LDC.L @Rm+, SSR {:
nkeynes@359
  1012
    CHECKPRIV();
nkeynes@359
  1013
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1014
    sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
  1015
    sh4r.r[Rm] +=4;
nkeynes@359
  1016
:}
nkeynes@359
  1017
LDC Rm, SSR {:
nkeynes@359
  1018
    CHECKPRIV();
nkeynes@359
  1019
    sh4r.ssr = sh4r.r[Rm];
nkeynes@359
  1020
:}
nkeynes@359
  1021
STC.L SPC, @-Rn {:
nkeynes@359
  1022
    CHECKPRIV();
nkeynes@359
  1023
    sh4r.r[Rn] -= 4;
nkeynes@359
  1024
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1025
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
nkeynes@359
  1026
:}
nkeynes@359
  1027
LDC.L @Rm+, SPC {:
nkeynes@359
  1028
    CHECKPRIV();
nkeynes@359
  1029
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1030
    sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
  1031
    sh4r.r[Rm] +=4;
nkeynes@359
  1032
:}
nkeynes@359
  1033
LDC Rm, SPC {:
nkeynes@359
  1034
    CHECKPRIV();
nkeynes@359
  1035
    sh4r.spc = sh4r.r[Rm];
nkeynes@359
  1036
:}
nkeynes@359
  1037
STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
nkeynes@359
  1038
STS.L FPUL, @-Rn {:
nkeynes@359
  1039
    sh4r.r[Rn] -= 4;
nkeynes@359
  1040
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1041
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
nkeynes@359
  1042
:}
nkeynes@359
  1043
LDS.L @Rm+, FPUL {:
nkeynes@359
  1044
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1045
    sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
  1046
    sh4r.r[Rm] +=4;
nkeynes@359
  1047
:}
nkeynes@359
  1048
LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
nkeynes@359
  1049
STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
nkeynes@359
  1050
STS.L FPSCR, @-Rn {:
nkeynes@359
  1051
    sh4r.r[Rn] -= 4;
nkeynes@359
  1052
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1053
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
nkeynes@359
  1054
:}
nkeynes@359
  1055
LDS.L @Rm+, FPSCR {:
nkeynes@359
  1056
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1057
    sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
  1058
    sh4r.r[Rm] +=4;
nkeynes@359
  1059
:}
nkeynes@359
  1060
LDS Rm, FPSCR {: sh4r.fpscr = sh4r.r[Rm]; :}
nkeynes@359
  1061
STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
nkeynes@359
  1062
STC.L DBR, @-Rn {:
nkeynes@359
  1063
    CHECKPRIV();
nkeynes@359
  1064
    sh4r.r[Rn] -= 4;
nkeynes@359
  1065
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1066
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
nkeynes@359
  1067
:}
nkeynes@359
  1068
LDC.L @Rm+, DBR {:
nkeynes@359
  1069
    CHECKPRIV();
nkeynes@359
  1070
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1071
    sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
nkeynes@359
  1072
    sh4r.r[Rm] +=4;
nkeynes@359
  1073
:}
nkeynes@359
  1074
LDC Rm, DBR {:
nkeynes@359
  1075
    CHECKPRIV();
nkeynes@359
  1076
    sh4r.dbr = sh4r.r[Rm];
nkeynes@359
  1077
:}
nkeynes@359
  1078
STC.L Rm_BANK, @-Rn {:
nkeynes@359
  1079
    CHECKPRIV();
nkeynes@359
  1080
    sh4r.r[Rn] -= 4;
nkeynes@359
  1081
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@359
  1082
    MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
nkeynes@359
  1083
:}
nkeynes@359
  1084
LDC.L @Rm+, Rn_BANK {:
nkeynes@359
  1085
    CHECKPRIV();
nkeynes@359
  1086
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@359
  1087
    sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
nkeynes@359
  1088
    sh4r.r[Rm] += 4;
nkeynes@359
  1089
:}
nkeynes@359
  1090
LDC Rm, Rn_BANK {:
nkeynes@359
  1091
    CHECKPRIV();
nkeynes@359
  1092
    sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
nkeynes@359
  1093
:}
nkeynes@359
  1094
STC SR, Rn {: 
nkeynes@359
  1095
    CHECKPRIV();
nkeynes@359
  1096
    sh4r.r[Rn] = sh4_read_sr();
nkeynes@359
  1097
:}
nkeynes@359
  1098
STC GBR, Rn {:
nkeynes@359
  1099
    CHECKPRIV();
nkeynes@359
  1100
    sh4r.r[Rn] = sh4r.gbr;
nkeynes@359
  1101
:}
nkeynes@359
  1102
STC VBR, Rn {:
nkeynes@359
  1103
    CHECKPRIV();
nkeynes@359
  1104
    sh4r.r[Rn] = sh4r.vbr;
nkeynes@359
  1105
:}
nkeynes@359
  1106
STC SSR, Rn {:
nkeynes@359
  1107
    CHECKPRIV();
nkeynes@359
  1108
    sh4r.r[Rn] = sh4r.ssr;
nkeynes@359
  1109
:}
nkeynes@359
  1110
STC SPC, Rn {:
nkeynes@359
  1111
    CHECKPRIV();
nkeynes@359
  1112
    sh4r.r[Rn] = sh4r.spc;
nkeynes@359
  1113
:}
nkeynes@359
  1114
STC Rm_BANK, Rn {:
nkeynes@359
  1115
    CHECKPRIV();
nkeynes@359
  1116
    sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
nkeynes@359
  1117
:}
nkeynes@359
  1118
nkeynes@359
  1119
FADD FRm, FRn {:
nkeynes@359
  1120
    CHECKFPUEN();
nkeynes@359
  1121
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1122
	DR(FRn) += DR(FRm);
nkeynes@359
  1123
    } else {
nkeynes@359
  1124
	FR(FRn) += FR(FRm);
nkeynes@359
  1125
    }
nkeynes@359
  1126
:}
nkeynes@359
  1127
FSUB FRm, FRn {:
nkeynes@359
  1128
    CHECKFPUEN();
nkeynes@359
  1129
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1130
	DR(FRn) -= DR(FRm);
nkeynes@359
  1131
    } else {
nkeynes@359
  1132
	FR(FRn) -= FR(FRm);
nkeynes@359
  1133
    }
nkeynes@359
  1134
:}
nkeynes@359
  1135
nkeynes@359
  1136
FMUL FRm, FRn {:
nkeynes@359
  1137
    CHECKFPUEN();
nkeynes@359
  1138
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1139
	DR(FRn) *= DR(FRm);
nkeynes@359
  1140
    } else {
nkeynes@359
  1141
	FR(FRn) *= FR(FRm);
nkeynes@359
  1142
    }
nkeynes@359
  1143
:}
nkeynes@359
  1144
nkeynes@359
  1145
FDIV FRm, FRn {:
nkeynes@359
  1146
    CHECKFPUEN();
nkeynes@359
  1147
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1148
	DR(FRn) /= DR(FRm);
nkeynes@359
  1149
    } else {
nkeynes@359
  1150
	FR(FRn) /= FR(FRm);
nkeynes@359
  1151
    }
nkeynes@359
  1152
:}
nkeynes@359
  1153
nkeynes@359
  1154
FCMP/EQ FRm, FRn {:
nkeynes@359
  1155
    CHECKFPUEN();
nkeynes@359
  1156
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1157
	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
nkeynes@359
  1158
    } else {
nkeynes@359
  1159
	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
nkeynes@359
  1160
    }
nkeynes@359
  1161
:}
nkeynes@359
  1162
nkeynes@359
  1163
FCMP/GT FRm, FRn {:
nkeynes@359
  1164
    CHECKFPUEN();
nkeynes@359
  1165
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1166
	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
nkeynes@359
  1167
    } else {
nkeynes@359
  1168
	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
nkeynes@359
  1169
    }
nkeynes@359
  1170
:}
nkeynes@359
  1171
nkeynes@359
  1172
FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
nkeynes@359
  1173
FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
nkeynes@359
  1174
FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
nkeynes@359
  1175
FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
nkeynes@359
  1176
FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
nkeynes@359
  1177
FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
nkeynes@359
  1178
FMOV FRm, FRn {: 
nkeynes@359
  1179
    if( IS_FPU_DOUBLESIZE() )
nkeynes@359
  1180
	DR(FRn) = DR(FRm);
nkeynes@359
  1181
    else
nkeynes@359
  1182
	FR(FRn) = FR(FRm);
nkeynes@359
  1183
:}
nkeynes@359
  1184
FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
nkeynes@359
  1185
FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
nkeynes@359
  1186
FLOAT FPUL, FRn {: 
nkeynes@359
  1187
    CHECKFPUEN();
nkeynes@359
  1188
    if( IS_FPU_DOUBLEPREC() )
nkeynes@359
  1189
	DR(FRn) = (float)FPULi;
nkeynes@359
  1190
    else
nkeynes@359
  1191
	FR(FRn) = (float)FPULi;
nkeynes@359
  1192
:}
nkeynes@359
  1193
FTRC FRm, FPUL {:
nkeynes@359
  1194
    CHECKFPUEN();
nkeynes@359
  1195
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1196
        dtmp = DR(FRm);
nkeynes@359
  1197
        if( dtmp >= MAX_INTF )
nkeynes@359
  1198
            FPULi = MAX_INT;
nkeynes@359
  1199
        else if( dtmp <= MIN_INTF )
nkeynes@359
  1200
            FPULi = MIN_INT;
nkeynes@359
  1201
        else 
nkeynes@359
  1202
            FPULi = (int32_t)dtmp;
nkeynes@359
  1203
    } else {
nkeynes@359
  1204
	ftmp = FR(FRm);
nkeynes@359
  1205
	if( ftmp >= MAX_INTF )
nkeynes@359
  1206
	    FPULi = MAX_INT;
nkeynes@359
  1207
	else if( ftmp <= MIN_INTF )
nkeynes@359
  1208
	    FPULi = MIN_INT;
nkeynes@359
  1209
	else
nkeynes@359
  1210
	    FPULi = (int32_t)ftmp;
nkeynes@359
  1211
    }
nkeynes@359
  1212
:}
nkeynes@359
  1213
FNEG FRn {:
nkeynes@359
  1214
    CHECKFPUEN();
nkeynes@359
  1215
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1216
	DR(FRn) = -DR(FRn);
nkeynes@359
  1217
    } else {
nkeynes@359
  1218
        FR(FRn) = -FR(FRn);
nkeynes@359
  1219
    }
nkeynes@359
  1220
:}
nkeynes@359
  1221
FABS FRn {:
nkeynes@359
  1222
    CHECKFPUEN();
nkeynes@359
  1223
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1224
	DR(FRn) = fabs(DR(FRn));
nkeynes@359
  1225
    } else {
nkeynes@359
  1226
        FR(FRn) = fabsf(FR(FRn));
nkeynes@359
  1227
    }
nkeynes@359
  1228
:}
nkeynes@359
  1229
FSQRT FRn {:
nkeynes@359
  1230
    CHECKFPUEN();
nkeynes@359
  1231
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1232
	DR(FRn) = sqrt(DR(FRn));
nkeynes@359
  1233
    } else {
nkeynes@359
  1234
        FR(FRn) = sqrtf(FR(FRn));
nkeynes@359
  1235
    }
nkeynes@359
  1236
:}
nkeynes@359
  1237
FLDI0 FRn {:
nkeynes@359
  1238
    CHECKFPUEN();
nkeynes@359
  1239
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1240
	DR(FRn) = 0.0;
nkeynes@359
  1241
    } else {
nkeynes@359
  1242
        FR(FRn) = 0.0;
nkeynes@359
  1243
    }
nkeynes@359
  1244
:}
nkeynes@359
  1245
FLDI1 FRn {:
nkeynes@359
  1246
    CHECKFPUEN();
nkeynes@359
  1247
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1248
	DR(FRn) = 1.0;
nkeynes@359
  1249
    } else {
nkeynes@359
  1250
        FR(FRn) = 1.0;
nkeynes@359
  1251
    }
nkeynes@359
  1252
:}
nkeynes@359
  1253
FMAC FR0, FRm, FRn {:
nkeynes@359
  1254
    CHECKFPUEN();
nkeynes@359
  1255
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1256
        DR(FRn) += DR(FRm)*DR(0);
nkeynes@359
  1257
    } else {
nkeynes@359
  1258
	FR(FRn) += FR(FRm)*FR(0);
nkeynes@359
  1259
    }
nkeynes@359
  1260
:}
nkeynes@359
  1261
FRCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR; :}
nkeynes@359
  1262
FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
nkeynes@359
  1263
FCNVSD FPUL, FRn {:
nkeynes@359
  1264
    CHECKFPUEN();
nkeynes@359
  1265
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1266
	DR(FRn) = (double)FPULf;
nkeynes@359
  1267
    }
nkeynes@359
  1268
:}
nkeynes@359
  1269
FCNVDS FRm, FPUL {:
nkeynes@359
  1270
    CHECKFPUEN();
nkeynes@359
  1271
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1272
	FPULf = (float)DR(FRm);
nkeynes@359
  1273
    }
nkeynes@359
  1274
:}
nkeynes@359
  1275
nkeynes@359
  1276
FSRRA FRn {:
nkeynes@359
  1277
    CHECKFPUEN();
nkeynes@359
  1278
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1279
	FR(FRn) = 1.0/sqrtf(FR(FRn));
nkeynes@359
  1280
    }
nkeynes@359
  1281
:}
nkeynes@359
  1282
FIPR FVm, FVn {:
nkeynes@359
  1283
    CHECKFPUEN();
nkeynes@359
  1284
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1285
        int tmp2 = FVn<<2;
nkeynes@359
  1286
        tmp = FVm<<2;
nkeynes@359
  1287
        FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@359
  1288
            FR(tmp+1)*FR(tmp2+1) +
nkeynes@359
  1289
            FR(tmp+2)*FR(tmp2+2) +
nkeynes@359
  1290
            FR(tmp+3)*FR(tmp2+3);
nkeynes@359
  1291
    }
nkeynes@359
  1292
:}
nkeynes@359
  1293
FSCA FPUL, FRn {:
nkeynes@359
  1294
    CHECKFPUEN();
nkeynes@359
  1295
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1296
        float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
nkeynes@359
  1297
        FR(FRn) = sinf(angle);
nkeynes@359
  1298
        FR((FRn)+1) = cosf(angle);
nkeynes@359
  1299
    }
nkeynes@359
  1300
:}
nkeynes@359
  1301
FTRV XMTRX, FVn {:
nkeynes@359
  1302
    CHECKFPUEN();
nkeynes@359
  1303
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1304
        tmp = FVn<<2;
nkeynes@359
  1305
        float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
nkeynes@359
  1306
        FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
nkeynes@359
  1307
	    XF(8)*fv[2] + XF(12)*fv[3];
nkeynes@359
  1308
        FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
nkeynes@359
  1309
	    XF(9)*fv[2] + XF(13)*fv[3];
nkeynes@359
  1310
        FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
nkeynes@359
  1311
	    XF(10)*fv[2] + XF(14)*fv[3];
nkeynes@359
  1312
        FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
nkeynes@359
  1313
	    XF(11)*fv[2] + XF(15)*fv[3];
nkeynes@359
  1314
    }
nkeynes@359
  1315
:}
nkeynes@359
  1316
UNDEF {:
nkeynes@359
  1317
    UNDEF(ir);
nkeynes@359
  1318
:}
nkeynes@359
  1319
%%
nkeynes@359
  1320
    sh4r.pc = sh4r.new_pc;
nkeynes@359
  1321
    sh4r.new_pc += 2;
nkeynes@359
  1322
    sh4r.in_delay_slot = 0;
nkeynes@359
  1323
    return TRUE;
nkeynes@359
  1324
}
.