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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 905:4c17ebd9ef5e
prev904:5b92e51ac06b
next908:a00debcf2600
author nkeynes
date Wed Oct 29 23:51:58 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Use regparam calling conventions for all functions called from translated code,
along with a few other high-use functions. Can probably extend this to all functions,
but as it is this is a nice performance boost
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    // Note: Include the push/pop ebx sequence in case of PIC builds. This 
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    // isn't exactly on a critical path anyway
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    __asm__ __volatile__(
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        "pushl %%ebx\n\t"
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t"
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        "popl %%ebx" : "=c" (features) : : "eax", "edx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
nkeynes@586
   311
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   312
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   313
 */
nkeynes@586
   314
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   315
nkeynes@590
   316
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   317
nkeynes@539
   318
/****** Import appropriate calling conventions ******/
nkeynes@675
   319
#if SIZEOF_VOID_P == 8
nkeynes@539
   320
#include "sh4/ia64abi.h"
nkeynes@675
   321
#else /* 32-bit system */
nkeynes@539
   322
#ifdef APPLE_BUILD
nkeynes@539
   323
#include "sh4/ia32mac.h"
nkeynes@539
   324
#else
nkeynes@539
   325
#include "sh4/ia32abi.h"
nkeynes@539
   326
#endif
nkeynes@539
   327
#endif
nkeynes@539
   328
nkeynes@901
   329
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   330
{
nkeynes@901
   331
	enter_block();
nkeynes@901
   332
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   333
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   334
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   335
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   336
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   337
    sh4_x86.block_start_pc = pc;
nkeynes@901
   338
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   340
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   341
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   342
}
nkeynes@901
   343
nkeynes@901
   344
nkeynes@593
   345
uint32_t sh4_translate_end_block_size()
nkeynes@593
   346
{
nkeynes@596
   347
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   348
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   349
    } else {
nkeynes@901
   350
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   351
    }
nkeynes@593
   352
}
nkeynes@593
   353
nkeynes@593
   354
nkeynes@590
   355
/**
nkeynes@590
   356
 * Embed a breakpoint into the generated code
nkeynes@590
   357
 */
nkeynes@586
   358
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   359
{
nkeynes@591
   360
    load_imm32( R_EAX, pc );
nkeynes@591
   361
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   363
}
nkeynes@590
   364
nkeynes@601
   365
nkeynes@601
   366
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   367
nkeynes@590
   368
/**
nkeynes@590
   369
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   370
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   371
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   372
 *
nkeynes@601
   373
 * Performs:
nkeynes@601
   374
 *   Set PC = endpc
nkeynes@601
   375
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   376
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   377
 *   Call sh4_execute_instruction
nkeynes@601
   378
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   379
 */
nkeynes@601
   380
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   381
{
nkeynes@590
   382
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   383
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   384
    
nkeynes@601
   385
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   386
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   387
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   388
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   389
nkeynes@590
   390
    call_func0( sh4_execute_instruction );    
nkeynes@601
   391
    load_spreg( R_EAX, R_PC );
nkeynes@590
   392
    if( sh4_x86.tlb_on ) {
nkeynes@590
   393
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   394
    } else {
nkeynes@590
   395
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   396
    }
nkeynes@601
   397
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   398
    POP_r32(R_EBP);
nkeynes@590
   399
    RET();
nkeynes@590
   400
} 
nkeynes@539
   401
nkeynes@359
   402
/**
nkeynes@359
   403
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   404
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   405
 * 
nkeynes@586
   406
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   407
 *
nkeynes@359
   408
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   409
 * (eg a branch or 
nkeynes@359
   410
 */
nkeynes@590
   411
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   412
{
nkeynes@388
   413
    uint32_t ir;
nkeynes@586
   414
    /* Read instruction from icache */
nkeynes@586
   415
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   416
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   417
    
nkeynes@586
   418
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   419
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   420
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   421
	 * almost certainly in a delay slot.
nkeynes@586
   422
	 *
nkeynes@586
   423
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   424
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   425
	 * small repairs to cope with the different environment).
nkeynes@586
   426
	 */
nkeynes@586
   427
nkeynes@586
   428
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   429
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   430
    }
nkeynes@359
   431
%%
nkeynes@359
   432
/* ALU operations */
nkeynes@359
   433
ADD Rm, Rn {:
nkeynes@671
   434
    COUNT_INST(I_ADD);
nkeynes@359
   435
    load_reg( R_EAX, Rm );
nkeynes@359
   436
    load_reg( R_ECX, Rn );
nkeynes@359
   437
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   438
    store_reg( R_ECX, Rn );
nkeynes@417
   439
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   440
:}
nkeynes@359
   441
ADD #imm, Rn {:  
nkeynes@671
   442
    COUNT_INST(I_ADDI);
nkeynes@359
   443
    load_reg( R_EAX, Rn );
nkeynes@359
   444
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   445
    store_reg( R_EAX, Rn );
nkeynes@417
   446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   447
:}
nkeynes@359
   448
ADDC Rm, Rn {:
nkeynes@671
   449
    COUNT_INST(I_ADDC);
nkeynes@417
   450
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   451
	LDC_t();
nkeynes@417
   452
    }
nkeynes@359
   453
    load_reg( R_EAX, Rm );
nkeynes@359
   454
    load_reg( R_ECX, Rn );
nkeynes@359
   455
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   456
    store_reg( R_ECX, Rn );
nkeynes@359
   457
    SETC_t();
nkeynes@417
   458
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   459
:}
nkeynes@359
   460
ADDV Rm, Rn {:
nkeynes@671
   461
    COUNT_INST(I_ADDV);
nkeynes@359
   462
    load_reg( R_EAX, Rm );
nkeynes@359
   463
    load_reg( R_ECX, Rn );
nkeynes@359
   464
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   465
    store_reg( R_ECX, Rn );
nkeynes@359
   466
    SETO_t();
nkeynes@417
   467
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   468
:}
nkeynes@359
   469
AND Rm, Rn {:
nkeynes@671
   470
    COUNT_INST(I_AND);
nkeynes@359
   471
    load_reg( R_EAX, Rm );
nkeynes@359
   472
    load_reg( R_ECX, Rn );
nkeynes@359
   473
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   474
    store_reg( R_ECX, Rn );
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   476
:}
nkeynes@359
   477
AND #imm, R0 {:  
nkeynes@671
   478
    COUNT_INST(I_ANDI);
nkeynes@359
   479
    load_reg( R_EAX, 0 );
nkeynes@359
   480
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   481
    store_reg( R_EAX, 0 );
nkeynes@417
   482
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   483
:}
nkeynes@359
   484
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   485
    COUNT_INST(I_ANDB);
nkeynes@359
   486
    load_reg( R_EAX, 0 );
nkeynes@359
   487
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   488
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   489
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   490
    PUSH_realigned_r32(R_EAX);
nkeynes@905
   491
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
   492
    POP_realigned_r32(R_EAX);
nkeynes@905
   493
    AND_imm32_r32(imm, R_EDX );
nkeynes@905
   494
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   496
:}
nkeynes@359
   497
CMP/EQ Rm, Rn {:  
nkeynes@671
   498
    COUNT_INST(I_CMPEQ);
nkeynes@359
   499
    load_reg( R_EAX, Rm );
nkeynes@359
   500
    load_reg( R_ECX, Rn );
nkeynes@359
   501
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   502
    SETE_t();
nkeynes@417
   503
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   504
:}
nkeynes@359
   505
CMP/EQ #imm, R0 {:  
nkeynes@671
   506
    COUNT_INST(I_CMPEQI);
nkeynes@359
   507
    load_reg( R_EAX, 0 );
nkeynes@359
   508
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   509
    SETE_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/GE Rm, Rn {:  
nkeynes@671
   513
    COUNT_INST(I_CMPGE);
nkeynes@359
   514
    load_reg( R_EAX, Rm );
nkeynes@359
   515
    load_reg( R_ECX, Rn );
nkeynes@359
   516
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   517
    SETGE_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/GT Rm, Rn {: 
nkeynes@671
   521
    COUNT_INST(I_CMPGT);
nkeynes@359
   522
    load_reg( R_EAX, Rm );
nkeynes@359
   523
    load_reg( R_ECX, Rn );
nkeynes@359
   524
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   525
    SETG_t();
nkeynes@417
   526
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   527
:}
nkeynes@359
   528
CMP/HI Rm, Rn {:  
nkeynes@671
   529
    COUNT_INST(I_CMPHI);
nkeynes@359
   530
    load_reg( R_EAX, Rm );
nkeynes@359
   531
    load_reg( R_ECX, Rn );
nkeynes@359
   532
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   533
    SETA_t();
nkeynes@417
   534
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   535
:}
nkeynes@359
   536
CMP/HS Rm, Rn {: 
nkeynes@671
   537
    COUNT_INST(I_CMPHS);
nkeynes@359
   538
    load_reg( R_EAX, Rm );
nkeynes@359
   539
    load_reg( R_ECX, Rn );
nkeynes@359
   540
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   541
    SETAE_t();
nkeynes@417
   542
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   543
 :}
nkeynes@359
   544
CMP/PL Rn {: 
nkeynes@671
   545
    COUNT_INST(I_CMPPL);
nkeynes@359
   546
    load_reg( R_EAX, Rn );
nkeynes@359
   547
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   548
    SETG_t();
nkeynes@417
   549
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   550
:}
nkeynes@359
   551
CMP/PZ Rn {:  
nkeynes@671
   552
    COUNT_INST(I_CMPPZ);
nkeynes@359
   553
    load_reg( R_EAX, Rn );
nkeynes@359
   554
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   555
    SETGE_t();
nkeynes@417
   556
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   557
:}
nkeynes@361
   558
CMP/STR Rm, Rn {:  
nkeynes@671
   559
    COUNT_INST(I_CMPSTR);
nkeynes@368
   560
    load_reg( R_EAX, Rm );
nkeynes@368
   561
    load_reg( R_ECX, Rn );
nkeynes@368
   562
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   563
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   564
    JE_rel8(target1);
nkeynes@669
   565
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   566
    JE_rel8(target2);
nkeynes@669
   567
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   568
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   569
    JE_rel8(target3);
nkeynes@669
   570
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   571
    JMP_TARGET(target1);
nkeynes@380
   572
    JMP_TARGET(target2);
nkeynes@380
   573
    JMP_TARGET(target3);
nkeynes@368
   574
    SETE_t();
nkeynes@417
   575
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   576
:}
nkeynes@361
   577
DIV0S Rm, Rn {:
nkeynes@671
   578
    COUNT_INST(I_DIV0S);
nkeynes@361
   579
    load_reg( R_EAX, Rm );
nkeynes@386
   580
    load_reg( R_ECX, Rn );
nkeynes@361
   581
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   582
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   583
    store_spreg( R_EAX, R_M );
nkeynes@361
   584
    store_spreg( R_ECX, R_Q );
nkeynes@361
   585
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   586
    SETNE_t();
nkeynes@417
   587
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   588
:}
nkeynes@361
   589
DIV0U {:  
nkeynes@671
   590
    COUNT_INST(I_DIV0U);
nkeynes@361
   591
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   592
    store_spreg( R_EAX, R_Q );
nkeynes@361
   593
    store_spreg( R_EAX, R_M );
nkeynes@361
   594
    store_spreg( R_EAX, R_T );
nkeynes@417
   595
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   596
:}
nkeynes@386
   597
DIV1 Rm, Rn {:
nkeynes@671
   598
    COUNT_INST(I_DIV1);
nkeynes@386
   599
    load_spreg( R_ECX, R_M );
nkeynes@386
   600
    load_reg( R_EAX, Rn );
nkeynes@417
   601
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   602
	LDC_t();
nkeynes@417
   603
    }
nkeynes@386
   604
    RCL1_r32( R_EAX );
nkeynes@386
   605
    SETC_r8( R_DL ); // Q'
nkeynes@386
   606
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   607
    JE_rel8(mqequal);
nkeynes@386
   608
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   609
    JMP_rel8(end);
nkeynes@380
   610
    JMP_TARGET(mqequal);
nkeynes@386
   611
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   612
    JMP_TARGET(end);
nkeynes@386
   613
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   614
    SETC_r8(R_AL); // tmp1
nkeynes@386
   615
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   616
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   617
    store_spreg( R_ECX, R_Q );
nkeynes@386
   618
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   619
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   620
    store_spreg( R_EAX, R_T );
nkeynes@417
   621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   622
:}
nkeynes@361
   623
DMULS.L Rm, Rn {:  
nkeynes@671
   624
    COUNT_INST(I_DMULS);
nkeynes@361
   625
    load_reg( R_EAX, Rm );
nkeynes@361
   626
    load_reg( R_ECX, Rn );
nkeynes@361
   627
    IMUL_r32(R_ECX);
nkeynes@361
   628
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   629
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   630
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   631
:}
nkeynes@361
   632
DMULU.L Rm, Rn {:  
nkeynes@671
   633
    COUNT_INST(I_DMULU);
nkeynes@361
   634
    load_reg( R_EAX, Rm );
nkeynes@361
   635
    load_reg( R_ECX, Rn );
nkeynes@361
   636
    MUL_r32(R_ECX);
nkeynes@361
   637
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   638
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   639
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   640
:}
nkeynes@359
   641
DT Rn {:  
nkeynes@671
   642
    COUNT_INST(I_DT);
nkeynes@359
   643
    load_reg( R_EAX, Rn );
nkeynes@382
   644
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   645
    store_reg( R_EAX, Rn );
nkeynes@359
   646
    SETE_t();
nkeynes@417
   647
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   648
:}
nkeynes@359
   649
EXTS.B Rm, Rn {:  
nkeynes@671
   650
    COUNT_INST(I_EXTSB);
nkeynes@359
   651
    load_reg( R_EAX, Rm );
nkeynes@359
   652
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   653
    store_reg( R_EAX, Rn );
nkeynes@359
   654
:}
nkeynes@361
   655
EXTS.W Rm, Rn {:  
nkeynes@671
   656
    COUNT_INST(I_EXTSW);
nkeynes@361
   657
    load_reg( R_EAX, Rm );
nkeynes@361
   658
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   659
    store_reg( R_EAX, Rn );
nkeynes@361
   660
:}
nkeynes@361
   661
EXTU.B Rm, Rn {:  
nkeynes@671
   662
    COUNT_INST(I_EXTUB);
nkeynes@361
   663
    load_reg( R_EAX, Rm );
nkeynes@361
   664
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   665
    store_reg( R_EAX, Rn );
nkeynes@361
   666
:}
nkeynes@361
   667
EXTU.W Rm, Rn {:  
nkeynes@671
   668
    COUNT_INST(I_EXTUW);
nkeynes@361
   669
    load_reg( R_EAX, Rm );
nkeynes@361
   670
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   671
    store_reg( R_EAX, Rn );
nkeynes@361
   672
:}
nkeynes@586
   673
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   674
    COUNT_INST(I_MACL);
nkeynes@586
   675
    if( Rm == Rn ) {
nkeynes@586
   676
	load_reg( R_EAX, Rm );
nkeynes@586
   677
	check_ralign32( R_EAX );
nkeynes@586
   678
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   679
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   680
	load_reg( R_EAX, Rn );
nkeynes@586
   681
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   682
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   683
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   684
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   685
	// adding a page-boundary check to skip the second translation
nkeynes@586
   686
    } else {
nkeynes@586
   687
	load_reg( R_EAX, Rm );
nkeynes@586
   688
	check_ralign32( R_EAX );
nkeynes@586
   689
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   690
	load_reg( R_ECX, Rn );
nkeynes@596
   691
	check_ralign32( R_ECX );
nkeynes@586
   692
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   693
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   694
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   695
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   696
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   697
    }
nkeynes@586
   698
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   699
    POP_r32( R_ECX );
nkeynes@586
   700
    PUSH_r32( R_EAX );
nkeynes@386
   701
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   702
    POP_realigned_r32( R_ECX );
nkeynes@586
   703
nkeynes@386
   704
    IMUL_r32( R_ECX );
nkeynes@386
   705
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   706
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   707
nkeynes@386
   708
    load_spreg( R_ECX, R_S );
nkeynes@386
   709
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   710
    JE_rel8( nosat );
nkeynes@386
   711
    call_func0( signsat48 );
nkeynes@386
   712
    JMP_TARGET( nosat );
nkeynes@417
   713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   714
:}
nkeynes@386
   715
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   716
    COUNT_INST(I_MACW);
nkeynes@586
   717
    if( Rm == Rn ) {
nkeynes@586
   718
	load_reg( R_EAX, Rm );
nkeynes@586
   719
	check_ralign16( R_EAX );
nkeynes@586
   720
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   721
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   722
	load_reg( R_EAX, Rn );
nkeynes@586
   723
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   724
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   725
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   726
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   727
	// adding a page-boundary check to skip the second translation
nkeynes@586
   728
    } else {
nkeynes@586
   729
	load_reg( R_EAX, Rm );
nkeynes@586
   730
	check_ralign16( R_EAX );
nkeynes@586
   731
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   732
	load_reg( R_ECX, Rn );
nkeynes@596
   733
	check_ralign16( R_ECX );
nkeynes@586
   734
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   735
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   736
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   737
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   738
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   739
    }
nkeynes@586
   740
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   741
    POP_r32( R_ECX );
nkeynes@586
   742
    PUSH_r32( R_EAX );
nkeynes@386
   743
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   744
    POP_realigned_r32( R_ECX );
nkeynes@386
   745
    IMUL_r32( R_ECX );
nkeynes@386
   746
nkeynes@386
   747
    load_spreg( R_ECX, R_S );
nkeynes@386
   748
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   749
    JE_rel8( nosat );
nkeynes@386
   750
nkeynes@386
   751
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   752
    JNO_rel8( end );            // 2
nkeynes@386
   753
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   754
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   755
    JS_rel8( positive );        // 2
nkeynes@386
   756
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   757
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   758
    JMP_rel8(end2);           // 2
nkeynes@386
   759
nkeynes@386
   760
    JMP_TARGET(positive);
nkeynes@386
   761
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   762
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   763
    JMP_rel8(end3);            // 2
nkeynes@386
   764
nkeynes@386
   765
    JMP_TARGET(nosat);
nkeynes@386
   766
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   767
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   768
    JMP_TARGET(end);
nkeynes@386
   769
    JMP_TARGET(end2);
nkeynes@386
   770
    JMP_TARGET(end3);
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   772
:}
nkeynes@359
   773
MOVT Rn {:  
nkeynes@671
   774
    COUNT_INST(I_MOVT);
nkeynes@359
   775
    load_spreg( R_EAX, R_T );
nkeynes@359
   776
    store_reg( R_EAX, Rn );
nkeynes@359
   777
:}
nkeynes@361
   778
MUL.L Rm, Rn {:  
nkeynes@671
   779
    COUNT_INST(I_MULL);
nkeynes@361
   780
    load_reg( R_EAX, Rm );
nkeynes@361
   781
    load_reg( R_ECX, Rn );
nkeynes@361
   782
    MUL_r32( R_ECX );
nkeynes@361
   783
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   784
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   785
:}
nkeynes@374
   786
MULS.W Rm, Rn {:
nkeynes@671
   787
    COUNT_INST(I_MULSW);
nkeynes@374
   788
    load_reg16s( R_EAX, Rm );
nkeynes@374
   789
    load_reg16s( R_ECX, Rn );
nkeynes@374
   790
    MUL_r32( R_ECX );
nkeynes@374
   791
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   792
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   793
:}
nkeynes@374
   794
MULU.W Rm, Rn {:  
nkeynes@671
   795
    COUNT_INST(I_MULUW);
nkeynes@374
   796
    load_reg16u( R_EAX, Rm );
nkeynes@374
   797
    load_reg16u( R_ECX, Rn );
nkeynes@374
   798
    MUL_r32( R_ECX );
nkeynes@374
   799
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   801
:}
nkeynes@359
   802
NEG Rm, Rn {:
nkeynes@671
   803
    COUNT_INST(I_NEG);
nkeynes@359
   804
    load_reg( R_EAX, Rm );
nkeynes@359
   805
    NEG_r32( R_EAX );
nkeynes@359
   806
    store_reg( R_EAX, Rn );
nkeynes@417
   807
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   808
:}
nkeynes@359
   809
NEGC Rm, Rn {:  
nkeynes@671
   810
    COUNT_INST(I_NEGC);
nkeynes@359
   811
    load_reg( R_EAX, Rm );
nkeynes@359
   812
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   813
    LDC_t();
nkeynes@359
   814
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   815
    store_reg( R_ECX, Rn );
nkeynes@359
   816
    SETC_t();
nkeynes@417
   817
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   818
:}
nkeynes@359
   819
NOT Rm, Rn {:  
nkeynes@671
   820
    COUNT_INST(I_NOT);
nkeynes@359
   821
    load_reg( R_EAX, Rm );
nkeynes@359
   822
    NOT_r32( R_EAX );
nkeynes@359
   823
    store_reg( R_EAX, Rn );
nkeynes@417
   824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   825
:}
nkeynes@359
   826
OR Rm, Rn {:  
nkeynes@671
   827
    COUNT_INST(I_OR);
nkeynes@359
   828
    load_reg( R_EAX, Rm );
nkeynes@359
   829
    load_reg( R_ECX, Rn );
nkeynes@359
   830
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   831
    store_reg( R_ECX, Rn );
nkeynes@417
   832
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   833
:}
nkeynes@359
   834
OR #imm, R0 {:
nkeynes@671
   835
    COUNT_INST(I_ORI);
nkeynes@359
   836
    load_reg( R_EAX, 0 );
nkeynes@359
   837
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   838
    store_reg( R_EAX, 0 );
nkeynes@417
   839
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   840
:}
nkeynes@374
   841
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   842
    COUNT_INST(I_ORB);
nkeynes@374
   843
    load_reg( R_EAX, 0 );
nkeynes@374
   844
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   845
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   846
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   847
    PUSH_realigned_r32(R_EAX);
nkeynes@905
   848
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
   849
    POP_realigned_r32(R_EAX);
nkeynes@905
   850
    OR_imm32_r32(imm, R_EDX );
nkeynes@905
   851
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   852
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   853
:}
nkeynes@359
   854
ROTCL Rn {:
nkeynes@671
   855
    COUNT_INST(I_ROTCL);
nkeynes@359
   856
    load_reg( R_EAX, Rn );
nkeynes@417
   857
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   858
	LDC_t();
nkeynes@417
   859
    }
nkeynes@359
   860
    RCL1_r32( R_EAX );
nkeynes@359
   861
    store_reg( R_EAX, Rn );
nkeynes@359
   862
    SETC_t();
nkeynes@417
   863
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   864
:}
nkeynes@359
   865
ROTCR Rn {:  
nkeynes@671
   866
    COUNT_INST(I_ROTCR);
nkeynes@359
   867
    load_reg( R_EAX, Rn );
nkeynes@417
   868
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   869
	LDC_t();
nkeynes@417
   870
    }
nkeynes@359
   871
    RCR1_r32( R_EAX );
nkeynes@359
   872
    store_reg( R_EAX, Rn );
nkeynes@359
   873
    SETC_t();
nkeynes@417
   874
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   875
:}
nkeynes@359
   876
ROTL Rn {:  
nkeynes@671
   877
    COUNT_INST(I_ROTL);
nkeynes@359
   878
    load_reg( R_EAX, Rn );
nkeynes@359
   879
    ROL1_r32( R_EAX );
nkeynes@359
   880
    store_reg( R_EAX, Rn );
nkeynes@359
   881
    SETC_t();
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   883
:}
nkeynes@359
   884
ROTR Rn {:  
nkeynes@671
   885
    COUNT_INST(I_ROTR);
nkeynes@359
   886
    load_reg( R_EAX, Rn );
nkeynes@359
   887
    ROR1_r32( R_EAX );
nkeynes@359
   888
    store_reg( R_EAX, Rn );
nkeynes@359
   889
    SETC_t();
nkeynes@417
   890
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   891
:}
nkeynes@359
   892
SHAD Rm, Rn {:
nkeynes@671
   893
    COUNT_INST(I_SHAD);
nkeynes@359
   894
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   895
    load_reg( R_EAX, Rn );
nkeynes@361
   896
    load_reg( R_ECX, Rm );
nkeynes@361
   897
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   898
    JGE_rel8(doshl);
nkeynes@361
   899
                    
nkeynes@361
   900
    NEG_r32( R_ECX );      // 2
nkeynes@361
   901
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   902
    JE_rel8(emptysar);     // 2
nkeynes@361
   903
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   904
    JMP_rel8(end);          // 2
nkeynes@386
   905
nkeynes@386
   906
    JMP_TARGET(emptysar);
nkeynes@386
   907
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   908
    JMP_rel8(end2);
nkeynes@382
   909
nkeynes@380
   910
    JMP_TARGET(doshl);
nkeynes@361
   911
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   912
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   913
    JMP_TARGET(end);
nkeynes@386
   914
    JMP_TARGET(end2);
nkeynes@361
   915
    store_reg( R_EAX, Rn );
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   917
:}
nkeynes@359
   918
SHLD Rm, Rn {:  
nkeynes@671
   919
    COUNT_INST(I_SHLD);
nkeynes@368
   920
    load_reg( R_EAX, Rn );
nkeynes@368
   921
    load_reg( R_ECX, Rm );
nkeynes@382
   922
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   923
    JGE_rel8(doshl);
nkeynes@368
   924
nkeynes@382
   925
    NEG_r32( R_ECX );      // 2
nkeynes@382
   926
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   927
    JE_rel8(emptyshr );
nkeynes@382
   928
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   929
    JMP_rel8(end);          // 2
nkeynes@386
   930
nkeynes@386
   931
    JMP_TARGET(emptyshr);
nkeynes@386
   932
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   933
    JMP_rel8(end2);
nkeynes@382
   934
nkeynes@382
   935
    JMP_TARGET(doshl);
nkeynes@382
   936
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   937
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   938
    JMP_TARGET(end);
nkeynes@386
   939
    JMP_TARGET(end2);
nkeynes@368
   940
    store_reg( R_EAX, Rn );
nkeynes@417
   941
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   942
:}
nkeynes@359
   943
SHAL Rn {: 
nkeynes@671
   944
    COUNT_INST(I_SHAL);
nkeynes@359
   945
    load_reg( R_EAX, Rn );
nkeynes@359
   946
    SHL1_r32( R_EAX );
nkeynes@397
   947
    SETC_t();
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@417
   949
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   950
:}
nkeynes@359
   951
SHAR Rn {:  
nkeynes@671
   952
    COUNT_INST(I_SHAR);
nkeynes@359
   953
    load_reg( R_EAX, Rn );
nkeynes@359
   954
    SAR1_r32( R_EAX );
nkeynes@397
   955
    SETC_t();
nkeynes@359
   956
    store_reg( R_EAX, Rn );
nkeynes@417
   957
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   958
:}
nkeynes@359
   959
SHLL Rn {:  
nkeynes@671
   960
    COUNT_INST(I_SHLL);
nkeynes@359
   961
    load_reg( R_EAX, Rn );
nkeynes@359
   962
    SHL1_r32( R_EAX );
nkeynes@397
   963
    SETC_t();
nkeynes@359
   964
    store_reg( R_EAX, Rn );
nkeynes@417
   965
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   966
:}
nkeynes@359
   967
SHLL2 Rn {:
nkeynes@671
   968
    COUNT_INST(I_SHLL);
nkeynes@359
   969
    load_reg( R_EAX, Rn );
nkeynes@359
   970
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   971
    store_reg( R_EAX, Rn );
nkeynes@417
   972
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   973
:}
nkeynes@359
   974
SHLL8 Rn {:  
nkeynes@671
   975
    COUNT_INST(I_SHLL);
nkeynes@359
   976
    load_reg( R_EAX, Rn );
nkeynes@359
   977
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   978
    store_reg( R_EAX, Rn );
nkeynes@417
   979
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   980
:}
nkeynes@359
   981
SHLL16 Rn {:  
nkeynes@671
   982
    COUNT_INST(I_SHLL);
nkeynes@359
   983
    load_reg( R_EAX, Rn );
nkeynes@359
   984
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   985
    store_reg( R_EAX, Rn );
nkeynes@417
   986
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   987
:}
nkeynes@359
   988
SHLR Rn {:  
nkeynes@671
   989
    COUNT_INST(I_SHLR);
nkeynes@359
   990
    load_reg( R_EAX, Rn );
nkeynes@359
   991
    SHR1_r32( R_EAX );
nkeynes@397
   992
    SETC_t();
nkeynes@359
   993
    store_reg( R_EAX, Rn );
nkeynes@417
   994
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   995
:}
nkeynes@359
   996
SHLR2 Rn {:  
nkeynes@671
   997
    COUNT_INST(I_SHLR);
nkeynes@359
   998
    load_reg( R_EAX, Rn );
nkeynes@359
   999
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1000
    store_reg( R_EAX, Rn );
nkeynes@417
  1001
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1002
:}
nkeynes@359
  1003
SHLR8 Rn {:  
nkeynes@671
  1004
    COUNT_INST(I_SHLR);
nkeynes@359
  1005
    load_reg( R_EAX, Rn );
nkeynes@359
  1006
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1007
    store_reg( R_EAX, Rn );
nkeynes@417
  1008
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1009
:}
nkeynes@359
  1010
SHLR16 Rn {:  
nkeynes@671
  1011
    COUNT_INST(I_SHLR);
nkeynes@359
  1012
    load_reg( R_EAX, Rn );
nkeynes@359
  1013
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1014
    store_reg( R_EAX, Rn );
nkeynes@417
  1015
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1016
:}
nkeynes@359
  1017
SUB Rm, Rn {:  
nkeynes@671
  1018
    COUNT_INST(I_SUB);
nkeynes@359
  1019
    load_reg( R_EAX, Rm );
nkeynes@359
  1020
    load_reg( R_ECX, Rn );
nkeynes@359
  1021
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1022
    store_reg( R_ECX, Rn );
nkeynes@417
  1023
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1024
:}
nkeynes@359
  1025
SUBC Rm, Rn {:  
nkeynes@671
  1026
    COUNT_INST(I_SUBC);
nkeynes@359
  1027
    load_reg( R_EAX, Rm );
nkeynes@359
  1028
    load_reg( R_ECX, Rn );
nkeynes@417
  1029
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1030
	LDC_t();
nkeynes@417
  1031
    }
nkeynes@359
  1032
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1033
    store_reg( R_ECX, Rn );
nkeynes@394
  1034
    SETC_t();
nkeynes@417
  1035
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1036
:}
nkeynes@359
  1037
SUBV Rm, Rn {:  
nkeynes@671
  1038
    COUNT_INST(I_SUBV);
nkeynes@359
  1039
    load_reg( R_EAX, Rm );
nkeynes@359
  1040
    load_reg( R_ECX, Rn );
nkeynes@359
  1041
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1042
    store_reg( R_ECX, Rn );
nkeynes@359
  1043
    SETO_t();
nkeynes@417
  1044
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1045
:}
nkeynes@359
  1046
SWAP.B Rm, Rn {:  
nkeynes@671
  1047
    COUNT_INST(I_SWAPB);
nkeynes@359
  1048
    load_reg( R_EAX, Rm );
nkeynes@601
  1049
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1050
    store_reg( R_EAX, Rn );
nkeynes@359
  1051
:}
nkeynes@359
  1052
SWAP.W Rm, Rn {:  
nkeynes@671
  1053
    COUNT_INST(I_SWAPB);
nkeynes@359
  1054
    load_reg( R_EAX, Rm );
nkeynes@359
  1055
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1056
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1057
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1058
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1059
    store_reg( R_ECX, Rn );
nkeynes@417
  1060
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1061
:}
nkeynes@361
  1062
TAS.B @Rn {:  
nkeynes@671
  1063
    COUNT_INST(I_TASB);
nkeynes@586
  1064
    load_reg( R_EAX, Rn );
nkeynes@586
  1065
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1066
    PUSH_realigned_r32( R_EAX );
nkeynes@905
  1067
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1068
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1069
    SETE_t();
nkeynes@905
  1070
    OR_imm8_r8( 0x80, R_DL );
nkeynes@905
  1071
    POP_realigned_r32( R_EAX );
nkeynes@905
  1072
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1073
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1074
:}
nkeynes@361
  1075
TST Rm, Rn {:  
nkeynes@671
  1076
    COUNT_INST(I_TST);
nkeynes@361
  1077
    load_reg( R_EAX, Rm );
nkeynes@361
  1078
    load_reg( R_ECX, Rn );
nkeynes@361
  1079
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1080
    SETE_t();
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1082
:}
nkeynes@368
  1083
TST #imm, R0 {:  
nkeynes@671
  1084
    COUNT_INST(I_TSTI);
nkeynes@368
  1085
    load_reg( R_EAX, 0 );
nkeynes@368
  1086
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1087
    SETE_t();
nkeynes@417
  1088
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1089
:}
nkeynes@368
  1090
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1091
    COUNT_INST(I_TSTB);
nkeynes@368
  1092
    load_reg( R_EAX, 0);
nkeynes@368
  1093
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1094
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1095
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1096
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1097
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1098
    SETE_t();
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1100
:}
nkeynes@359
  1101
XOR Rm, Rn {:  
nkeynes@671
  1102
    COUNT_INST(I_XOR);
nkeynes@359
  1103
    load_reg( R_EAX, Rm );
nkeynes@359
  1104
    load_reg( R_ECX, Rn );
nkeynes@359
  1105
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1106
    store_reg( R_ECX, Rn );
nkeynes@417
  1107
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1108
:}
nkeynes@359
  1109
XOR #imm, R0 {:  
nkeynes@671
  1110
    COUNT_INST(I_XORI);
nkeynes@359
  1111
    load_reg( R_EAX, 0 );
nkeynes@359
  1112
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1113
    store_reg( R_EAX, 0 );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
:}
nkeynes@359
  1116
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1117
    COUNT_INST(I_XORB);
nkeynes@359
  1118
    load_reg( R_EAX, 0 );
nkeynes@359
  1119
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1120
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1121
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1122
    PUSH_realigned_r32(R_EAX);
nkeynes@905
  1123
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@905
  1124
    POP_realigned_r32(R_EAX);
nkeynes@905
  1125
    XOR_imm32_r32( imm, R_EDX );
nkeynes@905
  1126
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1127
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1128
:}
nkeynes@361
  1129
XTRCT Rm, Rn {:
nkeynes@671
  1130
    COUNT_INST(I_XTRCT);
nkeynes@361
  1131
    load_reg( R_EAX, Rm );
nkeynes@394
  1132
    load_reg( R_ECX, Rn );
nkeynes@394
  1133
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1134
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1135
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1136
    store_reg( R_ECX, Rn );
nkeynes@417
  1137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1138
:}
nkeynes@359
  1139
nkeynes@359
  1140
/* Data move instructions */
nkeynes@359
  1141
MOV Rm, Rn {:  
nkeynes@671
  1142
    COUNT_INST(I_MOV);
nkeynes@359
  1143
    load_reg( R_EAX, Rm );
nkeynes@359
  1144
    store_reg( R_EAX, Rn );
nkeynes@359
  1145
:}
nkeynes@359
  1146
MOV #imm, Rn {:  
nkeynes@671
  1147
    COUNT_INST(I_MOVI);
nkeynes@359
  1148
    load_imm32( R_EAX, imm );
nkeynes@359
  1149
    store_reg( R_EAX, Rn );
nkeynes@359
  1150
:}
nkeynes@359
  1151
MOV.B Rm, @Rn {:  
nkeynes@671
  1152
    COUNT_INST(I_MOVB);
nkeynes@586
  1153
    load_reg( R_EAX, Rn );
nkeynes@586
  1154
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1155
    load_reg( R_EDX, Rm );
nkeynes@586
  1156
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1157
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1158
:}
nkeynes@359
  1159
MOV.B Rm, @-Rn {:  
nkeynes@671
  1160
    COUNT_INST(I_MOVB);
nkeynes@586
  1161
    load_reg( R_EAX, Rn );
nkeynes@586
  1162
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1163
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1164
    load_reg( R_EDX, Rm );
nkeynes@586
  1165
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1166
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1167
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1168
:}
nkeynes@359
  1169
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1170
    COUNT_INST(I_MOVB);
nkeynes@359
  1171
    load_reg( R_EAX, 0 );
nkeynes@359
  1172
    load_reg( R_ECX, Rn );
nkeynes@586
  1173
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1174
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1175
    load_reg( R_EDX, Rm );
nkeynes@586
  1176
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1178
:}
nkeynes@359
  1179
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1180
    COUNT_INST(I_MOVB);
nkeynes@586
  1181
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1182
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1183
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1184
    load_reg( R_EDX, 0 );
nkeynes@586
  1185
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1186
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1187
:}
nkeynes@359
  1188
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1189
    COUNT_INST(I_MOVB);
nkeynes@586
  1190
    load_reg( R_EAX, Rn );
nkeynes@586
  1191
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1192
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1193
    load_reg( R_EDX, 0 );
nkeynes@586
  1194
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1196
:}
nkeynes@359
  1197
MOV.B @Rm, Rn {:  
nkeynes@671
  1198
    COUNT_INST(I_MOVB);
nkeynes@586
  1199
    load_reg( R_EAX, Rm );
nkeynes@586
  1200
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1201
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1202
    store_reg( R_EAX, Rn );
nkeynes@417
  1203
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1204
:}
nkeynes@359
  1205
MOV.B @Rm+, Rn {:  
nkeynes@671
  1206
    COUNT_INST(I_MOVB);
nkeynes@586
  1207
    load_reg( R_EAX, Rm );
nkeynes@586
  1208
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1209
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1210
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1211
    store_reg( R_EAX, Rn );
nkeynes@417
  1212
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1213
:}
nkeynes@359
  1214
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1215
    COUNT_INST(I_MOVB);
nkeynes@359
  1216
    load_reg( R_EAX, 0 );
nkeynes@359
  1217
    load_reg( R_ECX, Rm );
nkeynes@586
  1218
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1219
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1220
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1221
    store_reg( R_EAX, Rn );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@359
  1224
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1225
    COUNT_INST(I_MOVB);
nkeynes@586
  1226
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1227
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1228
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1229
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1230
    store_reg( R_EAX, 0 );
nkeynes@417
  1231
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1232
:}
nkeynes@359
  1233
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1234
    COUNT_INST(I_MOVB);
nkeynes@586
  1235
    load_reg( R_EAX, Rm );
nkeynes@586
  1236
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1237
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1238
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1239
    store_reg( R_EAX, 0 );
nkeynes@417
  1240
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1241
:}
nkeynes@374
  1242
MOV.L Rm, @Rn {:
nkeynes@671
  1243
    COUNT_INST(I_MOVL);
nkeynes@586
  1244
    load_reg( R_EAX, Rn );
nkeynes@586
  1245
    check_walign32(R_EAX);
nkeynes@586
  1246
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1247
    load_reg( R_EDX, Rm );
nkeynes@586
  1248
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1250
:}
nkeynes@361
  1251
MOV.L Rm, @-Rn {:  
nkeynes@671
  1252
    COUNT_INST(I_MOVL);
nkeynes@586
  1253
    load_reg( R_EAX, Rn );
nkeynes@586
  1254
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1255
    check_walign32( R_EAX );
nkeynes@586
  1256
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1257
    load_reg( R_EDX, Rm );
nkeynes@586
  1258
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1259
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1261
:}
nkeynes@361
  1262
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1263
    COUNT_INST(I_MOVL);
nkeynes@361
  1264
    load_reg( R_EAX, 0 );
nkeynes@361
  1265
    load_reg( R_ECX, Rn );
nkeynes@586
  1266
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1267
    check_walign32( R_EAX );
nkeynes@586
  1268
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1269
    load_reg( R_EDX, Rm );
nkeynes@586
  1270
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1271
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1272
:}
nkeynes@361
  1273
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1274
    COUNT_INST(I_MOVL);
nkeynes@586
  1275
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1276
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1277
    check_walign32( R_EAX );
nkeynes@586
  1278
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1279
    load_reg( R_EDX, 0 );
nkeynes@586
  1280
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1281
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1282
:}
nkeynes@361
  1283
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1284
    COUNT_INST(I_MOVL);
nkeynes@586
  1285
    load_reg( R_EAX, Rn );
nkeynes@586
  1286
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1287
    check_walign32( R_EAX );
nkeynes@586
  1288
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1289
    load_reg( R_EDX, Rm );
nkeynes@586
  1290
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1292
:}
nkeynes@361
  1293
MOV.L @Rm, Rn {:  
nkeynes@671
  1294
    COUNT_INST(I_MOVL);
nkeynes@586
  1295
    load_reg( R_EAX, Rm );
nkeynes@586
  1296
    check_ralign32( R_EAX );
nkeynes@586
  1297
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1298
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1299
    store_reg( R_EAX, Rn );
nkeynes@417
  1300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1301
:}
nkeynes@361
  1302
MOV.L @Rm+, Rn {:  
nkeynes@671
  1303
    COUNT_INST(I_MOVL);
nkeynes@361
  1304
    load_reg( R_EAX, Rm );
nkeynes@382
  1305
    check_ralign32( R_EAX );
nkeynes@586
  1306
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1307
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1308
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1309
    store_reg( R_EAX, Rn );
nkeynes@417
  1310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1311
:}
nkeynes@361
  1312
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1313
    COUNT_INST(I_MOVL);
nkeynes@361
  1314
    load_reg( R_EAX, 0 );
nkeynes@361
  1315
    load_reg( R_ECX, Rm );
nkeynes@586
  1316
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1317
    check_ralign32( R_EAX );
nkeynes@586
  1318
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1319
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1320
    store_reg( R_EAX, Rn );
nkeynes@417
  1321
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1322
:}
nkeynes@361
  1323
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1324
    COUNT_INST(I_MOVL);
nkeynes@586
  1325
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1326
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1327
    check_ralign32( R_EAX );
nkeynes@586
  1328
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1329
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1330
    store_reg( R_EAX, 0 );
nkeynes@417
  1331
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1332
:}
nkeynes@361
  1333
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1334
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1335
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1336
	SLOTILLEGAL();
nkeynes@374
  1337
    } else {
nkeynes@388
  1338
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1339
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1340
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1341
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1342
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1343
nkeynes@586
  1344
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1345
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1346
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1347
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1348
	    // behaviour though.
nkeynes@586
  1349
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1350
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1351
	} else {
nkeynes@586
  1352
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1353
	    // different virtual address than the translation was done with,
nkeynes@586
  1354
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1355
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1356
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1357
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1358
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1359
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1360
	}
nkeynes@382
  1361
	store_reg( R_EAX, Rn );
nkeynes@374
  1362
    }
nkeynes@361
  1363
:}
nkeynes@361
  1364
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1365
    COUNT_INST(I_MOVL);
nkeynes@586
  1366
    load_reg( R_EAX, Rm );
nkeynes@586
  1367
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1368
    check_ralign32( R_EAX );
nkeynes@586
  1369
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1370
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1371
    store_reg( R_EAX, Rn );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1373
:}
nkeynes@361
  1374
MOV.W Rm, @Rn {:  
nkeynes@671
  1375
    COUNT_INST(I_MOVW);
nkeynes@586
  1376
    load_reg( R_EAX, Rn );
nkeynes@586
  1377
    check_walign16( R_EAX );
nkeynes@586
  1378
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1379
    load_reg( R_EDX, Rm );
nkeynes@586
  1380
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1382
:}
nkeynes@361
  1383
MOV.W Rm, @-Rn {:  
nkeynes@671
  1384
    COUNT_INST(I_MOVW);
nkeynes@586
  1385
    load_reg( R_EAX, Rn );
nkeynes@586
  1386
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1387
    check_walign16( R_EAX );
nkeynes@586
  1388
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1389
    load_reg( R_EDX, Rm );
nkeynes@586
  1390
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1391
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1393
:}
nkeynes@361
  1394
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1395
    COUNT_INST(I_MOVW);
nkeynes@361
  1396
    load_reg( R_EAX, 0 );
nkeynes@361
  1397
    load_reg( R_ECX, Rn );
nkeynes@586
  1398
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1399
    check_walign16( R_EAX );
nkeynes@586
  1400
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1401
    load_reg( R_EDX, Rm );
nkeynes@586
  1402
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1404
:}
nkeynes@361
  1405
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1406
    COUNT_INST(I_MOVW);
nkeynes@586
  1407
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1408
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1409
    check_walign16( R_EAX );
nkeynes@586
  1410
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1411
    load_reg( R_EDX, 0 );
nkeynes@586
  1412
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1413
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1414
:}
nkeynes@361
  1415
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1416
    COUNT_INST(I_MOVW);
nkeynes@586
  1417
    load_reg( R_EAX, Rn );
nkeynes@586
  1418
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1419
    check_walign16( R_EAX );
nkeynes@586
  1420
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1421
    load_reg( R_EDX, 0 );
nkeynes@586
  1422
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1423
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1424
:}
nkeynes@361
  1425
MOV.W @Rm, Rn {:  
nkeynes@671
  1426
    COUNT_INST(I_MOVW);
nkeynes@586
  1427
    load_reg( R_EAX, Rm );
nkeynes@586
  1428
    check_ralign16( R_EAX );
nkeynes@586
  1429
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1430
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1431
    store_reg( R_EAX, Rn );
nkeynes@417
  1432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOV.W @Rm+, Rn {:  
nkeynes@671
  1435
    COUNT_INST(I_MOVW);
nkeynes@361
  1436
    load_reg( R_EAX, Rm );
nkeynes@374
  1437
    check_ralign16( R_EAX );
nkeynes@586
  1438
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1439
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1440
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1441
    store_reg( R_EAX, Rn );
nkeynes@417
  1442
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1443
:}
nkeynes@361
  1444
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1445
    COUNT_INST(I_MOVW);
nkeynes@361
  1446
    load_reg( R_EAX, 0 );
nkeynes@361
  1447
    load_reg( R_ECX, Rm );
nkeynes@586
  1448
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1449
    check_ralign16( R_EAX );
nkeynes@586
  1450
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1451
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1452
    store_reg( R_EAX, Rn );
nkeynes@417
  1453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1454
:}
nkeynes@361
  1455
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1456
    COUNT_INST(I_MOVW);
nkeynes@586
  1457
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1458
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1459
    check_ralign16( R_EAX );
nkeynes@586
  1460
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1461
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1462
    store_reg( R_EAX, 0 );
nkeynes@417
  1463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1464
:}
nkeynes@361
  1465
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1466
    COUNT_INST(I_MOVW);
nkeynes@374
  1467
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1468
	SLOTILLEGAL();
nkeynes@374
  1469
    } else {
nkeynes@586
  1470
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1471
	uint32_t target = pc + disp + 4;
nkeynes@586
  1472
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1473
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1474
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1475
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1476
	} else {
nkeynes@586
  1477
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1478
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1479
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1480
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1481
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1482
	}
nkeynes@374
  1483
	store_reg( R_EAX, Rn );
nkeynes@374
  1484
    }
nkeynes@361
  1485
:}
nkeynes@361
  1486
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1487
    COUNT_INST(I_MOVW);
nkeynes@586
  1488
    load_reg( R_EAX, Rm );
nkeynes@586
  1489
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1490
    check_ralign16( R_EAX );
nkeynes@586
  1491
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1492
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1493
    store_reg( R_EAX, 0 );
nkeynes@417
  1494
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1495
:}
nkeynes@361
  1496
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1497
    COUNT_INST(I_MOVA);
nkeynes@374
  1498
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1499
	SLOTILLEGAL();
nkeynes@374
  1500
    } else {
nkeynes@586
  1501
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1502
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1503
	store_reg( R_ECX, 0 );
nkeynes@586
  1504
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1505
    }
nkeynes@361
  1506
:}
nkeynes@361
  1507
MOVCA.L R0, @Rn {:  
nkeynes@671
  1508
    COUNT_INST(I_MOVCA);
nkeynes@586
  1509
    load_reg( R_EAX, Rn );
nkeynes@586
  1510
    check_walign32( R_EAX );
nkeynes@586
  1511
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1512
    load_reg( R_EDX, 0 );
nkeynes@586
  1513
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1514
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1515
:}
nkeynes@359
  1516
nkeynes@359
  1517
/* Control transfer instructions */
nkeynes@374
  1518
BF disp {:
nkeynes@671
  1519
    COUNT_INST(I_BF);
nkeynes@374
  1520
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1521
	SLOTILLEGAL();
nkeynes@374
  1522
    } else {
nkeynes@586
  1523
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1524
	JT_rel8( nottaken );
nkeynes@586
  1525
	exit_block_rel(target, pc+2 );
nkeynes@380
  1526
	JMP_TARGET(nottaken);
nkeynes@408
  1527
	return 2;
nkeynes@374
  1528
    }
nkeynes@374
  1529
:}
nkeynes@374
  1530
BF/S disp {:
nkeynes@671
  1531
    COUNT_INST(I_BFS);
nkeynes@374
  1532
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1533
	SLOTILLEGAL();
nkeynes@374
  1534
    } else {
nkeynes@590
  1535
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1536
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1537
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1538
	    JT_rel8(nottaken);
nkeynes@601
  1539
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1540
	    JMP_TARGET(nottaken);
nkeynes@601
  1541
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1542
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1543
	    exit_block_emu(pc+2);
nkeynes@601
  1544
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1545
	    return 2;
nkeynes@601
  1546
	} else {
nkeynes@601
  1547
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1548
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1549
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1550
	    }
nkeynes@601
  1551
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1552
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1553
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1554
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1555
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1556
	    
nkeynes@601
  1557
	    // not taken
nkeynes@601
  1558
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1559
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1560
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1561
	    return 4;
nkeynes@417
  1562
	}
nkeynes@374
  1563
    }
nkeynes@374
  1564
:}
nkeynes@374
  1565
BRA disp {:  
nkeynes@671
  1566
    COUNT_INST(I_BRA);
nkeynes@374
  1567
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1568
	SLOTILLEGAL();
nkeynes@374
  1569
    } else {
nkeynes@590
  1570
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1571
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1572
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1573
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1574
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1575
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1576
	    exit_block_emu(pc+2);
nkeynes@601
  1577
	    return 2;
nkeynes@601
  1578
	} else {
nkeynes@601
  1579
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1580
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1581
	    return 4;
nkeynes@601
  1582
	}
nkeynes@374
  1583
    }
nkeynes@374
  1584
:}
nkeynes@374
  1585
BRAF Rn {:  
nkeynes@671
  1586
    COUNT_INST(I_BRAF);
nkeynes@374
  1587
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1588
	SLOTILLEGAL();
nkeynes@374
  1589
    } else {
nkeynes@590
  1590
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1591
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1592
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1593
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1594
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1595
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1596
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1597
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1598
	    exit_block_emu(pc+2);
nkeynes@601
  1599
	    return 2;
nkeynes@601
  1600
	} else {
nkeynes@601
  1601
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1602
	    exit_block_newpcset(pc+2);
nkeynes@601
  1603
	    return 4;
nkeynes@601
  1604
	}
nkeynes@374
  1605
    }
nkeynes@374
  1606
:}
nkeynes@374
  1607
BSR disp {:  
nkeynes@671
  1608
    COUNT_INST(I_BSR);
nkeynes@374
  1609
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1610
	SLOTILLEGAL();
nkeynes@374
  1611
    } else {
nkeynes@590
  1612
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1613
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1614
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1615
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1616
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1617
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1618
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1619
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1620
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1621
	    exit_block_emu(pc+2);
nkeynes@601
  1622
	    return 2;
nkeynes@601
  1623
	} else {
nkeynes@601
  1624
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1625
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1626
	    return 4;
nkeynes@601
  1627
	}
nkeynes@374
  1628
    }
nkeynes@374
  1629
:}
nkeynes@374
  1630
BSRF Rn {:  
nkeynes@671
  1631
    COUNT_INST(I_BSRF);
nkeynes@374
  1632
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1633
	SLOTILLEGAL();
nkeynes@374
  1634
    } else {
nkeynes@590
  1635
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1636
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1637
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1638
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1639
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1640
nkeynes@601
  1641
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1642
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1643
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1644
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1645
	    exit_block_emu(pc+2);
nkeynes@601
  1646
	    return 2;
nkeynes@601
  1647
	} else {
nkeynes@601
  1648
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1649
	    exit_block_newpcset(pc+2);
nkeynes@601
  1650
	    return 4;
nkeynes@601
  1651
	}
nkeynes@374
  1652
    }
nkeynes@374
  1653
:}
nkeynes@374
  1654
BT disp {:
nkeynes@671
  1655
    COUNT_INST(I_BT);
nkeynes@374
  1656
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1657
	SLOTILLEGAL();
nkeynes@374
  1658
    } else {
nkeynes@586
  1659
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1660
	JF_rel8( nottaken );
nkeynes@586
  1661
	exit_block_rel(target, pc+2 );
nkeynes@380
  1662
	JMP_TARGET(nottaken);
nkeynes@408
  1663
	return 2;
nkeynes@374
  1664
    }
nkeynes@374
  1665
:}
nkeynes@374
  1666
BT/S disp {:
nkeynes@671
  1667
    COUNT_INST(I_BTS);
nkeynes@374
  1668
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1669
	SLOTILLEGAL();
nkeynes@374
  1670
    } else {
nkeynes@590
  1671
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1672
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1673
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1674
	    JF_rel8(nottaken);
nkeynes@601
  1675
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1676
	    JMP_TARGET(nottaken);
nkeynes@601
  1677
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1678
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1679
	    exit_block_emu(pc+2);
nkeynes@601
  1680
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1681
	    return 2;
nkeynes@601
  1682
	} else {
nkeynes@601
  1683
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1684
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1685
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1686
	    }
nkeynes@601
  1687
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1688
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1689
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1690
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1691
	    // not taken
nkeynes@601
  1692
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1693
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1694
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1695
	    return 4;
nkeynes@417
  1696
	}
nkeynes@374
  1697
    }
nkeynes@374
  1698
:}
nkeynes@374
  1699
JMP @Rn {:  
nkeynes@671
  1700
    COUNT_INST(I_JMP);
nkeynes@374
  1701
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1702
	SLOTILLEGAL();
nkeynes@374
  1703
    } else {
nkeynes@408
  1704
	load_reg( R_ECX, Rn );
nkeynes@590
  1705
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1706
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1707
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1708
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1709
	    exit_block_emu(pc+2);
nkeynes@601
  1710
	    return 2;
nkeynes@601
  1711
	} else {
nkeynes@601
  1712
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1713
	    exit_block_newpcset(pc+2);
nkeynes@601
  1714
	    return 4;
nkeynes@601
  1715
	}
nkeynes@374
  1716
    }
nkeynes@374
  1717
:}
nkeynes@374
  1718
JSR @Rn {:  
nkeynes@671
  1719
    COUNT_INST(I_JSR);
nkeynes@374
  1720
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1721
	SLOTILLEGAL();
nkeynes@374
  1722
    } else {
nkeynes@590
  1723
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1724
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1725
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1726
	load_reg( R_ECX, Rn );
nkeynes@590
  1727
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1728
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1729
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1730
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1731
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1732
	    exit_block_emu(pc+2);
nkeynes@601
  1733
	    return 2;
nkeynes@601
  1734
	} else {
nkeynes@601
  1735
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1736
	    exit_block_newpcset(pc+2);
nkeynes@601
  1737
	    return 4;
nkeynes@601
  1738
	}
nkeynes@374
  1739
    }
nkeynes@374
  1740
:}
nkeynes@374
  1741
RTE {:  
nkeynes@671
  1742
    COUNT_INST(I_RTE);
nkeynes@374
  1743
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1744
	SLOTILLEGAL();
nkeynes@374
  1745
    } else {
nkeynes@408
  1746
	check_priv();
nkeynes@408
  1747
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1748
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1749
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1750
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1751
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1752
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1753
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1754
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1755
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1756
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1757
	    exit_block_emu(pc+2);
nkeynes@601
  1758
	    return 2;
nkeynes@601
  1759
	} else {
nkeynes@601
  1760
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1761
	    exit_block_newpcset(pc+2);
nkeynes@601
  1762
	    return 4;
nkeynes@601
  1763
	}
nkeynes@374
  1764
    }
nkeynes@374
  1765
:}
nkeynes@374
  1766
RTS {:  
nkeynes@671
  1767
    COUNT_INST(I_RTS);
nkeynes@374
  1768
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1769
	SLOTILLEGAL();
nkeynes@374
  1770
    } else {
nkeynes@408
  1771
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1772
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1773
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1774
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1775
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1776
	    exit_block_emu(pc+2);
nkeynes@601
  1777
	    return 2;
nkeynes@601
  1778
	} else {
nkeynes@601
  1779
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1780
	    exit_block_newpcset(pc+2);
nkeynes@601
  1781
	    return 4;
nkeynes@601
  1782
	}
nkeynes@374
  1783
    }
nkeynes@374
  1784
:}
nkeynes@374
  1785
TRAPA #imm {:  
nkeynes@671
  1786
    COUNT_INST(I_TRAPA);
nkeynes@374
  1787
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1788
	SLOTILLEGAL();
nkeynes@374
  1789
    } else {
nkeynes@590
  1790
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1791
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1792
	load_imm32( R_EAX, imm );
nkeynes@527
  1793
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1794
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1795
	exit_block_pcset(pc);
nkeynes@409
  1796
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1797
	return 2;
nkeynes@374
  1798
    }
nkeynes@374
  1799
:}
nkeynes@374
  1800
UNDEF {:  
nkeynes@671
  1801
    COUNT_INST(I_UNDEF);
nkeynes@374
  1802
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1803
	SLOTILLEGAL();
nkeynes@374
  1804
    } else {
nkeynes@586
  1805
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1806
	return 2;
nkeynes@374
  1807
    }
nkeynes@368
  1808
:}
nkeynes@374
  1809
nkeynes@374
  1810
CLRMAC {:  
nkeynes@671
  1811
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1812
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1813
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1814
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1815
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1816
:}
nkeynes@374
  1817
CLRS {:
nkeynes@671
  1818
    COUNT_INST(I_CLRS);
nkeynes@374
  1819
    CLC();
nkeynes@374
  1820
    SETC_sh4r(R_S);
nkeynes@872
  1821
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1822
:}
nkeynes@374
  1823
CLRT {:  
nkeynes@671
  1824
    COUNT_INST(I_CLRT);
nkeynes@374
  1825
    CLC();
nkeynes@374
  1826
    SETC_t();
nkeynes@417
  1827
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1828
:}
nkeynes@374
  1829
SETS {:  
nkeynes@671
  1830
    COUNT_INST(I_SETS);
nkeynes@374
  1831
    STC();
nkeynes@374
  1832
    SETC_sh4r(R_S);
nkeynes@872
  1833
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1834
:}
nkeynes@374
  1835
SETT {:  
nkeynes@671
  1836
    COUNT_INST(I_SETT);
nkeynes@374
  1837
    STC();
nkeynes@374
  1838
    SETC_t();
nkeynes@417
  1839
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1840
:}
nkeynes@359
  1841
nkeynes@375
  1842
/* Floating point moves */
nkeynes@375
  1843
FMOV FRm, FRn {:  
nkeynes@671
  1844
    COUNT_INST(I_FMOV1);
nkeynes@377
  1845
    check_fpuen();
nkeynes@901
  1846
    if( sh4_x86.double_size ) {
nkeynes@901
  1847
        load_dr0( R_EAX, FRm );
nkeynes@901
  1848
        load_dr1( R_ECX, FRm );
nkeynes@901
  1849
        store_dr0( R_EAX, FRn );
nkeynes@901
  1850
        store_dr1( R_ECX, FRn );
nkeynes@901
  1851
    } else {
nkeynes@901
  1852
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1853
        store_fr( R_EAX, FRn );
nkeynes@901
  1854
    }
nkeynes@375
  1855
:}
nkeynes@416
  1856
FMOV FRm, @Rn {: 
nkeynes@671
  1857
    COUNT_INST(I_FMOV2);
nkeynes@586
  1858
    check_fpuen();
nkeynes@586
  1859
    load_reg( R_EAX, Rn );
nkeynes@901
  1860
    if( sh4_x86.double_size ) {
nkeynes@901
  1861
        check_walign64( R_EAX );
nkeynes@901
  1862
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1863
        load_dr0( R_EDX, FRm );
nkeynes@905
  1864
        load_dr1( R_ECX, FRm );
nkeynes@905
  1865
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1866
    } else {
nkeynes@901
  1867
        check_walign32( R_EAX );
nkeynes@901
  1868
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1869
        load_fr( R_EDX, FRm );
nkeynes@905
  1870
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1871
    }
nkeynes@417
  1872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1873
:}
nkeynes@375
  1874
FMOV @Rm, FRn {:  
nkeynes@671
  1875
    COUNT_INST(I_FMOV5);
nkeynes@586
  1876
    check_fpuen();
nkeynes@586
  1877
    load_reg( R_EAX, Rm );
nkeynes@901
  1878
    if( sh4_x86.double_size ) {
nkeynes@901
  1879
        check_ralign64( R_EAX );
nkeynes@901
  1880
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@905
  1881
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1882
        store_dr0( R_EDX, FRn );
nkeynes@901
  1883
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1884
    } else {
nkeynes@901
  1885
        check_ralign32( R_EAX );
nkeynes@901
  1886
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1887
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1888
        store_fr( R_EAX, FRn );
nkeynes@901
  1889
    }
nkeynes@417
  1890
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1891
:}
nkeynes@377
  1892
FMOV FRm, @-Rn {:  
nkeynes@671
  1893
    COUNT_INST(I_FMOV3);
nkeynes@586
  1894
    check_fpuen();
nkeynes@586
  1895
    load_reg( R_EAX, Rn );
nkeynes@901
  1896
    if( sh4_x86.double_size ) {
nkeynes@901
  1897
        check_walign64( R_EAX );
nkeynes@901
  1898
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1899
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1900
        load_dr0( R_EDX, FRm );
nkeynes@905
  1901
        load_dr1( R_ECX, FRm );
nkeynes@901
  1902
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@905
  1903
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1904
    } else {
nkeynes@901
  1905
        check_walign32( R_EAX );
nkeynes@901
  1906
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1907
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1908
        load_fr( R_EDX, FRm );
nkeynes@901
  1909
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@905
  1910
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1911
    }
nkeynes@417
  1912
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1913
:}
nkeynes@416
  1914
FMOV @Rm+, FRn {:
nkeynes@671
  1915
    COUNT_INST(I_FMOV6);
nkeynes@586
  1916
    check_fpuen();
nkeynes@586
  1917
    load_reg( R_EAX, Rm );
nkeynes@901
  1918
    if( sh4_x86.double_size ) {
nkeynes@901
  1919
        check_ralign64( R_EAX );
nkeynes@901
  1920
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1921
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@905
  1922
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1923
        store_dr0( R_EDX, FRn );
nkeynes@901
  1924
        store_dr1( R_EAX, FRn );
nkeynes@901
  1925
    } else {
nkeynes@901
  1926
        check_ralign32( R_EAX );
nkeynes@901
  1927
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1928
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1929
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1930
        store_fr( R_EAX, FRn );
nkeynes@901
  1931
    }
nkeynes@417
  1932
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1933
:}
nkeynes@377
  1934
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1935
    COUNT_INST(I_FMOV4);
nkeynes@586
  1936
    check_fpuen();
nkeynes@586
  1937
    load_reg( R_EAX, Rn );
nkeynes@586
  1938
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1939
    if( sh4_x86.double_size ) {
nkeynes@901
  1940
        check_walign64( R_EAX );
nkeynes@901
  1941
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1942
        load_dr0( R_EDX, FRm );
nkeynes@905
  1943
        load_dr1( R_ECX, FRm );
nkeynes@905
  1944
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1945
    } else {
nkeynes@901
  1946
        check_walign32( R_EAX );
nkeynes@901
  1947
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1948
        load_fr( R_EDX, FRm );
nkeynes@905
  1949
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1950
    }
nkeynes@417
  1951
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1952
:}
nkeynes@377
  1953
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1954
    COUNT_INST(I_FMOV7);
nkeynes@586
  1955
    check_fpuen();
nkeynes@586
  1956
    load_reg( R_EAX, Rm );
nkeynes@586
  1957
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1958
    if( sh4_x86.double_size ) {
nkeynes@901
  1959
        check_ralign64( R_EAX );
nkeynes@901
  1960
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1961
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1962
        store_dr0( R_ECX, FRn );
nkeynes@901
  1963
        store_dr1( R_EAX, FRn );
nkeynes@901
  1964
    } else {
nkeynes@901
  1965
        check_ralign32( R_EAX );
nkeynes@901
  1966
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1967
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1968
        store_fr( R_EAX, FRn );
nkeynes@901
  1969
    }
nkeynes@417
  1970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1971
:}
nkeynes@377
  1972
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1973
    COUNT_INST(I_FLDI0);
nkeynes@377
  1974
    check_fpuen();
nkeynes@901
  1975
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1976
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1977
        store_fr( R_EAX, FRn );
nkeynes@901
  1978
    }
nkeynes@417
  1979
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1980
:}
nkeynes@377
  1981
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1982
    COUNT_INST(I_FLDI1);
nkeynes@377
  1983
    check_fpuen();
nkeynes@901
  1984
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1985
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1986
        store_fr( R_EAX, FRn );
nkeynes@901
  1987
    }
nkeynes@377
  1988
:}
nkeynes@377
  1989
nkeynes@377
  1990
FLOAT FPUL, FRn {:  
nkeynes@671
  1991
    COUNT_INST(I_FLOAT);
nkeynes@377
  1992
    check_fpuen();
nkeynes@377
  1993
    FILD_sh4r(R_FPUL);
nkeynes@901
  1994
    if( sh4_x86.double_prec ) {
nkeynes@901
  1995
        pop_dr( FRn );
nkeynes@901
  1996
    } else {
nkeynes@901
  1997
        pop_fr( FRn );
nkeynes@901
  1998
    }
nkeynes@377
  1999
:}
nkeynes@377
  2000
FTRC FRm, FPUL {:  
nkeynes@671
  2001
    COUNT_INST(I_FTRC);
nkeynes@377
  2002
    check_fpuen();
nkeynes@901
  2003
    if( sh4_x86.double_prec ) {
nkeynes@901
  2004
        push_dr( FRm );
nkeynes@901
  2005
    } else {
nkeynes@901
  2006
        push_fr( FRm );
nkeynes@901
  2007
    }
nkeynes@789
  2008
    load_ptr( R_ECX, &max_int );
nkeynes@388
  2009
    FILD_r32ind( R_ECX );
nkeynes@388
  2010
    FCOMIP_st(1);
nkeynes@669
  2011
    JNA_rel8( sat );
nkeynes@789
  2012
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2013
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2014
    FCOMIP_st(1);                   // 2
nkeynes@669
  2015
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2016
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2017
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2018
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2019
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2020
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2021
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2022
    JMP_rel8(end);             // 2
nkeynes@388
  2023
nkeynes@388
  2024
    JMP_TARGET(sat);
nkeynes@388
  2025
    JMP_TARGET(sat2);
nkeynes@388
  2026
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2027
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2028
    FPOP_st();
nkeynes@388
  2029
    JMP_TARGET(end);
nkeynes@417
  2030
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2031
:}
nkeynes@377
  2032
FLDS FRm, FPUL {:  
nkeynes@671
  2033
    COUNT_INST(I_FLDS);
nkeynes@377
  2034
    check_fpuen();
nkeynes@669
  2035
    load_fr( R_EAX, FRm );
nkeynes@377
  2036
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2037
:}
nkeynes@377
  2038
FSTS FPUL, FRn {:  
nkeynes@671
  2039
    COUNT_INST(I_FSTS);
nkeynes@377
  2040
    check_fpuen();
nkeynes@377
  2041
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2042
    store_fr( R_EAX, FRn );
nkeynes@377
  2043
:}
nkeynes@377
  2044
FCNVDS FRm, FPUL {:  
nkeynes@671
  2045
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2046
    check_fpuen();
nkeynes@901
  2047
    if( sh4_x86.double_prec ) {
nkeynes@901
  2048
        push_dr( FRm );
nkeynes@901
  2049
        pop_fpul();
nkeynes@901
  2050
    }
nkeynes@377
  2051
:}
nkeynes@377
  2052
FCNVSD FPUL, FRn {:  
nkeynes@671
  2053
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2054
    check_fpuen();
nkeynes@901
  2055
    if( sh4_x86.double_prec ) {
nkeynes@901
  2056
        push_fpul();
nkeynes@901
  2057
        pop_dr( FRn );
nkeynes@901
  2058
    }
nkeynes@377
  2059
:}
nkeynes@375
  2060
nkeynes@359
  2061
/* Floating point instructions */
nkeynes@374
  2062
FABS FRn {:  
nkeynes@671
  2063
    COUNT_INST(I_FABS);
nkeynes@377
  2064
    check_fpuen();
nkeynes@901
  2065
    if( sh4_x86.double_prec ) {
nkeynes@901
  2066
        push_dr(FRn);
nkeynes@901
  2067
        FABS_st0();
nkeynes@901
  2068
        pop_dr(FRn);
nkeynes@901
  2069
    } else {
nkeynes@901
  2070
        push_fr(FRn);
nkeynes@901
  2071
        FABS_st0();
nkeynes@901
  2072
        pop_fr(FRn);
nkeynes@901
  2073
    }
nkeynes@374
  2074
:}
nkeynes@377
  2075
FADD FRm, FRn {:  
nkeynes@671
  2076
    COUNT_INST(I_FADD);
nkeynes@377
  2077
    check_fpuen();
nkeynes@901
  2078
    if( sh4_x86.double_prec ) {
nkeynes@901
  2079
        push_dr(FRm);
nkeynes@901
  2080
        push_dr(FRn);
nkeynes@901
  2081
        FADDP_st(1);
nkeynes@901
  2082
        pop_dr(FRn);
nkeynes@901
  2083
    } else {
nkeynes@901
  2084
        push_fr(FRm);
nkeynes@901
  2085
        push_fr(FRn);
nkeynes@901
  2086
        FADDP_st(1);
nkeynes@901
  2087
        pop_fr(FRn);
nkeynes@901
  2088
    }
nkeynes@375
  2089
:}
nkeynes@377
  2090
FDIV FRm, FRn {:  
nkeynes@671
  2091
    COUNT_INST(I_FDIV);
nkeynes@377
  2092
    check_fpuen();
nkeynes@901
  2093
    if( sh4_x86.double_prec ) {
nkeynes@901
  2094
        push_dr(FRn);
nkeynes@901
  2095
        push_dr(FRm);
nkeynes@901
  2096
        FDIVP_st(1);
nkeynes@901
  2097
        pop_dr(FRn);
nkeynes@901
  2098
    } else {
nkeynes@901
  2099
        push_fr(FRn);
nkeynes@901
  2100
        push_fr(FRm);
nkeynes@901
  2101
        FDIVP_st(1);
nkeynes@901
  2102
        pop_fr(FRn);
nkeynes@901
  2103
    }
nkeynes@375
  2104
:}
nkeynes@375
  2105
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2106
    COUNT_INST(I_FMAC);
nkeynes@377
  2107
    check_fpuen();
nkeynes@901
  2108
    if( sh4_x86.double_prec ) {
nkeynes@901
  2109
        push_dr( 0 );
nkeynes@901
  2110
        push_dr( FRm );
nkeynes@901
  2111
        FMULP_st(1);
nkeynes@901
  2112
        push_dr( FRn );
nkeynes@901
  2113
        FADDP_st(1);
nkeynes@901
  2114
        pop_dr( FRn );
nkeynes@901
  2115
    } else {
nkeynes@901
  2116
        push_fr( 0 );
nkeynes@901
  2117
        push_fr( FRm );
nkeynes@901
  2118
        FMULP_st(1);
nkeynes@901
  2119
        push_fr( FRn );
nkeynes@901
  2120
        FADDP_st(1);
nkeynes@901
  2121
        pop_fr( FRn );
nkeynes@901
  2122
    }
nkeynes@375
  2123
:}
nkeynes@375
  2124
nkeynes@377
  2125
FMUL FRm, FRn {:  
nkeynes@671
  2126
    COUNT_INST(I_FMUL);
nkeynes@377
  2127
    check_fpuen();
nkeynes@901
  2128
    if( sh4_x86.double_prec ) {
nkeynes@901
  2129
        push_dr(FRm);
nkeynes@901
  2130
        push_dr(FRn);
nkeynes@901
  2131
        FMULP_st(1);
nkeynes@901
  2132
        pop_dr(FRn);
nkeynes@901
  2133
    } else {
nkeynes@901
  2134
        push_fr(FRm);
nkeynes@901
  2135
        push_fr(FRn);
nkeynes@901
  2136
        FMULP_st(1);
nkeynes@901
  2137
        pop_fr(FRn);
nkeynes@901
  2138
    }
nkeynes@377
  2139
:}
nkeynes@377
  2140
FNEG FRn {:  
nkeynes@671
  2141
    COUNT_INST(I_FNEG);
nkeynes@377
  2142
    check_fpuen();
nkeynes@901
  2143
    if( sh4_x86.double_prec ) {
nkeynes@901
  2144
        push_dr(FRn);
nkeynes@901
  2145
        FCHS_st0();
nkeynes@901
  2146
        pop_dr(FRn);
nkeynes@901
  2147
    } else {
nkeynes@901
  2148
        push_fr(FRn);
nkeynes@901
  2149
        FCHS_st0();
nkeynes@901
  2150
        pop_fr(FRn);
nkeynes@901
  2151
    }
nkeynes@377
  2152
:}
nkeynes@377
  2153
FSRRA FRn {:  
nkeynes@671
  2154
    COUNT_INST(I_FSRRA);
nkeynes@377
  2155
    check_fpuen();
nkeynes@901
  2156
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2157
        FLD1_st0();
nkeynes@901
  2158
        push_fr(FRn);
nkeynes@901
  2159
        FSQRT_st0();
nkeynes@901
  2160
        FDIVP_st(1);
nkeynes@901
  2161
        pop_fr(FRn);
nkeynes@901
  2162
    }
nkeynes@377
  2163
:}
nkeynes@377
  2164
FSQRT FRn {:  
nkeynes@671
  2165
    COUNT_INST(I_FSQRT);
nkeynes@377
  2166
    check_fpuen();
nkeynes@901
  2167
    if( sh4_x86.double_prec ) {
nkeynes@901
  2168
        push_dr(FRn);
nkeynes@901
  2169
        FSQRT_st0();
nkeynes@901
  2170
        pop_dr(FRn);
nkeynes@901
  2171
    } else {
nkeynes@901
  2172
        push_fr(FRn);
nkeynes@901
  2173
        FSQRT_st0();
nkeynes@901
  2174
        pop_fr(FRn);
nkeynes@901
  2175
    }
nkeynes@377
  2176
:}
nkeynes@377
  2177
FSUB FRm, FRn {:  
nkeynes@671
  2178
    COUNT_INST(I_FSUB);
nkeynes@377
  2179
    check_fpuen();
nkeynes@901
  2180
    if( sh4_x86.double_prec ) {
nkeynes@901
  2181
        push_dr(FRn);
nkeynes@901
  2182
        push_dr(FRm);
nkeynes@901
  2183
        FSUBP_st(1);
nkeynes@901
  2184
        pop_dr(FRn);
nkeynes@901
  2185
    } else {
nkeynes@901
  2186
        push_fr(FRn);
nkeynes@901
  2187
        push_fr(FRm);
nkeynes@901
  2188
        FSUBP_st(1);
nkeynes@901
  2189
        pop_fr(FRn);
nkeynes@901
  2190
    }
nkeynes@377
  2191
:}
nkeynes@377
  2192
nkeynes@377
  2193
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2194
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2195
    check_fpuen();
nkeynes@901
  2196
    if( sh4_x86.double_prec ) {
nkeynes@901
  2197
        push_dr(FRm);
nkeynes@901
  2198
        push_dr(FRn);
nkeynes@901
  2199
    } else {
nkeynes@901
  2200
        push_fr(FRm);
nkeynes@901
  2201
        push_fr(FRn);
nkeynes@901
  2202
    }
nkeynes@377
  2203
    FCOMIP_st(1);
nkeynes@377
  2204
    SETE_t();
nkeynes@377
  2205
    FPOP_st();
nkeynes@901
  2206
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2207
:}
nkeynes@377
  2208
FCMP/GT FRm, FRn {:  
nkeynes@671
  2209
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2210
    check_fpuen();
nkeynes@901
  2211
    if( sh4_x86.double_prec ) {
nkeynes@901
  2212
        push_dr(FRm);
nkeynes@901
  2213
        push_dr(FRn);
nkeynes@901
  2214
    } else {
nkeynes@901
  2215
        push_fr(FRm);
nkeynes@901
  2216
        push_fr(FRn);
nkeynes@901
  2217
    }
nkeynes@377
  2218
    FCOMIP_st(1);
nkeynes@377
  2219
    SETA_t();
nkeynes@377
  2220
    FPOP_st();
nkeynes@901
  2221
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2222
:}
nkeynes@377
  2223
nkeynes@377
  2224
FSCA FPUL, FRn {:  
nkeynes@671
  2225
    COUNT_INST(I_FSCA);
nkeynes@377
  2226
    check_fpuen();
nkeynes@901
  2227
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2228
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2229
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2230
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2231
    }
nkeynes@417
  2232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2233
:}
nkeynes@377
  2234
FIPR FVm, FVn {:  
nkeynes@671
  2235
    COUNT_INST(I_FIPR);
nkeynes@377
  2236
    check_fpuen();
nkeynes@901
  2237
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2238
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2239
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2240
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2241
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2242
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2243
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2244
        } else {
nkeynes@904
  2245
            push_fr( FVm<<2 );
nkeynes@903
  2246
            push_fr( FVn<<2 );
nkeynes@903
  2247
            FMULP_st(1);
nkeynes@903
  2248
            push_fr( (FVm<<2)+1);
nkeynes@903
  2249
            push_fr( (FVn<<2)+1);
nkeynes@903
  2250
            FMULP_st(1);
nkeynes@903
  2251
            FADDP_st(1);
nkeynes@903
  2252
            push_fr( (FVm<<2)+2);
nkeynes@903
  2253
            push_fr( (FVn<<2)+2);
nkeynes@903
  2254
            FMULP_st(1);
nkeynes@903
  2255
            FADDP_st(1);
nkeynes@903
  2256
            push_fr( (FVm<<2)+3);
nkeynes@903
  2257
            push_fr( (FVn<<2)+3);
nkeynes@903
  2258
            FMULP_st(1);
nkeynes@903
  2259
            FADDP_st(1);
nkeynes@903
  2260
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2261
        }
nkeynes@901
  2262
    }
nkeynes@377
  2263
:}
nkeynes@377
  2264
FTRV XMTRX, FVn {:  
nkeynes@671
  2265
    COUNT_INST(I_FTRV);
nkeynes@377
  2266
    check_fpuen();
nkeynes@901
  2267
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2268
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2269
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2270
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2271
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2272
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2273
nkeynes@903
  2274
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2275
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2276
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2277
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2278
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2279
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2280
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2281
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2282
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2283
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2284
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2285
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2286
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2287
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2288
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2289
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2290
        } else {
nkeynes@903
  2291
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2292
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2293
        }
nkeynes@901
  2294
    }
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2296
:}
nkeynes@377
  2297
nkeynes@377
  2298
FRCHG {:  
nkeynes@671
  2299
    COUNT_INST(I_FRCHG);
nkeynes@377
  2300
    check_fpuen();
nkeynes@377
  2301
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2302
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2303
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2304
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2305
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2306
:}
nkeynes@377
  2307
FSCHG {:  
nkeynes@671
  2308
    COUNT_INST(I_FSCHG);
nkeynes@377
  2309
    check_fpuen();
nkeynes@377
  2310
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2311
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2312
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2314
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2315
:}
nkeynes@359
  2316
nkeynes@359
  2317
/* Processor control instructions */
nkeynes@368
  2318
LDC Rm, SR {:
nkeynes@671
  2319
    COUNT_INST(I_LDCSR);
nkeynes@386
  2320
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2321
	SLOTILLEGAL();
nkeynes@386
  2322
    } else {
nkeynes@386
  2323
	check_priv();
nkeynes@386
  2324
	load_reg( R_EAX, Rm );
nkeynes@386
  2325
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2326
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2327
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2328
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2329
    }
nkeynes@368
  2330
:}
nkeynes@359
  2331
LDC Rm, GBR {: 
nkeynes@671
  2332
    COUNT_INST(I_LDC);
nkeynes@359
  2333
    load_reg( R_EAX, Rm );
nkeynes@359
  2334
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2335
:}
nkeynes@359
  2336
LDC Rm, VBR {:  
nkeynes@671
  2337
    COUNT_INST(I_LDC);
nkeynes@386
  2338
    check_priv();
nkeynes@359
  2339
    load_reg( R_EAX, Rm );
nkeynes@359
  2340
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2342
:}
nkeynes@359
  2343
LDC Rm, SSR {:  
nkeynes@671
  2344
    COUNT_INST(I_LDC);
nkeynes@386
  2345
    check_priv();
nkeynes@359
  2346
    load_reg( R_EAX, Rm );
nkeynes@359
  2347
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2348
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2349
:}
nkeynes@359
  2350
LDC Rm, SGR {:  
nkeynes@671
  2351
    COUNT_INST(I_LDC);
nkeynes@386
  2352
    check_priv();
nkeynes@359
  2353
    load_reg( R_EAX, Rm );
nkeynes@359
  2354
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2356
:}
nkeynes@359
  2357
LDC Rm, SPC {:  
nkeynes@671
  2358
    COUNT_INST(I_LDC);
nkeynes@386
  2359
    check_priv();
nkeynes@359
  2360
    load_reg( R_EAX, Rm );
nkeynes@359
  2361
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2363
:}
nkeynes@359
  2364
LDC Rm, DBR {:  
nkeynes@671
  2365
    COUNT_INST(I_LDC);
nkeynes@386
  2366
    check_priv();
nkeynes@359
  2367
    load_reg( R_EAX, Rm );
nkeynes@359
  2368
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2370
:}
nkeynes@374
  2371
LDC Rm, Rn_BANK {:  
nkeynes@671
  2372
    COUNT_INST(I_LDC);
nkeynes@386
  2373
    check_priv();
nkeynes@374
  2374
    load_reg( R_EAX, Rm );
nkeynes@374
  2375
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2377
:}
nkeynes@359
  2378
LDC.L @Rm+, GBR {:  
nkeynes@671
  2379
    COUNT_INST(I_LDCM);
nkeynes@359
  2380
    load_reg( R_EAX, Rm );
nkeynes@395
  2381
    check_ralign32( R_EAX );
nkeynes@586
  2382
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2383
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2384
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2385
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
:}
nkeynes@368
  2388
LDC.L @Rm+, SR {:
nkeynes@671
  2389
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2390
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2391
	SLOTILLEGAL();
nkeynes@386
  2392
    } else {
nkeynes@586
  2393
	check_priv();
nkeynes@386
  2394
	load_reg( R_EAX, Rm );
nkeynes@395
  2395
	check_ralign32( R_EAX );
nkeynes@586
  2396
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2397
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2398
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2399
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2400
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2401
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2402
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2403
    }
nkeynes@359
  2404
:}
nkeynes@359
  2405
LDC.L @Rm+, VBR {:  
nkeynes@671
  2406
    COUNT_INST(I_LDCM);
nkeynes@586
  2407
    check_priv();
nkeynes@359
  2408
    load_reg( R_EAX, Rm );
nkeynes@395
  2409
    check_ralign32( R_EAX );
nkeynes@586
  2410
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2411
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2412
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2413
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2415
:}
nkeynes@359
  2416
LDC.L @Rm+, SSR {:
nkeynes@671
  2417
    COUNT_INST(I_LDCM);
nkeynes@586
  2418
    check_priv();
nkeynes@359
  2419
    load_reg( R_EAX, Rm );
nkeynes@416
  2420
    check_ralign32( R_EAX );
nkeynes@586
  2421
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2422
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2423
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2424
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2425
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2426
:}
nkeynes@359
  2427
LDC.L @Rm+, SGR {:  
nkeynes@671
  2428
    COUNT_INST(I_LDCM);
nkeynes@586
  2429
    check_priv();
nkeynes@359
  2430
    load_reg( R_EAX, Rm );
nkeynes@395
  2431
    check_ralign32( R_EAX );
nkeynes@586
  2432
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2433
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2434
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2435
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2437
:}
nkeynes@359
  2438
LDC.L @Rm+, SPC {:  
nkeynes@671
  2439
    COUNT_INST(I_LDCM);
nkeynes@586
  2440
    check_priv();
nkeynes@359
  2441
    load_reg( R_EAX, Rm );
nkeynes@395
  2442
    check_ralign32( R_EAX );
nkeynes@586
  2443
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2444
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2445
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2446
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2448
:}
nkeynes@359
  2449
LDC.L @Rm+, DBR {:  
nkeynes@671
  2450
    COUNT_INST(I_LDCM);
nkeynes@586
  2451
    check_priv();
nkeynes@359
  2452
    load_reg( R_EAX, Rm );
nkeynes@395
  2453
    check_ralign32( R_EAX );
nkeynes@586
  2454
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2455
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2456
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2457
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2458
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2459
:}
nkeynes@359
  2460
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2461
    COUNT_INST(I_LDCM);
nkeynes@586
  2462
    check_priv();
nkeynes@374
  2463
    load_reg( R_EAX, Rm );
nkeynes@395
  2464
    check_ralign32( R_EAX );
nkeynes@586
  2465
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2466
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2467
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2468
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2469
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2470
:}
nkeynes@626
  2471
LDS Rm, FPSCR {:
nkeynes@673
  2472
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2473
    check_fpuen();
nkeynes@359
  2474
    load_reg( R_EAX, Rm );
nkeynes@669
  2475
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2476
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2477
    return 2;
nkeynes@359
  2478
:}
nkeynes@359
  2479
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2480
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2481
    check_fpuen();
nkeynes@359
  2482
    load_reg( R_EAX, Rm );
nkeynes@395
  2483
    check_ralign32( R_EAX );
nkeynes@586
  2484
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2485
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2486
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2487
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2489
    return 2;
nkeynes@359
  2490
:}
nkeynes@359
  2491
LDS Rm, FPUL {:  
nkeynes@671
  2492
    COUNT_INST(I_LDS);
nkeynes@626
  2493
    check_fpuen();
nkeynes@359
  2494
    load_reg( R_EAX, Rm );
nkeynes@359
  2495
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2496
:}
nkeynes@359
  2497
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2498
    COUNT_INST(I_LDSM);
nkeynes@626
  2499
    check_fpuen();
nkeynes@359
  2500
    load_reg( R_EAX, Rm );
nkeynes@395
  2501
    check_ralign32( R_EAX );
nkeynes@586
  2502
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2503
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2504
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2505
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2507
:}
nkeynes@359
  2508
LDS Rm, MACH {: 
nkeynes@671
  2509
    COUNT_INST(I_LDS);
nkeynes@359
  2510
    load_reg( R_EAX, Rm );
nkeynes@359
  2511
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2512
:}
nkeynes@359
  2513
LDS.L @Rm+, MACH {:  
nkeynes@671
  2514
    COUNT_INST(I_LDSM);
nkeynes@359
  2515
    load_reg( R_EAX, Rm );
nkeynes@395
  2516
    check_ralign32( R_EAX );
nkeynes@586
  2517
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2518
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2519
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2520
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2521
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2522
:}
nkeynes@359
  2523
LDS Rm, MACL {:  
nkeynes@671
  2524
    COUNT_INST(I_LDS);
nkeynes@359
  2525
    load_reg( R_EAX, Rm );
nkeynes@359
  2526
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2527
:}
nkeynes@359
  2528
LDS.L @Rm+, MACL {:  
nkeynes@671
  2529
    COUNT_INST(I_LDSM);
nkeynes@359
  2530
    load_reg( R_EAX, Rm );
nkeynes@395
  2531
    check_ralign32( R_EAX );
nkeynes@586
  2532
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2533
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2534
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2535
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2537
:}
nkeynes@359
  2538
LDS Rm, PR {:  
nkeynes@671
  2539
    COUNT_INST(I_LDS);
nkeynes@359
  2540
    load_reg( R_EAX, Rm );
nkeynes@359
  2541
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2542
:}
nkeynes@359
  2543
LDS.L @Rm+, PR {:  
nkeynes@671
  2544
    COUNT_INST(I_LDSM);
nkeynes@359
  2545
    load_reg( R_EAX, Rm );
nkeynes@395
  2546
    check_ralign32( R_EAX );
nkeynes@586
  2547
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2548
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2549
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2550
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2551
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2552
:}
nkeynes@550
  2553
LDTLB {:  
nkeynes@671
  2554
    COUNT_INST(I_LDTLB);
nkeynes@553
  2555
    call_func0( MMU_ldtlb );
nkeynes@875
  2556
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2557
:}
nkeynes@671
  2558
OCBI @Rn {:
nkeynes@671
  2559
    COUNT_INST(I_OCBI);
nkeynes@671
  2560
:}
nkeynes@671
  2561
OCBP @Rn {:
nkeynes@671
  2562
    COUNT_INST(I_OCBP);
nkeynes@671
  2563
:}
nkeynes@671
  2564
OCBWB @Rn {:
nkeynes@671
  2565
    COUNT_INST(I_OCBWB);
nkeynes@671
  2566
:}
nkeynes@374
  2567
PREF @Rn {:
nkeynes@671
  2568
    COUNT_INST(I_PREF);
nkeynes@374
  2569
    load_reg( R_EAX, Rn );
nkeynes@532
  2570
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2571
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2572
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2573
    JNE_rel8(end);
nkeynes@905
  2574
    call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@586
  2575
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2576
    JE_exc(-1);
nkeynes@380
  2577
    JMP_TARGET(end);
nkeynes@417
  2578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2579
:}
nkeynes@388
  2580
SLEEP {: 
nkeynes@671
  2581
    COUNT_INST(I_SLEEP);
nkeynes@388
  2582
    check_priv();
nkeynes@388
  2583
    call_func0( sh4_sleep );
nkeynes@417
  2584
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2585
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2586
    return 2;
nkeynes@388
  2587
:}
nkeynes@386
  2588
STC SR, Rn {:
nkeynes@671
  2589
    COUNT_INST(I_STCSR);
nkeynes@386
  2590
    check_priv();
nkeynes@386
  2591
    call_func0(sh4_read_sr);
nkeynes@386
  2592
    store_reg( R_EAX, Rn );
nkeynes@417
  2593
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2594
:}
nkeynes@359
  2595
STC GBR, Rn {:  
nkeynes@671
  2596
    COUNT_INST(I_STC);
nkeynes@359
  2597
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2598
    store_reg( R_EAX, Rn );
nkeynes@359
  2599
:}
nkeynes@359
  2600
STC VBR, Rn {:  
nkeynes@671
  2601
    COUNT_INST(I_STC);
nkeynes@386
  2602
    check_priv();
nkeynes@359
  2603
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2604
    store_reg( R_EAX, Rn );
nkeynes@417
  2605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2606
:}
nkeynes@359
  2607
STC SSR, Rn {:  
nkeynes@671
  2608
    COUNT_INST(I_STC);
nkeynes@386
  2609
    check_priv();
nkeynes@359
  2610
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2611
    store_reg( R_EAX, Rn );
nkeynes@417
  2612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2613
:}
nkeynes@359
  2614
STC SPC, Rn {:  
nkeynes@671
  2615
    COUNT_INST(I_STC);
nkeynes@386
  2616
    check_priv();
nkeynes@359
  2617
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2618
    store_reg( R_EAX, Rn );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2620
:}
nkeynes@359
  2621
STC SGR, Rn {:  
nkeynes@671
  2622
    COUNT_INST(I_STC);
nkeynes@386
  2623
    check_priv();
nkeynes@359
  2624
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2625
    store_reg( R_EAX, Rn );
nkeynes@417
  2626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2627
:}
nkeynes@359
  2628
STC DBR, Rn {:  
nkeynes@671
  2629
    COUNT_INST(I_STC);
nkeynes@386
  2630
    check_priv();
nkeynes@359
  2631
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2632
    store_reg( R_EAX, Rn );
nkeynes@417
  2633
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2634
:}
nkeynes@374
  2635
STC Rm_BANK, Rn {:
nkeynes@671
  2636
    COUNT_INST(I_STC);
nkeynes@386
  2637
    check_priv();
nkeynes@374
  2638
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2639
    store_reg( R_EAX, Rn );
nkeynes@417
  2640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2641
:}
nkeynes@374
  2642
STC.L SR, @-Rn {:
nkeynes@671
  2643
    COUNT_INST(I_STCSRM);
nkeynes@586
  2644
    check_priv();
nkeynes@586
  2645
    load_reg( R_EAX, Rn );
nkeynes@586
  2646
    check_walign32( R_EAX );
nkeynes@586
  2647
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2648
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2649
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2650
    call_func0( sh4_read_sr );
nkeynes@586
  2651
    POP_realigned_r32( R_ECX );
nkeynes@586
  2652
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2653
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2654
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2655
:}
nkeynes@359
  2656
STC.L VBR, @-Rn {:  
nkeynes@671
  2657
    COUNT_INST(I_STCM);
nkeynes@586
  2658
    check_priv();
nkeynes@586
  2659
    load_reg( R_EAX, Rn );
nkeynes@586
  2660
    check_walign32( R_EAX );
nkeynes@586
  2661
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2662
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2663
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2664
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2665
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2667
:}
nkeynes@359
  2668
STC.L SSR, @-Rn {:  
nkeynes@671
  2669
    COUNT_INST(I_STCM);
nkeynes@586
  2670
    check_priv();
nkeynes@586
  2671
    load_reg( R_EAX, Rn );
nkeynes@586
  2672
    check_walign32( R_EAX );
nkeynes@586
  2673
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2674
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2675
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2676
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2677
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2678
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2679
:}
nkeynes@416
  2680
STC.L SPC, @-Rn {:
nkeynes@671
  2681
    COUNT_INST(I_STCM);
nkeynes@586
  2682
    check_priv();
nkeynes@586
  2683
    load_reg( R_EAX, Rn );
nkeynes@586
  2684
    check_walign32( R_EAX );
nkeynes@586
  2685
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2686
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2687
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2688
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2689
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2690
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2691
:}
nkeynes@359
  2692
STC.L SGR, @-Rn {:  
nkeynes@671
  2693
    COUNT_INST(I_STCM);
nkeynes@586
  2694
    check_priv();
nkeynes@586
  2695
    load_reg( R_EAX, Rn );
nkeynes@586
  2696
    check_walign32( R_EAX );
nkeynes@586
  2697
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2698
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2699
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2700
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2701
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2702
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2703
:}
nkeynes@359
  2704
STC.L DBR, @-Rn {:  
nkeynes@671
  2705
    COUNT_INST(I_STCM);
nkeynes@586
  2706
    check_priv();
nkeynes@586
  2707
    load_reg( R_EAX, Rn );
nkeynes@586
  2708
    check_walign32( R_EAX );
nkeynes@586
  2709
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2710
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2711
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2712
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2713
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2714
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2715
:}
nkeynes@374
  2716
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2717
    COUNT_INST(I_STCM);
nkeynes@586
  2718
    check_priv();
nkeynes@586
  2719
    load_reg( R_EAX, Rn );
nkeynes@586
  2720
    check_walign32( R_EAX );
nkeynes@586
  2721
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2722
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2723
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2724
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2725
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2726
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2727
:}
nkeynes@359
  2728
STC.L GBR, @-Rn {:  
nkeynes@671
  2729
    COUNT_INST(I_STCM);
nkeynes@586
  2730
    load_reg( R_EAX, Rn );
nkeynes@586
  2731
    check_walign32( R_EAX );
nkeynes@586
  2732
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2733
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2734
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2735
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2736
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2738
:}
nkeynes@359