filename | src/sh4/sh4x86.in |
changeset | 1112:4cac5e474d4c |
prev | 1092:7c4ffe27e7b5 |
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author | nkeynes |
date | Tue Jul 13 18:23:16 2010 +1000 (13 years ago) |
permissions | -rw-r--r-- |
last change | Rearrange the main translation loop to allow translated blocks to jump directly to their successors without needing to return to the main loop in between. Shaves about 6% off the core runtime. |
file | annotate | diff | log | raw |
nkeynes@359 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@359 | 3 | * |
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just |
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline |
nkeynes@359 | 6 | * to test the optimizing versions against. |
nkeynes@359 | 7 | * |
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes. |
nkeynes@359 | 9 | * |
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify |
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by |
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@359 | 13 | * (at your option) any later version. |
nkeynes@359 | 14 | * |
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful, |
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@359 | 18 | * GNU General Public License for more details. |
nkeynes@359 | 19 | */ |
nkeynes@359 | 20 | |
nkeynes@368 | 21 | #include <assert.h> |
nkeynes@388 | 22 | #include <math.h> |
nkeynes@368 | 23 | |
nkeynes@380 | 24 | #ifndef NDEBUG |
nkeynes@380 | 25 | #define DEBUG_JUMPS 1 |
nkeynes@380 | 26 | #endif |
nkeynes@380 | 27 | |
nkeynes@905 | 28 | #include "lxdream.h" |
nkeynes@368 | 29 | #include "sh4/sh4core.h" |
nkeynes@1091 | 30 | #include "sh4/sh4dasm.h" |
nkeynes@368 | 31 | #include "sh4/sh4trans.h" |
nkeynes@671 | 32 | #include "sh4/sh4stat.h" |
nkeynes@388 | 33 | #include "sh4/sh4mmio.h" |
nkeynes@939 | 34 | #include "sh4/mmu.h" |
nkeynes@991 | 35 | #include "xlat/xltcache.h" |
nkeynes@991 | 36 | #include "xlat/x86/x86op.h" |
nkeynes@1091 | 37 | #include "x86dasm/x86dasm.h" |
nkeynes@368 | 38 | #include "clock.h" |
nkeynes@368 | 39 | |
nkeynes@368 | 40 | #define DEFAULT_BACKPATCH_SIZE 4096 |
nkeynes@368 | 41 | |
nkeynes@991 | 42 | /* Offset of a reg relative to the sh4r structure */ |
nkeynes@991 | 43 | #define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128) |
nkeynes@991 | 44 | |
nkeynes@995 | 45 | #define R_T REG_OFFSET(t) |
nkeynes@995 | 46 | #define R_Q REG_OFFSET(q) |
nkeynes@995 | 47 | #define R_S REG_OFFSET(s) |
nkeynes@995 | 48 | #define R_M REG_OFFSET(m) |
nkeynes@995 | 49 | #define R_SR REG_OFFSET(sr) |
nkeynes@995 | 50 | #define R_GBR REG_OFFSET(gbr) |
nkeynes@995 | 51 | #define R_SSR REG_OFFSET(ssr) |
nkeynes@995 | 52 | #define R_SPC REG_OFFSET(spc) |
nkeynes@995 | 53 | #define R_VBR REG_OFFSET(vbr) |
nkeynes@995 | 54 | #define R_MACH REG_OFFSET(mac)+4 |
nkeynes@995 | 55 | #define R_MACL REG_OFFSET(mac) |
nkeynes@995 | 56 | #define R_PC REG_OFFSET(pc) |
nkeynes@991 | 57 | #define R_NEW_PC REG_OFFSET(new_pc) |
nkeynes@995 | 58 | #define R_PR REG_OFFSET(pr) |
nkeynes@995 | 59 | #define R_SGR REG_OFFSET(sgr) |
nkeynes@995 | 60 | #define R_FPUL REG_OFFSET(fpul) |
nkeynes@995 | 61 | #define R_FPSCR REG_OFFSET(fpscr) |
nkeynes@995 | 62 | #define R_DBR REG_OFFSET(dbr) |
nkeynes@995 | 63 | #define R_R(rn) REG_OFFSET(r[rn]) |
nkeynes@995 | 64 | #define R_FR(f) REG_OFFSET(fr[0][(f)^1]) |
nkeynes@995 | 65 | #define R_XF(f) REG_OFFSET(fr[1][(f)^1]) |
nkeynes@995 | 66 | #define R_DR(f) REG_OFFSET(fr[(f)&1][(f)&0x0E]) |
nkeynes@995 | 67 | #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01]) |
nkeynes@995 | 68 | #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E]) |
nkeynes@995 | 69 | |
nkeynes@995 | 70 | #define DELAY_NONE 0 |
nkeynes@995 | 71 | #define DELAY_PC 1 |
nkeynes@995 | 72 | #define DELAY_PC_PR 2 |
nkeynes@991 | 73 | |
nkeynes@1112 | 74 | #define SH4_MODE_UNKNOWN -1 |
nkeynes@1112 | 75 | |
nkeynes@586 | 76 | struct backpatch_record { |
nkeynes@604 | 77 | uint32_t fixup_offset; |
nkeynes@586 | 78 | uint32_t fixup_icount; |
nkeynes@596 | 79 | int32_t exc_code; |
nkeynes@586 | 80 | }; |
nkeynes@586 | 81 | |
nkeynes@368 | 82 | /** |
nkeynes@368 | 83 | * Struct to manage internal translation state. This state is not saved - |
nkeynes@368 | 84 | * it is only valid between calls to sh4_translate_begin_block() and |
nkeynes@368 | 85 | * sh4_translate_end_block() |
nkeynes@368 | 86 | */ |
nkeynes@368 | 87 | struct sh4_x86_state { |
nkeynes@590 | 88 | int in_delay_slot; |
nkeynes@1112 | 89 | uint8_t *code; |
nkeynes@368 | 90 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */ |
nkeynes@409 | 91 | gboolean branch_taken; /* true if we branched unconditionally */ |
nkeynes@901 | 92 | gboolean double_prec; /* true if FPU is in double-precision mode */ |
nkeynes@903 | 93 | gboolean double_size; /* true if FPU is in double-size mode */ |
nkeynes@903 | 94 | gboolean sse3_enabled; /* true if host supports SSE3 instructions */ |
nkeynes@408 | 95 | uint32_t block_start_pc; |
nkeynes@547 | 96 | uint32_t stack_posn; /* Trace stack height for alignment purposes */ |
nkeynes@1112 | 97 | uint32_t sh4_mode; /* Mirror of sh4r.xlat_sh4_mode */ |
nkeynes@417 | 98 | int tstate; |
nkeynes@368 | 99 | |
nkeynes@586 | 100 | /* mode flags */ |
nkeynes@586 | 101 | gboolean tlb_on; /* True if tlb translation is active */ |
nkeynes@586 | 102 | |
nkeynes@368 | 103 | /* Allocated memory for the (block-wide) back-patch list */ |
nkeynes@586 | 104 | struct backpatch_record *backpatch_list; |
nkeynes@368 | 105 | uint32_t backpatch_posn; |
nkeynes@368 | 106 | uint32_t backpatch_size; |
nkeynes@368 | 107 | }; |
nkeynes@368 | 108 | |
nkeynes@368 | 109 | static struct sh4_x86_state sh4_x86; |
nkeynes@368 | 110 | |
nkeynes@388 | 111 | static uint32_t max_int = 0x7FFFFFFF; |
nkeynes@388 | 112 | static uint32_t min_int = 0x80000000; |
nkeynes@394 | 113 | static uint32_t save_fcw; /* save value for fpu control word */ |
nkeynes@394 | 114 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */ |
nkeynes@386 | 115 | |
nkeynes@1091 | 116 | static struct x86_symbol x86_symbol_table[] = { |
nkeynes@1091 | 117 | { "sh4r+128", ((char *)&sh4r)+128 }, |
nkeynes@1091 | 118 | { "sh4_cpu_period", &sh4_cpu_period }, |
nkeynes@1091 | 119 | { "sh4_address_space", NULL }, |
nkeynes@1091 | 120 | { "sh4_user_address_space", NULL }, |
nkeynes@1091 | 121 | { "sh4_write_fpscr", sh4_write_fpscr }, |
nkeynes@1091 | 122 | { "sh4_write_sr", sh4_write_sr }, |
nkeynes@1091 | 123 | { "sh4_read_sr", sh4_read_sr }, |
nkeynes@1091 | 124 | { "sh4_sleep", sh4_sleep }, |
nkeynes@1091 | 125 | { "sh4_fsca", sh4_fsca }, |
nkeynes@1091 | 126 | { "sh4_ftrv", sh4_ftrv }, |
nkeynes@1091 | 127 | { "sh4_switch_fr_banks", sh4_switch_fr_banks }, |
nkeynes@1091 | 128 | { "sh4_execute_instruction", sh4_execute_instruction }, |
nkeynes@1091 | 129 | { "signsat48", signsat48 }, |
nkeynes@1091 | 130 | { "xlat_get_code_by_vma", xlat_get_code_by_vma }, |
nkeynes@1091 | 131 | { "xlat_get_code", xlat_get_code } |
nkeynes@1091 | 132 | }; |
nkeynes@1091 | 133 | |
nkeynes@1091 | 134 | |
nkeynes@903 | 135 | gboolean is_sse3_supported() |
nkeynes@903 | 136 | { |
nkeynes@903 | 137 | uint32_t features; |
nkeynes@903 | 138 | |
nkeynes@903 | 139 | __asm__ __volatile__( |
nkeynes@903 | 140 | "mov $0x01, %%eax\n\t" |
nkeynes@908 | 141 | "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx"); |
nkeynes@903 | 142 | return (features & 1) ? TRUE : FALSE; |
nkeynes@903 | 143 | } |
nkeynes@903 | 144 | |
nkeynes@669 | 145 | void sh4_translate_init(void) |
nkeynes@368 | 146 | { |
nkeynes@368 | 147 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE); |
nkeynes@586 | 148 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record); |
nkeynes@903 | 149 | sh4_x86.sse3_enabled = is_sse3_supported(); |
nkeynes@1091 | 150 | x86_symbol_table[2].ptr = sh4_address_space; |
nkeynes@1091 | 151 | x86_symbol_table[3].ptr = sh4_user_address_space; |
nkeynes@1091 | 152 | x86_disasm_init(); |
nkeynes@1091 | 153 | x86_set_symtab( x86_symbol_table, sizeof(x86_symbol_table)/sizeof(struct x86_symbol) ); |
nkeynes@368 | 154 | } |
nkeynes@368 | 155 | |
nkeynes@1091 | 156 | /** |
nkeynes@1091 | 157 | * Disassemble the given translated code block, and it's source SH4 code block |
nkeynes@1091 | 158 | * side-by-side. The current native pc will be marked if non-null. |
nkeynes@1091 | 159 | */ |
nkeynes@1091 | 160 | void sh4_translate_disasm_block( FILE *out, void *code, sh4addr_t source_start, void *native_pc ) |
nkeynes@1091 | 161 | { |
nkeynes@1091 | 162 | char buf[256]; |
nkeynes@1091 | 163 | char op[256]; |
nkeynes@1091 | 164 | |
nkeynes@1091 | 165 | uintptr_t target_start = (uintptr_t)code, target_pc; |
nkeynes@1091 | 166 | uintptr_t target_end = target_start + xlat_get_code_size(code); |
nkeynes@1091 | 167 | uint32_t source_pc = source_start; |
nkeynes@1091 | 168 | uint32_t source_end = source_pc; |
nkeynes@1091 | 169 | xlat_recovery_record_t source_recov_table = XLAT_RECOVERY_TABLE(code); |
nkeynes@1092 | 170 | xlat_recovery_record_t source_recov_end = source_recov_table + XLAT_BLOCK_FOR_CODE(code)->recover_table_size - 1; |
nkeynes@1091 | 171 | |
nkeynes@1091 | 172 | for( target_pc = target_start; target_pc < target_end; ) { |
nkeynes@1091 | 173 | uintptr_t pc2 = x86_disasm_instruction( target_pc, buf, sizeof(buf), op ); |
nkeynes@1092 | 174 | #if SIZEOF_VOID_P == 8 |
nkeynes@1092 | 175 | fprintf( out, "%c%016lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '), |
nkeynes@1092 | 176 | target_pc, op, buf ); |
nkeynes@1092 | 177 | #else |
nkeynes@1112 | 178 | fprintf( out, "%c%08lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '), |
nkeynes@1092 | 179 | target_pc, op, buf ); |
nkeynes@1092 | 180 | #endif |
nkeynes@1091 | 181 | if( source_recov_table < source_recov_end && |
nkeynes@1091 | 182 | target_pc >= (target_start + source_recov_table->xlat_offset) ) { |
nkeynes@1091 | 183 | source_recov_table++; |
nkeynes@1091 | 184 | if( source_end < (source_start + (source_recov_table->sh4_icount)*2) ) |
nkeynes@1091 | 185 | source_end = source_start + (source_recov_table->sh4_icount)*2; |
nkeynes@1091 | 186 | } |
nkeynes@1091 | 187 | |
nkeynes@1091 | 188 | if( source_pc < source_end ) { |
nkeynes@1091 | 189 | uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op ); |
nkeynes@1091 | 190 | fprintf( out, " %08X: %s %s\n", source_pc, op, buf ); |
nkeynes@1091 | 191 | source_pc = source_pc2; |
nkeynes@1091 | 192 | } else { |
nkeynes@1091 | 193 | fprintf( out, "\n" ); |
nkeynes@1091 | 194 | } |
nkeynes@1091 | 195 | |
nkeynes@1091 | 196 | target_pc = pc2; |
nkeynes@1091 | 197 | } |
nkeynes@1091 | 198 | |
nkeynes@1091 | 199 | while( source_pc < source_end ) { |
nkeynes@1091 | 200 | uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op ); |
nkeynes@1091 | 201 | fprintf( out, "%*c %08X: %s %s\n", 72,' ', source_pc, op, buf ); |
nkeynes@1091 | 202 | source_pc = source_pc2; |
nkeynes@1091 | 203 | } |
nkeynes@1091 | 204 | } |
nkeynes@368 | 205 | |
nkeynes@586 | 206 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code ) |
nkeynes@368 | 207 | { |
nkeynes@991 | 208 | int reloc_size = 4; |
nkeynes@991 | 209 | |
nkeynes@991 | 210 | if( exc_code == -2 ) { |
nkeynes@991 | 211 | reloc_size = sizeof(void *); |
nkeynes@991 | 212 | } |
nkeynes@991 | 213 | |
nkeynes@368 | 214 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) { |
nkeynes@368 | 215 | sh4_x86.backpatch_size <<= 1; |
nkeynes@586 | 216 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, |
nkeynes@586 | 217 | sh4_x86.backpatch_size * sizeof(struct backpatch_record)); |
nkeynes@368 | 218 | assert( sh4_x86.backpatch_list != NULL ); |
nkeynes@368 | 219 | } |
nkeynes@586 | 220 | if( sh4_x86.in_delay_slot ) { |
nkeynes@586 | 221 | fixup_pc -= 2; |
nkeynes@586 | 222 | } |
nkeynes@991 | 223 | |
nkeynes@604 | 224 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = |
nkeynes@991 | 225 | (((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size; |
nkeynes@586 | 226 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1; |
nkeynes@586 | 227 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code; |
nkeynes@586 | 228 | sh4_x86.backpatch_posn++; |
nkeynes@368 | 229 | } |
nkeynes@368 | 230 | |
nkeynes@991 | 231 | #define TSTATE_NONE -1 |
nkeynes@995 | 232 | #define TSTATE_O X86_COND_O |
nkeynes@995 | 233 | #define TSTATE_C X86_COND_C |
nkeynes@995 | 234 | #define TSTATE_E X86_COND_E |
nkeynes@995 | 235 | #define TSTATE_NE X86_COND_NE |
nkeynes@995 | 236 | #define TSTATE_G X86_COND_G |
nkeynes@995 | 237 | #define TSTATE_GE X86_COND_GE |
nkeynes@995 | 238 | #define TSTATE_A X86_COND_A |
nkeynes@995 | 239 | #define TSTATE_AE X86_COND_AE |
nkeynes@359 | 240 | |
nkeynes@991 | 241 | #define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1) |
nkeynes@991 | 242 | #define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x) |
nkeynes@368 | 243 | |
nkeynes@991 | 244 | /* Convenience instructions */ |
nkeynes@991 | 245 | #define LDC_t() CMPB_imms_rbpdisp(1,R_T); CMC() |
nkeynes@991 | 246 | #define SETE_t() SETCCB_cc_rbpdisp(X86_COND_E,R_T) |
nkeynes@991 | 247 | #define SETA_t() SETCCB_cc_rbpdisp(X86_COND_A,R_T) |
nkeynes@991 | 248 | #define SETAE_t() SETCCB_cc_rbpdisp(X86_COND_AE,R_T) |
nkeynes@991 | 249 | #define SETG_t() SETCCB_cc_rbpdisp(X86_COND_G,R_T) |
nkeynes@991 | 250 | #define SETGE_t() SETCCB_cc_rbpdisp(X86_COND_GE,R_T) |
nkeynes@991 | 251 | #define SETC_t() SETCCB_cc_rbpdisp(X86_COND_C,R_T) |
nkeynes@991 | 252 | #define SETO_t() SETCCB_cc_rbpdisp(X86_COND_O,R_T) |
nkeynes@991 | 253 | #define SETNE_t() SETCCB_cc_rbpdisp(X86_COND_NE,R_T) |
nkeynes@991 | 254 | #define SETC_r8(r1) SETCCB_cc_r8(X86_COND_C, r1) |
nkeynes@991 | 255 | #define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label) |
nkeynes@1112 | 256 | #define JBE_label(label) JCC_cc_rel8(X86_COND_BE,-1); MARK_JMP8(label) |
nkeynes@991 | 257 | #define JE_label(label) JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label) |
nkeynes@991 | 258 | #define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label) |
nkeynes@991 | 259 | #define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label) |
nkeynes@991 | 260 | #define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label) |
nkeynes@991 | 261 | #define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label) |
nkeynes@991 | 262 | #define JS_label(label) JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label) |
nkeynes@991 | 263 | #define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label) |
nkeynes@991 | 264 | #define JNE_exc(exc) JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc) |
nkeynes@374 | 265 | |
nkeynes@991 | 266 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */ |
nkeynes@991 | 267 | #define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@991 | 268 | CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@991 | 269 | JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label) |
nkeynes@368 | 270 | |
nkeynes@991 | 271 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */ |
nkeynes@991 | 272 | #define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@991 | 273 | CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@991 | 274 | JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label) |
nkeynes@359 | 275 | |
nkeynes@939 | 276 | |
nkeynes@991 | 277 | #define load_reg(x86reg,sh4reg) MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg ) |
nkeynes@991 | 278 | #define store_reg(x86reg,sh4reg) MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) ) |
nkeynes@374 | 279 | |
nkeynes@375 | 280 | /** |
nkeynes@375 | 281 | * Load an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 282 | * register (eg for register-to-register moves) |
nkeynes@375 | 283 | */ |
nkeynes@991 | 284 | #define load_fr(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg ) |
nkeynes@991 | 285 | #define load_xf(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg ) |
nkeynes@375 | 286 | |
nkeynes@375 | 287 | /** |
nkeynes@669 | 288 | * Load the low half of a DR register (DR or XD) into an integer x86 register |
nkeynes@669 | 289 | */ |
nkeynes@991 | 290 | #define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg ) |
nkeynes@991 | 291 | #define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg ) |
nkeynes@669 | 292 | |
nkeynes@669 | 293 | /** |
nkeynes@669 | 294 | * Store an FR register (single-precision floating point) from an integer x86+ |
nkeynes@375 | 295 | * register (eg for register-to-register moves) |
nkeynes@375 | 296 | */ |
nkeynes@991 | 297 | #define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 298 | #define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@375 | 299 | |
nkeynes@991 | 300 | #define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) ) |
nkeynes@991 | 301 | #define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) ) |
nkeynes@375 | 302 | |
nkeynes@374 | 303 | |
nkeynes@991 | 304 | #define push_fpul() FLDF_rbpdisp(R_FPUL) |
nkeynes@991 | 305 | #define pop_fpul() FSTPF_rbpdisp(R_FPUL) |
nkeynes@991 | 306 | #define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 307 | #define pop_fr(frm) FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 308 | #define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@991 | 309 | #define pop_xf(frm) FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@991 | 310 | #define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) |
nkeynes@991 | 311 | #define pop_dr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) |
nkeynes@991 | 312 | #define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) |
nkeynes@991 | 313 | #define pop_xdr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) |
nkeynes@377 | 314 | |
nkeynes@991 | 315 | #ifdef ENABLE_SH4STATS |
nkeynes@995 | 316 | #define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE |
nkeynes@991 | 317 | #else |
nkeynes@991 | 318 | #define COUNT_INST(id) |
nkeynes@991 | 319 | #endif |
nkeynes@377 | 320 | |
nkeynes@374 | 321 | |
nkeynes@368 | 322 | /* Exception checks - Note that all exception checks will clobber EAX */ |
nkeynes@416 | 323 | |
nkeynes@416 | 324 | #define check_priv( ) \ |
nkeynes@1112 | 325 | if( (sh4_x86.sh4_mode & SR_MD) == 0 ) { \ |
nkeynes@937 | 326 | if( sh4_x86.in_delay_slot ) { \ |
nkeynes@956 | 327 | exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \ |
nkeynes@937 | 328 | } else { \ |
nkeynes@956 | 329 | exit_block_exc(EXC_ILLEGAL, pc); \ |
nkeynes@937 | 330 | } \ |
nkeynes@956 | 331 | sh4_x86.branch_taken = TRUE; \ |
nkeynes@937 | 332 | sh4_x86.in_delay_slot = DELAY_NONE; \ |
nkeynes@937 | 333 | return 2; \ |
nkeynes@937 | 334 | } |
nkeynes@416 | 335 | |
nkeynes@416 | 336 | #define check_fpuen( ) \ |
nkeynes@416 | 337 | if( !sh4_x86.fpuen_checked ) {\ |
nkeynes@416 | 338 | sh4_x86.fpuen_checked = TRUE;\ |
nkeynes@995 | 339 | MOVL_rbpdisp_r32( R_SR, REG_EAX );\ |
nkeynes@991 | 340 | ANDL_imms_r32( SR_FD, REG_EAX );\ |
nkeynes@416 | 341 | if( sh4_x86.in_delay_slot ) {\ |
nkeynes@586 | 342 | JNE_exc(EXC_SLOT_FPU_DISABLED);\ |
nkeynes@416 | 343 | } else {\ |
nkeynes@586 | 344 | JNE_exc(EXC_FPU_DISABLED);\ |
nkeynes@416 | 345 | }\ |
nkeynes@875 | 346 | sh4_x86.tstate = TSTATE_NONE; \ |
nkeynes@416 | 347 | } |
nkeynes@416 | 348 | |
nkeynes@586 | 349 | #define check_ralign16( x86reg ) \ |
nkeynes@991 | 350 | TESTL_imms_r32( 0x00000001, x86reg ); \ |
nkeynes@586 | 351 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@416 | 352 | |
nkeynes@586 | 353 | #define check_walign16( x86reg ) \ |
nkeynes@991 | 354 | TESTL_imms_r32( 0x00000001, x86reg ); \ |
nkeynes@586 | 355 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 356 | |
nkeynes@586 | 357 | #define check_ralign32( x86reg ) \ |
nkeynes@991 | 358 | TESTL_imms_r32( 0x00000003, x86reg ); \ |
nkeynes@586 | 359 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@368 | 360 | |
nkeynes@586 | 361 | #define check_walign32( x86reg ) \ |
nkeynes@991 | 362 | TESTL_imms_r32( 0x00000003, x86reg ); \ |
nkeynes@586 | 363 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 364 | |
nkeynes@732 | 365 | #define check_ralign64( x86reg ) \ |
nkeynes@991 | 366 | TESTL_imms_r32( 0x00000007, x86reg ); \ |
nkeynes@732 | 367 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@732 | 368 | |
nkeynes@732 | 369 | #define check_walign64( x86reg ) \ |
nkeynes@991 | 370 | TESTL_imms_r32( 0x00000007, x86reg ); \ |
nkeynes@732 | 371 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@732 | 372 | |
nkeynes@1112 | 373 | #define address_space() ((sh4_x86.sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space) |
nkeynes@1004 | 374 | |
nkeynes@824 | 375 | #define UNDEF(ir) |
nkeynes@939 | 376 | /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so |
nkeynes@939 | 377 | * don't waste the cycles expecting them. Otherwise we need to save the exception pointer. |
nkeynes@586 | 378 | */ |
nkeynes@941 | 379 | #ifdef HAVE_FRAME_ADDRESS |
nkeynes@995 | 380 | static void call_read_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 381 | { |
nkeynes@1004 | 382 | decode_address(address_space(), addr_reg); |
nkeynes@1112 | 383 | if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { |
nkeynes@995 | 384 | CALL1_r32disp_r32(REG_ECX, offset, addr_reg); |
nkeynes@995 | 385 | } else { |
nkeynes@995 | 386 | if( addr_reg != REG_ARG1 ) { |
nkeynes@995 | 387 | MOVL_r32_r32( addr_reg, REG_ARG1 ); |
nkeynes@995 | 388 | } |
nkeynes@995 | 389 | MOVP_immptr_rptr( 0, REG_ARG2 ); |
nkeynes@995 | 390 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 391 | CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2); |
nkeynes@995 | 392 | } |
nkeynes@995 | 393 | if( value_reg != REG_RESULT1 ) { |
nkeynes@995 | 394 | MOVL_r32_r32( REG_RESULT1, value_reg ); |
nkeynes@995 | 395 | } |
nkeynes@995 | 396 | } |
nkeynes@995 | 397 | |
nkeynes@995 | 398 | static void call_write_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 399 | { |
nkeynes@1004 | 400 | decode_address(address_space(), addr_reg); |
nkeynes@1112 | 401 | if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { |
nkeynes@995 | 402 | CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg); |
nkeynes@995 | 403 | } else { |
nkeynes@995 | 404 | if( value_reg != REG_ARG2 ) { |
nkeynes@995 | 405 | MOVL_r32_r32( value_reg, REG_ARG2 ); |
nkeynes@995 | 406 | } |
nkeynes@995 | 407 | if( addr_reg != REG_ARG1 ) { |
nkeynes@995 | 408 | MOVL_r32_r32( addr_reg, REG_ARG1 ); |
nkeynes@995 | 409 | } |
nkeynes@995 | 410 | #if MAX_REG_ARG > 2 |
nkeynes@995 | 411 | MOVP_immptr_rptr( 0, REG_ARG3 ); |
nkeynes@995 | 412 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 413 | CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3); |
nkeynes@995 | 414 | #else |
nkeynes@995 | 415 | MOVL_imm32_rspdisp( 0, 0 ); |
nkeynes@995 | 416 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 417 | CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0); |
nkeynes@995 | 418 | #endif |
nkeynes@995 | 419 | } |
nkeynes@995 | 420 | } |
nkeynes@995 | 421 | #else |
nkeynes@995 | 422 | static void call_read_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 423 | { |
nkeynes@1004 | 424 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 425 | CALL1_r32disp_r32(REG_ECX, offset, addr_reg); |
nkeynes@995 | 426 | if( value_reg != REG_RESULT1 ) { |
nkeynes@995 | 427 | MOVL_r32_r32( REG_RESULT1, value_reg ); |
nkeynes@995 | 428 | } |
nkeynes@995 | 429 | } |
nkeynes@995 | 430 | |
nkeynes@996 | 431 | static void call_write_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 432 | { |
nkeynes@1004 | 433 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 434 | CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg); |
nkeynes@995 | 435 | } |
nkeynes@941 | 436 | #endif |
nkeynes@939 | 437 | |
nkeynes@995 | 438 | #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name ) |
nkeynes@995 | 439 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc) |
nkeynes@995 | 440 | #define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) |
nkeynes@995 | 441 | #define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc) |
nkeynes@995 | 442 | #define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc) |
nkeynes@995 | 443 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc) |
nkeynes@995 | 444 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc) |
nkeynes@995 | 445 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc) |
nkeynes@995 | 446 | #define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc) |
nkeynes@368 | 447 | |
nkeynes@956 | 448 | #define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2; |
nkeynes@539 | 449 | |
nkeynes@901 | 450 | void sh4_translate_begin_block( sh4addr_t pc ) |
nkeynes@901 | 451 | { |
nkeynes@1112 | 452 | sh4_x86.code = xlat_output; |
nkeynes@901 | 453 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@901 | 454 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@901 | 455 | sh4_x86.branch_taken = FALSE; |
nkeynes@901 | 456 | sh4_x86.backpatch_posn = 0; |
nkeynes@901 | 457 | sh4_x86.block_start_pc = pc; |
nkeynes@939 | 458 | sh4_x86.tlb_on = IS_TLB_ENABLED(); |
nkeynes@901 | 459 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 460 | sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR; |
nkeynes@903 | 461 | sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ; |
nkeynes@1112 | 462 | sh4_x86.sh4_mode = sh4r.xlat_sh4_mode; |
nkeynes@1112 | 463 | enter_block(); |
nkeynes@901 | 464 | } |
nkeynes@901 | 465 | |
nkeynes@901 | 466 | |
nkeynes@593 | 467 | uint32_t sh4_translate_end_block_size() |
nkeynes@593 | 468 | { |
nkeynes@596 | 469 | if( sh4_x86.backpatch_posn <= 3 ) { |
nkeynes@1008 | 470 | return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*24); |
nkeynes@596 | 471 | } else { |
nkeynes@1008 | 472 | return EPILOGUE_SIZE + 72 + (sh4_x86.backpatch_posn-3)*27; |
nkeynes@596 | 473 | } |
nkeynes@593 | 474 | } |
nkeynes@593 | 475 | |
nkeynes@593 | 476 | |
nkeynes@590 | 477 | /** |
nkeynes@590 | 478 | * Embed a breakpoint into the generated code |
nkeynes@590 | 479 | */ |
nkeynes@586 | 480 | void sh4_translate_emit_breakpoint( sh4vma_t pc ) |
nkeynes@586 | 481 | { |
nkeynes@995 | 482 | MOVL_imm32_r32( pc, REG_EAX ); |
nkeynes@995 | 483 | CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX ); |
nkeynes@875 | 484 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@586 | 485 | } |
nkeynes@590 | 486 | |
nkeynes@601 | 487 | |
nkeynes@601 | 488 | #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc) |
nkeynes@601 | 489 | |
nkeynes@1112 | 490 | /** Offset of xlat_sh4_mode field relative to the code pointer */ |
nkeynes@1112 | 491 | #define XLAT_SH4_MODE_CODE_OFFSET (uint32_t)(offsetof(struct xlat_cache_block, xlat_sh4_mode) - offsetof(struct xlat_cache_block,code) ) |
nkeynes@1112 | 492 | |
nkeynes@1112 | 493 | /** |
nkeynes@1112 | 494 | * Test if the loaded target code pointer in %eax is valid, and if so jump |
nkeynes@1112 | 495 | * directly into it, bypassing the normal exit. |
nkeynes@1112 | 496 | */ |
nkeynes@1112 | 497 | static void jump_next_block() |
nkeynes@1112 | 498 | { |
nkeynes@1112 | 499 | TESTP_rptr_rptr(REG_EAX, REG_EAX); |
nkeynes@1112 | 500 | JE_label(nocode); |
nkeynes@1112 | 501 | if( sh4_x86.sh4_mode == SH4_MODE_UNKNOWN ) { |
nkeynes@1112 | 502 | /* sr/fpscr was changed, possibly updated xlat_sh4_mode, so reload it */ |
nkeynes@1112 | 503 | MOVL_rbpdisp_r32( REG_OFFSET(xlat_sh4_mode), REG_ECX ); |
nkeynes@1112 | 504 | CMPL_r32_r32disp( REG_ECX, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET ); |
nkeynes@1112 | 505 | } else { |
nkeynes@1112 | 506 | CMPL_imms_r32disp( sh4_x86.sh4_mode, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET ); |
nkeynes@1112 | 507 | } |
nkeynes@1112 | 508 | JNE_label(wrongmode); |
nkeynes@1112 | 509 | LEAP_rptrdisp_rptr(REG_EAX, PROLOGUE_SIZE,REG_EAX); |
nkeynes@1112 | 510 | JMP_rptr(REG_EAX); |
nkeynes@1112 | 511 | JMP_TARGET(nocode); JMP_TARGET(wrongmode); |
nkeynes@1112 | 512 | } |
nkeynes@1112 | 513 | |
nkeynes@590 | 514 | /** |
nkeynes@995 | 515 | * Exit the block with sh4r.pc already written |
nkeynes@995 | 516 | */ |
nkeynes@995 | 517 | void exit_block_pcset( sh4addr_t pc ) |
nkeynes@995 | 518 | { |
nkeynes@995 | 519 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@1112 | 520 | ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX ); |
nkeynes@1112 | 521 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@1112 | 522 | CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) ); |
nkeynes@1112 | 523 | JBE_label(exitloop); |
nkeynes@995 | 524 | MOVL_rbpdisp_r32( R_PC, REG_ARG1 ); |
nkeynes@995 | 525 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 526 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1); |
nkeynes@995 | 527 | } else { |
nkeynes@995 | 528 | CALL1_ptr_r32(xlat_get_code,REG_ARG1); |
nkeynes@995 | 529 | } |
nkeynes@1112 | 530 | |
nkeynes@1112 | 531 | jump_next_block(); |
nkeynes@1112 | 532 | JMP_TARGET(exitloop); |
nkeynes@995 | 533 | exit_block(); |
nkeynes@995 | 534 | } |
nkeynes@995 | 535 | |
nkeynes@995 | 536 | /** |
nkeynes@995 | 537 | * Exit the block with sh4r.new_pc written with the target pc |
nkeynes@995 | 538 | */ |
nkeynes@995 | 539 | void exit_block_newpcset( sh4addr_t pc ) |
nkeynes@995 | 540 | { |
nkeynes@995 | 541 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@1112 | 542 | ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX ); |
nkeynes@1112 | 543 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 544 | MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 ); |
nkeynes@995 | 545 | MOVL_r32_rbpdisp( REG_ARG1, R_PC ); |
nkeynes@1112 | 546 | CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) ); |
nkeynes@1112 | 547 | JBE_label(exitloop); |
nkeynes@995 | 548 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 549 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1); |
nkeynes@995 | 550 | } else { |
nkeynes@995 | 551 | CALL1_ptr_r32(xlat_get_code,REG_ARG1); |
nkeynes@995 | 552 | } |
nkeynes@1112 | 553 | |
nkeynes@1112 | 554 | jump_next_block(); |
nkeynes@1112 | 555 | JMP_TARGET(exitloop); |
nkeynes@995 | 556 | exit_block(); |
nkeynes@995 | 557 | } |
nkeynes@995 | 558 | |
nkeynes@995 | 559 | |
nkeynes@995 | 560 | /** |
nkeynes@995 | 561 | * Exit the block to an absolute PC |
nkeynes@995 | 562 | */ |
nkeynes@995 | 563 | void exit_block_abs( sh4addr_t pc, sh4addr_t endpc ) |
nkeynes@995 | 564 | { |
nkeynes@1112 | 565 | MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@1112 | 566 | ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX ); |
nkeynes@1112 | 567 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@1112 | 568 | |
nkeynes@1112 | 569 | MOVL_imm32_r32( pc, REG_ARG1 ); |
nkeynes@1112 | 570 | MOVL_r32_rbpdisp( REG_ARG1, R_PC ); |
nkeynes@1112 | 571 | CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) ); |
nkeynes@1112 | 572 | JBE_label(exitloop); |
nkeynes@1112 | 573 | |
nkeynes@995 | 574 | if( IS_IN_ICACHE(pc) ) { |
nkeynes@995 | 575 | MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); |
nkeynes@995 | 576 | ANDP_imms_rptr( -4, REG_EAX ); |
nkeynes@995 | 577 | } else if( sh4_x86.tlb_on ) { |
nkeynes@1112 | 578 | CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1); |
nkeynes@995 | 579 | } else { |
nkeynes@1112 | 580 | CALL1_ptr_r32(xlat_get_code, REG_ARG1); |
nkeynes@995 | 581 | } |
nkeynes@1112 | 582 | jump_next_block(); |
nkeynes@1112 | 583 | JMP_TARGET(exitloop); |
nkeynes@995 | 584 | exit_block(); |
nkeynes@995 | 585 | } |
nkeynes@995 | 586 | |
nkeynes@995 | 587 | /** |
nkeynes@995 | 588 | * Exit the block to a relative PC |
nkeynes@995 | 589 | */ |
nkeynes@995 | 590 | void exit_block_rel( sh4addr_t pc, sh4addr_t endpc ) |
nkeynes@995 | 591 | { |
nkeynes@1112 | 592 | MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@1112 | 593 | ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX ); |
nkeynes@1112 | 594 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@1112 | 595 | |
nkeynes@1112 | 596 | if( pc == sh4_x86.block_start_pc && sh4_x86.sh4_mode == sh4r.xlat_sh4_mode ) { |
nkeynes@1112 | 597 | /* Special case for tight loops - the PC doesn't change, and |
nkeynes@1112 | 598 | * we already know the target address. Just check events pending before |
nkeynes@1112 | 599 | * looping. |
nkeynes@1112 | 600 | */ |
nkeynes@1112 | 601 | CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) ); |
nkeynes@1112 | 602 | uint32_t backdisp = ((uintptr_t)(sh4_x86.code - xlat_output)) + PROLOGUE_SIZE; |
nkeynes@1112 | 603 | JCC_cc_prerel(X86_COND_A, backdisp); |
nkeynes@1112 | 604 | } else { |
nkeynes@1112 | 605 | MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ARG1 ); |
nkeynes@1112 | 606 | ADDL_rbpdisp_r32( R_PC, REG_ARG1 ); |
nkeynes@1112 | 607 | MOVL_r32_rbpdisp( REG_ARG1, R_PC ); |
nkeynes@1112 | 608 | CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) ); |
nkeynes@1112 | 609 | JBE_label(exitloop2); |
nkeynes@1112 | 610 | |
nkeynes@1112 | 611 | if( IS_IN_ICACHE(pc) ) { |
nkeynes@1112 | 612 | MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); |
nkeynes@1112 | 613 | ANDP_imms_rptr( -4, REG_EAX ); |
nkeynes@1112 | 614 | } else if( sh4_x86.tlb_on ) { |
nkeynes@1112 | 615 | CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1); |
nkeynes@1112 | 616 | } else { |
nkeynes@1112 | 617 | CALL1_ptr_r32(xlat_get_code, REG_ARG1); |
nkeynes@1112 | 618 | } |
nkeynes@1112 | 619 | jump_next_block(); |
nkeynes@1112 | 620 | JMP_TARGET(exitloop2); |
nkeynes@995 | 621 | } |
nkeynes@995 | 622 | exit_block(); |
nkeynes@995 | 623 | } |
nkeynes@995 | 624 | |
nkeynes@995 | 625 | /** |
nkeynes@995 | 626 | * Exit unconditionally with a general exception |
nkeynes@995 | 627 | */ |
nkeynes@995 | 628 | void exit_block_exc( int code, sh4addr_t pc ) |
nkeynes@995 | 629 | { |
nkeynes@995 | 630 | MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX ); |
nkeynes@995 | 631 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 632 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 633 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 634 | MOVL_imm32_r32( code, REG_ARG1 ); |
nkeynes@995 | 635 | CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 ); |
nkeynes@995 | 636 | exit_block(); |
nkeynes@995 | 637 | } |
nkeynes@995 | 638 | |
nkeynes@995 | 639 | /** |
nkeynes@590 | 640 | * Embed a call to sh4_execute_instruction for situations that we |
nkeynes@601 | 641 | * can't translate (just page-crossing delay slots at the moment). |
nkeynes@601 | 642 | * Caller is responsible for setting new_pc before calling this function. |
nkeynes@601 | 643 | * |
nkeynes@601 | 644 | * Performs: |
nkeynes@601 | 645 | * Set PC = endpc |
nkeynes@601 | 646 | * Set sh4r.in_delay_slot = sh4_x86.in_delay_slot |
nkeynes@601 | 647 | * Update slice_cycle for endpc+2 (single step doesn't update slice_cycle) |
nkeynes@601 | 648 | * Call sh4_execute_instruction |
nkeynes@601 | 649 | * Call xlat_get_code_by_vma / xlat_get_code as for normal exit |
nkeynes@590 | 650 | */ |
nkeynes@601 | 651 | void exit_block_emu( sh4vma_t endpc ) |
nkeynes@590 | 652 | { |
nkeynes@995 | 653 | MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX ); // 5 |
nkeynes@991 | 654 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@586 | 655 | |
nkeynes@995 | 656 | MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5 |
nkeynes@991 | 657 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 6 |
nkeynes@995 | 658 | MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX ); |
nkeynes@995 | 659 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) ); |
nkeynes@590 | 660 | |
nkeynes@1112 | 661 | CALL_ptr( sh4_execute_instruction ); |
nkeynes@926 | 662 | exit_block(); |
nkeynes@590 | 663 | } |
nkeynes@539 | 664 | |
nkeynes@359 | 665 | /** |
nkeynes@995 | 666 | * Write the block trailer (exception handling block) |
nkeynes@995 | 667 | */ |
nkeynes@995 | 668 | void sh4_translate_end_block( sh4addr_t pc ) { |
nkeynes@995 | 669 | if( sh4_x86.branch_taken == FALSE ) { |
nkeynes@995 | 670 | // Didn't exit unconditionally already, so write the termination here |
nkeynes@995 | 671 | exit_block_rel( pc, pc ); |
nkeynes@995 | 672 | } |
nkeynes@995 | 673 | if( sh4_x86.backpatch_posn != 0 ) { |
nkeynes@995 | 674 | unsigned int i; |
nkeynes@995 | 675 | // Exception raised - cleanup and exit |
nkeynes@995 | 676 | uint8_t *end_ptr = xlat_output; |
nkeynes@995 | 677 | MOVL_r32_r32( REG_EDX, REG_ECX ); |
nkeynes@995 | 678 | ADDL_r32_r32( REG_EDX, REG_ECX ); |
nkeynes@995 | 679 | ADDL_r32_rbpdisp( REG_ECX, R_SPC ); |
nkeynes@995 | 680 | MOVL_moffptr_eax( &sh4_cpu_period ); |
nkeynes@995 | 681 | MULL_r32( REG_EDX ); |
nkeynes@995 | 682 | ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 683 | exit_block(); |
nkeynes@995 | 684 | |
nkeynes@995 | 685 | for( i=0; i< sh4_x86.backpatch_posn; i++ ) { |
nkeynes@995 | 686 | uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset]; |
nkeynes@995 | 687 | if( sh4_x86.backpatch_list[i].exc_code < 0 ) { |
nkeynes@995 | 688 | if( sh4_x86.backpatch_list[i].exc_code == -2 ) { |
nkeynes@995 | 689 | *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; |
nkeynes@995 | 690 | } else { |
nkeynes@995 | 691 | *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4; |
nkeynes@995 | 692 | } |
nkeynes@995 | 693 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX ); |
nkeynes@995 | 694 | int rel = end_ptr - xlat_output; |
nkeynes@995 | 695 | JMP_prerel(rel); |
nkeynes@995 | 696 | } else { |
nkeynes@995 | 697 | *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4; |
nkeynes@995 | 698 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 ); |
nkeynes@995 | 699 | CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 ); |
nkeynes@995 | 700 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX ); |
nkeynes@995 | 701 | int rel = end_ptr - xlat_output; |
nkeynes@995 | 702 | JMP_prerel(rel); |
nkeynes@995 | 703 | } |
nkeynes@995 | 704 | } |
nkeynes@995 | 705 | } |
nkeynes@995 | 706 | } |
nkeynes@539 | 707 | |
nkeynes@359 | 708 | /** |
nkeynes@359 | 709 | * Translate a single instruction. Delayed branches are handled specially |
nkeynes@359 | 710 | * by translating both branch and delayed instruction as a single unit (as |
nkeynes@359 | 711 | * |
nkeynes@586 | 712 | * The instruction MUST be in the icache (assert check) |
nkeynes@359 | 713 | * |
nkeynes@359 | 714 | * @return true if the instruction marks the end of a basic block |
nkeynes@359 | 715 | * (eg a branch or |
nkeynes@359 | 716 | */ |
nkeynes@590 | 717 | uint32_t sh4_translate_instruction( sh4vma_t pc ) |
nkeynes@359 | 718 | { |
nkeynes@388 | 719 | uint32_t ir; |
nkeynes@586 | 720 | /* Read instruction from icache */ |
nkeynes@586 | 721 | assert( IS_IN_ICACHE(pc) ); |
nkeynes@586 | 722 | ir = *(uint16_t *)GET_ICACHE_PTR(pc); |
nkeynes@586 | 723 | |
nkeynes@586 | 724 | if( !sh4_x86.in_delay_slot ) { |
nkeynes@596 | 725 | sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 ); |
nkeynes@388 | 726 | } |
nkeynes@1003 | 727 | |
nkeynes@1003 | 728 | /* check for breakpoints at this pc */ |
nkeynes@1003 | 729 | for( int i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@1003 | 730 | if( sh4_breakpoints[i].address == pc ) { |
nkeynes@1003 | 731 | sh4_translate_emit_breakpoint(pc); |
nkeynes@1003 | 732 | break; |
nkeynes@1003 | 733 | } |
nkeynes@571 | 734 | } |
nkeynes@359 | 735 | %% |
nkeynes@359 | 736 | /* ALU operations */ |
nkeynes@359 | 737 | ADD Rm, Rn {: |
nkeynes@671 | 738 | COUNT_INST(I_ADD); |
nkeynes@991 | 739 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 740 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 741 | ADDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 742 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 743 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 744 | :} |
nkeynes@359 | 745 | ADD #imm, Rn {: |
nkeynes@671 | 746 | COUNT_INST(I_ADDI); |
nkeynes@991 | 747 | ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 748 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 749 | :} |
nkeynes@359 | 750 | ADDC Rm, Rn {: |
nkeynes@671 | 751 | COUNT_INST(I_ADDC); |
nkeynes@417 | 752 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@911 | 753 | LDC_t(); |
nkeynes@417 | 754 | } |
nkeynes@991 | 755 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 756 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 757 | ADCL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 758 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 759 | SETC_t(); |
nkeynes@417 | 760 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 761 | :} |
nkeynes@359 | 762 | ADDV Rm, Rn {: |
nkeynes@671 | 763 | COUNT_INST(I_ADDV); |
nkeynes@991 | 764 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 765 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 766 | ADDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 767 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 768 | SETO_t(); |
nkeynes@417 | 769 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 770 | :} |
nkeynes@359 | 771 | AND Rm, Rn {: |
nkeynes@671 | 772 | COUNT_INST(I_AND); |
nkeynes@991 | 773 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 774 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 775 | ANDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 776 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 777 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 778 | :} |
nkeynes@359 | 779 | AND #imm, R0 {: |
nkeynes@671 | 780 | COUNT_INST(I_ANDI); |
nkeynes@991 | 781 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 782 | ANDL_imms_r32(imm, REG_EAX); |
nkeynes@991 | 783 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 784 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 785 | :} |
nkeynes@359 | 786 | AND.B #imm, @(R0, GBR) {: |
nkeynes@671 | 787 | COUNT_INST(I_ANDB); |
nkeynes@991 | 788 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 789 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 790 | MOVL_r32_rspdisp(REG_EAX, 0); |
nkeynes@991 | 791 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 792 | MOVL_rspdisp_r32(0, REG_EAX); |
nkeynes@991 | 793 | ANDL_imms_r32(imm, REG_EDX ); |
nkeynes@991 | 794 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 795 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 796 | :} |
nkeynes@359 | 797 | CMP/EQ Rm, Rn {: |
nkeynes@671 | 798 | COUNT_INST(I_CMPEQ); |
nkeynes@991 | 799 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 800 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 801 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 802 | SETE_t(); |
nkeynes@417 | 803 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 804 | :} |
nkeynes@359 | 805 | CMP/EQ #imm, R0 {: |
nkeynes@671 | 806 | COUNT_INST(I_CMPEQI); |
nkeynes@991 | 807 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 808 | CMPL_imms_r32(imm, REG_EAX); |
nkeynes@359 | 809 | SETE_t(); |
nkeynes@417 | 810 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 811 | :} |
nkeynes@359 | 812 | CMP/GE Rm, Rn {: |
nkeynes@671 | 813 | COUNT_INST(I_CMPGE); |
nkeynes@991 | 814 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 815 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 816 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 817 | SETGE_t(); |
nkeynes@417 | 818 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 819 | :} |
nkeynes@359 | 820 | CMP/GT Rm, Rn {: |
nkeynes@671 | 821 | COUNT_INST(I_CMPGT); |
nkeynes@991 | 822 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 823 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 824 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 825 | SETG_t(); |
nkeynes@417 | 826 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 827 | :} |
nkeynes@359 | 828 | CMP/HI Rm, Rn {: |
nkeynes@671 | 829 | COUNT_INST(I_CMPHI); |
nkeynes@991 | 830 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 831 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 832 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 833 | SETA_t(); |
nkeynes@417 | 834 | sh4_x86.tstate = TSTATE_A; |
nkeynes@359 | 835 | :} |
nkeynes@359 | 836 | CMP/HS Rm, Rn {: |
nkeynes@671 | 837 | COUNT_INST(I_CMPHS); |
nkeynes@991 | 838 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 839 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 840 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 841 | SETAE_t(); |
nkeynes@417 | 842 | sh4_x86.tstate = TSTATE_AE; |
nkeynes@359 | 843 | :} |
nkeynes@359 | 844 | CMP/PL Rn {: |
nkeynes@671 | 845 | COUNT_INST(I_CMPPL); |
nkeynes@991 | 846 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 847 | CMPL_imms_r32( 0, REG_EAX ); |
nkeynes@359 | 848 | SETG_t(); |
nkeynes@417 | 849 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 850 | :} |
nkeynes@359 | 851 | CMP/PZ Rn {: |
nkeynes@671 | 852 | COUNT_INST(I_CMPPZ); |
nkeynes@991 | 853 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 854 | CMPL_imms_r32( 0, REG_EAX ); |
nkeynes@359 | 855 | SETGE_t(); |
nkeynes@417 | 856 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 857 | :} |
nkeynes@361 | 858 | CMP/STR Rm, Rn {: |
nkeynes@671 | 859 | COUNT_INST(I_CMPSTR); |
nkeynes@991 | 860 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 861 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 862 | XORL_r32_r32( REG_ECX, REG_EAX ); |
nkeynes@991 | 863 | TESTB_r8_r8( REG_AL, REG_AL ); |
nkeynes@991 | 864 | JE_label(target1); |
nkeynes@991 | 865 | TESTB_r8_r8( REG_AH, REG_AH ); |
nkeynes@991 | 866 | JE_label(target2); |
nkeynes@991 | 867 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 868 | TESTB_r8_r8( REG_AL, REG_AL ); |
nkeynes@991 | 869 | JE_label(target3); |
nkeynes@991 | 870 | TESTB_r8_r8( REG_AH, REG_AH ); |
nkeynes@380 | 871 | JMP_TARGET(target1); |
nkeynes@380 | 872 | JMP_TARGET(target2); |
nkeynes@380 | 873 | JMP_TARGET(target3); |
nkeynes@368 | 874 | SETE_t(); |
nkeynes@417 | 875 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 876 | :} |
nkeynes@361 | 877 | DIV0S Rm, Rn {: |
nkeynes@671 | 878 | COUNT_INST(I_DIV0S); |
nkeynes@991 | 879 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 880 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 881 | SHRL_imm_r32( 31, REG_EAX ); |
nkeynes@991 | 882 | SHRL_imm_r32( 31, REG_ECX ); |
nkeynes@995 | 883 | MOVL_r32_rbpdisp( REG_EAX, R_M ); |
nkeynes@995 | 884 | MOVL_r32_rbpdisp( REG_ECX, R_Q ); |
nkeynes@991 | 885 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@386 | 886 | SETNE_t(); |
nkeynes@417 | 887 | sh4_x86.tstate = TSTATE_NE; |
nkeynes@361 | 888 | :} |
nkeynes@361 | 889 | DIV0U {: |
nkeynes@671 | 890 | COUNT_INST(I_DIV0U); |
nkeynes@991 | 891 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@995 | 892 | MOVL_r32_rbpdisp( REG_EAX, R_Q ); |
nkeynes@995 | 893 | MOVL_r32_rbpdisp( REG_EAX, R_M ); |
nkeynes@995 | 894 | MOVL_r32_rbpdisp( REG_EAX, R_T ); |
nkeynes@417 | 895 | sh4_x86.tstate = TSTATE_C; // works for DIV1 |
nkeynes@361 | 896 | :} |
nkeynes@386 | 897 | DIV1 Rm, Rn {: |
nkeynes@671 | 898 | COUNT_INST(I_DIV1); |
nkeynes@995 | 899 | MOVL_rbpdisp_r32( R_M, REG_ECX ); |
nkeynes@991 | 900 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 901 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 902 | LDC_t(); |
nkeynes@417 | 903 | } |
nkeynes@991 | 904 | RCLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 905 | SETC_r8( REG_DL ); // Q' |
nkeynes@991 | 906 | CMPL_rbpdisp_r32( R_Q, REG_ECX ); |
nkeynes@991 | 907 | JE_label(mqequal); |
nkeynes@991 | 908 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 909 | JMP_label(end); |
nkeynes@380 | 910 | JMP_TARGET(mqequal); |
nkeynes@991 | 911 | SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@386 | 912 | JMP_TARGET(end); |
nkeynes@991 | 913 | store_reg( REG_EAX, Rn ); // Done with Rn now |
nkeynes@991 | 914 | SETC_r8(REG_AL); // tmp1 |
nkeynes@991 | 915 | XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1 |
nkeynes@991 | 916 | XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M |
nkeynes@995 | 917 | MOVL_r32_rbpdisp( REG_ECX, R_Q ); |
nkeynes@991 | 918 | XORL_imms_r32( 1, REG_AL ); // T = !Q' |
nkeynes@991 | 919 | MOVZXL_r8_r32( REG_AL, REG_EAX ); |
nkeynes@995 | 920 | MOVL_r32_rbpdisp( REG_EAX, R_T ); |
nkeynes@417 | 921 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 922 | :} |
nkeynes@361 | 923 | DMULS.L Rm, Rn {: |
nkeynes@671 | 924 | COUNT_INST(I_DMULS); |
nkeynes@991 | 925 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 926 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 927 | IMULL_r32(REG_ECX); |
nkeynes@995 | 928 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@995 | 929 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 930 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 931 | :} |
nkeynes@361 | 932 | DMULU.L Rm, Rn {: |
nkeynes@671 | 933 | COUNT_INST(I_DMULU); |
nkeynes@991 | 934 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 935 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 936 | MULL_r32(REG_ECX); |
nkeynes@995 | 937 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@995 | 938 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 939 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 940 | :} |
nkeynes@359 | 941 | DT Rn {: |
nkeynes@671 | 942 | COUNT_INST(I_DT); |
nkeynes@991 | 943 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 944 | ADDL_imms_r32( -1, REG_EAX ); |
nkeynes@991 | 945 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 946 | SETE_t(); |
nkeynes@417 | 947 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 948 | :} |
nkeynes@359 | 949 | EXTS.B Rm, Rn {: |
nkeynes@671 | 950 | COUNT_INST(I_EXTSB); |
nkeynes@991 | 951 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 952 | MOVSXL_r8_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 953 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 954 | :} |
nkeynes@361 | 955 | EXTS.W Rm, Rn {: |
nkeynes@671 | 956 | COUNT_INST(I_EXTSW); |
nkeynes@991 | 957 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 958 | MOVSXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 959 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 960 | :} |
nkeynes@361 | 961 | EXTU.B Rm, Rn {: |
nkeynes@671 | 962 | COUNT_INST(I_EXTUB); |
nkeynes@991 | 963 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 964 | MOVZXL_r8_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 965 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 966 | :} |
nkeynes@361 | 967 | EXTU.W Rm, Rn {: |
nkeynes@671 | 968 | COUNT_INST(I_EXTUW); |
nkeynes@991 | 969 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 970 | MOVZXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 971 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 972 | :} |
nkeynes@586 | 973 | MAC.L @Rm+, @Rn+ {: |
nkeynes@671 | 974 | COUNT_INST(I_MACL); |
nkeynes@586 | 975 | if( Rm == Rn ) { |
nkeynes@991 | 976 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 977 | check_ralign32( REG_EAX ); |
nkeynes@991 | 978 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 979 | MOVL_r32_rspdisp(REG_EAX, 0); |
nkeynes@991 | 980 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 981 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 982 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 983 | ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) ); |
nkeynes@586 | 984 | } else { |
nkeynes@991 | 985 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 986 | check_ralign32( REG_EAX ); |
nkeynes@991 | 987 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 988 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 989 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 990 | check_ralign32( REG_EAX ); |
nkeynes@991 | 991 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 992 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@991 | 993 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@586 | 994 | } |
nkeynes@939 | 995 | |
nkeynes@991 | 996 | IMULL_rspdisp( 0 ); |
nkeynes@991 | 997 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@991 | 998 | ADCL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@386 | 999 | |
nkeynes@995 | 1000 | MOVL_rbpdisp_r32( R_S, REG_ECX ); |
nkeynes@991 | 1001 | TESTL_r32_r32(REG_ECX, REG_ECX); |
nkeynes@991 | 1002 | JE_label( nosat ); |
nkeynes@995 | 1003 | CALL_ptr( signsat48 ); |
nkeynes@386 | 1004 | JMP_TARGET( nosat ); |
nkeynes@417 | 1005 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 1006 | :} |
nkeynes@386 | 1007 | MAC.W @Rm+, @Rn+ {: |
nkeynes@671 | 1008 | COUNT_INST(I_MACW); |
nkeynes@586 | 1009 | if( Rm == Rn ) { |
nkeynes@991 | 1010 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1011 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1012 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1013 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1014 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1015 | LEAL_r32disp_r32( REG_EAX, 2, REG_EAX ); |
nkeynes@991 | 1016 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1017 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@586 | 1018 | // Note translate twice in case of page boundaries. Maybe worth |
nkeynes@586 | 1019 | // adding a page-boundary check to skip the second translation |
nkeynes@586 | 1020 | } else { |
nkeynes@991 | 1021 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1022 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1023 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1024 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1025 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1026 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1027 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1028 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) ); |
nkeynes@991 | 1029 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@586 | 1030 | } |
nkeynes@991 | 1031 | IMULL_rspdisp( 0 ); |
nkeynes@995 | 1032 | MOVL_rbpdisp_r32( R_S, REG_ECX ); |
nkeynes@991 | 1033 | TESTL_r32_r32( REG_ECX, REG_ECX ); |
nkeynes@991 | 1034 | JE_label( nosat ); |
nkeynes@386 | 1035 | |
nkeynes@991 | 1036 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 1037 | JNO_label( end ); // 2 |
nkeynes@995 | 1038 | MOVL_imm32_r32( 1, REG_EDX ); // 5 |
nkeynes@995 | 1039 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); // 6 |
nkeynes@991 | 1040 | JS_label( positive ); // 2 |
nkeynes@995 | 1041 | MOVL_imm32_r32( 0x80000000, REG_EAX );// 5 |
nkeynes@995 | 1042 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 1043 | JMP_label(end2); // 2 |
nkeynes@386 | 1044 | |
nkeynes@386 | 1045 | JMP_TARGET(positive); |
nkeynes@995 | 1046 | MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5 |
nkeynes@995 | 1047 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 1048 | JMP_label(end3); // 2 |
nkeynes@386 | 1049 | |
nkeynes@386 | 1050 | JMP_TARGET(nosat); |
nkeynes@991 | 1051 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 1052 | ADCL_r32_rbpdisp( REG_EDX, R_MACH ); // 6 |
nkeynes@386 | 1053 | JMP_TARGET(end); |
nkeynes@386 | 1054 | JMP_TARGET(end2); |
nkeynes@386 | 1055 | JMP_TARGET(end3); |
nkeynes@417 | 1056 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 1057 | :} |
nkeynes@359 | 1058 | MOVT Rn {: |
nkeynes@671 | 1059 | COUNT_INST(I_MOVT); |
nkeynes@995 | 1060 | MOVL_rbpdisp_r32( R_T, REG_EAX ); |
nkeynes@991 | 1061 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1062 | :} |
nkeynes@361 | 1063 | MUL.L Rm, Rn {: |
nkeynes@671 | 1064 | COUNT_INST(I_MULL); |
nkeynes@991 | 1065 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1066 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1067 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1068 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1069 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1070 | :} |
nkeynes@374 | 1071 | MULS.W Rm, Rn {: |
nkeynes@671 | 1072 | COUNT_INST(I_MULSW); |
nkeynes@995 | 1073 | MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX ); |
nkeynes@995 | 1074 | MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX ); |
nkeynes@991 | 1075 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1076 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1077 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1078 | :} |
nkeynes@374 | 1079 | MULU.W Rm, Rn {: |
nkeynes@671 | 1080 | COUNT_INST(I_MULUW); |
nkeynes@995 | 1081 | MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX ); |
nkeynes@995 | 1082 | MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX ); |
nkeynes@991 | 1083 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1084 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1085 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1086 | :} |
nkeynes@359 | 1087 | NEG Rm, Rn {: |
nkeynes@671 | 1088 | COUNT_INST(I_NEG); |
nkeynes@991 | 1089 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1090 | NEGL_r32( REG_EAX ); |
nkeynes@991 | 1091 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1092 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1093 | :} |
nkeynes@359 | 1094 | NEGC Rm, Rn {: |
nkeynes@671 | 1095 | COUNT_INST(I_NEGC); |
nkeynes@991 | 1096 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1097 | XORL_r32_r32( REG_ECX, REG_ECX ); |
nkeynes@359 | 1098 | LDC_t(); |
nkeynes@991 | 1099 | SBBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1100 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 1101 | SETC_t(); |
nkeynes@417 | 1102 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1103 | :} |
nkeynes@359 | 1104 | NOT Rm, Rn {: |
nkeynes@671 | 1105 | COUNT_INST(I_NOT); |
nkeynes@991 | 1106 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1107 | NOTL_r32( REG_EAX ); |
nkeynes@991 | 1108 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1109 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1110 | :} |
nkeynes@359 | 1111 | OR Rm, Rn {: |
nkeynes@671 | 1112 | COUNT_INST(I_OR); |
nkeynes@991 | 1113 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1114 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1115 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1116 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1117 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1118 | :} |
nkeynes@359 | 1119 | OR #imm, R0 {: |
nkeynes@671 | 1120 | COUNT_INST(I_ORI); |
nkeynes@991 | 1121 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1122 | ORL_imms_r32(imm, REG_EAX); |
nkeynes@991 | 1123 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1124 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1125 | :} |
nkeynes@374 | 1126 | OR.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1127 | COUNT_INST(I_ORB); |
nkeynes@991 | 1128 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1129 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1130 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1131 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1132 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1133 | ORL_imms_r32(imm, REG_EDX ); |
nkeynes@991 | 1134 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1135 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1136 | :} |
nkeynes@359 | 1137 | ROTCL Rn {: |
nkeynes@671 | 1138 | COUNT_INST(I_ROTCL); |
nkeynes@991 | 1139 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 1140 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1141 | LDC_t(); |
nkeynes@417 | 1142 | } |
nkeynes@991 | 1143 | RCLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1144 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1145 | SETC_t(); |
nkeynes@417 | 1146 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1147 | :} |
nkeynes@359 | 1148 | ROTCR Rn {: |
nkeynes@671 | 1149 | COUNT_INST(I_ROTCR); |
nkeynes@991 | 1150 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 1151 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1152 | LDC_t(); |
nkeynes@417 | 1153 | } |
nkeynes@991 | 1154 | RCRL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1155 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1156 | SETC_t(); |
nkeynes@417 | 1157 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1158 | :} |
nkeynes@359 | 1159 | ROTL Rn {: |
nkeynes@671 | 1160 | COUNT_INST(I_ROTL); |
nkeynes@991 | 1161 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1162 | ROLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1163 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1164 | SETC_t(); |
nkeynes@417 | 1165 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1166 | :} |
nkeynes@359 | 1167 | ROTR Rn {: |
nkeynes@671 | 1168 | COUNT_INST(I_ROTR); |
nkeynes@991 | 1169 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1170 | RORL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1171 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1172 | SETC_t(); |
nkeynes@417 | 1173 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1174 | :} |
nkeynes@359 | 1175 | SHAD Rm, Rn {: |
nkeynes@671 | 1176 | COUNT_INST(I_SHAD); |
nkeynes@359 | 1177 | /* Annoyingly enough, not directly convertible */ |
nkeynes@991 | 1178 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1179 | load_reg( REG_ECX, Rm ); |
nkeynes@991 | 1180 | CMPL_imms_r32( 0, REG_ECX ); |
nkeynes@991 | 1181 | JGE_label(doshl); |
nkeynes@361 | 1182 | |
nkeynes@991 | 1183 | NEGL_r32( REG_ECX ); // 2 |
nkeynes@991 | 1184 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1185 | JE_label(emptysar); // 2 |
nkeynes@991 | 1186 | SARL_cl_r32( REG_EAX ); // 2 |
nkeynes@991 | 1187 | JMP_label(end); // 2 |
nkeynes@386 | 1188 | |
nkeynes@386 | 1189 | JMP_TARGET(emptysar); |
nkeynes@991 | 1190 | SARL_imm_r32(31, REG_EAX ); // 3 |
nkeynes@991 | 1191 | JMP_label(end2); |
nkeynes@382 | 1192 | |
nkeynes@380 | 1193 | JMP_TARGET(doshl); |
nkeynes@991 | 1194 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1195 | SHLL_cl_r32( REG_EAX ); // 2 |
nkeynes@380 | 1196 | JMP_TARGET(end); |
nkeynes@386 | 1197 | JMP_TARGET(end2); |
nkeynes@991 | 1198 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1199 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1200 | :} |
nkeynes@359 | 1201 | SHLD Rm, Rn {: |
nkeynes@671 | 1202 | COUNT_INST(I_SHLD); |
nkeynes@991 | 1203 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1204 | load_reg( REG_ECX, Rm ); |
nkeynes@991 | 1205 | CMPL_imms_r32( 0, REG_ECX ); |
nkeynes@991 | 1206 | JGE_label(doshl); |
nkeynes@368 | 1207 | |
nkeynes@991 | 1208 | NEGL_r32( REG_ECX ); // 2 |
nkeynes@991 | 1209 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1210 | JE_label(emptyshr ); |
nkeynes@991 | 1211 | SHRL_cl_r32( REG_EAX ); // 2 |
nkeynes@991 | 1212 | JMP_label(end); // 2 |
nkeynes@386 | 1213 | |
nkeynes@386 | 1214 | JMP_TARGET(emptyshr); |
nkeynes@991 | 1215 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 1216 | JMP_label(end2); |
nkeynes@382 | 1217 | |
nkeynes@382 | 1218 | JMP_TARGET(doshl); |
nkeynes@991 | 1219 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1220 | SHLL_cl_r32( REG_EAX ); // 2 |
nkeynes@382 | 1221 | JMP_TARGET(end); |
nkeynes@386 | 1222 | JMP_TARGET(end2); |
nkeynes@991 | 1223 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1224 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1225 | :} |
nkeynes@359 | 1226 | SHAL Rn {: |
nkeynes@671 | 1227 | COUNT_INST(I_SHAL); |
nkeynes@991 | 1228 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1229 | SHLL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1230 | SETC_t(); |
nkeynes@991 | 1231 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1232 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1233 | :} |
nkeynes@359 | 1234 | SHAR Rn {: |
nkeynes@671 | 1235 | COUNT_INST(I_SHAR); |
nkeynes@991 | 1236 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1237 | SARL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1238 | SETC_t(); |
nkeynes@991 | 1239 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1240 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1241 | :} |
nkeynes@359 | 1242 | SHLL Rn {: |
nkeynes@671 | 1243 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1244 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1245 | SHLL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1246 | SETC_t(); |
nkeynes@991 | 1247 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1248 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1249 | :} |
nkeynes@359 | 1250 | SHLL2 Rn {: |
nkeynes@671 | 1251 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1252 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1253 | SHLL_imm_r32( 2, REG_EAX ); |
nkeynes@991 | 1254 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1255 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1256 | :} |
nkeynes@359 | 1257 | SHLL8 Rn {: |
nkeynes@671 | 1258 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1259 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1260 | SHLL_imm_r32( 8, REG_EAX ); |
nkeynes@991 | 1261 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1262 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1263 | :} |
nkeynes@359 | 1264 | SHLL16 Rn {: |
nkeynes@671 | 1265 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1266 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1267 | SHLL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1268 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1269 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1270 | :} |
nkeynes@359 | 1271 | SHLR Rn {: |
nkeynes@671 | 1272 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1273 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1274 | SHRL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1275 | SETC_t(); |
nkeynes@991 | 1276 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1277 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1278 | :} |
nkeynes@359 | 1279 | SHLR2 Rn {: |
nkeynes@671 | 1280 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1281 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1282 | SHRL_imm_r32( 2, REG_EAX ); |
nkeynes@991 | 1283 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1284 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1285 | :} |
nkeynes@359 | 1286 | SHLR8 Rn {: |
nkeynes@671 | 1287 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1288 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1289 | SHRL_imm_r32( 8, REG_EAX ); |
nkeynes@991 | 1290 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1291 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1292 | :} |
nkeynes@359 | 1293 | SHLR16 Rn {: |
nkeynes@671 | 1294 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1295 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1296 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1297 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1298 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1299 | :} |
nkeynes@359 | 1300 | SUB Rm, Rn {: |
nkeynes@671 | 1301 | COUNT_INST(I_SUB); |
nkeynes@991 | 1302 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1303 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1304 | SUBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1305 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1306 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1307 | :} |
nkeynes@359 | 1308 | SUBC Rm, Rn {: |
nkeynes@671 | 1309 | COUNT_INST(I_SUBC); |
nkeynes@991 | 1310 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1311 | load_reg( REG_ECX, Rn ); |
nkeynes@417 | 1312 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1313 | LDC_t(); |
nkeynes@417 | 1314 | } |
nkeynes@991 | 1315 | SBBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1316 | store_reg( REG_ECX, Rn ); |
nkeynes@394 | 1317 | SETC_t(); |
nkeynes@417 | 1318 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1319 | :} |
nkeynes@359 | 1320 | SUBV Rm, Rn {: |
nkeynes@671 | 1321 | COUNT_INST(I_SUBV); |
nkeynes@991 | 1322 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1323 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1324 | SUBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1325 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 1326 | SETO_t(); |
nkeynes@417 | 1327 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 1328 | :} |
nkeynes@359 | 1329 | SWAP.B Rm, Rn {: |
nkeynes@671 | 1330 | COUNT_INST(I_SWAPB); |
nkeynes@991 | 1331 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1332 | XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS |
nkeynes@991 | 1333 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1334 | :} |
nkeynes@359 | 1335 | SWAP.W Rm, Rn {: |
nkeynes@671 | 1336 | COUNT_INST(I_SWAPB); |
nkeynes@991 | 1337 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1338 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1339 | SHLL_imm_r32( 16, REG_ECX ); |
nkeynes@991 | 1340 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1341 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1342 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1343 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1344 | :} |
nkeynes@361 | 1345 | TAS.B @Rn {: |
nkeynes@671 | 1346 | COUNT_INST(I_TASB); |
nkeynes@991 | 1347 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1348 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1349 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1350 | TESTB_r8_r8( REG_DL, REG_DL ); |
nkeynes@361 | 1351 | SETE_t(); |
nkeynes@991 | 1352 | ORB_imms_r8( 0x80, REG_DL ); |
nkeynes@991 | 1353 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1354 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1355 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1356 | :} |
nkeynes@361 | 1357 | TST Rm, Rn {: |
nkeynes@671 | 1358 | COUNT_INST(I_TST); |
nkeynes@991 | 1359 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1360 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1361 | TESTL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@361 | 1362 | SETE_t(); |
nkeynes@417 | 1363 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 1364 | :} |
nkeynes@368 | 1365 | TST #imm, R0 {: |
nkeynes@671 | 1366 | COUNT_INST(I_TSTI); |
nkeynes@991 | 1367 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1368 | TESTL_imms_r32( imm, REG_EAX ); |
nkeynes@368 | 1369 | SETE_t(); |
nkeynes@417 | 1370 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 1371 | :} |
nkeynes@368 | 1372 | TST.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1373 | COUNT_INST(I_TSTB); |
nkeynes@991 | 1374 | load_reg( REG_EAX, 0); |
nkeynes@991 | 1375 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1376 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1377 | TESTB_imms_r8( imm, REG_AL ); |
nkeynes@368 | 1378 | SETE_t(); |
nkeynes@417 | 1379 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 1380 | :} |
nkeynes@359 | 1381 | XOR Rm, Rn {: |
nkeynes@671 | 1382 | COUNT_INST(I_XOR); |
nkeynes@991 | 1383 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1384 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1385 | XORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1386 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1387 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1388 | :} |
nkeynes@359 | 1389 | XOR #imm, R0 {: |
nkeynes@671 | 1390 | COUNT_INST(I_XORI); |
nkeynes@991 | 1391 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1392 | XORL_imms_r32( imm, REG_EAX ); |
nkeynes@991 | 1393 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1394 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1395 | :} |
nkeynes@359 | 1396 | XOR.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1397 | COUNT_INST(I_XORB); |
nkeynes@991 | 1398 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1399 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1400 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1401 | MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX); |
nkeynes@991 | 1402 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1403 | XORL_imms_r32( imm, REG_EDX ); |
nkeynes@991 | 1404 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1405 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1406 | :} |
nkeynes@361 | 1407 | XTRCT Rm, Rn {: |
nkeynes@671 | 1408 | COUNT_INST(I_XTRCT); |
nkeynes@991 | 1409 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1410 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1411 | SHLL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1412 | SHRL_imm_r32( 16, REG_ECX ); |
nkeynes@991 | 1413 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1414 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1415 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1416 | :} |
nkeynes@359 | 1417 | |
nkeynes@359 | 1418 | /* Data move instructions */ |
nkeynes@359 | 1419 | MOV Rm, Rn {: |
nkeynes@671 | 1420 | COUNT_INST(I_MOV); |
nkeynes@991 | 1421 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1422 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1423 | :} |
nkeynes@359 | 1424 | MOV #imm, Rn {: |
nkeynes@671 | 1425 | COUNT_INST(I_MOVI); |
nkeynes@995 | 1426 | MOVL_imm32_r32( imm, REG_EAX ); |
nkeynes@991 | 1427 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1428 | :} |
nkeynes@359 | 1429 | MOV.B Rm, @Rn {: |
nkeynes@671 | 1430 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1431 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1432 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1433 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1434 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1435 | :} |
nkeynes@359 | 1436 | MOV.B Rm, @-Rn {: |
nkeynes@671 | 1437 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1438 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1439 | LEAL_r32disp_r32( REG_EAX, -1, REG_EAX ); |
nkeynes@991 | 1440 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1441 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1442 | ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1443 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1444 | :} |
nkeynes@359 | 1445 | MOV.B Rm, @(R0, Rn) {: |
nkeynes@671 | 1446 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1447 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1448 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1449 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1450 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1451 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1452 | :} |
nkeynes@359 | 1453 | MOV.B R0, @(disp, GBR) {: |
nkeynes@671 | 1454 | COUNT_INST(I_MOVB); |
nkeynes@995 | 1455 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1456 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1457 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1458 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1459 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1460 | :} |
nkeynes@359 | 1461 | MOV.B R0, @(disp, Rn) {: |
nkeynes@671 | 1462 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1463 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1464 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1465 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1466 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1467 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1468 | :} |
nkeynes@359 | 1469 | MOV.B @Rm, Rn {: |
nkeynes@671 | 1470 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1471 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1472 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1473 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1474 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1475 | :} |
nkeynes@359 | 1476 | MOV.B @Rm+, Rn {: |
nkeynes@671 | 1477 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1478 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1479 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@939 | 1480 | if( Rm != Rn ) { |
nkeynes@991 | 1481 | ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1482 | } |
nkeynes@991 | 1483 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1484 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1485 | :} |
nkeynes@359 | 1486 | MOV.B @(R0, Rm), Rn {: |
nkeynes@671 | 1487 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1488 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1489 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1490 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1491 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1492 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1493 | :} |
nkeynes@359 | 1494 | MOV.B @(disp, GBR), R0 {: |
nkeynes@671 | 1495 | COUNT_INST(I_MOVB); |
nkeynes@995 | 1496 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1497 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1498 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1499 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1500 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1501 | :} |
nkeynes@359 | 1502 | MOV.B @(disp, Rm), R0 {: |
nkeynes@671 | 1503 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1504 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1505 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1506 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1507 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1508 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1509 | :} |
nkeynes@374 | 1510 | MOV.L Rm, @Rn {: |
nkeynes@671 | 1511 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1512 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1513 | check_walign32(REG_EAX); |
nkeynes@991 | 1514 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1515 | ANDL_imms_r32( 0xFC000000, REG_ECX ); |
nkeynes@991 | 1516 | CMPL_imms_r32( 0xE0000000, REG_ECX ); |
nkeynes@991 | 1517 | JNE_label( notsq ); |
nkeynes@991 | 1518 | ANDL_imms_r32( 0x3C, REG_EAX ); |
nkeynes@991 | 1519 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1520 | MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); |
nkeynes@991 | 1521 | JMP_label(end); |
nkeynes@930 | 1522 | JMP_TARGET(notsq); |
nkeynes@991 | 1523 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1524 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@930 | 1525 | JMP_TARGET(end); |
nkeynes@417 | 1526 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1527 | :} |
nkeynes@361 | 1528 | MOV.L Rm, @-Rn {: |
nkeynes@671 | 1529 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1530 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1531 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@991 | 1532 | check_walign32( REG_EAX ); |
nkeynes@991 | 1533 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1534 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 1535 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1536 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1537 | :} |
nkeynes@361 | 1538 | MOV.L Rm, @(R0, Rn) {: |
nkeynes@671 | 1539 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1540 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1541 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1542 | check_walign32( REG_EAX ); |
nkeynes@991 | 1543 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1544 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1545 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1546 | :} |
nkeynes@361 | 1547 | MOV.L R0, @(disp, GBR) {: |
nkeynes@671 | 1548 | COUNT_INST(I_MOVL); |
nkeynes@995 | 1549 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1550 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1551 | check_walign32( REG_EAX ); |
nkeynes@991 | 1552 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1553 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1554 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1555 | :} |
nkeynes@361 | 1556 | MOV.L Rm, @(disp, Rn) {: |
nkeynes@671 | 1557 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1558 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1559 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1560 | check_walign32( REG_EAX ); |
nkeynes@991 | 1561 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1562 | ANDL_imms_r32( 0xFC000000, REG_ECX ); |
nkeynes@991 | 1563 | CMPL_imms_r32( 0xE0000000, REG_ECX ); |
nkeynes@991 | 1564 | JNE_label( notsq ); |
nkeynes@991 | 1565 | ANDL_imms_r32( 0x3C, REG_EAX ); |
nkeynes@991 | 1566 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1567 | MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); |
nkeynes@991 | 1568 | JMP_label(end); |
nkeynes@930 | 1569 | JMP_TARGET(notsq); |
nkeynes@991 | 1570 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1571 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@930 | 1572 | JMP_TARGET(end); |
nkeynes@417 | 1573 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1574 | :} |
nkeynes@361 | 1575 | MOV.L @Rm, Rn {: |
nkeynes@671 | 1576 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1577 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1578 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1579 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1580 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1581 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1582 | :} |
nkeynes@361 | 1583 | MOV.L @Rm+, Rn {: |
nkeynes@671 | 1584 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1585 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1586 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1587 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@939 | 1588 | if( Rm != Rn ) { |
nkeynes@991 | 1589 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1590 | } |
nkeynes@991 | 1591 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1592 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1593 | :} |
nkeynes@361 | 1594 | MOV.L @(R0, Rm), Rn {: |
nkeynes@671 | 1595 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1596 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1597 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1598 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1599 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1600 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1601 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1602 | :} |
nkeynes@361 | 1603 | MOV.L @(disp, GBR), R0 {: |
nkeynes@671 | 1604 | COUNT_INST(I_MOVL); |
nkeynes@995 | 1605 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1606 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1607 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1608 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1609 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1610 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1611 | :} |
nkeynes@361 | 1612 | MOV.L @(disp, PC), Rn {: |
nkeynes@671 | 1613 | COUNT_INST(I_MOVLPC); |
nkeynes@374 | 1614 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1615 | SLOTILLEGAL(); |
nkeynes@374 | 1616 | } else { |
nkeynes@388 | 1617 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4; |
nkeynes@586 | 1618 | if( IS_IN_ICACHE(target) ) { |
nkeynes@586 | 1619 | // If the target address is in the same page as the code, it's |
nkeynes@586 | 1620 | // pretty safe to just ref it directly and circumvent the whole |
nkeynes@586 | 1621 | // memory subsystem. (this is a big performance win) |
nkeynes@586 | 1622 | |
nkeynes@586 | 1623 | // FIXME: There's a corner-case that's not handled here when |
nkeynes@586 | 1624 | // the current code-page is in the ITLB but not in the UTLB. |
nkeynes@586 | 1625 | // (should generate a TLB miss although need to test SH4 |
nkeynes@586 | 1626 | // behaviour to confirm) Unlikely to be anyone depending on this |
nkeynes@586 | 1627 | // behaviour though. |
nkeynes@586 | 1628 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@991 | 1629 | MOVL_moffptr_eax( ptr ); |
nkeynes@388 | 1630 | } else { |
nkeynes@586 | 1631 | // Note: we use sh4r.pc for the calc as we could be running at a |
nkeynes@586 | 1632 | // different virtual address than the translation was done with, |
nkeynes@586 | 1633 | // but we can safely assume that the low bits are the same. |
nkeynes@995 | 1634 | MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX ); |
nkeynes@991 | 1635 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1636 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@586 | 1637 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@388 | 1638 | } |
nkeynes@991 | 1639 | store_reg( REG_EAX, Rn ); |
nkeynes@374 | 1640 | } |
nkeynes@361 | 1641 | :} |
nkeynes@361 | 1642 | MOV.L @(disp, Rm), Rn {: |
nkeynes@671 | 1643 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1644 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1645 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1646 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1647 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1648 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1649 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1650 | :} |
nkeynes@361 | 1651 | MOV.W Rm, @Rn {: |
nkeynes@671 | 1652 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1653 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1654 | check_walign16( REG_EAX ); |
nkeynes@991 | 1655 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1656 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1657 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1658 | :} |
nkeynes@361 | 1659 | MOV.W Rm, @-Rn {: |
nkeynes@671 | 1660 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1661 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1662 | check_walign16( REG_EAX ); |
nkeynes@991 | 1663 | LEAL_r32disp_r32( REG_EAX, -2, REG_EAX ); |
nkeynes@991 | 1664 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1665 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@991 | 1666 | ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1667 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1668 | :} |
nkeynes@361 | 1669 | MOV.W Rm, @(R0, Rn) {: |
nkeynes@671 | 1670 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1671 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1672 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1673 | check_walign16( REG_EAX ); |
nkeynes@991 | 1674 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1675 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1676 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1677 | :} |
nkeynes@361 | 1678 | MOV.W R0, @(disp, GBR) {: |
nkeynes@671 | 1679 | COUNT_INST(I_MOVW); |
nkeynes@995 | 1680 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1681 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1682 | check_walign16( REG_EAX ); |
nkeynes@991 | 1683 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1684 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1685 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1686 | :} |
nkeynes@361 | 1687 | MOV.W R0, @(disp, Rn) {: |
nkeynes@671 | 1688 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1689 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1690 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1691 | check_walign16( REG_EAX ); |
nkeynes@991 | 1692 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1693 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1694 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1695 | :} |
nkeynes@361 | 1696 | MOV.W @Rm, Rn {: |
nkeynes@671 | 1697 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1698 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1699 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1700 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1701 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1702 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1703 | :} |
nkeynes@361 | 1704 | MOV.W @Rm+, Rn {: |
nkeynes@671 | 1705 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1706 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1707 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1708 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@939 | 1709 | if( Rm != Rn ) { |
nkeynes@991 | 1710 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1711 | } |
nkeynes@991 | 1712 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1713 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1714 | :} |
nkeynes@361 | 1715 | MOV.W @(R0, Rm), Rn {: |
nkeynes@671 | 1716 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1717 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1718 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1719 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1720 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1721 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1722 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1723 | :} |
nkeynes@361 | 1724 | MOV.W @(disp, GBR), R0 {: |
nkeynes@671 | 1725 | COUNT_INST(I_MOVW); |
nkeynes@995 | 1726 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1727 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1728 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1729 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1730 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1731 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1732 | :} |
nkeynes@361 | 1733 | MOV.W @(disp, PC), Rn {: |
nkeynes@671 | 1734 | COUNT_INST(I_MOVW); |
nkeynes@374 | 1735 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1736 | SLOTILLEGAL(); |
nkeynes@374 | 1737 | } else { |
nkeynes@586 | 1738 | // See comments for MOV.L @(disp, PC), Rn |
nkeynes@586 | 1739 | uint32_t target = pc + disp + 4; |
nkeynes@586 | 1740 | if( IS_IN_ICACHE(target) ) { |
nkeynes@586 | 1741 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@991 | 1742 | MOVL_moffptr_eax( ptr ); |
nkeynes@991 | 1743 | MOVSXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@586 | 1744 | } else { |
nkeynes@995 | 1745 | MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX ); |
nkeynes@991 | 1746 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1747 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@586 | 1748 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@586 | 1749 | } |
nkeynes@991 | 1750 | store_reg( REG_EAX, Rn ); |
nkeynes@374 | 1751 | } |
nkeynes@361 | 1752 | :} |
nkeynes@361 | 1753 | MOV.W @(disp, Rm), R0 {: |
nkeynes@671 | 1754 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1755 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1756 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1757 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1758 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1759 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1760 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1761 | :} |
nkeynes@361 | 1762 | MOVA @(disp, PC), R0 {: |
nkeynes@671 | 1763 | COUNT_INST(I_MOVA); |
nkeynes@374 | 1764 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1765 | SLOTILLEGAL(); |
nkeynes@374 | 1766 | } else { |
nkeynes@995 | 1767 | MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX ); |
nkeynes@991 | 1768 | ADDL_rbpdisp_r32( R_PC, REG_ECX ); |
nkeynes@991 | 1769 | store_reg( REG_ECX, 0 ); |
nkeynes@586 | 1770 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1771 | } |
nkeynes@361 | 1772 | :} |
nkeynes@361 | 1773 | MOVCA.L R0, @Rn {: |
nkeynes@671 | 1774 | COUNT_INST(I_MOVCA); |
nkeynes@991 | 1775 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1776 | check_walign32( REG_EAX ); |
nkeynes@991 | 1777 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1778 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1779 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1780 | :} |
nkeynes@359 | 1781 | |
nkeynes@359 | 1782 | /* Control transfer instructions */ |
nkeynes@374 | 1783 | BF disp {: |
nkeynes@671 | 1784 | COUNT_INST(I_BF); |
nkeynes@374 | 1785 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1786 | SLOTILLEGAL(); |
nkeynes@374 | 1787 | } else { |
nkeynes@586 | 1788 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1789 | JT_label( nottaken ); |
nkeynes@586 | 1790 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1791 | JMP_TARGET(nottaken); |
nkeynes@408 | 1792 | return 2; |
nkeynes@374 | 1793 | } |
nkeynes@374 | 1794 | :} |
nkeynes@374 | 1795 | BF/S disp {: |
nkeynes@671 | 1796 | COUNT_INST(I_BFS); |
nkeynes@374 | 1797 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1798 | SLOTILLEGAL(); |
nkeynes@374 | 1799 | } else { |
nkeynes@590 | 1800 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@601 | 1801 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1802 | MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1803 | JT_label(nottaken); |
nkeynes@991 | 1804 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@601 | 1805 | JMP_TARGET(nottaken); |
nkeynes@991 | 1806 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@995 | 1807 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1808 | exit_block_emu(pc+2); |
nkeynes@601 | 1809 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1810 | return 2; |
nkeynes@601 | 1811 | } else { |
nkeynes@601 | 1812 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@991 | 1813 | CMPL_imms_rbpdisp( 1, R_T ); |
nkeynes@601 | 1814 | sh4_x86.tstate = TSTATE_E; |
nkeynes@601 | 1815 | } |
nkeynes@601 | 1816 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1817 | JCC_cc_rel32(sh4_x86.tstate,0); |
nkeynes@991 | 1818 | uint32_t *patch = ((uint32_t *)xlat_output)-1; |
nkeynes@879 | 1819 | int save_tstate = sh4_x86.tstate; |
nkeynes@601 | 1820 | sh4_translate_instruction(pc+2); |
nkeynes@1091 | 1821 | sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */ |
nkeynes@601 | 1822 | exit_block_rel( target, pc+4 ); |
nkeynes@601 | 1823 | |
nkeynes@601 | 1824 | // not taken |
nkeynes@601 | 1825 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@879 | 1826 | sh4_x86.tstate = save_tstate; |
nkeynes@601 | 1827 | sh4_translate_instruction(pc+2); |
nkeynes@601 | 1828 | return 4; |
nkeynes@417 | 1829 | } |
nkeynes@374 | 1830 | } |
nkeynes@374 | 1831 | :} |
nkeynes@374 | 1832 | BRA disp {: |
nkeynes@671 | 1833 | COUNT_INST(I_BRA); |
nkeynes@374 | 1834 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1835 | SLOTILLEGAL(); |
nkeynes@374 | 1836 | } else { |
nkeynes@590 | 1837 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1838 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1839 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1840 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1841 | ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1842 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1843 | exit_block_emu(pc+2); |
nkeynes@601 | 1844 | return 2; |
nkeynes@601 | 1845 | } else { |
nkeynes@601 | 1846 | sh4_translate_instruction( pc + 2 ); |
nkeynes@601 | 1847 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1848 | return 4; |
nkeynes@601 | 1849 | } |
nkeynes@374 | 1850 | } |
nkeynes@374 | 1851 | :} |
nkeynes@374 | 1852 | BRAF Rn {: |
nkeynes@671 | 1853 | COUNT_INST(I_BRAF); |
nkeynes@374 | 1854 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1855 | SLOTILLEGAL(); |
nkeynes@374 | 1856 | } else { |
nkeynes@995 | 1857 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1858 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1859 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@995 | 1860 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@590 | 1861 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@417 | 1862 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 1863 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1864 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1865 | exit_block_emu(pc+2); |
nkeynes@601 | 1866 | return 2; |
nkeynes@601 | 1867 | } else { |
nkeynes@601 | 1868 | sh4_translate_instruction( pc + 2 ); |
nkeynes@974 | 1869 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1870 | return 4; |
nkeynes@601 | 1871 | } |
nkeynes@374 | 1872 | } |
nkeynes@374 | 1873 | :} |
nkeynes@374 | 1874 | BSR disp {: |
nkeynes@671 | 1875 | COUNT_INST(I_BSR); |
nkeynes@374 | 1876 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1877 | SLOTILLEGAL(); |
nkeynes@374 | 1878 | } else { |
nkeynes@995 | 1879 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1880 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1881 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@590 | 1882 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1883 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1884 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@601 | 1885 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@991 | 1886 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@995 | 1887 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1888 | exit_block_emu(pc+2); |
nkeynes@601 | 1889 | return 2; |
nkeynes@601 | 1890 | } else { |
nkeynes@601 | 1891 | sh4_translate_instruction( pc + 2 ); |
nkeynes@601 | 1892 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1893 | return 4; |
nkeynes@601 | 1894 | } |
nkeynes@374 | 1895 | } |
nkeynes@374 | 1896 | :} |
nkeynes@374 | 1897 | BSRF Rn {: |
nkeynes@671 | 1898 | COUNT_INST(I_BSRF); |
nkeynes@374 | 1899 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1900 | SLOTILLEGAL(); |
nkeynes@374 | 1901 | } else { |
nkeynes@995 | 1902 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1903 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1904 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@991 | 1905 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@995 | 1906 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@590 | 1907 | |
nkeynes@601 | 1908 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@417 | 1909 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 1910 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1911 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1912 | exit_block_emu(pc+2); |
nkeynes@601 | 1913 | return 2; |
nkeynes@601 | 1914 | } else { |
nkeynes@601 | 1915 | sh4_translate_instruction( pc + 2 ); |
nkeynes@974 | 1916 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1917 | return 4; |
nkeynes@601 | 1918 | } |
nkeynes@374 | 1919 | } |
nkeynes@374 | 1920 | :} |
nkeynes@374 | 1921 | BT disp {: |
nkeynes@671 | 1922 | COUNT_INST(I_BT); |
nkeynes@374 | 1923 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1924 | SLOTILLEGAL(); |
nkeynes@374 | 1925 | } else { |
nkeynes@586 | 1926 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1927 | JF_label( nottaken ); |
nkeynes@586 | 1928 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1929 | JMP_TARGET(nottaken); |
nkeynes@408 | 1930 | return 2; |
nkeynes@374 | 1931 | } |
nkeynes@374 | 1932 | :} |
nkeynes@374 | 1933 | BT/S disp {: |
nkeynes@671 | 1934 | COUNT_INST(I_BTS); |
nkeynes@374 | 1935 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1936 | SLOTILLEGAL(); |
nkeynes@374 | 1937 | } else { |
nkeynes@590 | 1938 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@601 | 1939 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1940 | MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1941 | JF_label(nottaken); |
nkeynes@991 | 1942 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@601 | 1943 | JMP_TARGET(nottaken); |
nkeynes@991 | 1944 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@995 | 1945 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1946 | exit_block_emu(pc+2); |
nkeynes@601 | 1947 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1948 | return 2; |
nkeynes@601 | 1949 | } else { |
nkeynes@601 | 1950 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@991 | 1951 | CMPL_imms_rbpdisp( 1, R_T ); |
nkeynes@601 | 1952 | sh4_x86.tstate = TSTATE_E; |
nkeynes@601 | 1953 | } |
nkeynes@991 | 1954 | JCC_cc_rel32(sh4_x86.tstate^1,0); |
nkeynes@991 | 1955 | uint32_t *patch = ((uint32_t *)xlat_output)-1; |
nkeynes@991 | 1956 | |
nkeynes@879 | 1957 | int save_tstate = sh4_x86.tstate; |
nkeynes@601 | 1958 | sh4_translate_instruction(pc+2); |
nkeynes@1091 | 1959 | sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */ |
nkeynes@601 | 1960 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1961 | // not taken |
nkeynes@601 | 1962 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@879 | 1963 | sh4_x86.tstate = save_tstate; |
nkeynes@601 | 1964 | sh4_translate_instruction(pc+2); |
nkeynes@601 | 1965 | return 4; |
nkeynes@417 | 1966 | } |
nkeynes@374 | 1967 | } |
nkeynes@374 | 1968 | :} |
nkeynes@374 | 1969 | JMP @Rn {: |
nkeynes@671 | 1970 | COUNT_INST(I_JMP); |
nkeynes@374 | 1971 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1972 | SLOTILLEGAL(); |
nkeynes@374 | 1973 | } else { |
nkeynes@991 | 1974 | load_reg( REG_ECX, Rn ); |
nkeynes@995 | 1975 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@590 | 1976 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1977 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1978 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1979 | exit_block_emu(pc+2); |
nkeynes@601 | 1980 | return 2; |
nkeynes@601 | 1981 | } else { |
nkeynes@601 | 1982 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 1983 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1984 | return 4; |
nkeynes@601 | 1985 | } |
nkeynes@374 | 1986 | } |
nkeynes@374 | 1987 | :} |
nkeynes@374 | 1988 | JSR @Rn {: |
nkeynes@671 | 1989 | COUNT_INST(I_JSR); |
nkeynes@374 | 1990 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1991 | SLOTILLEGAL(); |
nkeynes@374 | 1992 | } else { |
nkeynes@995 | 1993 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1994 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1995 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@991 | 1996 | load_reg( REG_ECX, Rn ); |
nkeynes@995 | 1997 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@601 | 1998 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1999 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 2000 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@601 | 2001 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 2002 | exit_block_emu(pc+2); |
nkeynes@601 | 2003 | return 2; |
nkeynes@601 | 2004 | } else { |
nkeynes@601 | 2005 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 2006 | exit_block_newpcset(pc+4); |
nkeynes@601 | 2007 | return 4; |
nkeynes@601 | 2008 | } |
nkeynes@374 | 2009 | } |
nkeynes@374 | 2010 | :} |
nkeynes@374 | 2011 | RTE {: |
nkeynes@671 | 2012 | COUNT_INST(I_RTE); |
nkeynes@374 | 2013 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2014 | SLOTILLEGAL(); |
nkeynes@374 | 2015 | } else { |
nkeynes@408 | 2016 | check_priv(); |
nkeynes@995 | 2017 | MOVL_rbpdisp_r32( R_SPC, REG_ECX ); |
nkeynes@995 | 2018 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@995 | 2019 | MOVL_rbpdisp_r32( R_SSR, REG_EAX ); |
nkeynes@995 | 2020 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@590 | 2021 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@377 | 2022 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2023 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 2024 | sh4_x86.branch_taken = TRUE; |
nkeynes@1112 | 2025 | sh4_x86.sh4_mode = SH4_MODE_UNKNOWN; |
nkeynes@601 | 2026 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 2027 | exit_block_emu(pc+2); |
nkeynes@601 | 2028 | return 2; |
nkeynes@601 | 2029 | } else { |
nkeynes@601 | 2030 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 2031 | exit_block_newpcset(pc+4); |
nkeynes@601 | 2032 | return 4; |
nkeynes@601 | 2033 | } |
nkeynes@374 | 2034 | } |
nkeynes@374 | 2035 | :} |
nkeynes@374 | 2036 | RTS {: |
nkeynes@671 | 2037 | COUNT_INST(I_RTS); |
nkeynes@374 | 2038 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2039 | SLOTILLEGAL(); |
nkeynes@374 | 2040 | } else { |
nkeynes@995 | 2041 | MOVL_rbpdisp_r32( R_PR, REG_ECX ); |
nkeynes@995 | 2042 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@590 | 2043 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 2044 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 2045 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 2046 | exit_block_emu(pc+2); |
nkeynes@601 | 2047 | return 2; |
nkeynes@601 | 2048 | } else { |
nkeynes@601 | 2049 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 2050 | exit_block_newpcset(pc+4); |
nkeynes@601 | 2051 | return 4; |
nkeynes@601 | 2052 | } |
nkeynes@374 | 2053 | } |
nkeynes@374 | 2054 | :} |
nkeynes@374 | 2055 | TRAPA #imm {: |
nkeynes@671 | 2056 | COUNT_INST(I_TRAPA); |
nkeynes@374 | 2057 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2058 | SLOTILLEGAL(); |
nkeynes@374 | 2059 | } else { |
nkeynes@995 | 2060 | MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX ); // 5 |
nkeynes@991 | 2061 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 2062 | MOVL_imm32_r32( imm, REG_EAX ); |
nkeynes@995 | 2063 | CALL1_ptr_r32( sh4_raise_trap, REG_EAX ); |
nkeynes@417 | 2064 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@974 | 2065 | exit_block_pcset(pc+2); |
nkeynes@409 | 2066 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 2067 | return 2; |
nkeynes@374 | 2068 | } |
nkeynes@374 | 2069 | :} |
nkeynes@374 | 2070 | UNDEF {: |
nkeynes@671 | 2071 | COUNT_INST(I_UNDEF); |
nkeynes@374 | 2072 | if( sh4_x86.in_delay_slot ) { |
nkeynes@956 | 2073 | exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); |
nkeynes@374 | 2074 | } else { |
nkeynes@956 | 2075 | exit_block_exc(EXC_ILLEGAL, pc); |
nkeynes@408 | 2076 | return 2; |
nkeynes@374 | 2077 | } |
nkeynes@368 | 2078 | :} |
nkeynes@374 | 2079 | |
nkeynes@374 | 2080 | CLRMAC {: |
nkeynes@671 | 2081 | COUNT_INST(I_CLRMAC); |
nkeynes@991 | 2082 | XORL_r32_r32(REG_EAX, REG_EAX); |
nkeynes@995 | 2083 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@995 | 2084 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@417 | 2085 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@368 | 2086 | :} |
nkeynes@374 | 2087 | CLRS {: |
nkeynes@671 | 2088 | COUNT_INST(I_CLRS); |
nkeynes@374 | 2089 | CLC(); |
nkeynes@991 | 2090 | SETCCB_cc_rbpdisp(X86_COND_C, R_S); |
nkeynes@872 | 2091 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@368 | 2092 | :} |
nkeynes@374 | 2093 | CLRT {: |
nkeynes@671 | 2094 | COUNT_INST(I_CLRT); |
nkeynes@374 | 2095 | CLC(); |
nkeynes@374 | 2096 | SETC_t(); |
nkeynes@417 | 2097 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 2098 | :} |
nkeynes@374 | 2099 | SETS {: |
nkeynes@671 | 2100 | COUNT_INST(I_SETS); |
nkeynes@374 | 2101 | STC(); |
nkeynes@991 | 2102 | SETCCB_cc_rbpdisp(X86_COND_C, R_S); |
nkeynes@872 | 2103 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2104 | :} |
nkeynes@374 | 2105 | SETT {: |
nkeynes@671 | 2106 | COUNT_INST(I_SETT); |
nkeynes@374 | 2107 | STC(); |
nkeynes@374 | 2108 | SETC_t(); |
nkeynes@417 | 2109 | sh4_x86.tstate = TSTATE_C; |
nkeynes@374 | 2110 | :} |
nkeynes@359 | 2111 | |
nkeynes@375 | 2112 | /* Floating point moves */ |
nkeynes@375 | 2113 | FMOV FRm, FRn {: |
nkeynes@671 | 2114 | COUNT_INST(I_FMOV1); |
nkeynes@377 | 2115 | check_fpuen(); |
nkeynes@901 | 2116 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2117 | load_dr0( REG_EAX, FRm ); |
nkeynes@991 | 2118 | load_dr1( REG_ECX, FRm ); |
nkeynes@991 | 2119 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2120 | store_dr1( REG_ECX, FRn ); |
nkeynes@901 | 2121 | } else { |
nkeynes@991 | 2122 | load_fr( REG_EAX, FRm ); // SZ=0 branch |
nkeynes@991 | 2123 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2124 | } |
nkeynes@375 | 2125 | :} |
nkeynes@416 | 2126 | FMOV FRm, @Rn {: |
nkeynes@671 | 2127 | COUNT_INST(I_FMOV2); |
nkeynes@586 | 2128 | check_fpuen(); |
nkeynes@991 | 2129 | load_reg( REG_EAX, Rn ); |
nkeynes@901 | 2130 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2131 | check_walign64( REG_EAX ); |
nkeynes@991 | 2132 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2133 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2134 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2135 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2136 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2137 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2138 | } else { |
nkeynes@991 | 2139 | check_walign32( REG_EAX ); |
nkeynes@991 | 2140 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2141 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2142 | } |
nkeynes@417 | 2143 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2144 | :} |
nkeynes@375 | 2145 | FMOV @Rm, FRn {: |
nkeynes@671 | 2146 | COUNT_INST(I_FMOV5); |
nkeynes@586 | 2147 | check_fpuen(); |
nkeynes@991 | 2148 | load_reg( REG_EAX, Rm ); |
nkeynes@901 | 2149 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2150 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2151 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2152 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2153 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2154 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2155 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2156 | store_dr1( REG_EAX, FRn ); |
nkeynes@901 | 2157 | } else { |
nkeynes@991 | 2158 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2159 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2160 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2161 | } |
nkeynes@417 | 2162 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2163 | :} |
nkeynes@377 | 2164 | FMOV FRm, @-Rn {: |
nkeynes@671 | 2165 | COUNT_INST(I_FMOV3); |
nkeynes@586 | 2166 | check_fpuen(); |
nkeynes@991 | 2167 | load_reg( REG_EAX, Rn ); |
nkeynes@901 | 2168 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2169 | check_walign64( REG_EAX ); |
nkeynes@991 | 2170 | LEAL_r32disp_r32( REG_EAX, -8, REG_EAX ); |
nkeynes@991 | 2171 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2172 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2173 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2174 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2175 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2176 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2177 | ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn])); |
nkeynes@901 | 2178 | } else { |
nkeynes@991 | 2179 | check_walign32( REG_EAX ); |
nkeynes@991 | 2180 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2181 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2182 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2183 | ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn])); |
nkeynes@901 | 2184 | } |
nkeynes@417 | 2185 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2186 | :} |
nkeynes@416 | 2187 | FMOV @Rm+, FRn {: |
nkeynes@671 | 2188 | COUNT_INST(I_FMOV6); |
nkeynes@586 | 2189 | check_fpuen(); |
nkeynes@991 | 2190 | load_reg( REG_EAX, Rm ); |
nkeynes@901 | 2191 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2192 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2193 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2194 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2195 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2196 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2197 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2198 | store_dr1( REG_EAX, FRn ); |
nkeynes@991 | 2199 | ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) ); |
nkeynes@901 | 2200 | } else { |
nkeynes@991 | 2201 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2202 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2203 | store_fr( REG_EAX, FRn ); |
nkeynes@991 | 2204 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@901 | 2205 | } |
nkeynes@417 | 2206 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2207 | :} |
nkeynes@377 | 2208 | FMOV FRm, @(R0, Rn) {: |
nkeynes@671 | 2209 | COUNT_INST(I_FMOV4); |
nkeynes@586 | 2210 | check_fpuen(); |
nkeynes@991 | 2211 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2212 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@901 | 2213 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2214 | check_walign64( REG_EAX ); |
nkeynes@991 | 2215 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2216 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2217 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2218 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@991 | 2219 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2220 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2221 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2222 | } else { |
nkeynes@991 | 2223 | check_walign32( REG_EAX ); |
nkeynes@991 | 2224 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2225 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12 |
nkeynes@901 | 2226 | } |
nkeynes@417 | 2227 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2228 | :} |
nkeynes@377 | 2229 | FMOV @(R0, Rm), FRn {: |
nkeynes@671 | 2230 | COUNT_INST(I_FMOV7); |
nkeynes@586 | 2231 | check_fpuen(); |
nkeynes@991 | 2232 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2233 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@901 | 2234 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2235 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2236 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2237 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2238 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2239 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@991 | 2240 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2241 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2242 | store_dr1( REG_EAX, FRn ); |
nkeynes@901 | 2243 | } else { |
nkeynes@991 | 2244 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2245 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2246 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2247 | } |
nkeynes@417 | 2248 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2249 | :} |
nkeynes@377 | 2250 | FLDI0 FRn {: /* IFF PR=0 */ |
nkeynes@671 | 2251 | COUNT_INST(I_FLDI0); |
nkeynes@377 | 2252 | check_fpuen(); |
nkeynes@901 | 2253 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@991 | 2254 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 2255 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2256 | } |
nkeynes@417 | 2257 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2258 | :} |
nkeynes@377 | 2259 | FLDI1 FRn {: /* IFF PR=0 */ |
nkeynes@671 | 2260 | COUNT_INST(I_FLDI1); |
nkeynes@377 | 2261 | check_fpuen(); |
nkeynes@901 | 2262 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@995 | 2263 | MOVL_imm32_r32( 0x3F800000, REG_EAX ); |
nkeynes@991 | 2264 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2265 | } |
nkeynes@377 | 2266 | :} |
nkeynes@377 | 2267 | |
nkeynes@377 | 2268 | FLOAT FPUL, FRn {: |
nkeynes@671 | 2269 | COUNT_INST(I_FLOAT); |
nkeynes@377 | 2270 | check_fpuen(); |
nkeynes@991 | 2271 | FILD_rbpdisp(R_FPUL); |
nkeynes@901 | 2272 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2273 | pop_dr( FRn ); |
nkeynes@901 | 2274 | } else { |
nkeynes@901 | 2275 | pop_fr( FRn ); |
nkeynes@901 | 2276 | } |
nkeynes@377 | 2277 | :} |
nkeynes@377 | 2278 | FTRC FRm, FPUL {: |
nkeynes@671 | 2279 | COUNT_INST(I_FTRC); |
nkeynes@377 | 2280 | check_fpuen(); |
nkeynes@901 | 2281 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2282 | push_dr( FRm ); |
nkeynes@901 | 2283 | } else { |
nkeynes@901 | 2284 | push_fr( FRm ); |
nkeynes@901 | 2285 | } |
nkeynes@995 | 2286 | MOVP_immptr_rptr( &max_int, REG_ECX ); |
nkeynes@991 | 2287 | FILD_r32disp( REG_ECX, 0 ); |
nkeynes@388 | 2288 | FCOMIP_st(1); |
nkeynes@991 | 2289 | JNA_label( sat ); |
nkeynes@995 | 2290 | MOVP_immptr_rptr( &min_int, REG_ECX ); |
nkeynes@995 | 2291 | FILD_r32disp( REG_ECX, 0 ); |
nkeynes@995 | 2292 | FCOMIP_st(1); |
nkeynes@995 | 2293 | JAE_label( sat2 ); |
nkeynes@995 | 2294 | MOVP_immptr_rptr( &save_fcw, REG_EAX ); |
nkeynes@991 | 2295 | FNSTCW_r32disp( REG_EAX, 0 ); |
nkeynes@995 | 2296 | MOVP_immptr_rptr( &trunc_fcw, REG_EDX ); |
nkeynes@991 | 2297 | FLDCW_r32disp( REG_EDX, 0 ); |
nkeynes@995 | 2298 | FISTP_rbpdisp(R_FPUL); |
nkeynes@991 | 2299 | FLDCW_r32disp( REG_EAX, 0 ); |
nkeynes@995 | 2300 | JMP_label(end); |
nkeynes@388 | 2301 | |
nkeynes@388 | 2302 | JMP_TARGET(sat); |
nkeynes@388 | 2303 | JMP_TARGET(sat2); |
nkeynes@991 | 2304 | MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2 |
nkeynes@995 | 2305 | MOVL_r32_rbpdisp( REG_ECX, R_FPUL ); |
nkeynes@388 | 2306 | FPOP_st(); |
nkeynes@388 | 2307 | JMP_TARGET(end); |
nkeynes@417 | 2308 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2309 | :} |
nkeynes@377 | 2310 | FLDS FRm, FPUL {: |
nkeynes@671 | 2311 | COUNT_INST(I_FLDS); |
nkeynes@377 | 2312 | check_fpuen(); |
nkeynes@991 | 2313 | load_fr( REG_EAX, FRm ); |
nkeynes@995 | 2314 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@377 | 2315 | :} |
nkeynes@377 | 2316 | FSTS FPUL, FRn {: |
nkeynes@671 | 2317 | COUNT_INST(I_FSTS); |
nkeynes@377 | 2318 | check_fpuen(); |
nkeynes@995 | 2319 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@991 | 2320 | store_fr( REG_EAX, FRn ); |
nkeynes@377 | 2321 | :} |
nkeynes@377 | 2322 | FCNVDS FRm, FPUL {: |
nkeynes@671 | 2323 | COUNT_INST(I_FCNVDS); |
nkeynes@377 | 2324 | check_fpuen(); |
nkeynes@901 | 2325 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2326 | push_dr( FRm ); |
nkeynes@901 | 2327 | pop_fpul(); |
nkeynes@901 | 2328 | } |
nkeynes@377 | 2329 | :} |
nkeynes@377 | 2330 | FCNVSD FPUL, FRn {: |
nkeynes@671 | 2331 | COUNT_INST(I_FCNVSD); |
nkeynes@377 | 2332 | check_fpuen(); |
nkeynes@901 | 2333 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2334 | push_fpul(); |
nkeynes@901 | 2335 | pop_dr( FRn ); |
nkeynes@901 | 2336 | } |
nkeynes@377 | 2337 | :} |
nkeynes@375 | 2338 | |
nkeynes@359 | 2339 | /* Floating point instructions */ |
nkeynes@374 | 2340 | FABS FRn {: |
nkeynes@671 | 2341 | COUNT_INST(I_FABS); |
nkeynes@377 | 2342 | check_fpuen(); |
nkeynes@901 | 2343 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2344 | push_dr(FRn); |
nkeynes@901 | 2345 | FABS_st0(); |
nkeynes@901 | 2346 | pop_dr(FRn); |
nkeynes@901 | 2347 | } else { |
nkeynes@901 | 2348 | push_fr(FRn); |
nkeynes@901 | 2349 | FABS_st0(); |
nkeynes@901 | 2350 | pop_fr(FRn); |
nkeynes@901 | 2351 | } |
nkeynes@374 | 2352 | :} |
nkeynes@377 | 2353 | FADD FRm, FRn {: |
nkeynes@671 | 2354 | COUNT_INST(I_FADD); |
nkeynes@377 | 2355 | check_fpuen(); |
nkeynes@901 | 2356 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2357 | push_dr(FRm); |
nkeynes@901 | 2358 | push_dr(FRn); |
nkeynes@901 | 2359 | FADDP_st(1); |
nkeynes@901 | 2360 | pop_dr(FRn); |
nkeynes@901 | 2361 | } else { |
nkeynes@901 | 2362 | push_fr(FRm); |
nkeynes@901 | 2363 | push_fr(FRn); |
nkeynes@901 | 2364 | FADDP_st(1); |
nkeynes@901 | 2365 | pop_fr(FRn); |
nkeynes@901 | 2366 | } |
nkeynes@375 | 2367 | :} |
nkeynes@377 | 2368 | FDIV FRm, FRn {: |
nkeynes@671 | 2369 | COUNT_INST(I_FDIV); |
nkeynes@377 | 2370 | check_fpuen(); |
nkeynes@901 | 2371 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2372 | push_dr(FRn); |
nkeynes@901 | 2373 | push_dr(FRm); |
nkeynes@901 | 2374 | FDIVP_st(1); |
nkeynes@901 | 2375 | pop_dr(FRn); |
nkeynes@901 | 2376 | } else { |
nkeynes@901 | 2377 | push_fr(FRn); |
nkeynes@901 | 2378 | push_fr(FRm); |
nkeynes@901 | 2379 | FDIVP_st(1); |
nkeynes@901 | 2380 | pop_fr(FRn); |
nkeynes@901 | 2381 | } |
nkeynes@375 | 2382 | :} |
nkeynes@375 | 2383 | FMAC FR0, FRm, FRn {: |
nkeynes@671 | 2384 | COUNT_INST(I_FMAC); |
nkeynes@377 | 2385 | check_fpuen(); |
nkeynes@901 | 2386 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2387 | push_dr( 0 ); |
nkeynes@901 | 2388 | push_dr( FRm ); |
nkeynes@901 | 2389 | FMULP_st(1); |
nkeynes@901 | 2390 | push_dr( FRn ); |
nkeynes@901 | 2391 | FADDP_st(1); |
nkeynes@901 | 2392 | pop_dr( FRn ); |
nkeynes@901 | 2393 | } else { |
nkeynes@901 | 2394 | push_fr( 0 ); |
nkeynes@901 | 2395 | push_fr( FRm ); |
nkeynes@901 | 2396 | FMULP_st(1); |
nkeynes@901 | 2397 | push_fr( FRn ); |
nkeynes@901 | 2398 | FADDP_st(1); |
nkeynes@901 | 2399 | pop_fr( FRn ); |
nkeynes@901 | 2400 | } |
nkeynes@375 | 2401 | :} |
nkeynes@375 | 2402 | |
nkeynes@377 | 2403 | FMUL FRm, FRn {: |
nkeynes@671 | 2404 | COUNT_INST(I_FMUL); |
nkeynes@377 | 2405 | check_fpuen(); |
nkeynes@901 | 2406 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2407 | push_dr(FRm); |
nkeynes@901 | 2408 | push_dr(FRn); |
nkeynes@901 | 2409 | FMULP_st(1); |
nkeynes@901 | 2410 | pop_dr(FRn); |
nkeynes@901 | 2411 | } else { |
nkeynes@901 | 2412 | push_fr(FRm); |
nkeynes@901 | 2413 | push_fr(FRn); |
nkeynes@901 | 2414 | FMULP_st(1); |
nkeynes@901 | 2415 | pop_fr(FRn); |
nkeynes@901 | 2416 | } |
nkeynes@377 | 2417 | :} |
nkeynes@377 | 2418 | FNEG FRn {: |
nkeynes@671 | 2419 | COUNT_INST(I_FNEG); |
nkeynes@377 | 2420 | check_fpuen(); |
nkeynes@901 | 2421 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2422 | push_dr(FRn); |
nkeynes@901 | 2423 | FCHS_st0(); |
nkeynes@901 | 2424 | pop_dr(FRn); |
nkeynes@901 | 2425 | } else { |
nkeynes@901 | 2426 | push_fr(FRn); |
nkeynes@901 | 2427 | FCHS_st0(); |
nkeynes@901 | 2428 | pop_fr(FRn); |
nkeynes@901 | 2429 | } |
nkeynes@377 | 2430 | :} |
nkeynes@377 | 2431 | FSRRA FRn {: |
nkeynes@671 | 2432 | COUNT_INST(I_FSRRA); |
nkeynes@377 | 2433 | check_fpuen(); |
nkeynes@901 | 2434 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@901 | 2435 | FLD1_st0(); |
nkeynes@901 | 2436 | push_fr(FRn); |
nkeynes@901 | 2437 | FSQRT_st0(); |
nkeynes@901 | 2438 | FDIVP_st(1); |
nkeynes@901 | 2439 | pop_fr(FRn); |
nkeynes@901 | 2440 | } |
nkeynes@377 | 2441 | :} |
nkeynes@377 | 2442 | FSQRT FRn {: |
nkeynes@671 | 2443 | COUNT_INST(I_FSQRT); |
nkeynes@377 | 2444 | check_fpuen(); |
nkeynes@901 | 2445 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2446 | push_dr(FRn); |
nkeynes@901 | 2447 | FSQRT_st0(); |
nkeynes@901 | 2448 | pop_dr(FRn); |
nkeynes@901 | 2449 | } else { |
nkeynes@901 | 2450 | push_fr(FRn); |
nkeynes@901 | 2451 | FSQRT_st0(); |
nkeynes@901 | 2452 | pop_fr(FRn); |
nkeynes@901 | 2453 | } |
nkeynes@377 | 2454 | :} |
nkeynes@377 | 2455 | FSUB FRm, FRn {: |
nkeynes@671 | 2456 | COUNT_INST(I_FSUB); |
nkeynes@377 | 2457 | check_fpuen(); |
nkeynes@901 | 2458 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2459 | push_dr(FRn); |
nkeynes@901 | 2460 | push_dr(FRm); |
nkeynes@901 | 2461 | FSUBP_st(1); |
nkeynes@901 | 2462 | pop_dr(FRn); |
nkeynes@901 | 2463 | } else { |
nkeynes@901 | 2464 | push_fr(FRn); |
nkeynes@901 | 2465 | push_fr(FRm); |
nkeynes@901 | 2466 | FSUBP_st(1); |
nkeynes@901 | 2467 | pop_fr(FRn); |
nkeynes@901 | 2468 | } |
nkeynes@377 | 2469 | :} |
nkeynes@377 | 2470 | |
nkeynes@377 | 2471 | FCMP/EQ FRm, FRn {: |
nkeynes@671 | 2472 | COUNT_INST(I_FCMPEQ); |
nkeynes@377 | 2473 | check_fpuen(); |
nkeynes@901 | 2474 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2475 | push_dr(FRm); |
nkeynes@901 | 2476 | push_dr(FRn); |
nkeynes@901 | 2477 | } else { |
nkeynes@901 | 2478 | push_fr(FRm); |
nkeynes@901 | 2479 | push_fr(FRn); |
nkeynes@901 | 2480 | } |
nkeynes@377 | 2481 | FCOMIP_st(1); |
nkeynes@377 | 2482 | SETE_t(); |
nkeynes@377 | 2483 | FPOP_st(); |
nkeynes@901 | 2484 | sh4_x86.tstate = TSTATE_E; |
nkeynes@377 | 2485 | :} |
nkeynes@377 | 2486 | FCMP/GT FRm, FRn {: |
nkeynes@671 | 2487 | COUNT_INST(I_FCMPGT); |
nkeynes@377 | 2488 | check_fpuen(); |
nkeynes@901 | 2489 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2490 | push_dr(FRm); |
nkeynes@901 | 2491 | push_dr(FRn); |
nkeynes@901 | 2492 | } else { |
nkeynes@901 | 2493 | push_fr(FRm); |
nkeynes@901 | 2494 | push_fr(FRn); |
nkeynes@901 | 2495 | } |
nkeynes@377 | 2496 | FCOMIP_st(1); |
nkeynes@377 | 2497 | SETA_t(); |
nkeynes@377 | 2498 | FPOP_st(); |
nkeynes@901 | 2499 | sh4_x86.tstate = TSTATE_A; |
nkeynes@377 | 2500 | :} |
nkeynes@377 | 2501 | |
nkeynes@377 | 2502 | FSCA FPUL, FRn {: |
nkeynes@671 | 2503 | COUNT_INST(I_FSCA); |
nkeynes@377 | 2504 | check_fpuen(); |
nkeynes@901 | 2505 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@991 | 2506 | LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX ); |
nkeynes@995 | 2507 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@995 | 2508 | CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX ); |
nkeynes@901 | 2509 | } |
nkeynes@417 | 2510 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2511 | :} |
nkeynes@377 | 2512 | FIPR FVm, FVn {: |
nkeynes@671 | 2513 | COUNT_INST(I_FIPR); |
nkeynes@377 | 2514 | check_fpuen(); |
nkeynes@901 | 2515 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@904 | 2516 | if( sh4_x86.sse3_enabled ) { |
nkeynes@991 | 2517 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 ); |
nkeynes@991 | 2518 | MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); |
nkeynes@903 | 2519 | HADDPS_xmm_xmm( 4, 4 ); |
nkeynes@903 | 2520 | HADDPS_xmm_xmm( 4, 4 ); |
nkeynes@991 | 2521 | MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) ); |
nkeynes@903 | 2522 | } else { |
nkeynes@904 | 2523 | push_fr( FVm<<2 ); |
nkeynes@903 | 2524 | push_fr( FVn<<2 ); |
nkeynes@903 | 2525 | FMULP_st(1); |
nkeynes@903 | 2526 | push_fr( (FVm<<2)+1); |
nkeynes@903 | 2527 | push_fr( (FVn<<2)+1); |
nkeynes@903 | 2528 | FMULP_st(1); |
nkeynes@903 | 2529 | FADDP_st(1); |
nkeynes@903 | 2530 | push_fr( (FVm<<2)+2); |
nkeynes@903 | 2531 | push_fr( (FVn<<2)+2); |
nkeynes@903 | 2532 | FMULP_st(1); |
nkeynes@903 | 2533 | FADDP_st(1); |
nkeynes@903 | 2534 | push_fr( (FVm<<2)+3); |
nkeynes@903 | 2535 | push_fr( (FVn<<2)+3); |
nkeynes@903 | 2536 | FMULP_st(1); |
nkeynes@903 | 2537 | FADDP_st(1); |
nkeynes@903 | 2538 | pop_fr( (FVn<<2)+3); |
nkeynes@904 | 2539 | } |
nkeynes@901 | 2540 | } |
nkeynes@377 | 2541 | :} |
nkeynes@377 | 2542 | FTRV XMTRX, FVn {: |
nkeynes@671 | 2543 | COUNT_INST(I_FTRV); |
nkeynes@377 | 2544 | check_fpuen(); |
nkeynes@901 | 2545 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@903 | 2546 | if( sh4_x86.sse3_enabled ) { |
nkeynes@991 | 2547 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2 |
nkeynes@991 | 2548 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6 |
nkeynes@991 | 2549 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10 |
nkeynes@991 | 2550 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14 |
nkeynes@903 | 2551 | |
nkeynes@991 | 2552 | MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3 |
nkeynes@991 | 2553 | MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2 |
nkeynes@991 | 2554 | MOV_xmm_xmm( 4, 6 ); |
nkeynes@991 | 2555 | MOV_xmm_xmm( 5, 7 ); |
nkeynes@903 | 2556 | MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V1 |
nkeynes@903 | 2557 | MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V3 |
nkeynes@903 | 2558 | MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V0 |
nkeynes@903 | 2559 | MOVHLPS_xmm_xmm( 7, 7 ); // V2 V2 V2 V2 |
nkeynes@903 | 2560 | MULPS_xmm_xmm( 0, 4 ); |
nkeynes@903 | 2561 | MULPS_xmm_xmm( 1, 5 ); |
nkeynes@903 | 2562 | MULPS_xmm_xmm( 2, 6 ); |
nkeynes@903 | 2563 | MULPS_xmm_xmm( 3, 7 ); |
nkeynes@903 | 2564 | ADDPS_xmm_xmm( 5, 4 ); |
nkeynes@903 | 2565 | ADDPS_xmm_xmm( 7, 6 ); |
nkeynes@903 | 2566 | ADDPS_xmm_xmm( 6, 4 ); |
nkeynes@991 | 2567 | MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) ); |
nkeynes@903 | 2568 | } else { |
nkeynes@991 | 2569 | LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX ); |
nkeynes@995 | 2570 | CALL1_ptr_r32( sh4_ftrv, REG_EAX ); |
nkeynes@903 | 2571 | } |
nkeynes@901 | 2572 | } |
nkeynes@417 | 2573 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2574 | :} |
nkeynes@377 | 2575 | |
nkeynes@377 | 2576 | FRCHG {: |
nkeynes@671 | 2577 | COUNT_INST(I_FRCHG); |
nkeynes@377 | 2578 | check_fpuen(); |
nkeynes@991 | 2579 | XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR ); |
nkeynes@995 | 2580 | CALL_ptr( sh4_switch_fr_banks ); |
nkeynes@417 | 2581 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2582 | :} |
nkeynes@377 | 2583 | FSCHG {: |
nkeynes@671 | 2584 | COUNT_INST(I_FSCHG); |
nkeynes@377 | 2585 | check_fpuen(); |
nkeynes@991 | 2586 | XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR); |
nkeynes@991 | 2587 | XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) ); |
nkeynes@417 | 2588 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 2589 | sh4_x86.double_size = !sh4_x86.double_size; |
nkeynes@1112 | 2590 | sh4_x86.sh4_mode = sh4_x86.sh4_mode ^ FPSCR_SZ; |
nkeynes@377 | 2591 | :} |
nkeynes@359 | 2592 | |
nkeynes@359 | 2593 | /* Processor control instructions */ |
nkeynes@368 | 2594 | LDC Rm, SR {: |
nkeynes@671 | 2595 | COUNT_INST(I_LDCSR); |
nkeynes@386 | 2596 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2597 | SLOTILLEGAL(); |
nkeynes@386 | 2598 | } else { |
nkeynes@386 | 2599 | check_priv(); |
nkeynes@991 | 2600 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2601 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@386 | 2602 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2603 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@1112 | 2604 | sh4_x86.sh4_mode = SH4_MODE_UNKNOWN; |
nkeynes@937 | 2605 | return 2; |
nkeynes@386 | 2606 | } |
nkeynes@368 | 2607 | :} |
nkeynes@359 | 2608 | LDC Rm, GBR {: |
nkeynes@671 | 2609 | COUNT_INST(I_LDC); |
nkeynes@991 | 2610 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2611 | MOVL_r32_rbpdisp( REG_EAX, R_GBR ); |
nkeynes@359 | 2612 | :} |
nkeynes@359 | 2613 | LDC Rm, VBR {: |
nkeynes@671 | 2614 | COUNT_INST(I_LDC); |
nkeynes@386 | 2615 | check_priv(); |
nkeynes@991 | 2616 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2617 | MOVL_r32_rbpdisp( REG_EAX, R_VBR ); |
nkeynes@417 | 2618 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2619 | :} |
nkeynes@359 | 2620 | LDC Rm, SSR {: |
nkeynes@671 | 2621 | COUNT_INST(I_LDC); |
nkeynes@386 | 2622 | check_priv(); |
nkeynes@991 | 2623 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2624 | MOVL_r32_rbpdisp( REG_EAX, R_SSR ); |
nkeynes@417 | 2625 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2626 | :} |
nkeynes@359 | 2627 | LDC Rm, SGR {: |
nkeynes@671 | 2628 | COUNT_INST(I_LDC); |
nkeynes@386 | 2629 | check_priv(); |
nkeynes@991 | 2630 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2631 | MOVL_r32_rbpdisp( REG_EAX, R_SGR ); |
nkeynes@417 | 2632 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2633 | :} |
nkeynes@359 | 2634 | LDC Rm, SPC {: |
nkeynes@671 | 2635 | COUNT_INST(I_LDC); |
nkeynes@386 | 2636 | check_priv(); |
nkeynes@991 | 2637 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2638 | MOVL_r32_rbpdisp( REG_EAX, R_SPC ); |
nkeynes@417 | 2639 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2640 | :} |
nkeynes@359 | 2641 | LDC Rm, DBR {: |
nkeynes@671 | 2642 | COUNT_INST(I_LDC); |
nkeynes@386 | 2643 | check_priv(); |
nkeynes@991 | 2644 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2645 | MOVL_r32_rbpdisp( REG_EAX, R_DBR ); |
nkeynes@417 | 2646 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2647 | :} |
nkeynes@374 | 2648 | LDC Rm, Rn_BANK {: |
nkeynes@671 | 2649 | COUNT_INST(I_LDC); |
nkeynes@386 | 2650 | check_priv(); |
nkeynes@991 | 2651 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2652 | MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2653 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2654 | :} |
nkeynes@359 | 2655 | LDC.L @Rm+, GBR {: |
nkeynes@671 | 2656 | COUNT_INST(I_LDCM); |
nkeynes@991 | 2657 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2658 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2659 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2660 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2661 | MOVL_r32_rbpdisp( REG_EAX, R_GBR ); |
nkeynes@417 | 2662 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2663 | :} |
nkeynes@368 | 2664 | LDC.L @Rm+, SR {: |
nkeynes@671 | 2665 | COUNT_INST(I_LDCSRM); |
nkeynes@386 | 2666 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2667 | SLOTILLEGAL(); |
nkeynes@386 | 2668 | } else { |
nkeynes@586 | 2669 | check_priv(); |
nkeynes@991 | 2670 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2671 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2672 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2673 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2674 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@386 | 2675 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2676 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@1112 | 2677 | sh4_x86.sh4_mode = SH4_MODE_UNKNOWN; |
nkeynes@937 | 2678 | return 2; |
nkeynes@386 | 2679 | } |
nkeynes@359 | 2680 | :} |
nkeynes@359 | 2681 | LDC.L @Rm+, VBR {: |
nkeynes@671 | 2682 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2683 | check_priv(); |
nkeynes@991 | 2684 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2685 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2686 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2687 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2688 | MOVL_r32_rbpdisp( REG_EAX, R_VBR ); |
nkeynes@417 | 2689 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2690 | :} |
nkeynes@359 | 2691 | LDC.L @Rm+, SSR {: |
nkeynes@671 | 2692 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2693 | check_priv(); |
nkeynes@991 | 2694 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2695 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2696 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2697 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2698 | MOVL_r32_rbpdisp( REG_EAX, R_SSR ); |
nkeynes@417 | 2699 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2700 | :} |
nkeynes@359 | 2701 | LDC.L @Rm+, SGR {: |
nkeynes@671 | 2702 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2703 | check_priv(); |
nkeynes@991 | 2704 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2705 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2706 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2707 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2708 | MOVL_r32_rbpdisp( REG_EAX, R_SGR ); |
nkeynes@417 | 2709 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2710 | :} |
nkeynes@359 | 2711 | LDC.L @Rm+, SPC {: |
nkeynes@671 | 2712 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2713 | check_priv(); |
nkeynes@991 | 2714 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2715 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2716 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2717 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2718 | MOVL_r32_rbpdisp( REG_EAX, R_SPC ); |
nkeynes@417 | 2719 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2720 | :} |
nkeynes@359 | 2721 | LDC.L @Rm+, DBR {: |
nkeynes@671 | 2722 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2723 | check_priv(); |
nkeynes@991 | 2724 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2725 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2726 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2727 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2728 | MOVL_r32_rbpdisp( REG_EAX, R_DBR ); |
nkeynes@417 | 2729 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2730 | :} |
nkeynes@359 | 2731 | LDC.L @Rm+, Rn_BANK {: |
nkeynes@671 | 2732 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2733 | check_priv(); |
nkeynes@991 | 2734 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2735 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2736 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2737 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2738 | MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2739 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2740 | :} |
nkeynes@626 | 2741 | LDS Rm, FPSCR {: |
nkeynes@673 | 2742 | COUNT_INST(I_LDSFPSCR); |
nkeynes@626 | 2743 | check_fpuen(); |
nkeynes@991 | 2744 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2745 | CALL1_ptr_r32( sh4_write_fpscr, REG_EAX ); |
nkeynes@417 | 2746 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@1112 | 2747 | sh4_x86.sh4_mode = SH4_MODE_UNKNOWN; |
nkeynes@901 | 2748 | return 2; |
nkeynes@359 | 2749 | :} |
nkeynes@359 | 2750 | LDS.L @Rm+, FPSCR {: |
nkeynes@673 | 2751 | COUNT_INST(I_LDSFPSCRM); |
nkeynes@626 | 2752 | check_fpuen(); |
nkeynes@991 | 2753 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2754 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2755 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2756 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2757 | CALL1_ptr_r32( sh4_write_fpscr, REG_EAX ); |
nkeynes@417 | 2758 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@1112 | 2759 | sh4_x86.sh4_mode = SH4_MODE_UNKNOWN; |
nkeynes@901 | 2760 | return 2; |
nkeynes@359 | 2761 | :} |
nkeynes@359 | 2762 | LDS Rm, FPUL {: |
nkeynes@671 | 2763 | COUNT_INST(I_LDS); |
nkeynes@626 | 2764 | check_fpuen(); |
nkeynes@991 | 2765 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2766 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@359 | 2767 | :} |
nkeynes@359 | 2768 | LDS.L @Rm+, FPUL {: |
nkeynes@671 | 2769 | COUNT_INST(I_LDSM); |
nkeynes@626 | 2770 | check_fpuen(); |
nkeynes@991 | 2771 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2772 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2773 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2774 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2775 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@417 | 2776 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2777 | :} |
nkeynes@359 | 2778 | LDS Rm, MACH {: |
nkeynes@671 | 2779 | COUNT_INST(I_LDS); |
nkeynes@991 | 2780 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2781 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@359 | 2782 | :} |
nkeynes@359 | 2783 | LDS.L @Rm+, MACH {: |
nkeynes@671 | 2784 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2785 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2786 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2787 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2788 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2789 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@417 | 2790 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2791 | :} |
nkeynes@359 | 2792 | LDS Rm, MACL {: |
nkeynes@671 | 2793 | COUNT_INST(I_LDS); |
nkeynes@991 | 2794 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2795 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@359 | 2796 | :} |
nkeynes@359 | 2797 | LDS.L @Rm+, MACL {: |
nkeynes@671 | 2798 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2799 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2800 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2801 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2802 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2803 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 2804 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2805 | :} |
nkeynes@359 | 2806 | LDS Rm, PR {: |
nkeynes@671 | 2807 | COUNT_INST(I_LDS); |
nkeynes@991 | 2808 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2809 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@359 | 2810 | :} |
nkeynes@359 | 2811 | LDS.L @Rm+, PR {: |
nkeynes@671 | 2812 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2813 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2814 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2815 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2816 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2817 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@417 | 2818 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2819 | :} |
nkeynes@550 | 2820 | LDTLB {: |
nkeynes@671 | 2821 | COUNT_INST(I_LDTLB); |
nkeynes@995 | 2822 | CALL_ptr( MMU_ldtlb ); |
nkeynes@875 | 2823 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@550 | 2824 | :} |
nkeynes@671 | 2825 | OCBI @Rn {: |
nkeynes@671 | 2826 | COUNT_INST(I_OCBI); |
nkeynes@671 | 2827 | :} |
nkeynes@671 | 2828 | OCBP @Rn {: |
nkeynes@671 | 2829 | COUNT_INST(I_OCBP); |
nkeynes@671 | 2830 | :} |
nkeynes@671 | 2831 | OCBWB @Rn {: |
nkeynes@671 | 2832 | COUNT_INST(I_OCBWB); |
nkeynes@671 | 2833 | :} |
nkeynes@374 | 2834 | PREF @Rn {: |
nkeynes@671 | 2835 | COUNT_INST(I_PREF); |
nkeynes@991 | 2836 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2837 | MEM_PREFETCH( REG_EAX ); |
nkeynes@417 | 2838 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2839 | :} |
nkeynes@388 | 2840 | SLEEP {: |
nkeynes@671 | 2841 | COUNT_INST(I_SLEEP); |
nkeynes@388 | 2842 | check_priv(); |
nkeynes@995 | 2843 | CALL_ptr( sh4_sleep ); |
nkeynes@417 | 2844 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@590 | 2845 | sh4_x86.in_delay_slot = DELAY_NONE; |
nkeynes@408 | 2846 | return 2; |
nkeynes@388 | 2847 | :} |
nkeynes@386 | 2848 | STC SR, Rn {: |
nkeynes@671 | 2849 | COUNT_INST(I_STCSR); |
nkeynes@386 | 2850 | check_priv(); |
nkeynes@995 | 2851 | CALL_ptr(sh4_read_sr); |
nkeynes@991 | 2852 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2853 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2854 | :} |
nkeynes@359 | 2855 | STC GBR, Rn {: |
nkeynes@671 | 2856 | COUNT_INST(I_STC); |
nkeynes@995 | 2857 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 2858 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2859 | :} |
nkeynes@359 | 2860 | STC VBR, Rn {: |
nkeynes@671 | 2861 | COUNT_INST(I_STC); |
nkeynes@386 | 2862 | check_priv(); |
nkeynes@995 | 2863 | MOVL_rbpdisp_r32( R_VBR, REG_EAX ); |
nkeynes@991 | 2864 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2865 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2866 | :} |
nkeynes@359 | 2867 | STC SSR, Rn {: |
nkeynes@671 | 2868 | COUNT_INST(I_STC); |
nkeynes@386 | 2869 | check_priv(); |
nkeynes@995 | 2870 | MOVL_rbpdisp_r32( R_SSR, REG_EAX ); |
nkeynes@991 | 2871 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2872 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2873 | :} |
nkeynes@359 | 2874 | STC SPC, Rn {: |
nkeynes@671 | 2875 | COUNT_INST(I_STC); |
nkeynes@386 | 2876 | check_priv(); |
nkeynes@995 | 2877 | MOVL_rbpdisp_r32( R_SPC, REG_EAX ); |
nkeynes@991 | 2878 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2879 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2880 | :} |
nkeynes@359 | 2881 | STC SGR, Rn {: |
nkeynes@671 | 2882 | COUNT_INST(I_STC); |
nkeynes@386 | 2883 | check_priv(); |
nkeynes@995 | 2884 | MOVL_rbpdisp_r32( R_SGR, REG_EAX ); |
nkeynes@991 | 2885 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2886 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2887 | :} |
nkeynes@359 | 2888 | STC DBR, Rn {: |
nkeynes@671 | 2889 | COUNT_INST(I_STC); |
nkeynes@386 | 2890 | check_priv(); |
nkeynes@995 | 2891 | MOVL_rbpdisp_r32( R_DBR, REG_EAX ); |
nkeynes@991 | 2892 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2893 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2894 | :} |
nkeynes@374 | 2895 | STC Rm_BANK, Rn {: |
nkeynes@671 | 2896 | COUNT_INST(I_STC); |
nkeynes@386 | 2897 | check_priv(); |
nkeynes@995 | 2898 | MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EAX ); |
nkeynes@991 | 2899 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2900 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2901 | :} |
nkeynes@374 | 2902 | STC.L SR, @-Rn {: |
nkeynes@671 | 2903 | COUNT_INST(I_STCSRM); |
nkeynes@586 | 2904 | check_priv(); |
nkeynes@995 | 2905 | CALL_ptr( sh4_read_sr ); |
nkeynes@991 | 2906 | MOVL_r32_r32( REG_EAX, REG_EDX ); |
nkeynes@991 | 2907 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2908 | check_walign32( REG_EAX ); |
nkeynes@991 | 2909 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2910 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2911 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2912 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2913 | :} |
nkeynes@359 | 2914 | STC.L VBR, @-Rn {: |
nkeynes@671 | 2915 | COUNT_INST(I_STCM); |
nkeynes@586 | 2916 | check_priv(); |
nkeynes@991 | 2917 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2918 | check_walign32( REG_EAX ); |
nkeynes@991 | 2919 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2920 | MOVL_rbpdisp_r32( R_VBR, REG_EDX ); |
nkeynes@991 | 2921 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2922 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2923 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2924 | :} |
nkeynes@359 | 2925 | STC.L SSR, @-Rn {: |
nkeynes@671 | 2926 | COUNT_INST(I_STCM); |
nkeynes@586 | 2927 | check_priv(); |
nkeynes@991 | 2928 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2929 | check_walign32( REG_EAX ); |
nkeynes@991 | 2930 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2931 | MOVL_rbpdisp_r32( R_SSR, REG_EDX ); |
nkeynes@991 | 2932 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2933 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2934 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2935 | :} |
nkeynes@416 | 2936 | STC.L SPC, @-Rn {: |
nkeynes@671 | 2937 | COUNT_INST(I_STCM); |
nkeynes@586 | 2938 | check_priv(); |
nkeynes@991 | 2939 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2940 | check_walign32( REG_EAX ); |
nkeynes@991 | 2941 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2942 | MOVL_rbpdisp_r32( R_SPC, REG_EDX ); |
nkeynes@991 | 2943 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2944 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2945 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2946 | :} |
nkeynes@359 | 2947 | STC.L SGR, @-Rn {: |
nkeynes@671 | 2948 | COUNT_INST(I_STCM); |
nkeynes@586 | 2949 | check_priv(); |
nkeynes@991 | 2950 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2951 | check_walign32( REG_EAX ); |
nkeynes@991 | 2952 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2953 | MOVL_rbpdisp_r32( R_SGR, REG_EDX ); |
nkeynes@991 | 2954 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2955 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2956 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2957 | :} |
nkeynes@359 | 2958 | STC.L DBR, @-Rn {: |
nkeynes@671 | 2959 | COUNT_INST(I_STCM); |
nkeynes@586 | 2960 | check_priv(); |
nkeynes@991 | 2961 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2962 | check_walign32( REG_EAX ); |
nkeynes@991 | 2963 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2964 | MOVL_rbpdisp_r32( R_DBR, REG_EDX ); |
nkeynes@991 | 2965 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2966 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2967 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2968 | :} |
nkeynes@374 | 2969 | STC.L Rm_BANK, @-Rn {: |
nkeynes@671 | 2970 | COUNT_INST(I_STCM); |
nkeynes@586 | 2971 | check_priv(); |
nkeynes@991 | 2972 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2973 | check_walign32( REG_EAX ); |
nkeynes@991 | 2974 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2975 | MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EDX ); |
nkeynes@991 | 2976 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2977 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2978 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2979 | :} |
nkeynes@359 | 2980 | STC.L GBR, @-Rn {: |
nkeynes@671 | 2981 | COUNT_INST(I_STCM); |
nkeynes@991 | 2982 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2983 | check_walign32( REG_EAX ); |
nkeynes@991 | 2984 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2985 | MOVL_rbpdisp_r32( R_GBR, REG_EDX ); |
nkeynes@991 | 2986 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2987 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2988 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2989 | :} |
nkeynes@359 | 2990 | STS FPSCR, Rn {: |
nkeynes@673 | 2991 | COUNT_INST(I_STSFPSCR); |
nkeynes@626 | 2992 | check_fpuen(); |
nkeynes@995 | 2993 | MOVL_rbpdisp_r32( R_FPSCR, REG_EAX ); |
nkeynes@991 | 2994 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2995 | :} |
nkeynes@359 | 2996 | STS.L FPSCR, @-Rn {: |
nkeynes@673 | 2997 | COUNT_INST(I_STSFPSCRM); |
nkeynes@626 | 2998 | check_fpuen(); |
nkeynes@991 | 2999 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3000 | check_walign32( REG_EAX ); |
nkeynes@991 | 3001 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3002 | MOVL_rbpdisp_r32( R_FPSCR, REG_EDX ); |
nkeynes@991 | 3003 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3004 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3005 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3006 | :} |
nkeynes@359 | 3007 | STS FPUL, Rn {: |
nkeynes@671 | 3008 | COUNT_INST(I_STS); |
nkeynes@626 | 3009 | check_fpuen(); |
nkeynes@995 | 3010 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@991 | 3011 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 3012 | :} |
nkeynes@359 | 3013 | STS.L FPUL, @-Rn {: |
nkeynes@671 | 3014 | COUNT_INST(I_STSM); |
nkeynes@626 | 3015 | check_fpuen(); |
nkeynes@991 | 3016 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3017 | check_walign32( REG_EAX ); |
nkeynes@991 | 3018 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3019 | MOVL_rbpdisp_r32( R_FPUL, REG_EDX ); |
nkeynes@991 | 3020 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3021 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3022 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3023 | :} |
nkeynes@359 | 3024 | STS MACH, Rn {: |
nkeynes@671 | 3025 | COUNT_INST(I_STS); |
nkeynes@995 | 3026 | MOVL_rbpdisp_r32( R_MACH, REG_EAX ); |
nkeynes@991 | 3027 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 3028 | :} |
nkeynes@359 | 3029 | STS.L MACH, @-Rn {: |
nkeynes@671 | 3030 | COUNT_INST(I_STSM); |
nkeynes@991 | 3031 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3032 | check_walign32( REG_EAX ); |
nkeynes@991 | 3033 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3034 | MOVL_rbpdisp_r32( R_MACH, REG_EDX ); |
nkeynes@991 | 3035 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3036 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3037 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3038 | :} |
nkeynes@359 | 3039 | STS MACL, Rn {: |
nkeynes@671 | 3040 | COUNT_INST(I_STS); |
nkeynes@995 | 3041 | MOVL_rbpdisp_r32( R_MACL, REG_EAX ); |
nkeynes@991 | 3042 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 3043 | :} |
nkeynes@359 | 3044 | STS.L MACL, @-Rn {: |
nkeynes@671 | 3045 | COUNT_INST(I_STSM); |
nkeynes@991 | 3046 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3047 | check_walign32( REG_EAX ); |
nkeynes@991 | 3048 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3049 | MOVL_rbpdisp_r32( R_MACL, REG_EDX ); |
nkeynes@991 | 3050 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3051 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3052 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3053 | :} |
nkeynes@359 | 3054 | STS PR, Rn {: |
nkeynes@671 | 3055 | COUNT_INST(I_STS); |
nkeynes@995 | 3056 | MOVL_rbpdisp_r32( R_PR, REG_EAX ); |
nkeynes@991 | 3057 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 3058 | :} |
nkeynes@359 | 3059 | STS.L PR, @-Rn {: |
nkeynes@671 | 3060 | COUNT_INST(I_STSM); |
nkeynes@991 | 3061 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3062 | check_walign32( REG_EAX ); |
nkeynes@991 | 3063 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3064 | MOVL_rbpdisp_r32( R_PR, REG_EDX ); |
nkeynes@991 | 3065 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3066 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3067 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3068 | :} |
nkeynes@359 | 3069 | |
nkeynes@671 | 3070 | NOP {: |
nkeynes@671 | 3071 | COUNT_INST(I_NOP); |
nkeynes@671 | 3072 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ |
nkeynes@671 | 3073 | :} |
nkeynes@359 | 3074 | %% |
nkeynes@590 | 3075 | sh4_x86.in_delay_slot = DELAY_NONE; |
nkeynes@359 | 3076 | return 0; |
nkeynes@359 | 3077 | } |
nkeynes@995 | 3078 | |
nkeynes@995 | 3079 | |
nkeynes@995 | 3080 | /** |
nkeynes@995 | 3081 | * The unwind methods only work if we compiled with DWARF2 frame information |
nkeynes@995 | 3082 | * (ie -fexceptions), otherwise we have to use the direct frame scan. |
nkeynes@995 | 3083 | */ |
nkeynes@995 | 3084 | #ifdef HAVE_EXCEPTIONS |
nkeynes@995 | 3085 | #include <unwind.h> |
nkeynes@995 | 3086 | |
nkeynes@995 | 3087 | struct UnwindInfo { |
nkeynes@995 | 3088 | uintptr_t block_start; |
nkeynes@995 | 3089 | uintptr_t block_end; |
nkeynes@995 | 3090 | void *pc; |
nkeynes@995 | 3091 | }; |
nkeynes@995 | 3092 | |
nkeynes@995 | 3093 | static _Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg ) |
nkeynes@995 | 3094 | { |
nkeynes@995 | 3095 | struct UnwindInfo *info = arg; |
nkeynes@995 | 3096 | void *pc = (void *)_Unwind_GetIP(context); |
nkeynes@995 | 3097 | if( ((uintptr_t)pc) >= info->block_start && ((uintptr_t)pc) < info->block_end ) { |
nkeynes@995 | 3098 | info->pc = pc; |
nkeynes@995 | 3099 | return _URC_NORMAL_STOP; |
nkeynes@995 | 3100 | } |
nkeynes@995 | 3101 | return _URC_NO_REASON; |
nkeynes@995 | 3102 | } |
nkeynes@995 | 3103 | |
nkeynes@995 | 3104 | void *xlat_get_native_pc( void *code, uint32_t code_size ) |
nkeynes@995 | 3105 | { |
nkeynes@995 | 3106 | struct _Unwind_Exception exc; |
nkeynes@995 | 3107 | struct UnwindInfo info; |
nkeynes@995 | 3108 | |
nkeynes@995 | 3109 | info.pc = NULL; |
nkeynes@995 | 3110 | info.block_start = (uintptr_t)code; |
nkeynes@995 | 3111 | info.block_end = info.block_start + code_size; |
nkeynes@995 | 3112 | void *result = NULL; |
nkeynes@995 | 3113 | _Unwind_Backtrace( xlat_check_frame, &info ); |
nkeynes@995 | 3114 | return info.pc; |
nkeynes@995 | 3115 | } |
nkeynes@995 | 3116 | #else |
nkeynes@995 | 3117 | /* Assume this is an ia32 build - amd64 should always have dwarf information */ |
nkeynes@995 | 3118 | void *xlat_get_native_pc( void *code, uint32_t code_size ) |
nkeynes@995 | 3119 | { |
nkeynes@995 | 3120 | void *result = NULL; |
nkeynes@995 | 3121 | asm( |
nkeynes@995 | 3122 | "mov %%ebp, %%eax\n\t" |
nkeynes@995 | 3123 | "mov $0x8, %%ecx\n\t" |
nkeynes@995 | 3124 | "mov %1, %%edx\n" |
nkeynes@995 | 3125 | "frame_loop: test %%eax, %%eax\n\t" |
nkeynes@995 | 3126 | "je frame_not_found\n\t" |
nkeynes@995 | 3127 | "cmp (%%eax), %%edx\n\t" |
nkeynes@995 | 3128 | "je frame_found\n\t" |
nkeynes@995 | 3129 | "sub $0x1, %%ecx\n\t" |
nkeynes@995 | 3130 | "je frame_not_found\n\t" |
nkeynes@995 | 3131 | "movl (%%eax), %%eax\n\t" |
nkeynes@995 | 3132 | "jmp frame_loop\n" |
nkeynes@995 | 3133 | "frame_found: movl 0x4(%%eax), %0\n" |
nkeynes@995 | 3134 | "frame_not_found:" |
nkeynes@995 | 3135 | : "=r" (result) |
nkeynes@995 | 3136 | : "r" (((uint8_t *)&sh4r) + 128 ) |
nkeynes@995 | 3137 | : "eax", "ecx", "edx" ); |
nkeynes@995 | 3138 | return result; |
nkeynes@995 | 3139 | } |
nkeynes@995 | 3140 | #endif |
nkeynes@995 | 3141 |
.