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lxdream.org :: lxdream/src/sh4/ia32mac.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/ia32mac.h
changeset 590:4db6a084ca3c
prev586:2a3ba82cf243
next596:dfc0c93d882e
author nkeynes
date Wed Jan 16 09:39:16 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Ensure PC correctness in presence of delay-slot exceptions
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * Provides the implementation for the ia32 ABI (eg prologue, epilogue, and
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 * calling conventions)
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef __lxdream_ia32abi_H
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#define __lxdream_ia32abi_H 1
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#define load_ptr( reg, ptr ) load_imm32( reg, (uint32_t)ptr );
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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#define CALL_FUNC0_SIZE 13
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static inline void call_func0( void *ptr )
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{
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    int adj = (-sh4_x86.stack_posn)&0x0F;
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    SUB_imm8s_r32( adj, R_ESP );
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( adj, R_ESP );
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}
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#define CALL_FUNC1_SIZE 14
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static inline void call_func1( void *ptr, int arg1 )
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{
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    int adj = (-4-sh4_x86.stack_posn)&0x0F;
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    SUB_imm8s_r32( adj, R_ESP );
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    PUSH_r32(arg1);
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( adj+4, R_ESP );
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    sh4_x86.stack_posn -= 4;
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}
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#define CALL_FUNC2_SIZE 15
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    int adj = (-8-sh4_x86.stack_posn)&0x0F;
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    SUB_imm8s_r32( adj, R_ESP );
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( adj+8, R_ESP );
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    sh4_x86.stack_posn -= 8;
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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#define MEM_WRITE_DOUBLE_SIZE 36
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    int adj = (-8-sh4_x86.stack_posn)&0x0F;
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    SUB_imm8s_r32( adj, R_ESP );
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    SUB_imm8s_r32( 8, R_ESP );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    load_imm32(R_EAX, (uint32_t)sh4_write_long);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( 16, R_ESP );
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    load_imm32(R_EAX, (uint32_t)sh4_write_long);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( adj+8, R_ESP );
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    sh4_x86.stack_posn -= 16;
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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#define MEM_READ_DOUBLE_SIZE 36
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    int adj = (-4-sh4_x86.stack_posn)&0x0F;
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    int adj2 = (-8-sh4_x86.stack_posn)&0x0F;
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    SUB_imm8s_r32( adj, R_ESP );
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    PUSH_r32(addr);
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    load_imm32(R_EAX, (uint32_t)sh4_read_long);
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    CALL_r32(R_EAX);
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    POP_r32(R_ECX);
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    SUB_imm8s_r32( adj2-adj, R_ESP );
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, R_ECX );
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    PUSH_r32(R_ECX);
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    load_imm32(R_EAX, (uint32_t)sh4_read_long);
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    CALL_r32(R_EAX);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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    ADD_imm8s_r32( adj2, R_ESP );
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    sh4_x86.stack_posn -= 4;
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}
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block( sh4addr_t pc ) 
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{
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    PUSH_r32(R_EBP);
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    /* mov &sh4r, ebp */
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    load_ptr( R_EBP, &sh4r );
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    sh4_x86.in_delay_slot = FALSE;
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    sh4_x86.priv_checked = FALSE;
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    sh4_x86.fpuen_checked = FALSE;
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    sh4_x86.branch_taken = FALSE;
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    sh4_x86.backpatch_posn = 0;
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    sh4_x86.recovery_posn = 0;
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    sh4_x86.block_start_pc = pc;
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    sh4_x86.tstate = TSTATE_NONE;
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    sh4_x86.tlb_on = IS_MMU_ENABLED();
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    sh4_x86.stack_posn = 8;
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}
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/**
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 * Exit the block with sh4r.new_pc written with the target pc
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 */
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void exit_block_pcset( sh4addr_t pc )
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{
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    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
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    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
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    load_spreg( R_EAX, R_PC );
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    if( sh4_x86.tlb_on ) {
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	call_func1(xlat_get_code_by_vma,R_EAX);
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    } else {
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	call_func1(xlat_get_code,R_EAX);
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    }
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    POP_r32(R_EBP);
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    RET();
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}
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/**
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 * Exit the block with sh4r.new_pc written with the target pc
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 */
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void exit_block_newpcset( sh4addr_t pc )
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{
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    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
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    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
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    load_spreg( R_EAX, R_NEW_PC );
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    store_spreg( R_EAX, R_PC );
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    if( sh4_x86.tlb_on ) {
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	call_func1(xlat_get_code_by_vma,R_EAX);
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    } else {
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	call_func1(xlat_get_code,R_EAX);
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    }
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    POP_r32(R_EBP);
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    RET();
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}
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#define EXIT_BLOCK_SIZE(pc)  (24 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
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/**
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 * Exit the block to an absolute PC
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 */
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void exit_block( sh4addr_t pc, sh4addr_t endpc )
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{
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    load_imm32( R_ECX, pc );                            // 5
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    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
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    if( IS_IN_ICACHE(pc) ) {
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	MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
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    } else if( sh4_x86.tlb_on ) {
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	call_func1(xlat_get_code_by_vma,R_ECX);
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    } else {
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	call_func1(xlat_get_code,R_ECX);
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    }
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    AND_imm8s_r32( 0xFC, R_EAX ); // 3
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    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
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    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
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    POP_r32(R_EBP);
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    RET();
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}
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#define EXIT_BLOCK_REL_SIZE(pc)  (27 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
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/**
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 * Exit the block to a relative PC
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 */
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void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
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{
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    load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
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    ADD_sh4r_r32( R_PC, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
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    if( IS_IN_ICACHE(pc) ) {
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	MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
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    } else if( sh4_x86.tlb_on ) {
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	call_func1(xlat_get_code_by_vma,R_ECX);
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    } else {
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	call_func1(xlat_get_code,R_ECX);
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    }
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    AND_imm8s_r32( 0xFC, R_EAX ); // 3
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    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
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    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
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    POP_r32(R_EBP);
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    RET();
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}
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/**
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 * Write the block trailer (exception handling block)
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 */
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void sh4_translate_end_block( sh4addr_t pc ) {
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    if( sh4_x86.branch_taken == FALSE ) {
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	// Didn't exit unconditionally already, so write the termination here
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	exit_block_rel( pc, pc );
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    }
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    if( sh4_x86.backpatch_posn != 0 ) {
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	unsigned int i;
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	// Raise exception
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	uint8_t *end_ptr = xlat_output;
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	MOV_r32_r32( R_EDX, R_ECX );
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	ADD_r32_r32( R_EDX, R_ECX );
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	ADD_r32_sh4r( R_ECX, R_PC );
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	MOV_moff32_EAX( &sh4_cpu_period );
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	MUL_r32( R_EDX );
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	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
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        POP_r32(R_EDX);
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        call_func1( sh4_raise_exception, R_EDX );
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   245
	load_spreg( R_EAX, R_PC );
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	if( sh4_x86.tlb_on ) {
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	    call_func1(xlat_get_code_by_vma,R_EAX);
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	} else {
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	    call_func1(xlat_get_code,R_EAX);
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	}
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	POP_r32(R_EBP);
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	RET();
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	// Exception already raised - just cleanup
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	uint8_t *preexc_ptr = xlat_output;
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	MOV_r32_r32( R_EDX, R_ECX );
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	ADD_r32_r32( R_EDX, R_ECX );
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   258
	ADD_r32_sh4r( R_ECX, R_SPC );
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   259
	MOV_moff32_EAX( &sh4_cpu_period );
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   260
	MUL_r32( R_EDX );
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	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
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   262
	load_spreg( R_EAX, R_PC );
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   263
	if( sh4_x86.tlb_on ) {
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	    call_func1(xlat_get_code_by_vma,R_EAX);
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   265
	} else {
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   266
	    call_func1(xlat_get_code,R_EAX);
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   267
	}
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   268
	POP_r32(R_EBP);
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   269
	RET();
nkeynes@586
   270
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   271
	for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
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	    *sh4_x86.backpatch_list[i].fixup_addr =
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		xlat_output - ((uint8_t *)sh4_x86.backpatch_list[i].fixup_addr) - 4;
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   274
	    if( sh4_x86.backpatch_list[i].exc_code == -1 ) {
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   275
		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
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   276
		int rel = preexc_ptr - xlat_output;
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   277
		JMP_rel(rel);
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   278
	    } else {
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   279
		PUSH_imm32( sh4_x86.backpatch_list[i].exc_code );
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   280
		load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
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   281
		int rel = end_ptr - xlat_output;
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		JMP_rel(rel);
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   283
	    }
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   284
	}
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    }
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   286
}
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   287
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   288
void *xlat_get_native_pc()
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   289
{
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   290
    void *result = NULL;
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   291
    asm(
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   292
	"mov %%ebp, %%eax\n\t"
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   293
	"mov $0x8, %%ecx\n\t"
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   294
	"mov %1, %%edx\n"
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   295
"frame_loop: test %%eax, %%eax\n\t"
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   296
	"je frame_not_found\n\t"
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   297
	"cmp (%%eax), %%edx\n\t"
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   298
	"je frame_found\n\t"
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   299
	"sub $0x1, %%ecx\n\t"
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   300
	"je frame_not_found\n\t"
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   301
	"movl (%%eax), %%eax\n\t"
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   302
	"jmp frame_loop\n"
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   303
"frame_found: movl 0x4(%%eax), %0\n"
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   304
"frame_not_found:"
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   305
	: "=r" (result)
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   306
	: "r" (&sh4r)
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   307
	: "eax", "ecx", "edx" );
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   308
    return result;
nkeynes@586
   309
}
nkeynes@586
   310
nkeynes@586
   311
nkeynes@539
   312
#endif
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   313
nkeynes@539
   314
.