Search
lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.c
changeset 590:4db6a084ca3c
prev586:2a3ba82cf243
next591:7b9612fd2395
author nkeynes
date Wed Jan 16 09:39:16 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Ensure PC correctness in presence of delay-slot exceptions
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@586
     2
 * $Id$
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359
    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359
    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@368
    21
#include <assert.h>
nkeynes@388
    22
#include <math.h>
nkeynes@368
    23
nkeynes@380
    24
#ifndef NDEBUG
nkeynes@380
    25
#define DEBUG_JUMPS 1
nkeynes@380
    26
#endif
nkeynes@380
    27
nkeynes@417
    28
#include "sh4/xltcache.h"
nkeynes@368
    29
#include "sh4/sh4core.h"
nkeynes@368
    30
#include "sh4/sh4trans.h"
nkeynes@388
    31
#include "sh4/sh4mmio.h"
nkeynes@368
    32
#include "sh4/x86op.h"
nkeynes@368
    33
#include "clock.h"
nkeynes@368
    34
nkeynes@368
    35
#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368
    36
nkeynes@586
    37
struct backpatch_record {
nkeynes@586
    38
    uint32_t *fixup_addr;
nkeynes@586
    39
    uint32_t fixup_icount;
nkeynes@586
    40
    uint32_t exc_code;
nkeynes@586
    41
};
nkeynes@586
    42
nkeynes@586
    43
#define MAX_RECOVERY_SIZE 2048
nkeynes@586
    44
nkeynes@590
    45
#define DELAY_NONE 0
nkeynes@590
    46
#define DELAY_PC 1
nkeynes@590
    47
#define DELAY_PC_PR 2
nkeynes@590
    48
nkeynes@368
    49
/** 
nkeynes@368
    50
 * Struct to manage internal translation state. This state is not saved -
nkeynes@368
    51
 * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368
    52
 * sh4_translate_end_block()
nkeynes@368
    53
 */
nkeynes@368
    54
struct sh4_x86_state {
nkeynes@590
    55
    int in_delay_slot;
nkeynes@368
    56
    gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368
    57
    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409
    58
    gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@408
    59
    uint32_t block_start_pc;
nkeynes@547
    60
    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
nkeynes@417
    61
    int tstate;
nkeynes@368
    62
nkeynes@586
    63
    /* mode flags */
nkeynes@586
    64
    gboolean tlb_on; /* True if tlb translation is active */
nkeynes@586
    65
nkeynes@368
    66
    /* Allocated memory for the (block-wide) back-patch list */
nkeynes@586
    67
    struct backpatch_record *backpatch_list;
nkeynes@368
    68
    uint32_t backpatch_posn;
nkeynes@368
    69
    uint32_t backpatch_size;
nkeynes@586
    70
    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
nkeynes@586
    71
    uint32_t recovery_posn;
nkeynes@368
    72
};
nkeynes@368
    73
nkeynes@417
    74
#define TSTATE_NONE -1
nkeynes@417
    75
#define TSTATE_O    0
nkeynes@417
    76
#define TSTATE_C    2
nkeynes@417
    77
#define TSTATE_E    4
nkeynes@417
    78
#define TSTATE_NE   5
nkeynes@417
    79
#define TSTATE_G    0xF
nkeynes@417
    80
#define TSTATE_GE   0xD
nkeynes@417
    81
#define TSTATE_A    7
nkeynes@417
    82
#define TSTATE_AE   3
nkeynes@417
    83
nkeynes@417
    84
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@417
    85
#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    86
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    87
    OP(0x70+sh4_x86.tstate); OP(rel8); \
nkeynes@417
    88
    MARK_JMP(rel8,label)
nkeynes@417
    89
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@417
    90
#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    91
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    92
    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
nkeynes@417
    93
    MARK_JMP(rel8, label)
nkeynes@417
    94
nkeynes@368
    95
static struct sh4_x86_state sh4_x86;
nkeynes@368
    96
nkeynes@388
    97
static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388
    98
static uint32_t min_int = 0x80000000;
nkeynes@394
    99
static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394
   100
static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386
   101
nkeynes@368
   102
void sh4_x86_init()
nkeynes@368
   103
{
nkeynes@368
   104
    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@586
   105
    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@368
   106
}
nkeynes@368
   107
nkeynes@368
   108
nkeynes@586
   109
static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368
   110
{
nkeynes@368
   111
    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368
   112
	sh4_x86.backpatch_size <<= 1;
nkeynes@586
   113
	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
nkeynes@586
   114
					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368
   115
	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368
   116
    }
nkeynes@586
   117
    if( sh4_x86.in_delay_slot ) {
nkeynes@586
   118
	fixup_pc -= 2;
nkeynes@586
   119
    }
nkeynes@586
   120
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
nkeynes@586
   121
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@586
   122
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@586
   123
    sh4_x86.backpatch_posn++;
nkeynes@368
   124
}
nkeynes@368
   125
nkeynes@586
   126
void sh4_x86_add_recovery( uint32_t pc )
nkeynes@368
   127
{
nkeynes@586
   128
    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
nkeynes@586
   129
    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
nkeynes@586
   130
    xlat_recovery_posn++;
nkeynes@368
   131
}
nkeynes@368
   132
nkeynes@359
   133
/**
nkeynes@359
   134
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
   135
 */
nkeynes@359
   136
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
   137
{
nkeynes@359
   138
    /* mov [bp+n], reg */
nkeynes@361
   139
    OP(0x8B);
nkeynes@361
   140
    OP(0x45 + (x86reg<<3));
nkeynes@359
   141
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   142
}
nkeynes@359
   143
nkeynes@374
   144
static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368
   145
{
nkeynes@374
   146
    OP(0x0F);
nkeynes@374
   147
    OP(0xBF);
nkeynes@374
   148
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368
   149
}
nkeynes@368
   150
nkeynes@374
   151
static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368
   152
{
nkeynes@374
   153
    OP(0x0F);
nkeynes@374
   154
    OP(0xB7);
nkeynes@374
   155
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374
   156
nkeynes@368
   157
}
nkeynes@368
   158
nkeynes@380
   159
#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380
   160
#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359
   161
/**
nkeynes@359
   162
 * Emit an instruction to load an immediate value into a register
nkeynes@359
   163
 */
nkeynes@359
   164
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
   165
    /* mov #value, reg */
nkeynes@359
   166
    OP(0xB8 + x86reg);
nkeynes@359
   167
    OP32(value);
nkeynes@359
   168
}
nkeynes@359
   169
nkeynes@359
   170
/**
nkeynes@527
   171
 * Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527
   172
 */
nkeynes@527
   173
static inline void load_imm64( int x86reg, uint32_t value ) {
nkeynes@527
   174
    /* mov #value, reg */
nkeynes@527
   175
    REXW();
nkeynes@527
   176
    OP(0xB8 + x86reg);
nkeynes@527
   177
    OP64(value);
nkeynes@527
   178
}
nkeynes@527
   179
nkeynes@527
   180
nkeynes@527
   181
/**
nkeynes@359
   182
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
   183
 */
nkeynes@359
   184
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
   185
    /* mov reg, [bp+n] */
nkeynes@361
   186
    OP(0x89);
nkeynes@361
   187
    OP(0x45 + (x86reg<<3));
nkeynes@359
   188
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   189
}
nkeynes@374
   190
nkeynes@374
   191
#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374
   192
nkeynes@375
   193
/**
nkeynes@375
   194
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   195
 * register (eg for register-to-register moves)
nkeynes@375
   196
 */
nkeynes@375
   197
void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375
   198
{
nkeynes@375
   199
    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375
   200
}
nkeynes@375
   201
nkeynes@375
   202
/**
nkeynes@375
   203
 * Store an FR register (single-precision floating point) into an integer x86
nkeynes@375
   204
 * register (eg for register-to-register moves)
nkeynes@375
   205
 */
nkeynes@375
   206
void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375
   207
{
nkeynes@375
   208
    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375
   209
}
nkeynes@375
   210
nkeynes@375
   211
nkeynes@375
   212
/**
nkeynes@375
   213
 * Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375
   214
 * bankreg must have been previously loaded with FPSCR.
nkeynes@388
   215
 * NB: 12 bytes
nkeynes@375
   216
 */
nkeynes@374
   217
static inline void load_xf_bank( int bankreg )
nkeynes@374
   218
{
nkeynes@386
   219
    NOT_r32( bankreg );
nkeynes@374
   220
    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374
   221
    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
nkeynes@374
   222
    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374
   223
}
nkeynes@374
   224
nkeynes@375
   225
/**
nkeynes@386
   226
 * Update the fr_bank pointer based on the current fpscr value.
nkeynes@386
   227
 */
nkeynes@386
   228
static inline void update_fr_bank( int fpscrreg )
nkeynes@386
   229
{
nkeynes@386
   230
    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386
   231
    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
nkeynes@386
   232
    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386
   233
    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386
   234
}
nkeynes@386
   235
/**
nkeynes@377
   236
 * Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377
   237
 */
nkeynes@377
   238
static inline void push_fpul( )
nkeynes@377
   239
{
nkeynes@377
   240
    OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377
   241
}
nkeynes@377
   242
nkeynes@377
   243
/**
nkeynes@377
   244
 * Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377
   245
 */
nkeynes@377
   246
static inline void pop_fpul( )
nkeynes@377
   247
{
nkeynes@377
   248
    OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377
   249
}
nkeynes@377
   250
nkeynes@377
   251
/**
nkeynes@375
   252
 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375
   253
 * with the location of the current fp bank.
nkeynes@375
   254
 */
nkeynes@374
   255
static inline void push_fr( int bankreg, int frm ) 
nkeynes@374
   256
{
nkeynes@374
   257
    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
nkeynes@374
   258
}
nkeynes@374
   259
nkeynes@375
   260
/**
nkeynes@375
   261
 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
nkeynes@375
   262
 * with bankreg previously loaded with the location of the current fp bank.
nkeynes@375
   263
 */
nkeynes@374
   264
static inline void pop_fr( int bankreg, int frm )
nkeynes@374
   265
{
nkeynes@374
   266
    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374
   267
}
nkeynes@374
   268
nkeynes@375
   269
/**
nkeynes@375
   270
 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375
   271
 * with the location of the current fp bank.
nkeynes@375
   272
 */
nkeynes@374
   273
static inline void push_dr( int bankreg, int frm )
nkeynes@374
   274
{
nkeynes@377
   275
    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374
   276
}
nkeynes@374
   277
nkeynes@374
   278
static inline void pop_dr( int bankreg, int frm )
nkeynes@374
   279
{
nkeynes@377
   280
    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374
   281
}
nkeynes@374
   282
nkeynes@368
   283
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   284
nkeynes@416
   285
#define check_priv( ) \
nkeynes@416
   286
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   287
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   288
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   289
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   290
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   291
	    JE_exc( EXC_SLOT_ILLEGAL );\
nkeynes@416
   292
	} else {\
nkeynes@586
   293
	    JE_exc( EXC_ILLEGAL );\
nkeynes@416
   294
	}\
nkeynes@416
   295
    }\
nkeynes@416
   296
nkeynes@416
   297
#define check_fpuen( ) \
nkeynes@416
   298
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   299
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   300
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   301
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   302
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   303
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   304
	} else {\
nkeynes@586
   305
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   306
	}\
nkeynes@416
   307
    }
nkeynes@416
   308
nkeynes@586
   309
#define check_ralign16( x86reg ) \
nkeynes@586
   310
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586
   311
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   312
nkeynes@586
   313
#define check_walign16( x86reg ) \
nkeynes@586
   314
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586
   315
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   316
nkeynes@586
   317
#define check_ralign32( x86reg ) \
nkeynes@586
   318
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586
   319
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   320
nkeynes@586
   321
#define check_walign32( x86reg ) \
nkeynes@586
   322
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586
   323
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   324
nkeynes@361
   325
#define UNDEF()
nkeynes@361
   326
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   327
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   328
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   329
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   330
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   331
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   332
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   333
nkeynes@586
   334
/**
nkeynes@586
   335
 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
nkeynes@586
   336
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   337
 */
nkeynes@586
   338
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   339
/**
nkeynes@586
   340
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   341
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   342
 */
nkeynes@586
   343
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   344
nkeynes@586
   345
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   346
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   347
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   348
nkeynes@590
   349
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   350
nkeynes@539
   351
/****** Import appropriate calling conventions ******/
nkeynes@539
   352
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   353
#include "sh4/ia64abi.h"
nkeynes@539
   354
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   355
#ifdef APPLE_BUILD
nkeynes@539
   356
#include "sh4/ia32mac.h"
nkeynes@539
   357
#else
nkeynes@539
   358
#include "sh4/ia32abi.h"
nkeynes@539
   359
#endif
nkeynes@539
   360
#endif
nkeynes@539
   361
nkeynes@590
   362
/**
nkeynes@590
   363
 * Embed a breakpoint into the generated code
nkeynes@590
   364
 */
nkeynes@586
   365
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   366
{
nkeynes@586
   367
    load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );
nkeynes@586
   368
    call_func1( sh4_translate_exit, R_EAX );
nkeynes@586
   369
}
nkeynes@590
   370
nkeynes@590
   371
/**
nkeynes@590
   372
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@590
   373
 * can't translate (mainly page-crossing delay slots at the moment).
nkeynes@590
   374
 * Caller is responsible for setting new_pc.
nkeynes@590
   375
 */
nkeynes@590
   376
void sh4_emulator_exit( sh4vma_t endpc )
nkeynes@590
   377
{
nkeynes@590
   378
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   379
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   380
    
nkeynes@590
   381
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@590
   382
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   383
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   384
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   385
nkeynes@590
   386
    call_func0( sh4_execute_instruction );    
nkeynes@590
   387
    load_imm32( R_EAX, R_PC );
nkeynes@590
   388
    if( sh4_x86.tlb_on ) {
nkeynes@590
   389
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   390
    } else {
nkeynes@590
   391
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   392
    }
nkeynes@590
   393
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@590
   394
    POP_r32(R_EBP);
nkeynes@590
   395
    RET();
nkeynes@590
   396
} 
nkeynes@539
   397
nkeynes@359
   398
/**
nkeynes@359
   399
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   400
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   401
 * 
nkeynes@586
   402
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   403
 *
nkeynes@359
   404
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   405
 * (eg a branch or 
nkeynes@359
   406
 */
nkeynes@590
   407
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   408
{
nkeynes@388
   409
    uint32_t ir;
nkeynes@586
   410
    /* Read instruction from icache */
nkeynes@586
   411
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   412
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   413
    
nkeynes@586
   414
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   415
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   416
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   417
	 * almost certainly in a delay slot.
nkeynes@586
   418
	 *
nkeynes@586
   419
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   420
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   421
	 * small repairs to cope with the different environment).
nkeynes@586
   422
	 */
nkeynes@586
   423
nkeynes@586
   424
    if( !sh4_x86.in_delay_slot ) {
nkeynes@586
   425
	sh4_x86_add_recovery(pc);
nkeynes@388
   426
    }
nkeynes@359
   427
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   428
            case 0x0:
nkeynes@359
   429
                switch( ir&0xF ) {
nkeynes@359
   430
                    case 0x2:
nkeynes@359
   431
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   432
                            case 0x0:
nkeynes@359
   433
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   434
                                    case 0x0:
nkeynes@359
   435
                                        { /* STC SR, Rn */
nkeynes@359
   436
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   437
                                        check_priv();
nkeynes@374
   438
                                        call_func0(sh4_read_sr);
nkeynes@368
   439
                                        store_reg( R_EAX, Rn );
nkeynes@417
   440
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   441
                                        }
nkeynes@359
   442
                                        break;
nkeynes@359
   443
                                    case 0x1:
nkeynes@359
   444
                                        { /* STC GBR, Rn */
nkeynes@359
   445
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   446
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   447
                                        store_reg( R_EAX, Rn );
nkeynes@359
   448
                                        }
nkeynes@359
   449
                                        break;
nkeynes@359
   450
                                    case 0x2:
nkeynes@359
   451
                                        { /* STC VBR, Rn */
nkeynes@359
   452
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   453
                                        check_priv();
nkeynes@359
   454
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   455
                                        store_reg( R_EAX, Rn );
nkeynes@417
   456
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   457
                                        }
nkeynes@359
   458
                                        break;
nkeynes@359
   459
                                    case 0x3:
nkeynes@359
   460
                                        { /* STC SSR, Rn */
nkeynes@359
   461
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   462
                                        check_priv();
nkeynes@359
   463
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   464
                                        store_reg( R_EAX, Rn );
nkeynes@417
   465
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   466
                                        }
nkeynes@359
   467
                                        break;
nkeynes@359
   468
                                    case 0x4:
nkeynes@359
   469
                                        { /* STC SPC, Rn */
nkeynes@359
   470
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   471
                                        check_priv();
nkeynes@359
   472
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   473
                                        store_reg( R_EAX, Rn );
nkeynes@417
   474
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   475
                                        }
nkeynes@359
   476
                                        break;
nkeynes@359
   477
                                    default:
nkeynes@359
   478
                                        UNDEF();
nkeynes@359
   479
                                        break;
nkeynes@359
   480
                                }
nkeynes@359
   481
                                break;
nkeynes@359
   482
                            case 0x1:
nkeynes@359
   483
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   484
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   485
                                check_priv();
nkeynes@374
   486
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   487
                                store_reg( R_EAX, Rn );
nkeynes@417
   488
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   489
                                }
nkeynes@359
   490
                                break;
nkeynes@359
   491
                        }
nkeynes@359
   492
                        break;
nkeynes@359
   493
                    case 0x3:
nkeynes@359
   494
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   495
                            case 0x0:
nkeynes@359
   496
                                { /* BSRF Rn */
nkeynes@359
   497
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   498
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   499
                            	SLOTILLEGAL();
nkeynes@374
   500
                                } else {
nkeynes@590
   501
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   502
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   503
                            	store_spreg( R_EAX, R_PR );
nkeynes@590
   504
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   505
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   506
                            
nkeynes@417
   507
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   508
                            	sh4_translate_instruction( pc + 2 );
nkeynes@590
   509
                            	exit_block_newpcset(pc+2);
nkeynes@409
   510
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   511
                            	return 4;
nkeynes@374
   512
                                }
nkeynes@359
   513
                                }
nkeynes@359
   514
                                break;
nkeynes@359
   515
                            case 0x2:
nkeynes@359
   516
                                { /* BRAF Rn */
nkeynes@359
   517
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   518
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   519
                            	SLOTILLEGAL();
nkeynes@374
   520
                                } else {
nkeynes@590
   521
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   522
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   523
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   524
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   525
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   526
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   527
                            	sh4_translate_instruction( pc + 2 );
nkeynes@590
   528
                            	exit_block_newpcset(pc+2);
nkeynes@409
   529
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   530
                            	return 4;
nkeynes@374
   531
                                }
nkeynes@359
   532
                                }
nkeynes@359
   533
                                break;
nkeynes@359
   534
                            case 0x8:
nkeynes@359
   535
                                { /* PREF @Rn */
nkeynes@359
   536
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   537
                                load_reg( R_EAX, Rn );
nkeynes@532
   538
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   539
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   540
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
   541
                                JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
   542
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
   543
                                TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
   544
                                JE_exc(-1);
nkeynes@380
   545
                                JMP_TARGET(end);
nkeynes@417
   546
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   547
                                }
nkeynes@359
   548
                                break;
nkeynes@359
   549
                            case 0x9:
nkeynes@359
   550
                                { /* OCBI @Rn */
nkeynes@359
   551
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   552
                                }
nkeynes@359
   553
                                break;
nkeynes@359
   554
                            case 0xA:
nkeynes@359
   555
                                { /* OCBP @Rn */
nkeynes@359
   556
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   557
                                }
nkeynes@359
   558
                                break;
nkeynes@359
   559
                            case 0xB:
nkeynes@359
   560
                                { /* OCBWB @Rn */
nkeynes@359
   561
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   562
                                }
nkeynes@359
   563
                                break;
nkeynes@359
   564
                            case 0xC:
nkeynes@359
   565
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   566
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
   567
                                load_reg( R_EAX, Rn );
nkeynes@586
   568
                                check_walign32( R_EAX );
nkeynes@586
   569
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   570
                                load_reg( R_EDX, 0 );
nkeynes@586
   571
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   572
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   573
                                }
nkeynes@359
   574
                                break;
nkeynes@359
   575
                            default:
nkeynes@359
   576
                                UNDEF();
nkeynes@359
   577
                                break;
nkeynes@359
   578
                        }
nkeynes@359
   579
                        break;
nkeynes@359
   580
                    case 0x4:
nkeynes@359
   581
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   582
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   583
                        load_reg( R_EAX, 0 );
nkeynes@359
   584
                        load_reg( R_ECX, Rn );
nkeynes@586
   585
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   586
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   587
                        load_reg( R_EDX, Rm );
nkeynes@586
   588
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   589
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   590
                        }
nkeynes@359
   591
                        break;
nkeynes@359
   592
                    case 0x5:
nkeynes@359
   593
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   594
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   595
                        load_reg( R_EAX, 0 );
nkeynes@361
   596
                        load_reg( R_ECX, Rn );
nkeynes@586
   597
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   598
                        check_walign16( R_EAX );
nkeynes@586
   599
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   600
                        load_reg( R_EDX, Rm );
nkeynes@586
   601
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   602
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   603
                        }
nkeynes@359
   604
                        break;
nkeynes@359
   605
                    case 0x6:
nkeynes@359
   606
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   607
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   608
                        load_reg( R_EAX, 0 );
nkeynes@361
   609
                        load_reg( R_ECX, Rn );
nkeynes@586
   610
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   611
                        check_walign32( R_EAX );
nkeynes@586
   612
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   613
                        load_reg( R_EDX, Rm );
nkeynes@586
   614
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   615
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   616
                        }
nkeynes@359
   617
                        break;
nkeynes@359
   618
                    case 0x7:
nkeynes@359
   619
                        { /* MUL.L Rm, Rn */
nkeynes@359
   620
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   621
                        load_reg( R_EAX, Rm );
nkeynes@361
   622
                        load_reg( R_ECX, Rn );
nkeynes@361
   623
                        MUL_r32( R_ECX );
nkeynes@361
   624
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   625
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   626
                        }
nkeynes@359
   627
                        break;
nkeynes@359
   628
                    case 0x8:
nkeynes@359
   629
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   630
                            case 0x0:
nkeynes@359
   631
                                { /* CLRT */
nkeynes@374
   632
                                CLC();
nkeynes@374
   633
                                SETC_t();
nkeynes@417
   634
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   635
                                }
nkeynes@359
   636
                                break;
nkeynes@359
   637
                            case 0x1:
nkeynes@359
   638
                                { /* SETT */
nkeynes@374
   639
                                STC();
nkeynes@374
   640
                                SETC_t();
nkeynes@417
   641
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   642
                                }
nkeynes@359
   643
                                break;
nkeynes@359
   644
                            case 0x2:
nkeynes@359
   645
                                { /* CLRMAC */
nkeynes@374
   646
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   647
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   648
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   649
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   650
                                }
nkeynes@359
   651
                                break;
nkeynes@359
   652
                            case 0x3:
nkeynes@359
   653
                                { /* LDTLB */
nkeynes@553
   654
                                call_func0( MMU_ldtlb );
nkeynes@359
   655
                                }
nkeynes@359
   656
                                break;
nkeynes@359
   657
                            case 0x4:
nkeynes@359
   658
                                { /* CLRS */
nkeynes@374
   659
                                CLC();
nkeynes@374
   660
                                SETC_sh4r(R_S);
nkeynes@417
   661
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   662
                                }
nkeynes@359
   663
                                break;
nkeynes@359
   664
                            case 0x5:
nkeynes@359
   665
                                { /* SETS */
nkeynes@374
   666
                                STC();
nkeynes@374
   667
                                SETC_sh4r(R_S);
nkeynes@417
   668
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   669
                                }
nkeynes@359
   670
                                break;
nkeynes@359
   671
                            default:
nkeynes@359
   672
                                UNDEF();
nkeynes@359
   673
                                break;
nkeynes@359
   674
                        }
nkeynes@359
   675
                        break;
nkeynes@359
   676
                    case 0x9:
nkeynes@359
   677
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   678
                            case 0x0:
nkeynes@359
   679
                                { /* NOP */
nkeynes@359
   680
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   681
                                }
nkeynes@359
   682
                                break;
nkeynes@359
   683
                            case 0x1:
nkeynes@359
   684
                                { /* DIV0U */
nkeynes@361
   685
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   686
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   687
                                store_spreg( R_EAX, R_M );
nkeynes@361
   688
                                store_spreg( R_EAX, R_T );
nkeynes@417
   689
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   690
                                }
nkeynes@359
   691
                                break;
nkeynes@359
   692
                            case 0x2:
nkeynes@359
   693
                                { /* MOVT Rn */
nkeynes@359
   694
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   695
                                load_spreg( R_EAX, R_T );
nkeynes@359
   696
                                store_reg( R_EAX, Rn );
nkeynes@359
   697
                                }
nkeynes@359
   698
                                break;
nkeynes@359
   699
                            default:
nkeynes@359
   700
                                UNDEF();
nkeynes@359
   701
                                break;
nkeynes@359
   702
                        }
nkeynes@359
   703
                        break;
nkeynes@359
   704
                    case 0xA:
nkeynes@359
   705
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   706
                            case 0x0:
nkeynes@359
   707
                                { /* STS MACH, Rn */
nkeynes@359
   708
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   709
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   710
                                store_reg( R_EAX, Rn );
nkeynes@359
   711
                                }
nkeynes@359
   712
                                break;
nkeynes@359
   713
                            case 0x1:
nkeynes@359
   714
                                { /* STS MACL, Rn */
nkeynes@359
   715
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   716
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   717
                                store_reg( R_EAX, Rn );
nkeynes@359
   718
                                }
nkeynes@359
   719
                                break;
nkeynes@359
   720
                            case 0x2:
nkeynes@359
   721
                                { /* STS PR, Rn */
nkeynes@359
   722
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   723
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   724
                                store_reg( R_EAX, Rn );
nkeynes@359
   725
                                }
nkeynes@359
   726
                                break;
nkeynes@359
   727
                            case 0x3:
nkeynes@359
   728
                                { /* STC SGR, Rn */
nkeynes@359
   729
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   730
                                check_priv();
nkeynes@359
   731
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   732
                                store_reg( R_EAX, Rn );
nkeynes@417
   733
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   734
                                }
nkeynes@359
   735
                                break;
nkeynes@359
   736
                            case 0x5:
nkeynes@359
   737
                                { /* STS FPUL, Rn */
nkeynes@359
   738
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   739
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   740
                                store_reg( R_EAX, Rn );
nkeynes@359
   741
                                }
nkeynes@359
   742
                                break;
nkeynes@359
   743
                            case 0x6:
nkeynes@359
   744
                                { /* STS FPSCR, Rn */
nkeynes@359
   745
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   746
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   747
                                store_reg( R_EAX, Rn );
nkeynes@359
   748
                                }
nkeynes@359
   749
                                break;
nkeynes@359
   750
                            case 0xF:
nkeynes@359
   751
                                { /* STC DBR, Rn */
nkeynes@359
   752
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   753
                                check_priv();
nkeynes@359
   754
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   755
                                store_reg( R_EAX, Rn );
nkeynes@417
   756
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   757
                                }
nkeynes@359
   758
                                break;
nkeynes@359
   759
                            default:
nkeynes@359
   760
                                UNDEF();
nkeynes@359
   761
                                break;
nkeynes@359
   762
                        }
nkeynes@359
   763
                        break;
nkeynes@359
   764
                    case 0xB:
nkeynes@359
   765
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   766
                            case 0x0:
nkeynes@359
   767
                                { /* RTS */
nkeynes@374
   768
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   769
                            	SLOTILLEGAL();
nkeynes@374
   770
                                } else {
nkeynes@408
   771
                            	load_spreg( R_ECX, R_PR );
nkeynes@590
   772
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
   773
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
   774
                            	sh4_translate_instruction(pc+2);
nkeynes@590
   775
                            	exit_block_newpcset(pc+2);
nkeynes@409
   776
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   777
                            	return 4;
nkeynes@374
   778
                                }
nkeynes@359
   779
                                }
nkeynes@359
   780
                                break;
nkeynes@359
   781
                            case 0x1:
nkeynes@359
   782
                                { /* SLEEP */
nkeynes@388
   783
                                check_priv();
nkeynes@388
   784
                                call_func0( sh4_sleep );
nkeynes@417
   785
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
   786
                                sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
   787
                                return 2;
nkeynes@359
   788
                                }
nkeynes@359
   789
                                break;
nkeynes@359
   790
                            case 0x2:
nkeynes@359
   791
                                { /* RTE */
nkeynes@374
   792
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   793
                            	SLOTILLEGAL();
nkeynes@374
   794
                                } else {
nkeynes@408
   795
                            	check_priv();
nkeynes@408
   796
                            	load_spreg( R_ECX, R_SPC );
nkeynes@590
   797
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
   798
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   799
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
   800
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
   801
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   802
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   803
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   804
                            	sh4_translate_instruction(pc+2);
nkeynes@590
   805
                            	exit_block_newpcset(pc+2);
nkeynes@409
   806
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   807
                            	return 4;
nkeynes@374
   808
                                }
nkeynes@359
   809
                                }
nkeynes@359
   810
                                break;
nkeynes@359
   811
                            default:
nkeynes@359
   812
                                UNDEF();
nkeynes@359
   813
                                break;
nkeynes@359
   814
                        }
nkeynes@359
   815
                        break;
nkeynes@359
   816
                    case 0xC:
nkeynes@359
   817
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   818
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   819
                        load_reg( R_EAX, 0 );
nkeynes@359
   820
                        load_reg( R_ECX, Rm );
nkeynes@586
   821
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   822
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
   823
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   824
                        store_reg( R_EAX, Rn );
nkeynes@417
   825
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   826
                        }
nkeynes@359
   827
                        break;
nkeynes@359
   828
                    case 0xD:
nkeynes@359
   829
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   830
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   831
                        load_reg( R_EAX, 0 );
nkeynes@361
   832
                        load_reg( R_ECX, Rm );
nkeynes@586
   833
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   834
                        check_ralign16( R_EAX );
nkeynes@586
   835
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   836
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   837
                        store_reg( R_EAX, Rn );
nkeynes@417
   838
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   839
                        }
nkeynes@359
   840
                        break;
nkeynes@359
   841
                    case 0xE:
nkeynes@359
   842
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   843
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   844
                        load_reg( R_EAX, 0 );
nkeynes@361
   845
                        load_reg( R_ECX, Rm );
nkeynes@586
   846
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   847
                        check_ralign32( R_EAX );
nkeynes@586
   848
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   849
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   850
                        store_reg( R_EAX, Rn );
nkeynes@417
   851
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   852
                        }
nkeynes@359
   853
                        break;
nkeynes@359
   854
                    case 0xF:
nkeynes@359
   855
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   856
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   857
                        if( Rm == Rn ) {
nkeynes@586
   858
                    	load_reg( R_EAX, Rm );
nkeynes@586
   859
                    	check_ralign32( R_EAX );
nkeynes@586
   860
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   861
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   862
                    	load_reg( R_EAX, Rn );
nkeynes@586
   863
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@586
   864
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   865
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   866
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   867
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
   868
                        } else {
nkeynes@586
   869
                    	load_reg( R_EAX, Rm );
nkeynes@586
   870
                    	check_ralign32( R_EAX );
nkeynes@586
   871
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   872
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   873
                    	load_reg( R_EAX, Rn );
nkeynes@586
   874
                    	check_ralign32( R_EAX );
nkeynes@586
   875
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   876
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   877
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   878
                        }
nkeynes@586
   879
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   880
                        POP_r32( R_ECX );
nkeynes@586
   881
                        PUSH_r32( R_EAX );
nkeynes@386
   882
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   883
                        POP_realigned_r32( R_ECX );
nkeynes@586
   884
                    
nkeynes@386
   885
                        IMUL_r32( R_ECX );
nkeynes@386
   886
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   887
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   888
                    
nkeynes@386
   889
                        load_spreg( R_ECX, R_S );
nkeynes@386
   890
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   891
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   892
                        call_func0( signsat48 );
nkeynes@386
   893
                        JMP_TARGET( nosat );
nkeynes@417
   894
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   895
                        }
nkeynes@359
   896
                        break;
nkeynes@359
   897
                    default:
nkeynes@359
   898
                        UNDEF();
nkeynes@359
   899
                        break;
nkeynes@359
   900
                }
nkeynes@359
   901
                break;
nkeynes@359
   902
            case 0x1:
nkeynes@359
   903
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   904
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
   905
                load_reg( R_EAX, Rn );
nkeynes@586
   906
                ADD_imm32_r32( disp, R_EAX );
nkeynes@586
   907
                check_walign32( R_EAX );
nkeynes@586
   908
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   909
                load_reg( R_EDX, Rm );
nkeynes@586
   910
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   911
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   912
                }
nkeynes@359
   913
                break;
nkeynes@359
   914
            case 0x2:
nkeynes@359
   915
                switch( ir&0xF ) {
nkeynes@359
   916
                    case 0x0:
nkeynes@359
   917
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   918
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   919
                        load_reg( R_EAX, Rn );
nkeynes@586
   920
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   921
                        load_reg( R_EDX, Rm );
nkeynes@586
   922
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   923
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   924
                        }
nkeynes@359
   925
                        break;
nkeynes@359
   926
                    case 0x1:
nkeynes@359
   927
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   928
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   929
                        load_reg( R_EAX, Rn );
nkeynes@586
   930
                        check_walign16( R_EAX );
nkeynes@586
   931
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
   932
                        load_reg( R_EDX, Rm );
nkeynes@586
   933
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   934
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   935
                        }
nkeynes@359
   936
                        break;
nkeynes@359
   937
                    case 0x2:
nkeynes@359
   938
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   939
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   940
                        load_reg( R_EAX, Rn );
nkeynes@586
   941
                        check_walign32(R_EAX);
nkeynes@586
   942
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   943
                        load_reg( R_EDX, Rm );
nkeynes@586
   944
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   945
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   946
                        }
nkeynes@359
   947
                        break;
nkeynes@359
   948
                    case 0x4:
nkeynes@359
   949
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   950
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   951
                        load_reg( R_EAX, Rn );
nkeynes@586
   952
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
   953
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   954
                        load_reg( R_EDX, Rm );
nkeynes@586
   955
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
   956
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   957
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   958
                        }
nkeynes@359
   959
                        break;
nkeynes@359
   960
                    case 0x5:
nkeynes@359
   961
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   962
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   963
                        load_reg( R_EAX, Rn );
nkeynes@586
   964
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
   965
                        check_walign16( R_EAX );
nkeynes@586
   966
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   967
                        load_reg( R_EDX, Rm );
nkeynes@586
   968
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
   969
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   970
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
                        }
nkeynes@359
   972
                        break;
nkeynes@359
   973
                    case 0x6:
nkeynes@359
   974
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   975
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   976
                        load_reg( R_EAX, Rn );
nkeynes@586
   977
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
   978
                        check_walign32( R_EAX );
nkeynes@586
   979
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   980
                        load_reg( R_EDX, Rm );
nkeynes@586
   981
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
   982
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   983
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   984
                        }
nkeynes@359
   985
                        break;
nkeynes@359
   986
                    case 0x7:
nkeynes@359
   987
                        { /* DIV0S Rm, Rn */
nkeynes@359
   988
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   989
                        load_reg( R_EAX, Rm );
nkeynes@386
   990
                        load_reg( R_ECX, Rn );
nkeynes@361
   991
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   992
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   993
                        store_spreg( R_EAX, R_M );
nkeynes@361
   994
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   995
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   996
                        SETNE_t();
nkeynes@417
   997
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   998
                        }
nkeynes@359
   999
                        break;
nkeynes@359
  1000
                    case 0x8:
nkeynes@359
  1001
                        { /* TST Rm, Rn */
nkeynes@359
  1002
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1003
                        load_reg( R_EAX, Rm );
nkeynes@361
  1004
                        load_reg( R_ECX, Rn );
nkeynes@361
  1005
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1006
                        SETE_t();
nkeynes@417
  1007
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1008
                        }
nkeynes@359
  1009
                        break;
nkeynes@359
  1010
                    case 0x9:
nkeynes@359
  1011
                        { /* AND Rm, Rn */
nkeynes@359
  1012
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1013
                        load_reg( R_EAX, Rm );
nkeynes@359
  1014
                        load_reg( R_ECX, Rn );
nkeynes@359
  1015
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1016
                        store_reg( R_ECX, Rn );
nkeynes@417
  1017
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1018
                        }
nkeynes@359
  1019
                        break;
nkeynes@359
  1020
                    case 0xA:
nkeynes@359
  1021
                        { /* XOR Rm, Rn */
nkeynes@359
  1022
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1023
                        load_reg( R_EAX, Rm );
nkeynes@359
  1024
                        load_reg( R_ECX, Rn );
nkeynes@359
  1025
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1026
                        store_reg( R_ECX, Rn );
nkeynes@417
  1027
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1028
                        }
nkeynes@359
  1029
                        break;
nkeynes@359
  1030
                    case 0xB:
nkeynes@359
  1031
                        { /* OR Rm, Rn */
nkeynes@359
  1032
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1033
                        load_reg( R_EAX, Rm );
nkeynes@359
  1034
                        load_reg( R_ECX, Rn );
nkeynes@359
  1035
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1036
                        store_reg( R_ECX, Rn );
nkeynes@417
  1037
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1038
                        }
nkeynes@359
  1039
                        break;
nkeynes@359
  1040
                    case 0xC:
nkeynes@359
  1041
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1042
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1043
                        load_reg( R_EAX, Rm );
nkeynes@368
  1044
                        load_reg( R_ECX, Rn );
nkeynes@368
  1045
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1046
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1047
                        JE_rel8(13, target1);
nkeynes@368
  1048
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1049
                        JE_rel8(9, target2);
nkeynes@368
  1050
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1051
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1052
                        JE_rel8(2, target3);
nkeynes@368
  1053
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1054
                        JMP_TARGET(target1);
nkeynes@380
  1055
                        JMP_TARGET(target2);
nkeynes@380
  1056
                        JMP_TARGET(target3);
nkeynes@368
  1057
                        SETE_t();
nkeynes@417
  1058
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1059
                        }
nkeynes@359
  1060
                        break;
nkeynes@359
  1061
                    case 0xD:
nkeynes@359
  1062
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1063
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1064
                        load_reg( R_EAX, Rm );
nkeynes@394
  1065
                        load_reg( R_ECX, Rn );
nkeynes@394
  1066
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1067
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1068
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1069
                        store_reg( R_ECX, Rn );
nkeynes@417
  1070
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
                        }
nkeynes@359
  1072
                        break;
nkeynes@359
  1073
                    case 0xE:
nkeynes@359
  1074
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1075
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1076
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1077
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1078
                        MUL_r32( R_ECX );
nkeynes@374
  1079
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1080
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1081
                        }
nkeynes@359
  1082
                        break;
nkeynes@359
  1083
                    case 0xF:
nkeynes@359
  1084
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1085
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1086
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1087
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1088
                        MUL_r32( R_ECX );
nkeynes@374
  1089
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1090
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1091
                        }
nkeynes@359
  1092
                        break;
nkeynes@359
  1093
                    default:
nkeynes@359
  1094
                        UNDEF();
nkeynes@359
  1095
                        break;
nkeynes@359
  1096
                }
nkeynes@359
  1097
                break;
nkeynes@359
  1098
            case 0x3:
nkeynes@359
  1099
                switch( ir&0xF ) {
nkeynes@359
  1100
                    case 0x0:
nkeynes@359
  1101
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1102
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1103
                        load_reg( R_EAX, Rm );
nkeynes@359
  1104
                        load_reg( R_ECX, Rn );
nkeynes@359
  1105
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1106
                        SETE_t();
nkeynes@417
  1107
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1108
                        }
nkeynes@359
  1109
                        break;
nkeynes@359
  1110
                    case 0x2:
nkeynes@359
  1111
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1112
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1113
                        load_reg( R_EAX, Rm );
nkeynes@359
  1114
                        load_reg( R_ECX, Rn );
nkeynes@359
  1115
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1116
                        SETAE_t();
nkeynes@417
  1117
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1118
                        }
nkeynes@359
  1119
                        break;
nkeynes@359
  1120
                    case 0x3:
nkeynes@359
  1121
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1122
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1123
                        load_reg( R_EAX, Rm );
nkeynes@359
  1124
                        load_reg( R_ECX, Rn );
nkeynes@359
  1125
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1126
                        SETGE_t();
nkeynes@417
  1127
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1128
                        }
nkeynes@359
  1129
                        break;
nkeynes@359
  1130
                    case 0x4:
nkeynes@359
  1131
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1132
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1133
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1134
                        load_reg( R_EAX, Rn );
nkeynes@417
  1135
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1136
                    	LDC_t();
nkeynes@417
  1137
                        }
nkeynes@386
  1138
                        RCL1_r32( R_EAX );
nkeynes@386
  1139
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1140
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1141
                        JE_rel8(5, mqequal);
nkeynes@386
  1142
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1143
                        JMP_rel8(3, end);
nkeynes@380
  1144
                        JMP_TARGET(mqequal);
nkeynes@386
  1145
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1146
                        JMP_TARGET(end);
nkeynes@386
  1147
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1148
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1149
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1150
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1151
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1152
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1153
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1154
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1155
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1156
                        }
nkeynes@359
  1157
                        break;
nkeynes@359
  1158
                    case 0x5:
nkeynes@359
  1159
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1160
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1161
                        load_reg( R_EAX, Rm );
nkeynes@361
  1162
                        load_reg( R_ECX, Rn );
nkeynes@361
  1163
                        MUL_r32(R_ECX);
nkeynes@361
  1164
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1165
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1166
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1167
                        }
nkeynes@359
  1168
                        break;
nkeynes@359
  1169
                    case 0x6:
nkeynes@359
  1170
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1171
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1172
                        load_reg( R_EAX, Rm );
nkeynes@359
  1173
                        load_reg( R_ECX, Rn );
nkeynes@359
  1174
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1175
                        SETA_t();
nkeynes@417
  1176
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1177
                        }
nkeynes@359
  1178
                        break;
nkeynes@359
  1179
                    case 0x7:
nkeynes@359
  1180
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1181
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1182
                        load_reg( R_EAX, Rm );
nkeynes@359
  1183
                        load_reg( R_ECX, Rn );
nkeynes@359
  1184
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1185
                        SETG_t();
nkeynes@417
  1186
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1187
                        }
nkeynes@359
  1188
                        break;
nkeynes@359
  1189
                    case 0x8:
nkeynes@359
  1190
                        { /* SUB Rm, Rn */
nkeynes@359
  1191
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1192
                        load_reg( R_EAX, Rm );
nkeynes@359
  1193
                        load_reg( R_ECX, Rn );
nkeynes@359
  1194
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1195
                        store_reg( R_ECX, Rn );
nkeynes@417
  1196
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1197
                        }
nkeynes@359
  1198
                        break;
nkeynes@359
  1199
                    case 0xA:
nkeynes@359
  1200
                        { /* SUBC Rm, Rn */
nkeynes@359
  1201
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1202
                        load_reg( R_EAX, Rm );
nkeynes@359
  1203
                        load_reg( R_ECX, Rn );
nkeynes@417
  1204
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1205
                    	LDC_t();
nkeynes@417
  1206
                        }
nkeynes@359
  1207
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1208
                        store_reg( R_ECX, Rn );
nkeynes@394
  1209
                        SETC_t();
nkeynes@417
  1210
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1211
                        }
nkeynes@359
  1212
                        break;
nkeynes@359
  1213
                    case 0xB:
nkeynes@359
  1214
                        { /* SUBV Rm, Rn */
nkeynes@359
  1215
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1216
                        load_reg( R_EAX, Rm );
nkeynes@359
  1217
                        load_reg( R_ECX, Rn );
nkeynes@359
  1218
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1219
                        store_reg( R_ECX, Rn );
nkeynes@359
  1220
                        SETO_t();
nkeynes@417
  1221
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1222
                        }
nkeynes@359
  1223
                        break;
nkeynes@359
  1224
                    case 0xC:
nkeynes@359
  1225
                        { /* ADD Rm, Rn */
nkeynes@359
  1226
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1227
                        load_reg( R_EAX, Rm );
nkeynes@359
  1228
                        load_reg( R_ECX, Rn );
nkeynes@359
  1229
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1230
                        store_reg( R_ECX, Rn );
nkeynes@417
  1231
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1232
                        }
nkeynes@359
  1233
                        break;
nkeynes@359
  1234
                    case 0xD:
nkeynes@359
  1235
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1236
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1237
                        load_reg( R_EAX, Rm );
nkeynes@361
  1238
                        load_reg( R_ECX, Rn );
nkeynes@361
  1239
                        IMUL_r32(R_ECX);
nkeynes@361
  1240
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1241
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1242
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1243
                        }
nkeynes@359
  1244
                        break;
nkeynes@359
  1245
                    case 0xE:
nkeynes@359
  1246
                        { /* ADDC Rm, Rn */
nkeynes@359
  1247
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1248
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1249
                    	LDC_t();
nkeynes@417
  1250
                        }
nkeynes@359
  1251
                        load_reg( R_EAX, Rm );
nkeynes@359
  1252
                        load_reg( R_ECX, Rn );
nkeynes@359
  1253
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1254
                        store_reg( R_ECX, Rn );
nkeynes@359
  1255
                        SETC_t();
nkeynes@417
  1256
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1257
                        }
nkeynes@359
  1258
                        break;
nkeynes@359
  1259
                    case 0xF:
nkeynes@359
  1260
                        { /* ADDV Rm, Rn */
nkeynes@359
  1261
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1262
                        load_reg( R_EAX, Rm );
nkeynes@359
  1263
                        load_reg( R_ECX, Rn );
nkeynes@359
  1264
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1265
                        store_reg( R_ECX, Rn );
nkeynes@359
  1266
                        SETO_t();
nkeynes@417
  1267
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1268
                        }
nkeynes@359
  1269
                        break;
nkeynes@359
  1270
                    default:
nkeynes@359
  1271
                        UNDEF();
nkeynes@359
  1272
                        break;
nkeynes@359
  1273
                }
nkeynes@359
  1274
                break;
nkeynes@359
  1275
            case 0x4:
nkeynes@359
  1276
                switch( ir&0xF ) {
nkeynes@359
  1277
                    case 0x0:
nkeynes@359
  1278
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1279
                            case 0x0:
nkeynes@359
  1280
                                { /* SHLL Rn */
nkeynes@359
  1281
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1282
                                load_reg( R_EAX, Rn );
nkeynes@359
  1283
                                SHL1_r32( R_EAX );
nkeynes@397
  1284
                                SETC_t();
nkeynes@359
  1285
                                store_reg( R_EAX, Rn );
nkeynes@417
  1286
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1287
                                }
nkeynes@359
  1288
                                break;
nkeynes@359
  1289
                            case 0x1:
nkeynes@359
  1290
                                { /* DT Rn */
nkeynes@359
  1291
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1292
                                load_reg( R_EAX, Rn );
nkeynes@386
  1293
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1294
                                store_reg( R_EAX, Rn );
nkeynes@359
  1295
                                SETE_t();
nkeynes@417
  1296
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1297
                                }
nkeynes@359
  1298
                                break;
nkeynes@359
  1299
                            case 0x2:
nkeynes@359
  1300
                                { /* SHAL Rn */
nkeynes@359
  1301
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1302
                                load_reg( R_EAX, Rn );
nkeynes@359
  1303
                                SHL1_r32( R_EAX );
nkeynes@397
  1304
                                SETC_t();
nkeynes@359
  1305
                                store_reg( R_EAX, Rn );
nkeynes@417
  1306
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1307
                                }
nkeynes@359
  1308
                                break;
nkeynes@359
  1309
                            default:
nkeynes@359
  1310
                                UNDEF();
nkeynes@359
  1311
                                break;
nkeynes@359
  1312
                        }
nkeynes@359
  1313
                        break;
nkeynes@359
  1314
                    case 0x1:
nkeynes@359
  1315
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1316
                            case 0x0:
nkeynes@359
  1317
                                { /* SHLR Rn */
nkeynes@359
  1318
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1319
                                load_reg( R_EAX, Rn );
nkeynes@359
  1320
                                SHR1_r32( R_EAX );
nkeynes@397
  1321
                                SETC_t();
nkeynes@359
  1322
                                store_reg( R_EAX, Rn );
nkeynes@417
  1323
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1324
                                }
nkeynes@359
  1325
                                break;
nkeynes@359
  1326
                            case 0x1:
nkeynes@359
  1327
                                { /* CMP/PZ Rn */
nkeynes@359
  1328
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1329
                                load_reg( R_EAX, Rn );
nkeynes@359
  1330
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1331
                                SETGE_t();
nkeynes@417
  1332
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1333
                                }
nkeynes@359
  1334
                                break;
nkeynes@359
  1335
                            case 0x2:
nkeynes@359
  1336
                                { /* SHAR Rn */
nkeynes@359
  1337
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1338
                                load_reg( R_EAX, Rn );
nkeynes@359
  1339
                                SAR1_r32( R_EAX );
nkeynes@397
  1340
                                SETC_t();
nkeynes@359
  1341
                                store_reg( R_EAX, Rn );
nkeynes@417
  1342
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1343
                                }
nkeynes@359
  1344
                                break;
nkeynes@359
  1345
                            default:
nkeynes@359
  1346
                                UNDEF();
nkeynes@359
  1347
                                break;
nkeynes@359
  1348
                        }
nkeynes@359
  1349
                        break;
nkeynes@359
  1350
                    case 0x2:
nkeynes@359
  1351
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1352
                            case 0x0:
nkeynes@359
  1353
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1354
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1355
                                load_reg( R_EAX, Rn );
nkeynes@586
  1356
                                check_walign32( R_EAX );
nkeynes@586
  1357
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1358
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1359
                                load_spreg( R_EDX, R_MACH );
nkeynes@586
  1360
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1361
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1362
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1363
                                }
nkeynes@359
  1364
                                break;
nkeynes@359
  1365
                            case 0x1:
nkeynes@359
  1366
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1367
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1368
                                load_reg( R_EAX, Rn );
nkeynes@586
  1369
                                check_walign32( R_EAX );
nkeynes@586
  1370
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1371
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1372
                                load_spreg( R_EDX, R_MACL );
nkeynes@586
  1373
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1374
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1375
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1376
                                }
nkeynes@359
  1377
                                break;
nkeynes@359
  1378
                            case 0x2:
nkeynes@359
  1379
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1380
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1381
                                load_reg( R_EAX, Rn );
nkeynes@586
  1382
                                check_walign32( R_EAX );
nkeynes@586
  1383
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1384
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1385
                                load_spreg( R_EDX, R_PR );
nkeynes@586
  1386
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1387
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1388
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1389
                                }
nkeynes@359
  1390
                                break;
nkeynes@359
  1391
                            case 0x3:
nkeynes@359
  1392
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1393
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1394
                                check_priv();
nkeynes@586
  1395
                                load_reg( R_EAX, Rn );
nkeynes@586
  1396
                                check_walign32( R_EAX );
nkeynes@586
  1397
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1398
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1399
                                load_spreg( R_EDX, R_SGR );
nkeynes@586
  1400
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1401
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1402
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1403
                                }
nkeynes@359
  1404
                                break;
nkeynes@359
  1405
                            case 0x5:
nkeynes@359
  1406
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1407
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1408
                                load_reg( R_EAX, Rn );
nkeynes@586
  1409
                                check_walign32( R_EAX );
nkeynes@586
  1410
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1411
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1412
                                load_spreg( R_EDX, R_FPUL );
nkeynes@586
  1413
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1414
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1415
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1416
                                }
nkeynes@359
  1417
                                break;
nkeynes@359
  1418
                            case 0x6:
nkeynes@359
  1419
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1420
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1421
                                load_reg( R_EAX, Rn );
nkeynes@586
  1422
                                check_walign32( R_EAX );
nkeynes@586
  1423
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1424
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1425
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  1426
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1427
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1428
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1429
                                }
nkeynes@359
  1430
                                break;
nkeynes@359
  1431
                            case 0xF:
nkeynes@359
  1432
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1433
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1434
                                check_priv();
nkeynes@586
  1435
                                load_reg( R_EAX, Rn );
nkeynes@586
  1436
                                check_walign32( R_EAX );
nkeynes@586
  1437
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1438
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1439
                                load_spreg( R_EDX, R_DBR );
nkeynes@586
  1440
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1441
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1442
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1443
                                }
nkeynes@359
  1444
                                break;
nkeynes@359
  1445
                            default:
nkeynes@359
  1446
                                UNDEF();
nkeynes@359
  1447
                                break;
nkeynes@359
  1448
                        }
nkeynes@359
  1449
                        break;
nkeynes@359
  1450
                    case 0x3:
nkeynes@359
  1451
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1452
                            case 0x0:
nkeynes@359
  1453
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1454
                                    case 0x0:
nkeynes@359
  1455
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1456
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1457
                                        check_priv();
nkeynes@586
  1458
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1459
                                        check_walign32( R_EAX );
nkeynes@586
  1460
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1461
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1462
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1463
                                        call_func0( sh4_read_sr );
nkeynes@586
  1464
                                        POP_realigned_r32( R_ECX );
nkeynes@586
  1465
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1466
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1467
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1468
                                        }
nkeynes@359
  1469
                                        break;
nkeynes@359
  1470
                                    case 0x1:
nkeynes@359
  1471
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1472
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1473
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1474
                                        check_walign32( R_EAX );
nkeynes@586
  1475
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1476
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1477
                                        load_spreg( R_EDX, R_GBR );
nkeynes@586
  1478
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1479
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1480
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1481
                                        }
nkeynes@359
  1482
                                        break;
nkeynes@359
  1483
                                    case 0x2:
nkeynes@359
  1484
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1485
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1486
                                        check_priv();
nkeynes@586
  1487
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1488
                                        check_walign32( R_EAX );
nkeynes@586
  1489
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1490
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1491
                                        load_spreg( R_EDX, R_VBR );
nkeynes@586
  1492
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1493
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1494
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1495
                                        }
nkeynes@359
  1496
                                        break;
nkeynes@359
  1497
                                    case 0x3:
nkeynes@359
  1498
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1499
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1500
                                        check_priv();
nkeynes@586
  1501
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1502
                                        check_walign32( R_EAX );
nkeynes@586
  1503
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1504
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1505
                                        load_spreg( R_EDX, R_SSR );
nkeynes@586
  1506
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1507
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1508
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1509
                                        }
nkeynes@359
  1510
                                        break;
nkeynes@359
  1511
                                    case 0x4:
nkeynes@359
  1512
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1513
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1514
                                        check_priv();
nkeynes@586
  1515
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1516
                                        check_walign32( R_EAX );
nkeynes@586
  1517
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1518
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1519
                                        load_spreg( R_EDX, R_SPC );
nkeynes@586
  1520
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1521
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1522
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1523
                                        }
nkeynes@359
  1524
                                        break;
nkeynes@359
  1525
                                    default:
nkeynes@359
  1526
                                        UNDEF();
nkeynes@359
  1527
                                        break;
nkeynes@359
  1528
                                }
nkeynes@359
  1529
                                break;
nkeynes@359
  1530
                            case 0x1:
nkeynes@359
  1531
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1532
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1533
                                check_priv();
nkeynes@586
  1534
                                load_reg( R_EAX, Rn );
nkeynes@586
  1535
                                check_walign32( R_EAX );
nkeynes@586
  1536
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1537
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1538
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  1539
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1540
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1541
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1542
                                }
nkeynes@359
  1543
                                break;
nkeynes@359
  1544
                        }
nkeynes@359
  1545
                        break;
nkeynes@359
  1546
                    case 0x4:
nkeynes@359
  1547
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1548
                            case 0x0:
nkeynes@359
  1549
                                { /* ROTL Rn */
nkeynes@359
  1550
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1551
                                load_reg( R_EAX, Rn );
nkeynes@359
  1552
                                ROL1_r32( R_EAX );
nkeynes@359
  1553
                                store_reg( R_EAX, Rn );
nkeynes@359
  1554
                                SETC_t();
nkeynes@417
  1555
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1556
                                }
nkeynes@359
  1557
                                break;
nkeynes@359
  1558
                            case 0x2:
nkeynes@359
  1559
                                { /* ROTCL Rn */
nkeynes@359
  1560
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1561
                                load_reg( R_EAX, Rn );
nkeynes@417
  1562
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1563
                            	LDC_t();
nkeynes@417
  1564
                                }
nkeynes@359
  1565
                                RCL1_r32( R_EAX );
nkeynes@359
  1566
                                store_reg( R_EAX, Rn );
nkeynes@359
  1567
                                SETC_t();
nkeynes@417
  1568
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1569
                                }
nkeynes@359
  1570
                                break;
nkeynes@359
  1571
                            default:
nkeynes@359
  1572
                                UNDEF();
nkeynes@359
  1573
                                break;
nkeynes@359
  1574
                        }
nkeynes@359
  1575
                        break;
nkeynes@359
  1576
                    case 0x5:
nkeynes@359
  1577
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1578
                            case 0x0:
nkeynes@359
  1579
                                { /* ROTR Rn */
nkeynes@359
  1580
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1581
                                load_reg( R_EAX, Rn );
nkeynes@359
  1582
                                ROR1_r32( R_EAX );
nkeynes@359
  1583
                                store_reg( R_EAX, Rn );
nkeynes@359
  1584
                                SETC_t();
nkeynes@417
  1585
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1586
                                }
nkeynes@359
  1587
                                break;
nkeynes@359
  1588
                            case 0x1:
nkeynes@359
  1589
                                { /* CMP/PL Rn */
nkeynes@359
  1590
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1591
                                load_reg( R_EAX, Rn );
nkeynes@359
  1592
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1593
                                SETG_t();
nkeynes@417
  1594
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1595
                                }
nkeynes@359
  1596
                                break;
nkeynes@359
  1597
                            case 0x2:
nkeynes@359
  1598
                                { /* ROTCR Rn */
nkeynes@359
  1599
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1600
                                load_reg( R_EAX, Rn );
nkeynes@417
  1601
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1602
                            	LDC_t();
nkeynes@417
  1603
                                }
nkeynes@359
  1604
                                RCR1_r32( R_EAX );
nkeynes@359
  1605
                                store_reg( R_EAX, Rn );
nkeynes@359
  1606
                                SETC_t();
nkeynes@417
  1607
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1608
                                }
nkeynes@359
  1609
                                break;
nkeynes@359
  1610
                            default:
nkeynes@359
  1611
                                UNDEF();
nkeynes@359
  1612
                                break;
nkeynes@359
  1613
                        }
nkeynes@359
  1614
                        break;
nkeynes@359
  1615
                    case 0x6:
nkeynes@359
  1616
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1617
                            case 0x0:
nkeynes@359
  1618
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1619
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1620
                                load_reg( R_EAX, Rm );
nkeynes@395
  1621
                                check_ralign32( R_EAX );
nkeynes@586
  1622
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1623
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1624
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1625
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1626
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1627
                                }
nkeynes@359
  1628
                                break;
nkeynes@359
  1629
                            case 0x1:
nkeynes@359
  1630
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1631
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1632
                                load_reg( R_EAX, Rm );
nkeynes@395
  1633
                                check_ralign32( R_EAX );
nkeynes@586
  1634
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1635
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1636
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1637
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1638
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1639
                                }
nkeynes@359
  1640
                                break;
nkeynes@359
  1641
                            case 0x2:
nkeynes@359
  1642
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1643
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1644
                                load_reg( R_EAX, Rm );
nkeynes@395
  1645
                                check_ralign32( R_EAX );
nkeynes@586
  1646
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1647
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1648
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1649
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1650
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1651
                                }
nkeynes@359
  1652
                                break;
nkeynes@359
  1653
                            case 0x3:
nkeynes@359
  1654
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1655
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1656
                                check_priv();
nkeynes@359
  1657
                                load_reg( R_EAX, Rm );
nkeynes@395
  1658
                                check_ralign32( R_EAX );
nkeynes@586
  1659
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1660
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1661
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1662
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1663
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1664
                                }
nkeynes@359
  1665
                                break;
nkeynes@359
  1666
                            case 0x5:
nkeynes@359
  1667
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1668
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1669
                                load_reg( R_EAX, Rm );
nkeynes@395
  1670
                                check_ralign32( R_EAX );
nkeynes@586
  1671
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1672
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1673
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1674
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1675
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1676
                                }
nkeynes@359
  1677
                                break;
nkeynes@359
  1678
                            case 0x6:
nkeynes@359
  1679
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1680
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1681
                                load_reg( R_EAX, Rm );
nkeynes@395
  1682
                                check_ralign32( R_EAX );
nkeynes@586
  1683
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1684
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1685
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1686
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1687
                                update_fr_bank( R_EAX );
nkeynes@417
  1688
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1689
                                }
nkeynes@359
  1690
                                break;
nkeynes@359
  1691
                            case 0xF:
nkeynes@359
  1692
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1693
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1694
                                check_priv();
nkeynes@359
  1695
                                load_reg( R_EAX, Rm );
nkeynes@395
  1696
                                check_ralign32( R_EAX );
nkeynes@586
  1697
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1698
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1699
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1700
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1701
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1702
                                }
nkeynes@359
  1703
                                break;
nkeynes@359
  1704
                            default:
nkeynes@359
  1705
                                UNDEF();
nkeynes@359
  1706
                                break;
nkeynes@359
  1707
                        }
nkeynes@359
  1708
                        break;
nkeynes@359
  1709
                    case 0x7:
nkeynes@359
  1710
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1711
                            case 0x0:
nkeynes@359
  1712
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1713
                                    case 0x0:
nkeynes@359
  1714
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1715
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1716
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1717
                                    	SLOTILLEGAL();
nkeynes@386
  1718
                                        } else {
nkeynes@586
  1719
                                    	check_priv();
nkeynes@386
  1720
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1721
                                    	check_ralign32( R_EAX );
nkeynes@586
  1722
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1723
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1724
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1725
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1726
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1727
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1728
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1729
                                        }
nkeynes@359
  1730
                                        }
nkeynes@359
  1731
                                        break;
nkeynes@359
  1732
                                    case 0x1:
nkeynes@359
  1733
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1734
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1735
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1736
                                        check_ralign32( R_EAX );
nkeynes@586
  1737
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1738
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1739
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1740
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1741
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1742
                                        }
nkeynes@359
  1743
                                        break;
nkeynes@359
  1744
                                    case 0x2:
nkeynes@359
  1745
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1746
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1747
                                        check_priv();
nkeynes@359
  1748
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1749
                                        check_ralign32( R_EAX );
nkeynes@586
  1750
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1751
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1752
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1753
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1754
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1755
                                        }
nkeynes@359
  1756
                                        break;
nkeynes@359
  1757
                                    case 0x3:
nkeynes@359
  1758
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1759
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1760
                                        check_priv();
nkeynes@359
  1761
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1762
                                        check_ralign32( R_EAX );
nkeynes@586
  1763
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1764
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1765
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1766
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1767
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1768
                                        }
nkeynes@359
  1769
                                        break;
nkeynes@359
  1770
                                    case 0x4:
nkeynes@359
  1771
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1772
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1773
                                        check_priv();
nkeynes@359
  1774
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1775
                                        check_ralign32( R_EAX );
nkeynes@586
  1776
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1777
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1778
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1779
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1780
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1781
                                        }
nkeynes@359
  1782
                                        break;
nkeynes@359
  1783
                                    default:
nkeynes@359
  1784
                                        UNDEF();
nkeynes@359
  1785
                                        break;
nkeynes@359
  1786
                                }
nkeynes@359
  1787
                                break;
nkeynes@359
  1788
                            case 0x1:
nkeynes@359
  1789
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1790
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1791
                                check_priv();
nkeynes@374
  1792
                                load_reg( R_EAX, Rm );
nkeynes@395
  1793
                                check_ralign32( R_EAX );
nkeynes@586
  1794
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1795
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1796
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1797
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1798
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1799
                                }
nkeynes@359
  1800
                                break;
nkeynes@359
  1801
                        }
nkeynes@359
  1802
                        break;
nkeynes@359
  1803
                    case 0x8:
nkeynes@359
  1804
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1805
                            case 0x0:
nkeynes@359
  1806
                                { /* SHLL2 Rn */
nkeynes@359
  1807
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1808
                                load_reg( R_EAX, Rn );
nkeynes@359
  1809
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1810
                                store_reg( R_EAX, Rn );
nkeynes@417
  1811
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1812
                                }
nkeynes@359
  1813
                                break;
nkeynes@359
  1814
                            case 0x1:
nkeynes@359
  1815
                                { /* SHLL8 Rn */
nkeynes@359
  1816
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1817
                                load_reg( R_EAX, Rn );
nkeynes@359
  1818
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1819
                                store_reg( R_EAX, Rn );
nkeynes@417
  1820
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1821
                                }
nkeynes@359
  1822
                                break;
nkeynes@359
  1823
                            case 0x2:
nkeynes@359
  1824
                                { /* SHLL16 Rn */
nkeynes@359
  1825
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1826
                                load_reg( R_EAX, Rn );
nkeynes@359
  1827
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1828
                                store_reg( R_EAX, Rn );
nkeynes@417
  1829
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1830
                                }
nkeynes@359
  1831
                                break;
nkeynes@359
  1832
                            default:
nkeynes@359
  1833
                                UNDEF();
nkeynes@359
  1834
                                break;
nkeynes@359
  1835
                        }
nkeynes@359
  1836
                        break;
nkeynes@359
  1837
                    case 0x9:
nkeynes@359
  1838
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1839
                            case 0x0:
nkeynes@359
  1840
                                { /* SHLR2 Rn */
nkeynes@359
  1841
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1842
                                load_reg( R_EAX, Rn );
nkeynes@359
  1843
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1844
                                store_reg( R_EAX, Rn );
nkeynes@417
  1845
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1846
                                }
nkeynes@359
  1847
                                break;
nkeynes@359
  1848
                            case 0x1:
nkeynes@359
  1849
                                { /* SHLR8 Rn */
nkeynes@359
  1850
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1851
                                load_reg( R_EAX, Rn );
nkeynes@359
  1852
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1853
                                store_reg( R_EAX, Rn );
nkeynes@417
  1854
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1855
                                }
nkeynes@359
  1856
                                break;
nkeynes@359
  1857
                            case 0x2:
nkeynes@359
  1858
                                { /* SHLR16 Rn */
nkeynes@359
  1859
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1860
                                load_reg( R_EAX, Rn );
nkeynes@359
  1861
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1862
                                store_reg( R_EAX, Rn );
nkeynes@417
  1863
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1864
                                }
nkeynes@359
  1865
                                break;
nkeynes@359
  1866
                            default:
nkeynes@359
  1867
                                UNDEF();
nkeynes@359
  1868
                                break;
nkeynes@359
  1869
                        }
nkeynes@359
  1870
                        break;
nkeynes@359
  1871
                    case 0xA:
nkeynes@359
  1872
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1873
                            case 0x0:
nkeynes@359
  1874
                                { /* LDS Rm, MACH */
nkeynes@359
  1875
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1876
                                load_reg( R_EAX, Rm );
nkeynes@359
  1877
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1878
                                }
nkeynes@359
  1879
                                break;
nkeynes@359
  1880
                            case 0x1:
nkeynes@359
  1881
                                { /* LDS Rm, MACL */
nkeynes@359
  1882
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1883
                                load_reg( R_EAX, Rm );
nkeynes@359
  1884
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1885
                                }
nkeynes@359
  1886
                                break;
nkeynes@359
  1887
                            case 0x2:
nkeynes@359
  1888
                                { /* LDS Rm, PR */
nkeynes@359
  1889
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1890
                                load_reg( R_EAX, Rm );
nkeynes@359
  1891
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1892
                                }
nkeynes@359
  1893
                                break;
nkeynes@359
  1894
                            case 0x3:
nkeynes@359
  1895
                                { /* LDC Rm, SGR */
nkeynes@359
  1896
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1897
                                check_priv();
nkeynes@359
  1898
                                load_reg( R_EAX, Rm );
nkeynes@359
  1899
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1900
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1901
                                }
nkeynes@359
  1902
                                break;
nkeynes@359
  1903
                            case 0x5:
nkeynes@359
  1904
                                { /* LDS Rm, FPUL */
nkeynes@359
  1905
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1906
                                load_reg( R_EAX, Rm );
nkeynes@359
  1907
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1908
                                }
nkeynes@359
  1909
                                break;
nkeynes@359
  1910
                            case 0x6:
nkeynes@359
  1911
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1912
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1913
                                load_reg( R_EAX, Rm );
nkeynes@359
  1914
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1915
                                update_fr_bank( R_EAX );
nkeynes@417
  1916
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1917
                                }
nkeynes@359
  1918
                                break;
nkeynes@359
  1919
                            case 0xF:
nkeynes@359
  1920
                                { /* LDC Rm, DBR */
nkeynes@359
  1921
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1922
                                check_priv();
nkeynes@359
  1923
                                load_reg( R_EAX, Rm );
nkeynes@359
  1924
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1925
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1926
                                }
nkeynes@359
  1927
                                break;
nkeynes@359
  1928
                            default:
nkeynes@359
  1929
                                UNDEF();
nkeynes@359
  1930
                                break;
nkeynes@359
  1931
                        }
nkeynes@359
  1932
                        break;
nkeynes@359
  1933
                    case 0xB:
nkeynes@359
  1934
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1935
                            case 0x0:
nkeynes@359
  1936
                                { /* JSR @Rn */
nkeynes@359
  1937
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1938
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1939
                            	SLOTILLEGAL();
nkeynes@374
  1940
                                } else {
nkeynes@590
  1941
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
  1942
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1943
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1944
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1945
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@526
  1946
                            	sh4_translate_instruction(pc+2);
nkeynes@590
  1947
                            	exit_block_newpcset(pc+2);
nkeynes@409
  1948
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1949
                            	return 4;
nkeynes@374
  1950
                                }
nkeynes@359
  1951
                                }
nkeynes@359
  1952
                                break;
nkeynes@359
  1953
                            case 0x1:
nkeynes@359
  1954
                                { /* TAS.B @Rn */
nkeynes@359
  1955
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1956
                                load_reg( R_EAX, Rn );
nkeynes@586
  1957
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1958
                                PUSH_realigned_r32( R_EAX );
nkeynes@586
  1959
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1960
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1961
                                SETE_t();
nkeynes@361
  1962
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1963
                                POP_realigned_r32( R_ECX );
nkeynes@361
  1964
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1965
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1966
                                }
nkeynes@359
  1967
                                break;
nkeynes@359
  1968
                            case 0x2:
nkeynes@359
  1969
                                { /* JMP @Rn */
nkeynes@359
  1970
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1971
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1972
                            	SLOTILLEGAL();
nkeynes@374
  1973
                                } else {
nkeynes@408
  1974
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1975
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1976
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1977
                            	sh4_translate_instruction(pc+2);
nkeynes@590
  1978
                            	exit_block_newpcset(pc+2);
nkeynes@409
  1979
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1980
                            	return 4;
nkeynes@374
  1981
                                }
nkeynes@359
  1982
                                }
nkeynes@359
  1983
                                break;
nkeynes@359
  1984
                            default:
nkeynes@359
  1985
                                UNDEF();
nkeynes@359
  1986
                                break;
nkeynes@359
  1987
                        }
nkeynes@359
  1988
                        break;
nkeynes@359
  1989
                    case 0xC:
nkeynes@359
  1990
                        { /* SHAD Rm, Rn */
nkeynes@359
  1991
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1992
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1993
                        load_reg( R_EAX, Rn );
nkeynes@361
  1994
                        load_reg( R_ECX, Rm );
nkeynes@361
  1995
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1996
                        JGE_rel8(16, doshl);
nkeynes@361
  1997
                                        
nkeynes@361
  1998
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1999
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2000
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  2001
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  2002
                        JMP_rel8(10, end);          // 2
nkeynes@386
  2003
                    
nkeynes@386
  2004
                        JMP_TARGET(emptysar);
nkeynes@386
  2005
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  2006
                        JMP_rel8(5, end2);
nkeynes@386
  2007
                    
nkeynes@380
  2008
                        JMP_TARGET(doshl);
nkeynes@361
  2009
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2010
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2011
                        JMP_TARGET(end);
nkeynes@386
  2012
                        JMP_TARGET(end2);
nkeynes@361
  2013
                        store_reg( R_EAX, Rn );
nkeynes@417
  2014
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2015
                        }
nkeynes@359
  2016
                        break;
nkeynes@359
  2017
                    case 0xD:
nkeynes@359
  2018
                        { /* SHLD Rm, Rn */
nkeynes@359
  2019
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2020
                        load_reg( R_EAX, Rn );
nkeynes@368
  2021
                        load_reg( R_ECX, Rm );
nkeynes@386
  2022
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2023
                        JGE_rel8(15, doshl);
nkeynes@368
  2024
                    
nkeynes@386
  2025
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2026
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2027
                        JE_rel8( 4, emptyshr );
nkeynes@386
  2028
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  2029
                        JMP_rel8(9, end);          // 2
nkeynes@386
  2030
                    
nkeynes@386
  2031
                        JMP_TARGET(emptyshr);
nkeynes@386
  2032
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  2033
                        JMP_rel8(5, end2);
nkeynes@386
  2034
                    
nkeynes@386
  2035
                        JMP_TARGET(doshl);
nkeynes@386
  2036
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2037
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2038
                        JMP_TARGET(end);
nkeynes@386
  2039
                        JMP_TARGET(end2);
nkeynes@368
  2040
                        store_reg( R_EAX, Rn );
nkeynes@417
  2041
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2042
                        }
nkeynes@359
  2043
                        break;
nkeynes@359
  2044
                    case 0xE:
nkeynes@359
  2045
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2046
                            case 0x0:
nkeynes@359
  2047
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2048
                                    case 0x0:
nkeynes@359
  2049
                                        { /* LDC Rm, SR */
nkeynes@359
  2050
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2051
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2052
                                    	SLOTILLEGAL();
nkeynes@386
  2053
                                        } else {
nkeynes@386
  2054
                                    	check_priv();
nkeynes@386
  2055
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2056
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2057
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2058
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2059
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2060
                                        }
nkeynes@359
  2061
                                        }
nkeynes@359
  2062
                                        break;
nkeynes@359
  2063
                                    case 0x1:
nkeynes@359
  2064
                                        { /* LDC Rm, GBR */
nkeynes@359
  2065
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2066
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2067
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2068
                                        }
nkeynes@359
  2069
                                        break;
nkeynes@359
  2070
                                    case 0x2:
nkeynes@359
  2071
                                        { /* LDC Rm, VBR */
nkeynes@359
  2072
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2073
                                        check_priv();
nkeynes@359
  2074
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2075
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2076
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2077
                                        }
nkeynes@359
  2078
                                        break;
nkeynes@359
  2079
                                    case 0x3:
nkeynes@359
  2080
                                        { /* LDC Rm, SSR */
nkeynes@359
  2081
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2082
                                        check_priv();
nkeynes@359
  2083
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2084
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2085
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2086
                                        }
nkeynes@359
  2087
                                        break;
nkeynes@359
  2088
                                    case 0x4:
nkeynes@359
  2089
                                        { /* LDC Rm, SPC */
nkeynes@359
  2090
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2091
                                        check_priv();
nkeynes@359
  2092
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2093
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2094
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2095
                                        }
nkeynes@359
  2096
                                        break;
nkeynes@359
  2097
                                    default:
nkeynes@359
  2098
                                        UNDEF();
nkeynes@359
  2099
                                        break;
nkeynes@359
  2100
                                }
nkeynes@359
  2101
                                break;
nkeynes@359
  2102
                            case 0x1:
nkeynes@359
  2103
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2104
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2105
                                check_priv();
nkeynes@374
  2106
                                load_reg( R_EAX, Rm );
nkeynes@374
  2107
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2108
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2109
                                }
nkeynes@359
  2110
                                break;
nkeynes@359
  2111
                        }
nkeynes@359
  2112
                        break;
nkeynes@359
  2113
                    case 0xF:
nkeynes@359
  2114
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2115
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2116
                        if( Rm == Rn ) {
nkeynes@586
  2117
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2118
                    	check_ralign16( R_EAX );
nkeynes@586
  2119
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2120
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2121
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2122
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@586
  2123
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2124
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2125
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  2126
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
  2127
                        } else {
nkeynes@586
  2128
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2129
                    	check_ralign16( R_EAX );
nkeynes@586
  2130
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2131
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2132
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2133
                    	check_ralign16( R_EAX );
nkeynes@586
  2134
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2135
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
  2136
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2137
                        }
nkeynes@586
  2138
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2139
                        POP_r32( R_ECX );
nkeynes@586
  2140
                        PUSH_r32( R_EAX );
nkeynes@386
  2141
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2142
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2143
                        IMUL_r32( R_ECX );
nkeynes@386
  2144
                    
nkeynes@386
  2145
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2146
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2147
                        JE_rel8( 47, nosat );
nkeynes@386
  2148
                    
nkeynes@386
  2149
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2150
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2151
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2152
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2153
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2154
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2155
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2156
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2157
                    
nkeynes@386
  2158
                        JMP_TARGET(positive);
nkeynes@386
  2159
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2160
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2161
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2162
                    
nkeynes@386
  2163
                        JMP_TARGET(nosat);
nkeynes@386
  2164
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2165
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2166
                        JMP_TARGET(end);
nkeynes@386
  2167
                        JMP_TARGET(end2);
nkeynes@386
  2168
                        JMP_TARGET(end3);
nkeynes@417
  2169
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2170
                        }
nkeynes@359
  2171
                        break;
nkeynes@359
  2172
                }
nkeynes@359
  2173
                break;
nkeynes@359
  2174
            case 0x5:
nkeynes@359
  2175
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2176
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
  2177
                load_reg( R_EAX, Rm );
nkeynes@586
  2178
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  2179
                check_ralign32( R_EAX );
nkeynes@586
  2180
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2181
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2182
                store_reg( R_EAX, Rn );
nkeynes@417
  2183
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2184
                }
nkeynes@359
  2185
                break;
nkeynes@359
  2186
            case 0x6:
nkeynes@359
  2187
                switch( ir&0xF ) {
nkeynes@359
  2188
                    case 0x0:
nkeynes@359
  2189
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2190
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2191
                        load_reg( R_EAX, Rm );
nkeynes@586
  2192
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2193
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2194
                        store_reg( R_EAX, Rn );
nkeynes@417
  2195
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2196
                        }
nkeynes@359
  2197
                        break;
nkeynes@359
  2198
                    case 0x1:
nkeynes@359
  2199
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2200
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2201
                        load_reg( R_EAX, Rm );
nkeynes@586
  2202
                        check_ralign16( R_EAX );
nkeynes@586
  2203
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2204
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2205
                        store_reg( R_EAX, Rn );
nkeynes@417
  2206
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2207
                        }
nkeynes@359
  2208
                        break;
nkeynes@359
  2209
                    case 0x2:
nkeynes@359
  2210
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2211
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2212
                        load_reg( R_EAX, Rm );
nkeynes@586
  2213
                        check_ralign32( R_EAX );
nkeynes@586
  2214
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2215
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2216
                        store_reg( R_EAX, Rn );
nkeynes@417
  2217
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2218
                        }
nkeynes@359
  2219
                        break;
nkeynes@359
  2220
                    case 0x3:
nkeynes@359
  2221
                        { /* MOV Rm, Rn */
nkeynes@359
  2222
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2223
                        load_reg( R_EAX, Rm );
nkeynes@359
  2224
                        store_reg( R_EAX, Rn );
nkeynes@359
  2225
                        }
nkeynes@359
  2226
                        break;
nkeynes@359
  2227
                    case 0x4:
nkeynes@359
  2228
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2229
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2230
                        load_reg( R_EAX, Rm );
nkeynes@586
  2231
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2232
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  2233
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2234
                        store_reg( R_EAX, Rn );
nkeynes@417
  2235
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2236
                        }
nkeynes@359
  2237
                        break;
nkeynes@359
  2238
                    case 0x5:
nkeynes@359
  2239
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2240
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2241
                        load_reg( R_EAX, Rm );
nkeynes@374
  2242
                        check_ralign16( R_EAX );
nkeynes@586
  2243
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2244
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2245
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2246
                        store_reg( R_EAX, Rn );
nkeynes@417
  2247
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2248
                        }
nkeynes@359
  2249
                        break;
nkeynes@359
  2250
                    case 0x6:
nkeynes@359
  2251
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2252
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2253
                        load_reg( R_EAX, Rm );
nkeynes@386
  2254
                        check_ralign32( R_EAX );
nkeynes@586
  2255
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2256
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2257
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2258
                        store_reg( R_EAX, Rn );
nkeynes@417
  2259
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2260
                        }
nkeynes@359
  2261
                        break;
nkeynes@359
  2262
                    case 0x7:
nkeynes@359
  2263
                        { /* NOT Rm, Rn */
nkeynes@359
  2264
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2265
                        load_reg( R_EAX, Rm );
nkeynes@359
  2266
                        NOT_r32( R_EAX );
nkeynes@359
  2267
                        store_reg( R_EAX, Rn );
nkeynes@417
  2268
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2269
                        }
nkeynes@359
  2270
                        break;
nkeynes@359
  2271
                    case 0x8:
nkeynes@359
  2272
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2273
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2274
                        load_reg( R_EAX, Rm );
nkeynes@359
  2275
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2276
                        store_reg( R_EAX, Rn );
nkeynes@359
  2277
                        }
nkeynes@359
  2278
                        break;
nkeynes@359
  2279
                    case 0x9:
nkeynes@359
  2280
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2281
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2282
                        load_reg( R_EAX, Rm );
nkeynes@359
  2283
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2284
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2285
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2286
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2287
                        store_reg( R_ECX, Rn );
nkeynes@417
  2288
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2289
                        }
nkeynes@359
  2290
                        break;
nkeynes@359
  2291
                    case 0xA:
nkeynes@359
  2292
                        { /* NEGC Rm, Rn */
nkeynes@359
  2293
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2294
                        load_reg( R_EAX, Rm );
nkeynes@359
  2295
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2296
                        LDC_t();
nkeynes@359
  2297
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2298
                        store_reg( R_ECX, Rn );
nkeynes@359
  2299
                        SETC_t();
nkeynes@417
  2300
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2301
                        }
nkeynes@359
  2302
                        break;
nkeynes@359
  2303
                    case 0xB:
nkeynes@359
  2304
                        { /* NEG Rm, Rn */
nkeynes@359
  2305
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2306
                        load_reg( R_EAX, Rm );
nkeynes@359
  2307
                        NEG_r32( R_EAX );
nkeynes@359
  2308
                        store_reg( R_EAX, Rn );
nkeynes@417
  2309
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2310
                        }
nkeynes@359
  2311
                        break;
nkeynes@359
  2312
                    case 0xC:
nkeynes@359
  2313
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2314
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2315
                        load_reg( R_EAX, Rm );
nkeynes@361
  2316
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2317
                        store_reg( R_EAX, Rn );
nkeynes@359
  2318
                        }
nkeynes@359
  2319
                        break;
nkeynes@359
  2320
                    case 0xD:
nkeynes@359
  2321
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2322
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2323
                        load_reg( R_EAX, Rm );
nkeynes@361
  2324
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2325
                        store_reg( R_EAX, Rn );
nkeynes@359
  2326
                        }
nkeynes@359
  2327
                        break;
nkeynes@359
  2328
                    case 0xE:
nkeynes@359
  2329
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2330
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2331
                        load_reg( R_EAX, Rm );
nkeynes@359
  2332
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2333
                        store_reg( R_EAX, Rn );
nkeynes@359
  2334
                        }
nkeynes@359
  2335
                        break;
nkeynes@359
  2336
                    case 0xF:
nkeynes@359
  2337
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2338
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2339
                        load_reg( R_EAX, Rm );
nkeynes@361
  2340
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2341
                        store_reg( R_EAX, Rn );
nkeynes@359
  2342
                        }
nkeynes@359
  2343
                        break;
nkeynes@359
  2344
                }
nkeynes@359
  2345
                break;
nkeynes@359
  2346
            case 0x7:
nkeynes@359
  2347
                { /* ADD #imm, Rn */
nkeynes@359
  2348
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2349
                load_reg( R_EAX, Rn );
nkeynes@359
  2350
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2351
                store_reg( R_EAX, Rn );
nkeynes@417
  2352
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2353
                }
nkeynes@359
  2354
                break;
nkeynes@359
  2355
            case 0x8:
nkeynes@359
  2356
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2357
                    case 0x0:
nkeynes@359
  2358
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2359
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2360
                        load_reg( R_EAX, Rn );
nkeynes@586
  2361
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2362
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2363
                        load_reg( R_EDX, 0 );
nkeynes@586
  2364
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2365
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2366
                        }
nkeynes@359
  2367
                        break;
nkeynes@359
  2368
                    case 0x1:
nkeynes@359
  2369
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2370
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2371
                        load_reg( R_EAX, Rn );
nkeynes@586
  2372
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2373
                        check_walign16( R_EAX );
nkeynes@586
  2374
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2375
                        load_reg( R_EDX, 0 );
nkeynes@586
  2376
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2377
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2378
                        }
nkeynes@359
  2379
                        break;
nkeynes@359
  2380
                    case 0x4:
nkeynes@359
  2381
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2382
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2383
                        load_reg( R_EAX, Rm );
nkeynes@586
  2384
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2385
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2386
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2387
                        store_reg( R_EAX, 0 );
nkeynes@417
  2388
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2389
                        }
nkeynes@359
  2390
                        break;
nkeynes@359
  2391
                    case 0x5:
nkeynes@359
  2392
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2393
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2394
                        load_reg( R_EAX, Rm );
nkeynes@586
  2395
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2396
                        check_ralign16( R_EAX );
nkeynes@586
  2397
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2398
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2399
                        store_reg( R_EAX, 0 );
nkeynes@417
  2400
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2401
                        }
nkeynes@359
  2402
                        break;
nkeynes@359
  2403
                    case 0x8:
nkeynes@359
  2404
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2405
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2406
                        load_reg( R_EAX, 0 );
nkeynes@359
  2407
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2408
                        SETE_t();
nkeynes@417
  2409
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2410
                        }
nkeynes@359
  2411
                        break;
nkeynes@359
  2412
                    case 0x9:
nkeynes@359
  2413
                        { /* BT disp */
nkeynes@359
  2414
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2415
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2416
                    	SLOTILLEGAL();
nkeynes@374
  2417
                        } else {
nkeynes@586
  2418
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2419
                    	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2420
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2421
                    	JMP_TARGET(nottaken);
nkeynes@408
  2422
                    	return 2;
nkeynes@374
  2423
                        }
nkeynes@359
  2424
                        }
nkeynes@359
  2425
                        break;
nkeynes@359
  2426
                    case 0xB:
nkeynes@359
  2427
                        { /* BF disp */
nkeynes@359
  2428
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2429
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2430
                    	SLOTILLEGAL();
nkeynes@374
  2431
                        } else {
nkeynes@586
  2432
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2433
                    	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2434
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2435
                    	JMP_TARGET(nottaken);
nkeynes@408
  2436
                    	return 2;
nkeynes@374
  2437
                        }
nkeynes@359
  2438
                        }
nkeynes@359
  2439
                        break;
nkeynes@359
  2440
                    case 0xD:
nkeynes@359
  2441
                        { /* BT/S disp */
nkeynes@359
  2442
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2443
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2444
                    	SLOTILLEGAL();
nkeynes@374
  2445
                        } else {
nkeynes@590
  2446
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2447
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2448
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2449
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2450
                    	}
nkeynes@417
  2451
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2452
                    	sh4_translate_instruction(pc+2);
nkeynes@586
  2453
                    	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  2454
                    	// not taken
nkeynes@408
  2455
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2456
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2457
                    	return 4;
nkeynes@374
  2458
                        }
nkeynes@359
  2459
                        }
nkeynes@359
  2460
                        break;
nkeynes@359
  2461
                    case 0xF:
nkeynes@359
  2462
                        { /* BF/S disp */
nkeynes@359
  2463
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2464
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2465
                    	SLOTILLEGAL();
nkeynes@374
  2466
                        } else {
nkeynes@586
  2467
                    	sh4vma_t target = disp + pc + 4;
nkeynes@590
  2468
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2469
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2470
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2471
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2472
                    	}
nkeynes@417
  2473
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2474
                    	sh4_translate_instruction(pc+2);
nkeynes@586
  2475
                    	exit_block_rel( target, pc+4 );
nkeynes@408
  2476
                    	// not taken
nkeynes@408
  2477
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2478
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2479
                    	return 4;
nkeynes@374
  2480
                        }
nkeynes@359
  2481
                        }
nkeynes@359
  2482
                        break;
nkeynes@359
  2483
                    default:
nkeynes@359
  2484
                        UNDEF();
nkeynes@359
  2485
                        break;
nkeynes@359
  2486
                }
nkeynes@359
  2487
                break;
nkeynes@359
  2488
            case 0x9:
nkeynes@359
  2489
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2490
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2491
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2492
            	SLOTILLEGAL();
nkeynes@374
  2493
                } else {
nkeynes@586
  2494
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  2495
            	uint32_t target = pc + disp + 4;
nkeynes@586
  2496
            	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  2497
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  2498
            	    MOV_moff32_EAX( ptr );
nkeynes@586
  2499
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  2500
            	} else {
nkeynes@586
  2501
            	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  2502
            	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  2503
            	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2504
            	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2505
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  2506
            	}
nkeynes@374
  2507
            	store_reg( R_EAX, Rn );
nkeynes@374
  2508
                }
nkeynes@359
  2509
                }
nkeynes@359
  2510
                break;
nkeynes@359
  2511
            case 0xA:
nkeynes@359
  2512
                { /* BRA disp */
nkeynes@359
  2513
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2514
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2515
            	SLOTILLEGAL();
nkeynes@374
  2516
                } else {
nkeynes@590
  2517
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  2518
            	sh4_translate_instruction( pc + 2 );
nkeynes@586
  2519
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2520
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2521
            	return 4;
nkeynes@374
  2522
                }
nkeynes@359
  2523
                }
nkeynes@359
  2524
                break;
nkeynes@359
  2525
            case 0xB:
nkeynes@359
  2526
                { /* BSR disp */
nkeynes@359
  2527
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2528
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2529
            	SLOTILLEGAL();
nkeynes@374
  2530
                } else {
nkeynes@590
  2531
            	load_spreg( R_EAX, R_PC );
nkeynes@590
  2532
            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  2533
            	store_spreg( R_EAX, R_PR );
nkeynes@590
  2534
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  2535
            	sh4_translate_instruction( pc + 2 );
nkeynes@586
  2536
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2537
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2538
            	return 4;
nkeynes@374
  2539
                }
nkeynes@359
  2540
                }
nkeynes@359
  2541
                break;
nkeynes@359
  2542
            case 0xC:
nkeynes@359
  2543
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2544
                    case 0x0:
nkeynes@359
  2545
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2546
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2547
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2548
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2549
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2550
                        load_reg( R_EDX, 0 );
nkeynes@586
  2551
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2552
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2553
                        }
nkeynes@359
  2554
                        break;
nkeynes@359
  2555
                    case 0x1:
nkeynes@359
  2556
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2557
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2558
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2559
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2560
                        check_walign16( R_EAX );
nkeynes@586
  2561
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2562
                        load_reg( R_EDX, 0 );
nkeynes@586
  2563
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2564
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2565
                        }
nkeynes@359
  2566
                        break;
nkeynes@359
  2567
                    case 0x2:
nkeynes@359
  2568
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2569
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2570
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2571
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2572
                        check_walign32( R_EAX );
nkeynes@586
  2573
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2574
                        load_reg( R_EDX, 0 );
nkeynes@586
  2575
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2576
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2577
                        }
nkeynes@359
  2578
                        break;
nkeynes@359
  2579
                    case 0x3:
nkeynes@359
  2580
                        { /* TRAPA #imm */
nkeynes@359
  2581
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2582
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2583
                    	SLOTILLEGAL();
nkeynes@374
  2584
                        } else {
nkeynes@590
  2585
                    	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  2586
                    	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  2587
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2588
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2589
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2590
                    	exit_block_pcset(pc);
nkeynes@409
  2591
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2592
                    	return 2;
nkeynes@374
  2593
                        }
nkeynes@359
  2594
                        }
nkeynes@359
  2595
                        break;
nkeynes@359
  2596
                    case 0x4:
nkeynes@359
  2597
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2598
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2599
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2600
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2601
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2602
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2603
                        store_reg( R_EAX, 0 );
nkeynes@417
  2604
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2605
                        }
nkeynes@359
  2606
                        break;
nkeynes@359
  2607
                    case 0x5:
nkeynes@359
  2608
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2609
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2610
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2611
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2612
                        check_ralign16( R_EAX );
nkeynes@586
  2613
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2614
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2615
                        store_reg( R_EAX, 0 );
nkeynes@417
  2616
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2617
                        }
nkeynes@359
  2618
                        break;
nkeynes@359
  2619
                    case 0x6:
nkeynes@359
  2620
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2621
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2622
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2623
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2624
                        check_ralign32( R_EAX );
nkeynes@586
  2625
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2626
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2627
                        store_reg( R_EAX, 0 );
nkeynes@417
  2628
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2629
                        }
nkeynes@359
  2630
                        break;
nkeynes@359
  2631
                    case 0x7:
nkeynes@359
  2632
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2633
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2634
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2635
                    	SLOTILLEGAL();
nkeynes@374
  2636
                        } else {
nkeynes@586
  2637
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  2638
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2639
                    	store_reg( R_ECX, 0 );
nkeynes@586
  2640
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2641
                        }
nkeynes@359
  2642
                        }
nkeynes@359
  2643
                        break;
nkeynes@359
  2644
                    case 0x8:
nkeynes@359
  2645
                        { /* TST #imm, R0 */
nkeynes@359
  2646
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2647
                        load_reg( R_EAX, 0 );
nkeynes@368
  2648
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2649
                        SETE_t();
nkeynes@417
  2650
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2651
                        }
nkeynes@359
  2652
                        break;
nkeynes@359
  2653
                    case 0x9:
nkeynes@359
  2654
                        { /* AND #imm, R0 */
nkeynes@359
  2655
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2656
                        load_reg( R_EAX, 0 );
nkeynes@359
  2657
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2658
                        store_reg( R_EAX, 0 );
nkeynes@417
  2659
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2660
                        }
nkeynes@359
  2661
                        break;
nkeynes@359
  2662
                    case 0xA:
nkeynes@359
  2663
                        { /* XOR #imm, R0 */
nkeynes@359
  2664
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2665
                        load_reg( R_EAX, 0 );
nkeynes@359
  2666
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2667
                        store_reg( R_EAX, 0 );
nkeynes@417
  2668
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2669
                        }
nkeynes@359
  2670
                        break;
nkeynes@359
  2671
                    case 0xB:
nkeynes@359
  2672
                        { /* OR #imm, R0 */
nkeynes@359
  2673
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2674
                        load_reg( R_EAX, 0 );
nkeynes@359
  2675
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2676
                        store_reg( R_EAX, 0 );
nkeynes@417
  2677
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2678
                        }
nkeynes@359
  2679
                        break;
nkeynes@359
  2680
                    case 0xC:
nkeynes@359
  2681
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2682
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2683
                        load_reg( R_EAX, 0);
nkeynes@368
  2684
                        load_reg( R_ECX, R_GBR);
nkeynes@586
  2685
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2686
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2687
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  2688
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2689
                        SETE_t();
nkeynes@417
  2690
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2691
                        }
nkeynes@359
  2692
                        break;
nkeynes@359
  2693
                    case 0xD:
nkeynes@359
  2694
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2695
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2696
                        load_reg( R_EAX, 0 );
nkeynes@359
  2697
                        load_spreg( R_ECX, R_GBR );
nkeynes@586
  2698
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2699
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2700
                        PUSH_realigned_r32(R_EAX);
nkeynes@586
  2701
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
  2702
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2703
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2704
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2705
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2706
                        }
nkeynes@359
  2707
                        break;
nkeynes@359
  2708
                    case 0xE:
nkeynes@359
  2709
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2710
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2711
                        load_reg( R_EAX, 0 );
nkeynes@359
  2712
                        load_spreg( R_ECX, R_GBR );
nkeynes@586
  2713
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2714
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2715
                        PUSH_realigned_r32(R_EAX);
nkeynes@586
  2716
                        MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  2717
                        POP_realigned_r32(R_ECX);
nkeynes@359
  2718
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2719
<