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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 590:4db6a084ca3c
prev586:2a3ba82cf243
next591:7b9612fd2395
author nkeynes
date Wed Jan 16 09:39:16 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Ensure PC correctness in presence of delay-slot exceptions
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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    uint32_t recovery_posn;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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void sh4_x86_add_recovery( uint32_t pc )
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{
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    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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    xlat_recovery_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
nkeynes@586
   338
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   339
/**
nkeynes@586
   340
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   341
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   342
 */
nkeynes@586
   343
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   344
nkeynes@586
   345
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   346
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   347
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   348
nkeynes@590
   349
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   350
nkeynes@539
   351
/****** Import appropriate calling conventions ******/
nkeynes@539
   352
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   353
#include "sh4/ia64abi.h"
nkeynes@539
   354
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   355
#ifdef APPLE_BUILD
nkeynes@539
   356
#include "sh4/ia32mac.h"
nkeynes@539
   357
#else
nkeynes@539
   358
#include "sh4/ia32abi.h"
nkeynes@539
   359
#endif
nkeynes@539
   360
#endif
nkeynes@539
   361
nkeynes@590
   362
/**
nkeynes@590
   363
 * Embed a breakpoint into the generated code
nkeynes@590
   364
 */
nkeynes@586
   365
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   366
{
nkeynes@586
   367
    load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );
nkeynes@586
   368
    call_func1( sh4_translate_exit, R_EAX );
nkeynes@586
   369
}
nkeynes@590
   370
nkeynes@590
   371
/**
nkeynes@590
   372
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@590
   373
 * can't translate (mainly page-crossing delay slots at the moment).
nkeynes@590
   374
 * Caller is responsible for setting new_pc.
nkeynes@590
   375
 */
nkeynes@590
   376
void sh4_emulator_exit( sh4vma_t endpc )
nkeynes@590
   377
{
nkeynes@590
   378
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   379
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   380
    
nkeynes@590
   381
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@590
   382
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   383
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   384
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   385
nkeynes@590
   386
    call_func0( sh4_execute_instruction );    
nkeynes@590
   387
    load_imm32( R_EAX, R_PC );
nkeynes@590
   388
    if( sh4_x86.tlb_on ) {
nkeynes@590
   389
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   390
    } else {
nkeynes@590
   391
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   392
    }
nkeynes@590
   393
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@590
   394
    POP_r32(R_EBP);
nkeynes@590
   395
    RET();
nkeynes@590
   396
} 
nkeynes@539
   397
nkeynes@359
   398
/**
nkeynes@359
   399
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   400
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   401
 * 
nkeynes@586
   402
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   403
 *
nkeynes@359
   404
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   405
 * (eg a branch or 
nkeynes@359
   406
 */
nkeynes@590
   407
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   408
{
nkeynes@388
   409
    uint32_t ir;
nkeynes@586
   410
    /* Read instruction from icache */
nkeynes@586
   411
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   412
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   413
    
nkeynes@586
   414
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   415
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   416
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   417
	 * almost certainly in a delay slot.
nkeynes@586
   418
	 *
nkeynes@586
   419
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   420
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   421
	 * small repairs to cope with the different environment).
nkeynes@586
   422
	 */
nkeynes@586
   423
nkeynes@586
   424
    if( !sh4_x86.in_delay_slot ) {
nkeynes@586
   425
	sh4_x86_add_recovery(pc);
nkeynes@388
   426
    }
nkeynes@359
   427
%%
nkeynes@359
   428
/* ALU operations */
nkeynes@359
   429
ADD Rm, Rn {:
nkeynes@359
   430
    load_reg( R_EAX, Rm );
nkeynes@359
   431
    load_reg( R_ECX, Rn );
nkeynes@359
   432
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   433
    store_reg( R_ECX, Rn );
nkeynes@417
   434
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   435
:}
nkeynes@359
   436
ADD #imm, Rn {:  
nkeynes@359
   437
    load_reg( R_EAX, Rn );
nkeynes@359
   438
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   439
    store_reg( R_EAX, Rn );
nkeynes@417
   440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   441
:}
nkeynes@359
   442
ADDC Rm, Rn {:
nkeynes@417
   443
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   444
	LDC_t();
nkeynes@417
   445
    }
nkeynes@359
   446
    load_reg( R_EAX, Rm );
nkeynes@359
   447
    load_reg( R_ECX, Rn );
nkeynes@359
   448
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   449
    store_reg( R_ECX, Rn );
nkeynes@359
   450
    SETC_t();
nkeynes@417
   451
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   452
:}
nkeynes@359
   453
ADDV Rm, Rn {:
nkeynes@359
   454
    load_reg( R_EAX, Rm );
nkeynes@359
   455
    load_reg( R_ECX, Rn );
nkeynes@359
   456
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   457
    store_reg( R_ECX, Rn );
nkeynes@359
   458
    SETO_t();
nkeynes@417
   459
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   460
:}
nkeynes@359
   461
AND Rm, Rn {:
nkeynes@359
   462
    load_reg( R_EAX, Rm );
nkeynes@359
   463
    load_reg( R_ECX, Rn );
nkeynes@359
   464
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   465
    store_reg( R_ECX, Rn );
nkeynes@417
   466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   467
:}
nkeynes@359
   468
AND #imm, R0 {:  
nkeynes@359
   469
    load_reg( R_EAX, 0 );
nkeynes@359
   470
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   471
    store_reg( R_EAX, 0 );
nkeynes@417
   472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   473
:}
nkeynes@359
   474
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   475
    load_reg( R_EAX, 0 );
nkeynes@359
   476
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   477
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   478
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   479
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   480
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   481
    POP_realigned_r32(R_ECX);
nkeynes@386
   482
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   483
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   485
:}
nkeynes@359
   486
CMP/EQ Rm, Rn {:  
nkeynes@359
   487
    load_reg( R_EAX, Rm );
nkeynes@359
   488
    load_reg( R_ECX, Rn );
nkeynes@359
   489
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   490
    SETE_t();
nkeynes@417
   491
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   492
:}
nkeynes@359
   493
CMP/EQ #imm, R0 {:  
nkeynes@359
   494
    load_reg( R_EAX, 0 );
nkeynes@359
   495
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   496
    SETE_t();
nkeynes@417
   497
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   498
:}
nkeynes@359
   499
CMP/GE Rm, Rn {:  
nkeynes@359
   500
    load_reg( R_EAX, Rm );
nkeynes@359
   501
    load_reg( R_ECX, Rn );
nkeynes@359
   502
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   503
    SETGE_t();
nkeynes@417
   504
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   505
:}
nkeynes@359
   506
CMP/GT Rm, Rn {: 
nkeynes@359
   507
    load_reg( R_EAX, Rm );
nkeynes@359
   508
    load_reg( R_ECX, Rn );
nkeynes@359
   509
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   510
    SETG_t();
nkeynes@417
   511
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   512
:}
nkeynes@359
   513
CMP/HI Rm, Rn {:  
nkeynes@359
   514
    load_reg( R_EAX, Rm );
nkeynes@359
   515
    load_reg( R_ECX, Rn );
nkeynes@359
   516
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   517
    SETA_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/HS Rm, Rn {: 
nkeynes@359
   521
    load_reg( R_EAX, Rm );
nkeynes@359
   522
    load_reg( R_ECX, Rn );
nkeynes@359
   523
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   524
    SETAE_t();
nkeynes@417
   525
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   526
 :}
nkeynes@359
   527
CMP/PL Rn {: 
nkeynes@359
   528
    load_reg( R_EAX, Rn );
nkeynes@359
   529
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   530
    SETG_t();
nkeynes@417
   531
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   532
:}
nkeynes@359
   533
CMP/PZ Rn {:  
nkeynes@359
   534
    load_reg( R_EAX, Rn );
nkeynes@359
   535
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   536
    SETGE_t();
nkeynes@417
   537
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   538
:}
nkeynes@361
   539
CMP/STR Rm, Rn {:  
nkeynes@368
   540
    load_reg( R_EAX, Rm );
nkeynes@368
   541
    load_reg( R_ECX, Rn );
nkeynes@368
   542
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   543
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   544
    JE_rel8(13, target1);
nkeynes@368
   545
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   546
    JE_rel8(9, target2);
nkeynes@368
   547
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   548
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   549
    JE_rel8(2, target3);
nkeynes@368
   550
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   551
    JMP_TARGET(target1);
nkeynes@380
   552
    JMP_TARGET(target2);
nkeynes@380
   553
    JMP_TARGET(target3);
nkeynes@368
   554
    SETE_t();
nkeynes@417
   555
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   556
:}
nkeynes@361
   557
DIV0S Rm, Rn {:
nkeynes@361
   558
    load_reg( R_EAX, Rm );
nkeynes@386
   559
    load_reg( R_ECX, Rn );
nkeynes@361
   560
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   561
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   562
    store_spreg( R_EAX, R_M );
nkeynes@361
   563
    store_spreg( R_ECX, R_Q );
nkeynes@361
   564
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   565
    SETNE_t();
nkeynes@417
   566
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   567
:}
nkeynes@361
   568
DIV0U {:  
nkeynes@361
   569
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   570
    store_spreg( R_EAX, R_Q );
nkeynes@361
   571
    store_spreg( R_EAX, R_M );
nkeynes@361
   572
    store_spreg( R_EAX, R_T );
nkeynes@417
   573
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   574
:}
nkeynes@386
   575
DIV1 Rm, Rn {:
nkeynes@386
   576
    load_spreg( R_ECX, R_M );
nkeynes@386
   577
    load_reg( R_EAX, Rn );
nkeynes@417
   578
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   579
	LDC_t();
nkeynes@417
   580
    }
nkeynes@386
   581
    RCL1_r32( R_EAX );
nkeynes@386
   582
    SETC_r8( R_DL ); // Q'
nkeynes@386
   583
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   584
    JE_rel8(5, mqequal);
nkeynes@386
   585
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   586
    JMP_rel8(3, end);
nkeynes@380
   587
    JMP_TARGET(mqequal);
nkeynes@386
   588
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   589
    JMP_TARGET(end);
nkeynes@386
   590
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   591
    SETC_r8(R_AL); // tmp1
nkeynes@386
   592
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   593
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   594
    store_spreg( R_ECX, R_Q );
nkeynes@386
   595
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   596
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   597
    store_spreg( R_EAX, R_T );
nkeynes@417
   598
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   599
:}
nkeynes@361
   600
DMULS.L Rm, Rn {:  
nkeynes@361
   601
    load_reg( R_EAX, Rm );
nkeynes@361
   602
    load_reg( R_ECX, Rn );
nkeynes@361
   603
    IMUL_r32(R_ECX);
nkeynes@361
   604
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   605
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   606
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   607
:}
nkeynes@361
   608
DMULU.L Rm, Rn {:  
nkeynes@361
   609
    load_reg( R_EAX, Rm );
nkeynes@361
   610
    load_reg( R_ECX, Rn );
nkeynes@361
   611
    MUL_r32(R_ECX);
nkeynes@361
   612
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   613
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   615
:}
nkeynes@359
   616
DT Rn {:  
nkeynes@359
   617
    load_reg( R_EAX, Rn );
nkeynes@382
   618
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   619
    store_reg( R_EAX, Rn );
nkeynes@359
   620
    SETE_t();
nkeynes@417
   621
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   622
:}
nkeynes@359
   623
EXTS.B Rm, Rn {:  
nkeynes@359
   624
    load_reg( R_EAX, Rm );
nkeynes@359
   625
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   626
    store_reg( R_EAX, Rn );
nkeynes@359
   627
:}
nkeynes@361
   628
EXTS.W Rm, Rn {:  
nkeynes@361
   629
    load_reg( R_EAX, Rm );
nkeynes@361
   630
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   631
    store_reg( R_EAX, Rn );
nkeynes@361
   632
:}
nkeynes@361
   633
EXTU.B Rm, Rn {:  
nkeynes@361
   634
    load_reg( R_EAX, Rm );
nkeynes@361
   635
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   636
    store_reg( R_EAX, Rn );
nkeynes@361
   637
:}
nkeynes@361
   638
EXTU.W Rm, Rn {:  
nkeynes@361
   639
    load_reg( R_EAX, Rm );
nkeynes@361
   640
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   641
    store_reg( R_EAX, Rn );
nkeynes@361
   642
:}
nkeynes@586
   643
MAC.L @Rm+, @Rn+ {:
nkeynes@586
   644
    if( Rm == Rn ) {
nkeynes@586
   645
	load_reg( R_EAX, Rm );
nkeynes@586
   646
	check_ralign32( R_EAX );
nkeynes@586
   647
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   648
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   649
	load_reg( R_EAX, Rn );
nkeynes@586
   650
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@586
   651
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   652
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   653
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   654
	// adding a page-boundary check to skip the second translation
nkeynes@586
   655
    } else {
nkeynes@586
   656
	load_reg( R_EAX, Rm );
nkeynes@586
   657
	check_ralign32( R_EAX );
nkeynes@586
   658
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   659
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   660
	load_reg( R_EAX, Rn );
nkeynes@586
   661
	check_ralign32( R_EAX );
nkeynes@586
   662
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   663
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   664
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   665
    }
nkeynes@586
   666
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   667
    POP_r32( R_ECX );
nkeynes@586
   668
    PUSH_r32( R_EAX );
nkeynes@386
   669
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   670
    POP_realigned_r32( R_ECX );
nkeynes@586
   671
nkeynes@386
   672
    IMUL_r32( R_ECX );
nkeynes@386
   673
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   674
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   675
nkeynes@386
   676
    load_spreg( R_ECX, R_S );
nkeynes@386
   677
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   678
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   679
    call_func0( signsat48 );
nkeynes@386
   680
    JMP_TARGET( nosat );
nkeynes@417
   681
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   682
:}
nkeynes@386
   683
MAC.W @Rm+, @Rn+ {:  
nkeynes@586
   684
    if( Rm == Rn ) {
nkeynes@586
   685
	load_reg( R_EAX, Rm );
nkeynes@586
   686
	check_ralign16( R_EAX );
nkeynes@586
   687
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   688
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   689
	load_reg( R_EAX, Rn );
nkeynes@586
   690
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@586
   691
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   692
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   693
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   694
	// adding a page-boundary check to skip the second translation
nkeynes@586
   695
    } else {
nkeynes@586
   696
	load_reg( R_EAX, Rm );
nkeynes@586
   697
	check_ralign16( R_EAX );
nkeynes@586
   698
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   699
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   700
	load_reg( R_EAX, Rn );
nkeynes@586
   701
	check_ralign16( R_EAX );
nkeynes@586
   702
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   703
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   704
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   705
    }
nkeynes@586
   706
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   707
    POP_r32( R_ECX );
nkeynes@586
   708
    PUSH_r32( R_EAX );
nkeynes@386
   709
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   710
    POP_realigned_r32( R_ECX );
nkeynes@386
   711
    IMUL_r32( R_ECX );
nkeynes@386
   712
nkeynes@386
   713
    load_spreg( R_ECX, R_S );
nkeynes@386
   714
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   715
    JE_rel8( 47, nosat );
nkeynes@386
   716
nkeynes@386
   717
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   718
    JNO_rel8( 51, end );            // 2
nkeynes@386
   719
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   720
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   721
    JS_rel8( 13, positive );        // 2
nkeynes@386
   722
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   723
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   724
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   725
nkeynes@386
   726
    JMP_TARGET(positive);
nkeynes@386
   727
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   728
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   729
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   730
nkeynes@386
   731
    JMP_TARGET(nosat);
nkeynes@386
   732
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   733
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   734
    JMP_TARGET(end);
nkeynes@386
   735
    JMP_TARGET(end2);
nkeynes@386
   736
    JMP_TARGET(end3);
nkeynes@417
   737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   738
:}
nkeynes@359
   739
MOVT Rn {:  
nkeynes@359
   740
    load_spreg( R_EAX, R_T );
nkeynes@359
   741
    store_reg( R_EAX, Rn );
nkeynes@359
   742
:}
nkeynes@361
   743
MUL.L Rm, Rn {:  
nkeynes@361
   744
    load_reg( R_EAX, Rm );
nkeynes@361
   745
    load_reg( R_ECX, Rn );
nkeynes@361
   746
    MUL_r32( R_ECX );
nkeynes@361
   747
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   749
:}
nkeynes@374
   750
MULS.W Rm, Rn {:
nkeynes@374
   751
    load_reg16s( R_EAX, Rm );
nkeynes@374
   752
    load_reg16s( R_ECX, Rn );
nkeynes@374
   753
    MUL_r32( R_ECX );
nkeynes@374
   754
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   755
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   756
:}
nkeynes@374
   757
MULU.W Rm, Rn {:  
nkeynes@374
   758
    load_reg16u( R_EAX, Rm );
nkeynes@374
   759
    load_reg16u( R_ECX, Rn );
nkeynes@374
   760
    MUL_r32( R_ECX );
nkeynes@374
   761
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   762
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   763
:}
nkeynes@359
   764
NEG Rm, Rn {:
nkeynes@359
   765
    load_reg( R_EAX, Rm );
nkeynes@359
   766
    NEG_r32( R_EAX );
nkeynes@359
   767
    store_reg( R_EAX, Rn );
nkeynes@417
   768
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   769
:}
nkeynes@359
   770
NEGC Rm, Rn {:  
nkeynes@359
   771
    load_reg( R_EAX, Rm );
nkeynes@359
   772
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   773
    LDC_t();
nkeynes@359
   774
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   775
    store_reg( R_ECX, Rn );
nkeynes@359
   776
    SETC_t();
nkeynes@417
   777
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   778
:}
nkeynes@359
   779
NOT Rm, Rn {:  
nkeynes@359
   780
    load_reg( R_EAX, Rm );
nkeynes@359
   781
    NOT_r32( R_EAX );
nkeynes@359
   782
    store_reg( R_EAX, Rn );
nkeynes@417
   783
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   784
:}
nkeynes@359
   785
OR Rm, Rn {:  
nkeynes@359
   786
    load_reg( R_EAX, Rm );
nkeynes@359
   787
    load_reg( R_ECX, Rn );
nkeynes@359
   788
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   789
    store_reg( R_ECX, Rn );
nkeynes@417
   790
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   791
:}
nkeynes@359
   792
OR #imm, R0 {:
nkeynes@359
   793
    load_reg( R_EAX, 0 );
nkeynes@359
   794
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   795
    store_reg( R_EAX, 0 );
nkeynes@417
   796
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   797
:}
nkeynes@374
   798
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   799
    load_reg( R_EAX, 0 );
nkeynes@374
   800
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   801
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   802
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   803
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   804
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   805
    POP_realigned_r32(R_ECX);
nkeynes@386
   806
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   807
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   808
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   809
:}
nkeynes@359
   810
ROTCL Rn {:
nkeynes@359
   811
    load_reg( R_EAX, Rn );
nkeynes@417
   812
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   813
	LDC_t();
nkeynes@417
   814
    }
nkeynes@359
   815
    RCL1_r32( R_EAX );
nkeynes@359
   816
    store_reg( R_EAX, Rn );
nkeynes@359
   817
    SETC_t();
nkeynes@417
   818
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   819
:}
nkeynes@359
   820
ROTCR Rn {:  
nkeynes@359
   821
    load_reg( R_EAX, Rn );
nkeynes@417
   822
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   823
	LDC_t();
nkeynes@417
   824
    }
nkeynes@359
   825
    RCR1_r32( R_EAX );
nkeynes@359
   826
    store_reg( R_EAX, Rn );
nkeynes@359
   827
    SETC_t();
nkeynes@417
   828
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   829
:}
nkeynes@359
   830
ROTL Rn {:  
nkeynes@359
   831
    load_reg( R_EAX, Rn );
nkeynes@359
   832
    ROL1_r32( R_EAX );
nkeynes@359
   833
    store_reg( R_EAX, Rn );
nkeynes@359
   834
    SETC_t();
nkeynes@417
   835
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   836
:}
nkeynes@359
   837
ROTR Rn {:  
nkeynes@359
   838
    load_reg( R_EAX, Rn );
nkeynes@359
   839
    ROR1_r32( R_EAX );
nkeynes@359
   840
    store_reg( R_EAX, Rn );
nkeynes@359
   841
    SETC_t();
nkeynes@417
   842
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   843
:}
nkeynes@359
   844
SHAD Rm, Rn {:
nkeynes@359
   845
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   846
    load_reg( R_EAX, Rn );
nkeynes@361
   847
    load_reg( R_ECX, Rm );
nkeynes@361
   848
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   849
    JGE_rel8(16, doshl);
nkeynes@361
   850
                    
nkeynes@361
   851
    NEG_r32( R_ECX );      // 2
nkeynes@361
   852
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   853
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   854
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   855
    JMP_rel8(10, end);          // 2
nkeynes@386
   856
nkeynes@386
   857
    JMP_TARGET(emptysar);
nkeynes@386
   858
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   859
    JMP_rel8(5, end2);
nkeynes@382
   860
nkeynes@380
   861
    JMP_TARGET(doshl);
nkeynes@361
   862
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   863
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   864
    JMP_TARGET(end);
nkeynes@386
   865
    JMP_TARGET(end2);
nkeynes@361
   866
    store_reg( R_EAX, Rn );
nkeynes@417
   867
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   868
:}
nkeynes@359
   869
SHLD Rm, Rn {:  
nkeynes@368
   870
    load_reg( R_EAX, Rn );
nkeynes@368
   871
    load_reg( R_ECX, Rm );
nkeynes@382
   872
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   873
    JGE_rel8(15, doshl);
nkeynes@368
   874
nkeynes@382
   875
    NEG_r32( R_ECX );      // 2
nkeynes@382
   876
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   877
    JE_rel8( 4, emptyshr );
nkeynes@382
   878
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   879
    JMP_rel8(9, end);          // 2
nkeynes@386
   880
nkeynes@386
   881
    JMP_TARGET(emptyshr);
nkeynes@386
   882
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   883
    JMP_rel8(5, end2);
nkeynes@382
   884
nkeynes@382
   885
    JMP_TARGET(doshl);
nkeynes@382
   886
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   887
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   888
    JMP_TARGET(end);
nkeynes@386
   889
    JMP_TARGET(end2);
nkeynes@368
   890
    store_reg( R_EAX, Rn );
nkeynes@417
   891
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   892
:}
nkeynes@359
   893
SHAL Rn {: 
nkeynes@359
   894
    load_reg( R_EAX, Rn );
nkeynes@359
   895
    SHL1_r32( R_EAX );
nkeynes@397
   896
    SETC_t();
nkeynes@359
   897
    store_reg( R_EAX, Rn );
nkeynes@417
   898
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   899
:}
nkeynes@359
   900
SHAR Rn {:  
nkeynes@359
   901
    load_reg( R_EAX, Rn );
nkeynes@359
   902
    SAR1_r32( R_EAX );
nkeynes@397
   903
    SETC_t();
nkeynes@359
   904
    store_reg( R_EAX, Rn );
nkeynes@417
   905
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   906
:}
nkeynes@359
   907
SHLL Rn {:  
nkeynes@359
   908
    load_reg( R_EAX, Rn );
nkeynes@359
   909
    SHL1_r32( R_EAX );
nkeynes@397
   910
    SETC_t();
nkeynes@359
   911
    store_reg( R_EAX, Rn );
nkeynes@417
   912
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   913
:}
nkeynes@359
   914
SHLL2 Rn {:
nkeynes@359
   915
    load_reg( R_EAX, Rn );
nkeynes@359
   916
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   917
    store_reg( R_EAX, Rn );
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   919
:}
nkeynes@359
   920
SHLL8 Rn {:  
nkeynes@359
   921
    load_reg( R_EAX, Rn );
nkeynes@359
   922
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   923
    store_reg( R_EAX, Rn );
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   925
:}
nkeynes@359
   926
SHLL16 Rn {:  
nkeynes@359
   927
    load_reg( R_EAX, Rn );
nkeynes@359
   928
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   929
    store_reg( R_EAX, Rn );
nkeynes@417
   930
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   931
:}
nkeynes@359
   932
SHLR Rn {:  
nkeynes@359
   933
    load_reg( R_EAX, Rn );
nkeynes@359
   934
    SHR1_r32( R_EAX );
nkeynes@397
   935
    SETC_t();
nkeynes@359
   936
    store_reg( R_EAX, Rn );
nkeynes@417
   937
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   938
:}
nkeynes@359
   939
SHLR2 Rn {:  
nkeynes@359
   940
    load_reg( R_EAX, Rn );
nkeynes@359
   941
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   942
    store_reg( R_EAX, Rn );
nkeynes@417
   943
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   944
:}
nkeynes@359
   945
SHLR8 Rn {:  
nkeynes@359
   946
    load_reg( R_EAX, Rn );
nkeynes@359
   947
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@417
   949
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   950
:}
nkeynes@359
   951
SHLR16 Rn {:  
nkeynes@359
   952
    load_reg( R_EAX, Rn );
nkeynes@359
   953
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@417
   955
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   956
:}
nkeynes@359
   957
SUB Rm, Rn {:  
nkeynes@359
   958
    load_reg( R_EAX, Rm );
nkeynes@359
   959
    load_reg( R_ECX, Rn );
nkeynes@359
   960
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   961
    store_reg( R_ECX, Rn );
nkeynes@417
   962
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   963
:}
nkeynes@359
   964
SUBC Rm, Rn {:  
nkeynes@359
   965
    load_reg( R_EAX, Rm );
nkeynes@359
   966
    load_reg( R_ECX, Rn );
nkeynes@417
   967
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   968
	LDC_t();
nkeynes@417
   969
    }
nkeynes@359
   970
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   971
    store_reg( R_ECX, Rn );
nkeynes@394
   972
    SETC_t();
nkeynes@417
   973
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   974
:}
nkeynes@359
   975
SUBV Rm, Rn {:  
nkeynes@359
   976
    load_reg( R_EAX, Rm );
nkeynes@359
   977
    load_reg( R_ECX, Rn );
nkeynes@359
   978
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   979
    store_reg( R_ECX, Rn );
nkeynes@359
   980
    SETO_t();
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   982
:}
nkeynes@359
   983
SWAP.B Rm, Rn {:  
nkeynes@359
   984
    load_reg( R_EAX, Rm );
nkeynes@359
   985
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   986
    store_reg( R_EAX, Rn );
nkeynes@359
   987
:}
nkeynes@359
   988
SWAP.W Rm, Rn {:  
nkeynes@359
   989
    load_reg( R_EAX, Rm );
nkeynes@359
   990
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   991
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   992
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   993
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
    store_reg( R_ECX, Rn );
nkeynes@417
   995
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   996
:}
nkeynes@361
   997
TAS.B @Rn {:  
nkeynes@586
   998
    load_reg( R_EAX, Rn );
nkeynes@586
   999
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1000
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1001
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1002
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1003
    SETE_t();
nkeynes@361
  1004
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1005
    POP_realigned_r32( R_ECX );
nkeynes@361
  1006
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1008
:}
nkeynes@361
  1009
TST Rm, Rn {:  
nkeynes@361
  1010
    load_reg( R_EAX, Rm );
nkeynes@361
  1011
    load_reg( R_ECX, Rn );
nkeynes@361
  1012
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1013
    SETE_t();
nkeynes@417
  1014
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1015
:}
nkeynes@368
  1016
TST #imm, R0 {:  
nkeynes@368
  1017
    load_reg( R_EAX, 0 );
nkeynes@368
  1018
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1019
    SETE_t();
nkeynes@417
  1020
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1021
:}
nkeynes@368
  1022
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1023
    load_reg( R_EAX, 0);
nkeynes@368
  1024
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1025
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1026
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1027
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1028
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1029
    SETE_t();
nkeynes@417
  1030
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1031
:}
nkeynes@359
  1032
XOR Rm, Rn {:  
nkeynes@359
  1033
    load_reg( R_EAX, Rm );
nkeynes@359
  1034
    load_reg( R_ECX, Rn );
nkeynes@359
  1035
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1036
    store_reg( R_ECX, Rn );
nkeynes@417
  1037
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1038
:}
nkeynes@359
  1039
XOR #imm, R0 {:  
nkeynes@359
  1040
    load_reg( R_EAX, 0 );
nkeynes@359
  1041
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1042
    store_reg( R_EAX, 0 );
nkeynes@417
  1043
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1044
:}
nkeynes@359
  1045
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1046
    load_reg( R_EAX, 0 );
nkeynes@359
  1047
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1048
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1049
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1050
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1051
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1052
    POP_realigned_r32(R_ECX);
nkeynes@359
  1053
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1054
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1055
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1056
:}
nkeynes@361
  1057
XTRCT Rm, Rn {:
nkeynes@361
  1058
    load_reg( R_EAX, Rm );
nkeynes@394
  1059
    load_reg( R_ECX, Rn );
nkeynes@394
  1060
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1061
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1062
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1063
    store_reg( R_ECX, Rn );
nkeynes@417
  1064
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1065
:}
nkeynes@359
  1066
nkeynes@359
  1067
/* Data move instructions */
nkeynes@359
  1068
MOV Rm, Rn {:  
nkeynes@359
  1069
    load_reg( R_EAX, Rm );
nkeynes@359
  1070
    store_reg( R_EAX, Rn );
nkeynes@359
  1071
:}
nkeynes@359
  1072
MOV #imm, Rn {:  
nkeynes@359
  1073
    load_imm32( R_EAX, imm );
nkeynes@359
  1074
    store_reg( R_EAX, Rn );
nkeynes@359
  1075
:}
nkeynes@359
  1076
MOV.B Rm, @Rn {:  
nkeynes@586
  1077
    load_reg( R_EAX, Rn );
nkeynes@586
  1078
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1079
    load_reg( R_EDX, Rm );
nkeynes@586
  1080
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1082
:}
nkeynes@359
  1083
MOV.B Rm, @-Rn {:  
nkeynes@586
  1084
    load_reg( R_EAX, Rn );
nkeynes@586
  1085
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1086
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1087
    load_reg( R_EDX, Rm );
nkeynes@586
  1088
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1089
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1090
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1091
:}
nkeynes@359
  1092
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1093
    load_reg( R_EAX, 0 );
nkeynes@359
  1094
    load_reg( R_ECX, Rn );
nkeynes@586
  1095
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1096
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1097
    load_reg( R_EDX, Rm );
nkeynes@586
  1098
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1100
:}
nkeynes@359
  1101
MOV.B R0, @(disp, GBR) {:  
nkeynes@586
  1102
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1103
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1104
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1105
    load_reg( R_EDX, 0 );
nkeynes@586
  1106
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1107
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1108
:}
nkeynes@359
  1109
MOV.B R0, @(disp, Rn) {:  
nkeynes@586
  1110
    load_reg( R_EAX, Rn );
nkeynes@586
  1111
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1112
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1113
    load_reg( R_EDX, 0 );
nkeynes@586
  1114
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1116
:}
nkeynes@359
  1117
MOV.B @Rm, Rn {:  
nkeynes@586
  1118
    load_reg( R_EAX, Rm );
nkeynes@586
  1119
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1120
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1121
    store_reg( R_EAX, Rn );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1123
:}
nkeynes@359
  1124
MOV.B @Rm+, Rn {:  
nkeynes@586
  1125
    load_reg( R_EAX, Rm );
nkeynes@586
  1126
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1127
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1128
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1129
    store_reg( R_EAX, Rn );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
:}
nkeynes@359
  1132
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1133
    load_reg( R_EAX, 0 );
nkeynes@359
  1134
    load_reg( R_ECX, Rm );
nkeynes@586
  1135
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1136
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1137
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1138
    store_reg( R_EAX, Rn );
nkeynes@417
  1139
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1140
:}
nkeynes@359
  1141
MOV.B @(disp, GBR), R0 {:  
nkeynes@586
  1142
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1143
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1144
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1145
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1146
    store_reg( R_EAX, 0 );
nkeynes@417
  1147
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1148
:}
nkeynes@359
  1149
MOV.B @(disp, Rm), R0 {:  
nkeynes@586
  1150
    load_reg( R_EAX, Rm );
nkeynes@586
  1151
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1152
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1153
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1154
    store_reg( R_EAX, 0 );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1156
:}
nkeynes@374
  1157
MOV.L Rm, @Rn {:
nkeynes@586
  1158
    load_reg( R_EAX, Rn );
nkeynes@586
  1159
    check_walign32(R_EAX);
nkeynes@586
  1160
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1161
    load_reg( R_EDX, Rm );
nkeynes@586
  1162
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1164
:}
nkeynes@361
  1165
MOV.L Rm, @-Rn {:  
nkeynes@586
  1166
    load_reg( R_EAX, Rn );
nkeynes@586
  1167
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1168
    check_walign32( R_EAX );
nkeynes@586
  1169
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1170
    load_reg( R_EDX, Rm );
nkeynes@586
  1171
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1172
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1174
:}
nkeynes@361
  1175
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1176
    load_reg( R_EAX, 0 );
nkeynes@361
  1177
    load_reg( R_ECX, Rn );
nkeynes@586
  1178
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1179
    check_walign32( R_EAX );
nkeynes@586
  1180
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1181
    load_reg( R_EDX, Rm );
nkeynes@586
  1182
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1183
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1184
:}
nkeynes@361
  1185
MOV.L R0, @(disp, GBR) {:  
nkeynes@586
  1186
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1187
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1188
    check_walign32( R_EAX );
nkeynes@586
  1189
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1190
    load_reg( R_EDX, 0 );
nkeynes@586
  1191
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1193
:}
nkeynes@361
  1194
MOV.L Rm, @(disp, Rn) {:  
nkeynes@586
  1195
    load_reg( R_EAX, Rn );
nkeynes@586
  1196
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1197
    check_walign32( R_EAX );
nkeynes@586
  1198
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1199
    load_reg( R_EDX, Rm );
nkeynes@586
  1200
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1201
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1202
:}
nkeynes@361
  1203
MOV.L @Rm, Rn {:  
nkeynes@586
  1204
    load_reg( R_EAX, Rm );
nkeynes@586
  1205
    check_ralign32( R_EAX );
nkeynes@586
  1206
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1207
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1208
    store_reg( R_EAX, Rn );
nkeynes@417
  1209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1210
:}
nkeynes@361
  1211
MOV.L @Rm+, Rn {:  
nkeynes@361
  1212
    load_reg( R_EAX, Rm );
nkeynes@382
  1213
    check_ralign32( R_EAX );
nkeynes@586
  1214
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1215
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1216
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1217
    store_reg( R_EAX, Rn );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1219
:}
nkeynes@361
  1220
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1221
    load_reg( R_EAX, 0 );
nkeynes@361
  1222
    load_reg( R_ECX, Rm );
nkeynes@586
  1223
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1224
    check_ralign32( R_EAX );
nkeynes@586
  1225
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1226
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1227
    store_reg( R_EAX, Rn );
nkeynes@417
  1228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1229
:}
nkeynes@361
  1230
MOV.L @(disp, GBR), R0 {:
nkeynes@586
  1231
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1232
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1233
    check_ralign32( R_EAX );
nkeynes@586
  1234
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1235
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1236
    store_reg( R_EAX, 0 );
nkeynes@417
  1237
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1238
:}
nkeynes@361
  1239
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1240
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1241
	SLOTILLEGAL();
nkeynes@374
  1242
    } else {
nkeynes@388
  1243
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1244
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1245
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1246
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1247
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1248
nkeynes@586
  1249
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1250
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1251
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1252
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1253
	    // behaviour though.
nkeynes@586
  1254
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1255
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1256
	} else {
nkeynes@586
  1257
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1258
	    // different virtual address than the translation was done with,
nkeynes@586
  1259
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1260
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1261
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1262
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1263
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1264
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1265
	}
nkeynes@382
  1266
	store_reg( R_EAX, Rn );
nkeynes@374
  1267
    }
nkeynes@361
  1268
:}
nkeynes@361
  1269
MOV.L @(disp, Rm), Rn {:  
nkeynes@586
  1270
    load_reg( R_EAX, Rm );
nkeynes@586
  1271
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1272
    check_ralign32( R_EAX );
nkeynes@586
  1273
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1274
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1275
    store_reg( R_EAX, Rn );
nkeynes@417
  1276
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1277
:}
nkeynes@361
  1278
MOV.W Rm, @Rn {:  
nkeynes@586
  1279
    load_reg( R_EAX, Rn );
nkeynes@586
  1280
    check_walign16( R_EAX );
nkeynes@586
  1281
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1282
    load_reg( R_EDX, Rm );
nkeynes@586
  1283
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1284
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1285
:}
nkeynes@361
  1286
MOV.W Rm, @-Rn {:  
nkeynes@586
  1287
    load_reg( R_EAX, Rn );
nkeynes@586
  1288
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1289
    check_walign16( R_EAX );
nkeynes@586
  1290
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1291
    load_reg( R_EDX, Rm );
nkeynes@586
  1292
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1293
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1295
:}
nkeynes@361
  1296
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1297
    load_reg( R_EAX, 0 );
nkeynes@361
  1298
    load_reg( R_ECX, Rn );
nkeynes@586
  1299
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1300
    check_walign16( R_EAX );
nkeynes@586
  1301
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1302
    load_reg( R_EDX, Rm );
nkeynes@586
  1303
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1304
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1305
:}
nkeynes@361
  1306
MOV.W R0, @(disp, GBR) {:  
nkeynes@586
  1307
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1308
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1309
    check_walign16( R_EAX );
nkeynes@586
  1310
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1311
    load_reg( R_EDX, 0 );
nkeynes@586
  1312
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1314
:}
nkeynes@361
  1315
MOV.W R0, @(disp, Rn) {:  
nkeynes@586
  1316
    load_reg( R_EAX, Rn );
nkeynes@586
  1317
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1318
    check_walign16( R_EAX );
nkeynes@586
  1319
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1320
    load_reg( R_EDX, 0 );
nkeynes@586
  1321
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1323
:}
nkeynes@361
  1324
MOV.W @Rm, Rn {:  
nkeynes@586
  1325
    load_reg( R_EAX, Rm );
nkeynes@586
  1326
    check_ralign16( R_EAX );
nkeynes@586
  1327
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1328
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1329
    store_reg( R_EAX, Rn );
nkeynes@417
  1330
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1331
:}
nkeynes@361
  1332
MOV.W @Rm+, Rn {:  
nkeynes@361
  1333
    load_reg( R_EAX, Rm );
nkeynes@374
  1334
    check_ralign16( R_EAX );
nkeynes@586
  1335
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1336
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1337
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1338
    store_reg( R_EAX, Rn );
nkeynes@417
  1339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1340
:}
nkeynes@361
  1341
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1342
    load_reg( R_EAX, 0 );
nkeynes@361
  1343
    load_reg( R_ECX, Rm );
nkeynes@586
  1344
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1345
    check_ralign16( R_EAX );
nkeynes@586
  1346
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1347
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1348
    store_reg( R_EAX, Rn );
nkeynes@417
  1349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1350
:}
nkeynes@361
  1351
MOV.W @(disp, GBR), R0 {:  
nkeynes@586
  1352
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1353
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1354
    check_ralign16( R_EAX );
nkeynes@586
  1355
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1356
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1357
    store_reg( R_EAX, 0 );
nkeynes@417
  1358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1359
:}
nkeynes@361
  1360
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1361
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1362
	SLOTILLEGAL();
nkeynes@374
  1363
    } else {
nkeynes@586
  1364
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1365
	uint32_t target = pc + disp + 4;
nkeynes@586
  1366
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1367
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1368
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1369
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1370
	} else {
nkeynes@586
  1371
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1372
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1373
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1374
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1375
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1376
	}
nkeynes@374
  1377
	store_reg( R_EAX, Rn );
nkeynes@374
  1378
    }
nkeynes@361
  1379
:}
nkeynes@361
  1380
MOV.W @(disp, Rm), R0 {:  
nkeynes@586
  1381
    load_reg( R_EAX, Rm );
nkeynes@586
  1382
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1383
    check_ralign16( R_EAX );
nkeynes@586
  1384
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1385
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1386
    store_reg( R_EAX, 0 );
nkeynes@417
  1387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1388
:}
nkeynes@361
  1389
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1390
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1391
	SLOTILLEGAL();
nkeynes@374
  1392
    } else {
nkeynes@586
  1393
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1394
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1395
	store_reg( R_ECX, 0 );
nkeynes@586
  1396
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1397
    }
nkeynes@361
  1398
:}
nkeynes@361
  1399
MOVCA.L R0, @Rn {:  
nkeynes@586
  1400
    load_reg( R_EAX, Rn );
nkeynes@586
  1401
    check_walign32( R_EAX );
nkeynes@586
  1402
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1403
    load_reg( R_EDX, 0 );
nkeynes@586
  1404
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1406
:}
nkeynes@359
  1407
nkeynes@359
  1408
/* Control transfer instructions */
nkeynes@374
  1409
BF disp {:
nkeynes@374
  1410
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1411
	SLOTILLEGAL();
nkeynes@374
  1412
    } else {
nkeynes@586
  1413
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1414
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1415
	exit_block_rel(target, pc+2 );
nkeynes@380
  1416
	JMP_TARGET(nottaken);
nkeynes@408
  1417
	return 2;
nkeynes@374
  1418
    }
nkeynes@374
  1419
:}
nkeynes@374
  1420
BF/S disp {:
nkeynes@374
  1421
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1422
	SLOTILLEGAL();
nkeynes@374
  1423
    } else {
nkeynes@586
  1424
	sh4vma_t target = disp + pc + 4;
nkeynes@590
  1425
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1426
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1427
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1428
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1429
	}
nkeynes@417
  1430
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1431
	sh4_translate_instruction(pc+2);
nkeynes@586
  1432
	exit_block_rel( target, pc+4 );
nkeynes@408
  1433
	// not taken
nkeynes@408
  1434
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1435
	sh4_translate_instruction(pc+2);
nkeynes@408
  1436
	return 4;
nkeynes@374
  1437
    }
nkeynes@374
  1438
:}
nkeynes@374
  1439
BRA disp {:  
nkeynes@374
  1440
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1441
	SLOTILLEGAL();
nkeynes@374
  1442
    } else {
nkeynes@590
  1443
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1444
	sh4_translate_instruction( pc + 2 );
nkeynes@586
  1445
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1446
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1447
	return 4;
nkeynes@374
  1448
    }
nkeynes@374
  1449
:}
nkeynes@374
  1450
BRAF Rn {:  
nkeynes@374
  1451
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1452
	SLOTILLEGAL();
nkeynes@374
  1453
    } else {
nkeynes@590
  1454
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1455
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1456
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1457
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1458
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1459
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1460
	sh4_translate_instruction( pc + 2 );
nkeynes@590
  1461
	exit_block_newpcset(pc+2);
nkeynes@409
  1462
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1463
	return 4;
nkeynes@374
  1464
    }
nkeynes@374
  1465
:}
nkeynes@374
  1466
BSR disp {:  
nkeynes@374
  1467
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1468
	SLOTILLEGAL();
nkeynes@374
  1469
    } else {
nkeynes@590
  1470
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1471
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1472
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1473
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1474
	sh4_translate_instruction( pc + 2 );
nkeynes@586
  1475
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1476
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1477
	return 4;
nkeynes@374
  1478
    }
nkeynes@374
  1479
:}
nkeynes@374
  1480
BSRF Rn {:  
nkeynes@374
  1481
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1482
	SLOTILLEGAL();
nkeynes@374
  1483
    } else {
nkeynes@590
  1484
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1485
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1486
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1487
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1488
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1489
nkeynes@417
  1490
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1491
	sh4_translate_instruction( pc + 2 );
nkeynes@590
  1492
	exit_block_newpcset(pc+2);
nkeynes@409
  1493
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1494
	return 4;
nkeynes@374
  1495
    }
nkeynes@374
  1496
:}
nkeynes@374
  1497
BT disp {:
nkeynes@374
  1498
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1499
	SLOTILLEGAL();
nkeynes@374
  1500
    } else {
nkeynes@586
  1501
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1502
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1503
	exit_block_rel(target, pc+2 );
nkeynes@380
  1504
	JMP_TARGET(nottaken);
nkeynes@408
  1505
	return 2;
nkeynes@374
  1506
    }
nkeynes@374
  1507
:}
nkeynes@374
  1508
BT/S disp {:
nkeynes@374
  1509
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1510
	SLOTILLEGAL();
nkeynes@374
  1511
    } else {
nkeynes@590
  1512
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1513
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1514
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1515
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1516
	}
nkeynes@417
  1517
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1518
	sh4_translate_instruction(pc+2);
nkeynes@586
  1519
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  1520
	// not taken
nkeynes@408
  1521
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1522
	sh4_translate_instruction(pc+2);
nkeynes@408
  1523
	return 4;
nkeynes@374
  1524
    }
nkeynes@374
  1525
:}
nkeynes@374
  1526
JMP @Rn {:  
nkeynes@374
  1527
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1528
	SLOTILLEGAL();
nkeynes@374
  1529
    } else {
nkeynes@408
  1530
	load_reg( R_ECX, Rn );
nkeynes@590
  1531
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1532
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1533
	sh4_translate_instruction(pc+2);
nkeynes@590
  1534
	exit_block_newpcset(pc+2);
nkeynes@409
  1535
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1536
	return 4;
nkeynes@374
  1537
    }
nkeynes@374
  1538
:}
nkeynes@374
  1539
JSR @Rn {:  
nkeynes@374
  1540
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1541
	SLOTILLEGAL();
nkeynes@374
  1542
    } else {
nkeynes@590
  1543
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1544
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1545
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1546
	load_reg( R_ECX, Rn );
nkeynes@590
  1547
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@526
  1548
	sh4_translate_instruction(pc+2);
nkeynes@590
  1549
	exit_block_newpcset(pc+2);
nkeynes@409
  1550
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1551
	return 4;
nkeynes@374
  1552
    }
nkeynes@374
  1553
:}
nkeynes@374
  1554
RTE {:  
nkeynes@374
  1555
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1556
	SLOTILLEGAL();
nkeynes@374
  1557
    } else {
nkeynes@408
  1558
	check_priv();
nkeynes@408
  1559
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1560
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1561
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1562
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1563
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1564
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1565
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1566
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1567
	sh4_translate_instruction(pc+2);
nkeynes@590
  1568
	exit_block_newpcset(pc+2);
nkeynes@409
  1569
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1570
	return 4;
nkeynes@374
  1571
    }
nkeynes@374
  1572
:}
nkeynes@374
  1573
RTS {:  
nkeynes@374
  1574
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1575
	SLOTILLEGAL();
nkeynes@374
  1576
    } else {
nkeynes@408
  1577
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1578
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1579
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1580
	sh4_translate_instruction(pc+2);
nkeynes@590
  1581
	exit_block_newpcset(pc+2);
nkeynes@409
  1582
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1583
	return 4;
nkeynes@374
  1584
    }
nkeynes@374
  1585
:}
nkeynes@374
  1586
TRAPA #imm {:  
nkeynes@374
  1587
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1588
	SLOTILLEGAL();
nkeynes@374
  1589
    } else {
nkeynes@590
  1590
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1591
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1592
	load_imm32( R_EAX, imm );
nkeynes@527
  1593
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1594
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1595
	exit_block_pcset(pc);
nkeynes@409
  1596
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1597
	return 2;
nkeynes@374
  1598
    }
nkeynes@374
  1599
:}
nkeynes@374
  1600
UNDEF {:  
nkeynes@374
  1601
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1602
	SLOTILLEGAL();
nkeynes@374
  1603
    } else {
nkeynes@586
  1604
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1605
	return 2;
nkeynes@374
  1606
    }
nkeynes@368
  1607
:}
nkeynes@374
  1608
nkeynes@374
  1609
CLRMAC {:  
nkeynes@374
  1610
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1611
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1612
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1613
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1614
:}
nkeynes@374
  1615
CLRS {:
nkeynes@374
  1616
    CLC();
nkeynes@374
  1617
    SETC_sh4r(R_S);
nkeynes@417
  1618
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1619
:}
nkeynes@374
  1620
CLRT {:  
nkeynes@374
  1621
    CLC();
nkeynes@374
  1622
    SETC_t();
nkeynes@417
  1623
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1624
:}
nkeynes@374
  1625
SETS {:  
nkeynes@374
  1626
    STC();
nkeynes@374
  1627
    SETC_sh4r(R_S);
nkeynes@417
  1628
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1629
:}
nkeynes@374
  1630
SETT {:  
nkeynes@374
  1631
    STC();
nkeynes@374
  1632
    SETC_t();
nkeynes@417
  1633
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1634
:}
nkeynes@359
  1635
nkeynes@375
  1636
/* Floating point moves */
nkeynes@375
  1637
FMOV FRm, FRn {:  
nkeynes@375
  1638
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1639
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1640
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1641
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1642
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1643
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1644
     */
nkeynes@377
  1645
    check_fpuen();
nkeynes@375
  1646
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1647
    load_fr_bank( R_EDX );
nkeynes@375
  1648
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1649
    JNE_rel8(8, doublesize);
nkeynes@375
  1650
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1651
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1652
    if( FRm&1 ) {
nkeynes@386
  1653
	JMP_rel8(24, end);
nkeynes@380
  1654
	JMP_TARGET(doublesize);
nkeynes@375
  1655
	load_xf_bank( R_ECX ); 
nkeynes@375
  1656
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1657
	if( FRn&1 ) {
nkeynes@375
  1658
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1659
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1660
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1661
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1662
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1663
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1664
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1665
	}
nkeynes@380
  1666
	JMP_TARGET(end);
nkeynes@375
  1667
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1668
	if( FRn&1 ) {
nkeynes@386
  1669
	    JMP_rel8(24, end);
nkeynes@375
  1670
	    load_xf_bank( R_ECX );
nkeynes@375
  1671
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1672
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1673
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1674
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1675
	    JMP_TARGET(end);
nkeynes@375
  1676
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1677
	    JMP_rel8(12, end);
nkeynes@375
  1678
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1679
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1680
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1681
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1682
	    JMP_TARGET(end);
nkeynes@375
  1683
	}
nkeynes@375
  1684
    }
nkeynes@417
  1685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1686
:}
nkeynes@416
  1687
FMOV FRm, @Rn {: 
nkeynes@586
  1688
    check_fpuen();
nkeynes@586
  1689
    load_reg( R_EAX, Rn );
nkeynes@586
  1690
    check_walign32( R_EAX );
nkeynes@586
  1691
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1692
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1693
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1694
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1695
    load_fr_bank( R_EDX );
nkeynes@586
  1696
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1697
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1698
    if( FRm&1 ) {
nkeynes@527
  1699
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1700
	JMP_TARGET(doublesize);
nkeynes@416
  1701
	load_xf_bank( R_EDX );
nkeynes@586
  1702
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1703
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1704
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1705
	JMP_TARGET(end);
nkeynes@375
  1706
    } else {
nkeynes@527
  1707
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1708
	JMP_TARGET(doublesize);
nkeynes@416
  1709
	load_fr_bank( R_EDX );
nkeynes@586
  1710
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1711
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1712
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1713
	JMP_TARGET(end);
nkeynes@375
  1714
    }
nkeynes@417
  1715
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1716
:}
nkeynes@375
  1717
FMOV @Rm, FRn {:  
nkeynes@586
  1718
    check_fpuen();
nkeynes@586
  1719
    load_reg( R_EAX, Rm );
nkeynes@586
  1720
    check_ralign32( R_EAX );
nkeynes@586
  1721
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1722
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1723
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1724
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1725
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1726
    load_fr_bank( R_EDX );
nkeynes@416
  1727
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1728
    if( FRn&1 ) {
nkeynes@527
  1729
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1730
	JMP_TARGET(doublesize);
nkeynes@586
  1731
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1732
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1733
	load_xf_bank( R_EDX );
nkeynes@586
  1734
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1735
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1736
	JMP_TARGET(end);
nkeynes@375
  1737
    } else {
nkeynes@527
  1738
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1739
	JMP_TARGET(doublesize);
nkeynes@586
  1740
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1741
	load_fr_bank( R_EDX );
nkeynes@586
  1742
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1743
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1744
	JMP_TARGET(end);
nkeynes@375
  1745
    }
nkeynes@417
  1746
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1747
:}
nkeynes@377
  1748
FMOV FRm, @-Rn {:  
nkeynes@586
  1749
    check_fpuen();
nkeynes@586
  1750
    load_reg( R_EAX, Rn );
nkeynes@586
  1751
    check_walign32( R_EAX );
nkeynes@416
  1752
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1753
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1754
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@586
  1755
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1756
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1757
    load_fr_bank( R_EDX );
nkeynes@586
  1758
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1759
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@586
  1760
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1761
    if( FRm&1 ) {
nkeynes@586
  1762
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1763
	JMP_TARGET(doublesize);
nkeynes@586
  1764
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1765
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1766
	load_xf_bank( R_EDX );
nkeynes@586
  1767
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1768
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1769
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1770
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1771
	JMP_TARGET(end);
nkeynes@377
  1772
    } else {
nkeynes@586
  1773
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1774
	JMP_TARGET(doublesize);
nkeynes@586
  1775
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1776
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1777
	load_fr_bank( R_EDX );
nkeynes@586
  1778
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1779
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1780
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1781
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1782
	JMP_TARGET(end);
nkeynes@377
  1783
    }
nkeynes@417
  1784
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1785
:}
nkeynes@416
  1786
FMOV @Rm+, FRn {:
nkeynes@586
  1787
    check_fpuen();
nkeynes@586
  1788
    load_reg( R_EAX, Rm );
nkeynes@586
  1789
    check_ralign32( R_EAX );
nkeynes@586
  1790
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1791
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1792
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1793
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1794
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1795
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1796
    load_fr_bank( R_EDX );
nkeynes@416
  1797
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1798
    if( FRn&1 ) {
nkeynes@586
  1799
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1800
	JMP_TARGET(doublesize);
nkeynes@586
  1801
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1802
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1803
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1804
	load_xf_bank( R_EDX );
nkeynes@586
  1805
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1806
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1807
	JMP_TARGET(end);
nkeynes@377
  1808
    } else {
nkeynes@586
  1809
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@586
  1810
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1811
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1812
	load_fr_bank( R_EDX );
nkeynes@586
  1813
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1814
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1815
	JMP_TARGET(end);
nkeynes@377
  1816
    }
nkeynes@417
  1817
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1818
:}
nkeynes@377
  1819
FMOV FRm, @(R0, Rn) {:  
nkeynes@586
  1820
    check_fpuen();
nkeynes@586
  1821
    load_reg( R_EAX, Rn );
nkeynes@586
  1822
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1823
    check_walign32( R_EAX );
nkeynes@586
  1824
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1825
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1826
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1827
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1828
    load_fr_bank( R_EDX );
nkeynes@586
  1829
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1830
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1831
    if( FRm&1 ) {
nkeynes@527
  1832
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1833
	JMP_TARGET(doublesize);
nkeynes@416
  1834
	load_xf_bank( R_EDX );
nkeynes@586
  1835
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1836
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1837
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1838
	JMP_TARGET(end);
nkeynes@377
  1839
    } else {
nkeynes@527
  1840
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1841
	JMP_TARGET(doublesize);
nkeynes@416
  1842
	load_fr_bank( R_EDX );
nkeynes@586
  1843
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1844
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1845
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1846
	JMP_TARGET(end);
nkeynes@377
  1847
    }
nkeynes@417
  1848
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1849
:}
nkeynes@377
  1850
FMOV @(R0, Rm), FRn {:  
nkeynes@586
  1851
    check_fpuen();
nkeynes@586
  1852
    load_reg( R_EAX, Rm );
nkeynes@586
  1853
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1854
    check_ralign32( R_EAX );
nkeynes@586
  1855
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1856
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1857
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1858
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1859
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1860
    load_fr_bank( R_EDX );
nkeynes@416
  1861
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1862
    if( FRn&1 ) {
nkeynes@527
  1863
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1864
	JMP_TARGET(doublesize);
nkeynes@586
  1865
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1866
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1867
	load_xf_bank( R_EDX );
nkeynes@586
  1868
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1869
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1870
	JMP_TARGET(end);
nkeynes@377
  1871
    } else {
nkeynes@527
  1872
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1873
	JMP_TARGET(doublesize);
nkeynes@586
  1874
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1875
	load_fr_bank( R_EDX );
nkeynes@586
  1876
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1877
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1878
	JMP_TARGET(end);
nkeynes@377
  1879
    }
nkeynes@417
  1880
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1881
:}
nkeynes@377
  1882
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1883
    check_fpuen();
nkeynes@377
  1884
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1885
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1886
    JNE_rel8(8, end);
nkeynes@377
  1887
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1888
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1889
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1890
    JMP_TARGET(end);
nkeynes@417
  1891
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1892
:}
nkeynes@377
  1893
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1894
    check_fpuen();
nkeynes@377
  1895
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1896
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1897
    JNE_rel8(11, end);
nkeynes@377
  1898
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1899
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1900
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1901
    JMP_TARGET(end);
nkeynes@417
  1902
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1903
:}
nkeynes@377
  1904
nkeynes@377
  1905
FLOAT FPUL, FRn {:  
nkeynes@377
  1906
    check_fpuen();
nkeynes@377
  1907
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1908
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1909
    FILD_sh4r(R_FPUL);
nkeynes@377
  1910
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1911
    JNE_rel8(5, doubleprec);
nkeynes@377
  1912
    pop_fr( R_EDX, FRn );
nkeynes@380
  1913
    JMP_rel8(3, end);
nkeynes@380
  1914
    JMP_TARGET(doubleprec);
nkeynes@377
  1915
    pop_dr( R_EDX, FRn );
nkeynes@380
  1916
    JMP_TARGET(end);
nkeynes@417
  1917
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1918
:}
nkeynes@377
  1919
FTRC FRm, FPUL {:  
nkeynes@377
  1920
    check_fpuen();
nkeynes@388
  1921
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1922
    load_fr_bank( R_EDX );
nkeynes@388
  1923
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1924
    JNE_rel8(5, doubleprec);
nkeynes@388
  1925
    push_fr( R_EDX, FRm );
nkeynes@388
  1926
    JMP_rel8(3, doop);
nkeynes@388
  1927
    JMP_TARGET(doubleprec);
nkeynes@388
  1928
    push_dr( R_EDX, FRm );
nkeynes@388
  1929
    JMP_TARGET( doop );
nkeynes@388
  1930
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1931
    FILD_r32ind( R_ECX );
nkeynes@388
  1932
    FCOMIP_st(1);
nkeynes@394
  1933
    JNA_rel8( 32, sat );
nkeynes@388
  1934
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1935
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1936
    FCOMIP_st(1);                   // 2
nkeynes@394
  1937
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1938
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1939
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1940
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1941
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1942
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1943
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1944
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1945
nkeynes@388
  1946
    JMP_TARGET(sat);
nkeynes@388
  1947
    JMP_TARGET(sat2);
nkeynes@388
  1948
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1949
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1950
    FPOP_st();
nkeynes@388
  1951
    JMP_TARGET(end);
nkeynes@417
  1952
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1953
:}
nkeynes@377
  1954
FLDS FRm, FPUL {:  
nkeynes@377
  1955
    check_fpuen();
nkeynes@377
  1956
    load_fr_bank( R_ECX );
nkeynes@377
  1957
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1958
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1959
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1960
:}
nkeynes@377
  1961
FSTS FPUL, FRn {:  
nkeynes@377
  1962
    check_fpuen();
nkeynes@377
  1963
    load_fr_bank( R_ECX );
nkeynes@377
  1964
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1965
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1966
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1967
:}
nkeynes@377
  1968
FCNVDS FRm, FPUL {:  
nkeynes@377
  1969
    check_fpuen();
nkeynes@377
  1970
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1971
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1972
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1973
    load_fr_bank( R_ECX );
nkeynes@377
  1974
    push_dr( R_ECX, FRm );
nkeynes@377
  1975
    pop_fpul();
nkeynes@380
  1976
    JMP_TARGET(end);
nkeynes@417
  1977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1978
:}
nkeynes@377
  1979
FCNVSD FPUL, FRn {:  
nkeynes@377
  1980
    check_fpuen();
nkeynes@377
  1981
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1982
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1983
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1984
    load_fr_bank( R_ECX );
nkeynes@377
  1985
    push_fpul();
nkeynes@377
  1986
    pop_dr( R_ECX, FRn );
nkeynes@380
  1987
    JMP_TARGET(end);
nkeynes@417
  1988
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1989
:}
nkeynes@375
  1990
nkeynes@359
  1991
/* Floating point instructions */
nkeynes@374
  1992
FABS FRn {:  
nkeynes@377
  1993
    check_fpuen();
nkeynes@374
  1994
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1995
    load_fr_bank( R_EDX );
nkeynes@374
  1996
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1997
    JNE_rel8(10, doubleprec);
nkeynes@374
  1998
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1999
    FABS_st0(); // 2
nkeynes@374
  2000
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2001
    JMP_rel8(8,end); // 2
nkeynes@380
  2002
    JMP_TARGET(doubleprec);
nkeynes@374
  2003
    push_dr(R_EDX, FRn);
nkeynes@374
  2004
    FABS_st0();
nkeynes@374
  2005
    pop_dr(R_EDX, FRn);
nkeynes@380
  2006
    JMP_TARGET(end);
nkeynes@417
  2007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2008
:}
nkeynes@377
  2009
FADD FRm, FRn {:  
nkeynes@377
  2010
    check_fpuen();
nkeynes@375
  2011
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2012
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2013
    load_fr_bank( R_EDX );
nkeynes@380
  2014
    JNE_rel8(13,doubleprec);
nkeynes@377
  2015
    push_fr(R_EDX, FRm);
nkeynes@377
  2016
    push_fr(R_EDX, FRn);
nkeynes@377
  2017
    FADDP_st(1);
nkeynes@377
  2018
    pop_fr(R_EDX, FRn);
nkeynes@380
  2019
    JMP_rel8(11,end);
nkeynes@380
  2020
    JMP_TARGET(doubleprec);
nkeynes@377
  2021
    push_dr(R_EDX, FRm);
nkeynes@377
  2022
    push_dr(R_EDX, FRn);
nkeynes@377
  2023
    FADDP_st(1);
nkeynes@377
  2024
    pop_dr(R_EDX, FRn);
nkeynes@380
  2025
    JMP_TARGET(end);
nkeynes@417
  2026
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2027
:}
nkeynes@377
  2028
FDIV FRm, FRn {:  
nkeynes@377
  2029
    check_fpuen();
nkeynes@375
  2030
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2031
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2032
    load_fr_bank( R_EDX );
nkeynes@380
  2033
    JNE_rel8(13, doubleprec);
nkeynes@377
  2034
    push_fr(R_EDX, FRn);
nkeynes@377
  2035
    push_fr(R_EDX, FRm);
nkeynes@377
  2036
    FDIVP_st(1);
nkeynes@377
  2037
    pop_fr(R_EDX, FRn);
nkeynes@380
  2038
    JMP_rel8(11, end);
nkeynes@380
  2039
    JMP_TARGET(doubleprec);
nkeynes@377
  2040
    push_dr(R_EDX, FRn);
nkeynes@377
  2041
    push_dr(R_EDX, FRm);
nkeynes@377
  2042
    FDIVP_st(1);
nkeynes@377
  2043
    pop_dr(R_EDX, FRn);
nkeynes@380
  2044
    JMP_TARGET(end);
nkeynes@417
  2045
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2046
:}
nkeynes@375
  2047
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2048
    check_fpuen();
nkeynes@375
  2049
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2050
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2051
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2052
    JNE_rel8(18, doubleprec);
nkeynes@375
  2053
    push_fr( R_EDX, 0 );
nkeynes@375
  2054
    push_fr( R_EDX, FRm );
nkeynes@375
  2055
    FMULP_st(1);
nkeynes@375
  2056
    push_fr( R_EDX, FRn );
nkeynes@375
  2057
    FADDP_st(1);
nkeynes@375
  2058
    pop_fr( R_EDX, FRn );
nkeynes@380
  2059
    JMP_rel8(16, end);
nkeynes@380
  2060
    JMP_TARGET(doubleprec);
nkeynes@375
  2061
    push_dr( R_EDX, 0 );
nkeynes@375
  2062
    push_dr( R_EDX, FRm );
nkeynes@375
  2063
    FMULP_st(1);
nkeynes@375
  2064
    push_dr( R_EDX, FRn );
nkeynes@375
  2065
    FADDP_st(1);
nkeynes@375
  2066
    pop_dr( R_EDX, FRn );
nkeynes@380
  2067
    JMP_TARGET(end);
nkeynes@417
  2068
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2069
:}
nkeynes@375
  2070
nkeynes@377
  2071
FMUL FRm, FRn {:  
nkeynes@377
  2072
    check_fpuen();
nkeynes@377
  2073
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2074
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2075
    load_fr_bank( R_EDX );
nkeynes@380
  2076
    JNE_rel8(13, doubleprec);
nkeynes@377
  2077
    push_fr(R_EDX, FRm);
nkeynes@377
  2078
    push_fr(R_EDX, FRn);
nkeynes@377
  2079
    FMULP_st(1);
nkeynes@377
  2080
    pop_fr(R_EDX, FRn);
nkeynes@380
  2081
    JMP_rel8(11, end);
nkeynes@380
  2082
    JMP_TARGET(doubleprec);
nkeynes@377
  2083
    push_dr(R_EDX, FRm);
nkeynes@377
  2084
    push_dr(R_EDX, FRn);
nkeynes@377
  2085
    FMULP_st(1);
nkeynes@377
  2086
    pop_dr(R_EDX, FRn);
nkeynes@380
  2087
    JMP_TARGET(end);
nkeynes@417
  2088
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2089
:}
nkeynes@377
  2090
FNEG FRn {:  
nkeynes@377
  2091
    check_fpuen();
nkeynes@377
  2092
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2093
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2094
    load_fr_bank( R_EDX );
nkeynes@380
  2095
    JNE_rel8(10, doubleprec);
nkeynes@377
  2096
    push_fr(R_EDX, FRn);
nkeynes@377
  2097
    FCHS_st0();
nkeynes@377
  2098
    pop_fr(R_EDX, FRn);
nkeynes@380
  2099
    JMP_rel8(8, end);
nkeynes@380
  2100
    JMP_TARGET(doubleprec);
nkeynes@377
  2101
    push_dr(R_EDX, FRn);
nkeynes@377
  2102
    FCHS_st0();
nkeynes@377
  2103
    pop_dr(R_EDX, FRn);
nkeynes@380
  2104
    JMP_TARGET(end);
nkeynes@417
  2105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2106
:}
nkeynes@377
  2107
FSRRA FRn {:  
nkeynes@377
  2108
    check_fpuen();
nkeynes@377
  2109
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2110
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2111
    load_fr_bank( R_EDX );
nkeynes@380
  2112
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2113
    FLD1_st0();
nkeynes@377
  2114
    push_fr(R_EDX, FRn);
nkeynes@377
  2115
    FSQRT_st0();
nkeynes@377
  2116
    FDIVP_st(1);
nkeynes@377
  2117
    pop_fr(R_EDX, FRn);
nkeynes@380
  2118
    JMP_TARGET(end);
nkeynes@417
  2119
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2120
:}
nkeynes@377
  2121
FSQRT FRn {:  
nkeynes@377
  2122
    check_fpuen();
nkeynes@377
  2123
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2124
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2125
    load_fr_bank( R_EDX );
nkeynes@380
  2126
    JNE_rel8(10, doubleprec);
nkeynes@377
  2127
    push_fr(R_EDX, FRn);
nkeynes@377
  2128
    FSQRT_st0();
nkeynes@377
  2129
    pop_fr(R_EDX, FRn);
nkeynes@380
  2130
    JMP_rel8(8, end);
nkeynes@380
  2131
    JMP_TARGET(doubleprec);
nkeynes@377
  2132
    push_dr(R_EDX, FRn);
nkeynes@377
  2133
    FSQRT_st0();
nkeynes@377
  2134
    pop_dr(R_EDX, FRn);
nkeynes@380
  2135
    JMP_TARGET(end);
nkeynes@417
  2136
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2137
:}
nkeynes@377
  2138
FSUB FRm, FRn {:  
nkeynes@377
  2139
    check_fpuen();
nkeynes@377
  2140
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2141
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2142
    load_fr_bank( R_EDX );
nkeynes@380
  2143
    JNE_rel8(13, doubleprec);
nkeynes@377
  2144
    push_fr(R_EDX, FRn);
nkeynes@377
  2145
    push_fr(R_EDX, FRm);
nkeynes@388
  2146
    FSUBP_st(1);
nkeynes@377
  2147
    pop_fr(R_EDX, FRn);
nkeynes@380
  2148
    JMP_rel8(11, end);
nkeynes@380
  2149
    JMP_TARGET(doubleprec);
nkeynes@377
  2150
    push_dr(R_EDX, FRn);
nkeynes@377
  2151
    push_dr(R_EDX, FRm);
nkeynes@388
  2152
    FSUBP_st(1);
nkeynes@377
  2153
    pop_dr(R_EDX, FRn);
nkeynes@380
  2154
    JMP_TARGET(end);
nkeynes@417
  2155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2156
:}
nkeynes@377
  2157
nkeynes@377
  2158
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2159
    check_fpuen();
nkeynes@377
  2160
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2161
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2162
    load_fr_bank( R_EDX );
nkeynes@380
  2163
    JNE_rel8(8, doubleprec);
nkeynes@377
  2164
    push_fr(R_EDX, FRm);
nkeynes@377
  2165
    push_fr(R_EDX, FRn);
nkeynes@380
  2166
    JMP_rel8(6, end);
nkeynes@380
  2167
    JMP_TARGET(doubleprec);
nkeynes@377
  2168
    push_dr(R_EDX, FRm);
nkeynes@377
  2169
    push_dr(R_EDX, FRn);
nkeynes@382
  2170
    JMP_TARGET(end);
nkeynes@377
  2171
    FCOMIP_st(1);
nkeynes@377
  2172
    SETE_t();
nkeynes@377
  2173
    FPOP_st();
nkeynes@417
  2174
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2175
:}
nkeynes@377
  2176
FCMP/GT FRm, FRn {:  
nkeynes@377
  2177
    check_fpuen();
nkeynes@377
  2178
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2179
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2180
    load_fr_bank( R_EDX );
nkeynes@380
  2181
    JNE_rel8(8, doubleprec);
nkeynes@377
  2182
    push_fr(R_EDX, FRm);
nkeynes@377
  2183
    push_fr(R_EDX, FRn);
nkeynes@380
  2184
    JMP_rel8(6, end);
nkeynes@380
  2185
    JMP_TARGET(doubleprec);
nkeynes@377
  2186
    push_dr(R_EDX, FRm);
nkeynes@377
  2187
    push_dr(R_EDX, FRn);
nkeynes@380
  2188
    JMP_TARGET(end);
nkeynes@377
  2189
    FCOMIP_st(1);
nkeynes@377
  2190
    SETA_t();
nkeynes@377
  2191
    FPOP_st();
nkeynes@417
  2192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2193
:}
nkeynes@377
  2194
nkeynes@377
  2195
FSCA FPUL, FRn {:  
nkeynes@377
  2196
    check_fpuen();
nkeynes@388
  2197
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2198
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2199
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2200
    load_fr_bank( R_ECX );
nkeynes@388
  2201
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2202
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2203
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2204
    JMP_TARGET(doubleprec);
nkeynes@417
  2205
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2206
:}
nkeynes@377
  2207
FIPR FVm, FVn {:  
nkeynes@377
  2208
    check_fpuen();
nkeynes@388
  2209
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2210
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2211
    JNE_rel8(44, doubleprec);
nkeynes@388
  2212
    
nkeynes@388
  2213
    load_fr_bank( R_ECX );
nkeynes@388
  2214
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2215
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2216
    FMULP_st(1);
nkeynes@388
  2217
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2218
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2219
    FMULP_st(1);
nkeynes@388
  2220
    FADDP_st(1);
nkeynes@388
  2221
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2222
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2223
    FMULP_st(1);
nkeynes@388
  2224
    FADDP_st(1);
nkeynes@388
  2225
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2226
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2227
    FMULP_st(1);
nkeynes@388
  2228
    FADDP_st(1);
nkeynes@388
  2229
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2230
    JMP_TARGET(doubleprec);
nkeynes@417
  2231
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2232
:}
nkeynes@377
  2233
FTRV XMTRX, FVn {:  
nkeynes@377
  2234
    check_fpuen();
nkeynes@388
  2235
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2236
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2237
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2238
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2239
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2240
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2241
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2242
    JMP_TARGET(doubleprec);
nkeynes@417
  2243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2244
:}
nkeynes@377
  2245
nkeynes@377
  2246
FRCHG {:  
nkeynes@377
  2247
    check_fpuen();
nkeynes@377
  2248
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2249
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2250
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2251
    update_fr_bank( R_ECX );
nkeynes@417
  2252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2253
:}
nkeynes@377
  2254
FSCHG {:  
nkeynes@377
  2255
    check_fpuen();
nkeynes@377
  2256
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2257
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2258
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2260
:}
nkeynes@359
  2261
nkeynes@359
  2262
/* Processor control instructions */
nkeynes@368
  2263
LDC Rm, SR {:
nkeynes@386
  2264
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2265
	SLOTILLEGAL();
nkeynes@386
  2266
    } else {
nkeynes@386
  2267
	check_priv();
nkeynes@386
  2268
	load_reg( R_EAX, Rm );
nkeynes@386
  2269
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2270
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2271
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2272
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2273
    }
nkeynes@368
  2274
:}
nkeynes@359
  2275
LDC Rm, GBR {: 
nkeynes@359
  2276
    load_reg( R_EAX, Rm );
nkeynes@359
  2277
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2278
:}
nkeynes@359
  2279
LDC Rm, VBR {:  
nkeynes@386
  2280
    check_priv();
nkeynes@359
  2281
    load_reg( R_EAX, Rm );
nkeynes@359
  2282
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2284
:}
nkeynes@359
  2285
LDC Rm, SSR {:  
nkeynes@386
  2286
    check_priv();
nkeynes@359
  2287
    load_reg( R_EAX, Rm );
nkeynes@359
  2288
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC Rm, SGR {:  
nkeynes@386
  2292
    check_priv();
nkeynes@359
  2293
    load_reg( R_EAX, Rm );
nkeynes@359
  2294
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2296
:}
nkeynes@359
  2297
LDC Rm, SPC {:  
nkeynes@386
  2298
    check_priv();
nkeynes@359
  2299
    load_reg( R_EAX, Rm );
nkeynes@359
  2300
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2301
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2302
:}
nkeynes@359
  2303
LDC Rm, DBR {:  
nkeynes@386
  2304
    check_priv();
nkeynes@359
  2305
    load_reg( R_EAX, Rm );
nkeynes@359
  2306
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2307
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
:}
nkeynes@374
  2309
LDC Rm, Rn_BANK {:  
nkeynes@386
  2310
    check_priv();
nkeynes@374
  2311
    load_reg( R_EAX, Rm );
nkeynes@374
  2312
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2314
:}
nkeynes@359
  2315
LDC.L @Rm+, GBR {:  
nkeynes@359
  2316
    load_reg( R_EAX, Rm );
nkeynes@395
  2317
    check_ralign32( R_EAX );
nkeynes@586
  2318
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2319
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2320
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2321
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2323
:}
nkeynes@368
  2324
LDC.L @Rm+, SR {:
nkeynes@386
  2325
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2326
	SLOTILLEGAL();
nkeynes@386
  2327
    } else {
nkeynes@586
  2328
	check_priv();
nkeynes@386
  2329
	load_reg( R_EAX, Rm );
nkeynes@395
  2330
	check_ralign32( R_EAX );
nkeynes@586
  2331
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2332
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2333
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2334
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2335
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2336
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2337
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2338
    }
nkeynes@359
  2339
:}
nkeynes@359
  2340
LDC.L @Rm+, VBR {:  
nkeynes@586
  2341
    check_priv();
nkeynes@359
  2342
    load_reg( R_EAX, Rm );
nkeynes@395
  2343
    check_ralign32( R_EAX );
nkeynes@586
  2344
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2345
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2346
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2347
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2348
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2349
:}
nkeynes@359
  2350
LDC.L @Rm+, SSR {:
nkeynes@586
  2351
    check_priv();
nkeynes@359
  2352
    load_reg( R_EAX, Rm );
nkeynes@416
  2353
    check_ralign32( R_EAX );
nkeynes@586
  2354
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2355
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2356
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2357
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2359
:}
nkeynes@359
  2360
LDC.L @Rm+, SGR {:  
nkeynes@586
  2361
    check_priv();
nkeynes@359
  2362
    load_reg( R_EAX, Rm );
nkeynes@395
  2363
    check_ralign32( R_EAX );
nkeynes@586
  2364
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2365
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2366
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2367
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2369
:}
nkeynes@359
  2370
LDC.L @Rm+, SPC {:  
nkeynes@586
  2371
    check_priv();
nkeynes@359
  2372
    load_reg( R_EAX, Rm );
nkeynes@395
  2373
    check_ralign32( R_EAX );
nkeynes@586
  2374
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2375
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2376
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2377
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2379
:}
nkeynes@359
  2380
LDC.L @Rm+, DBR {:  
nkeynes@586
  2381
    check_priv();
nkeynes@359
  2382
    load_reg( R_EAX, Rm );
nkeynes@395
  2383
    check_ralign32( R_EAX );
nkeynes@586
  2384
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2385
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2386
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2387
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2388
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2389
:}
nkeynes@359
  2390
LDC.L @Rm+, Rn_BANK {:  
nkeynes@586
  2391
    check_priv();
nkeynes@374
  2392
    load_reg( R_EAX, Rm );
nkeynes@395
  2393
    check_ralign32( R_EAX );
nkeynes@586
  2394
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2395
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2396
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2397
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2399
:}
nkeynes@359
  2400
LDS Rm, FPSCR {:  
nkeynes@359
  2401
    load_reg( R_EAX, Rm );
nkeynes@359
  2402
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2403
    update_fr_bank( R_EAX );
nkeynes@417
  2404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2405
:}
nkeynes@359
  2406
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@395
  2408
    check_ralign32( R_EAX );
nkeynes@586
  2409
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2410
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2411
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2412
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2413
    update_fr_bank( R_EAX );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2415
:}
nkeynes@359
  2416
LDS Rm, FPUL {:  
nkeynes@359
  2417
    load_reg( R_EAX, Rm );
nkeynes@359
  2418
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2419
:}
nkeynes@359
  2420
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2421
    load_reg( R_EAX, Rm );
nkeynes@395
  2422
    check_ralign32( R_EAX );
nkeynes@586
  2423
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2424
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2425
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2426
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2428
:}
nkeynes@359
  2429
LDS Rm, MACH {: 
nkeynes@359
  2430
    load_reg( R_EAX, Rm );
nkeynes@359
  2431
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2432
:}
nkeynes@359
  2433
LDS.L @Rm+, MACH {:  
nkeynes@359
  2434
    load_reg( R_EAX, Rm );
nkeynes@395
  2435
    check_ralign32( R_EAX );
nkeynes@586
  2436
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2437
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2438
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2439
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2441
:}
nkeynes@359
  2442
LDS Rm, MACL {:  
nkeynes@359
  2443
    load_reg( R_EAX, Rm );
nkeynes@359
  2444
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2445
:}
nkeynes@359
  2446
LDS.L @Rm+, MACL {:  
nkeynes@359
  2447
    load_reg( R_EAX, Rm );
nkeynes@395
  2448
    check_ralign32( R_EAX );
nkeynes@586
  2449
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2450
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2451
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2452
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2454
:}
nkeynes@359
  2455
LDS Rm, PR {:  
nkeynes@359
  2456
    load_reg( R_EAX, Rm );
nkeynes@359
  2457
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2458
:}
nkeynes@359
  2459
LDS.L @Rm+, PR {:  
nkeynes@359
  2460
    load_reg( R_EAX, Rm );
nkeynes@395
  2461
    check_ralign32( R_EAX );
nkeynes@586
  2462
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2463
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2464
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2465
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2467
:}
nkeynes@550
  2468
LDTLB {:  
nkeynes@553
  2469
    call_func0( MMU_ldtlb );
nkeynes@550
  2470
:}
nkeynes@359
  2471
OCBI @Rn {:  :}
nkeynes@359
  2472
OCBP @Rn {:  :}
nkeynes@359
  2473
OCBWB @Rn {:  :}
nkeynes@374
  2474
PREF @Rn {:
nkeynes@374
  2475
    load_reg( R_EAX, Rn );
nkeynes@532
  2476
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2477
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2478
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
  2479
    JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
  2480
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2481
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2482
    JE_exc(-1);
nkeynes@380
  2483
    JMP_TARGET(end);
nkeynes@417
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2485
:}
nkeynes@388
  2486
SLEEP {: 
nkeynes@388
  2487
    check_priv();
nkeynes@388
  2488
    call_func0( sh4_sleep );
nkeynes@417
  2489
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2490
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2491
    return 2;
nkeynes@388
  2492
:}
nkeynes@386
  2493
STC SR, Rn {:
nkeynes@386
  2494
    check_priv();
nkeynes@386
  2495
    call_func0(sh4_read_sr);
nkeynes@386
  2496
    store_reg( R_EAX, Rn );
nkeynes@417
  2497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2498
:}
nkeynes@359
  2499
STC GBR, Rn {:  
nkeynes@359
  2500
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2501
    store_reg( R_EAX, Rn );
nkeynes@359
  2502
:}
nkeynes@359
  2503
STC VBR, Rn {:  
nkeynes@386
  2504
    check_priv();
nkeynes@359
  2505
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2506
    store_reg( R_EAX, Rn );
nkeynes@417
  2507
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2508
:}
nkeynes@359
  2509
STC SSR, Rn {:  
nkeynes@386
  2510
    check_priv();
nkeynes@359
  2511
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2512
    store_reg( R_EAX, Rn );
nkeynes@417
  2513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2514
:}
nkeynes@359
  2515
STC SPC, Rn {:  
nkeynes@386
  2516
    check_priv();
nkeynes@359
  2517
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2518
    store_reg( R_EAX, Rn );
nkeynes@417
  2519
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2520
:}
nkeynes@359
  2521
STC SGR, Rn {:  
nkeynes@386
  2522
    check_priv();
nkeynes@359
  2523
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2524
    store_reg( R_EAX, Rn );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
STC DBR, Rn {:  
nkeynes@386
  2528
    check_priv();
nkeynes@359
  2529
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2530
    store_reg( R_EAX, Rn );
nkeynes@417
  2531
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2532
:}
nkeynes@374
  2533
STC Rm_BANK, Rn {:
nkeynes@386
  2534
    check_priv();
nkeynes@374
  2535
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2536
    store_reg( R_EAX, Rn );
nkeynes@417
  2537
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2538
:}
nkeynes@374
  2539
STC.L SR, @-Rn {:
nkeynes@586
  2540
    check_priv();
nkeynes@586
  2541
    load_reg( R_EAX, Rn );
nkeynes@586
  2542
    check_walign32( R_EAX );
nkeynes@586
  2543
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2544
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2545
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2546
    call_func0( sh4_read_sr );
nkeynes@586
  2547
    POP_realigned_r32( R_ECX );
nkeynes@586
  2548
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2549
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2550
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2551
:}
nkeynes@359
  2552
STC.L VBR, @-Rn {:  
nkeynes@586
  2553
    check_priv();
nkeynes@586
  2554
    load_reg( R_EAX, Rn );
nkeynes@586
  2555
    check_walign32( R_EAX );
nkeynes@586
  2556
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2557
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2558
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2559
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2560
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2561
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2562
:}
nkeynes@359
  2563
STC.L SSR, @-Rn {:  
nkeynes@586
  2564
    check_priv();
nkeynes@586
  2565
    load_reg( R_EAX, Rn );
nkeynes@586
  2566
    check_walign32( R_EAX );
nkeynes@586
  2567
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2568
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2569
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2570
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2571
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2573
:}
nkeynes@416
  2574
STC.L SPC, @-Rn {:
nkeynes@586
  2575
    check_priv();
nkeynes@586
  2576
    load_reg( R_EAX, Rn );
nkeynes@586
  2577
    check_walign32( R_EAX );
nkeynes@586
  2578
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2579
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2580
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2581
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2582
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2583
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2584
:}
nkeynes@359
  2585
STC.L SGR, @-Rn {:  
nkeynes@586
  2586
    check_priv();
nkeynes@586
  2587
    load_reg( R_EAX, Rn );
nkeynes@586
  2588
    check_walign32( R_EAX );
nkeynes@586
  2589
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2590
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2591
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2592
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2593
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2594
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2595
:}
nkeynes@359
  2596
STC.L DBR, @-Rn {:  
nkeynes@586
  2597
    check_priv();
nkeynes@586
  2598
    load_reg( R_EAX, Rn );
nkeynes@586
  2599
    check_walign32( R_EAX );
nkeynes@586
  2600
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2601
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2602
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2603
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2604
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2606
:}
nkeynes@374
  2607
STC.L Rm_BANK, @-Rn {:  
nkeynes@586
  2608
    check_priv();
nkeynes@586
  2609
    load_reg( R_EAX, Rn );
nkeynes@586
  2610
    check_walign32( R_EAX );
nkeynes@586
  2611
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2612
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2613
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2614
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2615
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2616
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2617
:}
nkeynes@359
  2618
STC.L GBR, @-Rn {:  
nkeynes@586
  2619
    load_reg( R_EAX, Rn );
nkeynes@586
  2620
    check_walign32( R_EAX );
nkeynes@586
  2621
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2622
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2623
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2624
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2625
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2627
:}
nkeynes@359
  2628
STS FPSCR, Rn {:  
nkeynes@359
  2629
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2630
    store_reg( R_EAX, Rn );
nkeynes@359
  2631
:}
nkeynes@359
  2632
STS.L FPSCR, @-Rn {:  
nkeynes@586
  2633
    load_reg( R_EAX, Rn );
nkeynes@586
  2634
    check_walign32( R_EAX );
nkeynes@586
  2635
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2636
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2637
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2638
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2639
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2641
:}
nkeynes@359
  2642
STS FPUL, Rn {:  
nkeynes@359
  2643
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2644
    store_reg( R_EAX, Rn );
nkeynes@359
  2645
:}
nkeynes@359
  2646
STS.L FPUL, @-Rn {:  
nkeynes@586
  2647
    load_reg( R_EAX, Rn );
nkeynes@586
  2648
    check_walign32( R_EAX );
nkeynes@586
  2649
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2650
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2651
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2652
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2653
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2654
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2655
:}
nkeynes@359
  2656
STS MACH, Rn {:  
nkeynes@359
  2657
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2658
    store_reg( R_EAX, Rn );
nkeynes@359
  2659
:}
nkeynes@359
  2660
STS.L MACH, @-Rn {:  
nkeynes@586
  2661
    load_reg( R_EAX, Rn );
nkeynes@586
  2662
    check_walign32( R_EAX );
nkeynes@586
  2663
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2664
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2665
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2666
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2667
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2668
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2669
:}
nkeynes@359
  2670
STS MACL, Rn {:  
nkeynes@359
  2671
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2672
    store_reg( R_EAX, Rn );
nkeynes@359
  2673
:}
nkeynes@359
  2674
STS.L MACL, @-Rn {:  
nkeynes@586
  2675
    load_reg( R_EAX, Rn );
nkeynes@586
  2676
    check_walign32( R_EAX );
nkeynes@586
  2677
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2678
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2679
    load_spreg( R_EDX, R_MACL );
nkeynes@586
  2680
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2681
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2682
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2683
:}
nkeynes@359
  2684
STS PR, Rn {:  
nkeynes@359
  2685
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2686
    store_reg( R_EAX, Rn );
nkeynes@359
  2687
:}
nkeynes@359
  2688
STS.L PR, @-Rn {:  
nkeynes@586
  2689
    load_reg( R_EAX, Rn );
nkeynes@586
  2690
    check_walign32( R_EAX );
nkeynes@586
  2691
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2692
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2693
    load_spreg( R_EDX, R_PR );
nkeynes@586
  2694
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2695
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2697
:}
nkeynes@359
  2698
nkeynes@359
  2699
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2700
%%
nkeynes@590
  2701
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359
  2702
    return 0;
nkeynes@359
  2703
}
.