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lxdream.org :: lxdream/src/gdrom/ide.h
lxdream 0.9.1
released Jun 29
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filename src/gdrom/ide.h
changeset 561:533f6b478071
prev493:c8183f888b14
next736:a02d1475ccfd
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
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/**
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 * $Id$
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 *
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 * This file defines the interface and structures of the dreamcast's IDE 
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 * port. Note that the register definitions are in asic.h, as the registers
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 * fall into the general ASIC ranges (and I don't want to use smaller pages
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 * at this stage). The registers here are exactly as per the ATA 
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 * specifications, which makes things a little easier.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef dream_ide_H
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#define dream_ide_H 1
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#include "dream.h"
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#define GDROM_SENSE_LENGTH 10
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#define GDROM_MODE_LENGTH 32
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struct ide_registers {
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    /* IDE interface registers */
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    uint8_t status;  /* A05F709C + A05F7018 Read-only */
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    uint8_t control; /* A05F7018 Write-only 01110 */
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    uint8_t error;   /* A05F7084 Read-only  10001 */
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    uint8_t feature; /* A05F7084 Write-only 10001 */
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    uint8_t count;   /* A05F7088 Read/Write 10010 */
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    uint8_t disc;    /* A05F708C Read-only 10011 */
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    uint8_t lba0;    /* A05F708C Write-only 10011 (NB: Presumed, TBV */
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    uint8_t lba1;    /* A05F7090 Read/Write 10100 */
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    uint8_t lba2;    /* A05F7094 Read/Write 10101 */
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    uint8_t device;  /* A05F7098 Read/Write 10110 */
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    uint8_t command; /* A05F709C Write-only 10111 */
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    /* Internal IDE state */
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    uint8_t intrq_pending; /* Flag to indicate if the INTRQ line is active */
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    gboolean interface_enabled;
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    gboolean was_reset; /* Flag indicating that the device has just been reset */
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    uint32_t state;
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    uint32_t last_packet_command; /* Identifies the command executing during a r/w cycle */
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    /* Sense response for the last executed packet command */
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    unsigned char gdrom_sense[GDROM_SENSE_LENGTH];
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    unsigned char gdrom_mode[GDROM_MODE_LENGTH];
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    /* offset in the buffer of the next word to read/write, or -1
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     * if inactive.
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     */ 
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    int32_t data_offset;
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    int32_t data_length;
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    /* Status reporting information */
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    uint8_t last_read_track;
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    uint32_t current_lba;
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    uint32_t current_mode;
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    uint32_t sectors_left; /* sectors left after current read */
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};
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#define IDE_STATE_IDLE      0 
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#define IDE_STATE_CMD_WRITE 1
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#define IDE_STATE_PIO_READ  2
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#define IDE_STATE_PIO_WRITE 3
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#define IDE_STATE_DMA_READ  4
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#define IDE_STATE_DMA_WRITE 5
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#define IDE_STATE_BUSY      6
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/* Flag bits */
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#define IDE_STATUS_BSY  0x80    /* Busy */
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#define IDE_STATUS_DRDY 0x40    /* Device ready */
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#define IDE_STATUS_DMRD 0x20    /* DMA Request */
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#define IDE_STATUS_SERV 0x10   
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#define IDE_STATUS_DRQ  0x08
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#define IDE_STATUS_CHK  0x01    /* Check condition (ie error) */
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#define IDE_FEAT_DMA 0x01
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#define IDE_FEAT_OVL 0x02
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#define IDE_COUNT_CD 0x01       /* Command (1)/Data (0) */
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#define IDE_COUNT_IO 0x02       /* Input (1)/Output (0) */
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#define IDE_COUNT_REL 0x04      /* Release device */
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#define IDE_CTL_RESET 0x04
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#define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
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#define IDE_CMD_NOP 0x00
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#define IDE_CMD_RESET_DEVICE 0x08
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#define IDE_CMD_PACKET 0xA0
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#define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
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#define IDE_CMD_SERVICE 0xA2
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#define IDE_CMD_SET_FEATURE 0xEF
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#define IDE_FEAT_SET_TRANSFER_MODE 0x03
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#define IDE_XFER_PIO        0x00
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#define IDE_XFER_PIO_FLOW   0x08
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#define IDE_XFER_MULTI_DMA  0x20
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#define IDE_XFER_ULTRA_DMA  0x40
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extern struct ide_registers idereg;
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/* Note: control can be written at any time - all other registers are writable
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 * only when ide_can_write_regs() is true
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 */
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#define ide_can_write_regs() ((idereg.status&0x80)==0)
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#define IS_IDE_IRQ_ENABLED() ((idereg.control&0x02)==0)
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uint16_t ide_read_data_pio(void);
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void ide_write_data_pio( uint16_t value );
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uint32_t ide_read_data_dma( uint32_t addr, uint32_t length );
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uint8_t ide_read_status(void);
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uint8_t ide_get_drive_status(void);
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void ide_write_buffer( unsigned char *data, uint32_t length ); 
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void ide_write_command( uint8_t command );
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void ide_write_control( uint8_t value );
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void ide_dma_read_req( uint32_t addr, uint32_t length );
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#endif
.