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lxdream.org :: lxdream/src/sh4/intc.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/intc.h
changeset 561:533f6b478071
prev31:495e480360d7
next736:a02d1475ccfd
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
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/**
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 * $Id$
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 *
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 * SH4 onboard interrupt controller (INTC) definitions.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef sh4intc_H
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#define sh4intc_H 1
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#include "sh4core.h"
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#ifdef __cplusplus
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extern "C" {
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#if 0
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}
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#endif
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#endif
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#define INT_IRQ0        0     /* External Interrupt request 0 */
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#define INT_IRQ1        1
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#define INT_IRQ2        2
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#define INT_IRQ3        3
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#define INT_IRQ4        4
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#define INT_IRQ5        5
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#define INT_IRQ6        6
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#define INT_IRQ7        7
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#define INT_IRQ8        8
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#define INT_IRQ9        9
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#define INT_IRQ10      10
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#define INT_IRQ11      11
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#define INT_IRQ12      12
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#define INT_IRQ13      13
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#define INT_IRQ14      14
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#define INT_NMI        15     /* Non-Maskable Interrupt */
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#define INT_HUDI       16     /* Hitachi use debug interface */
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#define INT_GPIO       17     /* I/O port interrupt */
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#define INT_DMA_DMTE0  18     /* DMA transfer end 0 */
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#define INT_DMA_DMTE1  19     /* DMA transfer end 1 */
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#define INT_DMA_DMTE2  20     /* DMA transfer end 2 */
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#define INT_DMA_DMTE3  21     /* DMA transfer end 3 */
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#define INT_DMA_DMAE   22     /* DMA address error */
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#define INT_TMU_TUNI0  23     /* Timer underflow interrupt 0 */
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#define INT_TMU_TUNI1  24     /* Timer underflow interrupt 1 */
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#define INT_TMU_TUNI2  25     /* Timer underflow interrupt 2 */
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#define INT_TMU_TICPI2 26     /* Timer input capture interrupt */
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#define INT_RTC_ATI    27     /* RTC Alarm interrupt */
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#define INT_RTC_PRI    28     /* RTC periodic interrupt */
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#define INT_RTC_CUI    29     /* RTC Carry-up interrupt */
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#define INT_SCI_ERI    30     /* SCI receive-error interrupt */
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#define INT_SCI_RXI    31     /* SCI receive-data-full interrupt */
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#define INT_SCI_TXI    32     /* SCI transmit-data-empty interrupt */
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#define INT_SCI_TEI    33     /* SCI transmit-end interrupt */
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#define INT_SCIF_ERI   34     /* SCIF receive-error interrupt */
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#define INT_SCIF_RXI   35     /* SCIF receive-data-full interrupt */
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#define INT_SCIF_BRI   36     /* SCIF break interrupt request */
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#define INT_SCIF_TXI   37     /* SCIF Transmit-data-empty interrupt */
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#define INT_WDT_ITI    38     /* WDT Interval timer interval (CPG) */
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#define INT_REF_RCMI   39     /* Compare-match interrupt */
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#define INT_REF_ROVI   40     /* Refresh counter overflow interrupt */
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#define INT_NUM_SOURCES 41
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char *intc_get_interrupt_name( int which );
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void intc_raise_interrupt( int which );
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void intc_clear_interrupt( int which );
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uint32_t intc_accept_interrupt( void );
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void intc_reset( void );
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void intc_mask_changed( void );
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#ifdef __cplusplus
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}
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#endif
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#endif /* !sh4intc_H */
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