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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 561:533f6b478071
prev559:06714bc64271
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
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last change Enable Id keyword on all source files
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/**
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 * $Id$
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 * 
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "mem.h"
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#define OCRAM_START (0x1C000000>>PAGE_BITS)
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#define OCRAM_END   (0x20000000>>PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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	return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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	return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    switch(reg) {
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    case PTEH:
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	val &= 0xFFFFFCFF;
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	break;
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    case PTEL:
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	val &= 0x1FFFFDFF;
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	break;
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    case PTEA:
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	val &= 0x0000000F;
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	break;
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    case MMUCR:
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	if( val & MMUCR_TI ) {
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	    mmu_invalidate_tlb();
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	}
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	mmu_urc = (val >> 10) & 0x3F;
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	mmu_urb = (val >> 18) & 0x3F;
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	mmu_lrui = (val >> 26) & 0x3F;
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	val &= 0x00000301;
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	break;
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    case CCR:
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	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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	break;
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    default:
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	break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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	return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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	return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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        case MEM_OC_INDEX0: /* OIX=0 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
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            break;
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        case MEM_OC_INDEX1: /* OIX=1 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
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            break;
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        default: /* disabled */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = NULL;
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            break;
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    }
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}
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/* TLB maintanence */
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static inline void mmu_flush_pages( struct utlb_entry *ent )
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{
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    unsigned int vpn;
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    switch( ent->flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: xlat_flush_page( ent->vpn ); break;
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    case TLB_SIZE_4K: xlat_flush_page( ent->vpn ); break;
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    case TLB_SIZE_64K: 
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	for( vpn = ent->vpn; vpn < ent->vpn + 0x10000; vpn += 0x1000 ) {
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	    xlat_flush_page( vpn );
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	}
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	break;
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    case TLB_SIZE_1M:
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	for( vpn = ent->vpn; vpn < ent->vpn + 0x100000; vpn += 0x1000 ) {
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	    xlat_flush_page( vpn );
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	}
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	break;
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    }
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}
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/**
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 * The translations are excessively complicated, but unfortunately it's a 
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 * complicated system. It can undoubtedly be better optimized too.
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 */
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/**
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 * Perform the actual utlb lookup.
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 * Possible utcomes are:
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 *   0..63 Single match - good, return entry found
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 *   -1 No match - raise a tlb data miss exception
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 *   -2 Multiple matches - raise a multi-hit exception (reset)
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 * @param vpn virtual address to resolve
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 * @param asid Address space identifier
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 * @param use_asid whether to require an asid match on non-shared pages.
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 * @return the resultant UTLB entry, or an error.
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 */
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static inline int mmu_utlb_lookup_vpn( uint32_t vpn, uint32_t asid, int use_asid )
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{
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    int result = -1;
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    unsigned int i;
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    mmu_urc++;
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    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
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	mmu_urc = 0;
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    }
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    if( use_asid ) {
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	for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
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	    if( (mmu_utlb[i].flags & TLB_VALID) &&
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	        ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
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		((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
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		if( result != -1 ) {
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		    return -2;
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		}
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		result = i;
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	    }
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	}
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    } else {
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	for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
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	    if( (mmu_utlb[i].flags & TLB_VALID) &&
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		((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
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		if( result != -1 ) {
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		    return -2;
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		}
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		result = i;
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	    }
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	}
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   278
    }
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    return result;
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   280
}
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   281
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/**
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 * Find a UTLB entry for the associative TLB write - same as the normal
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 * lookup but ignores the valid bit.
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 */
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static inline mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
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{
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   288
    int result = -1;
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   289
    unsigned int i;
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   290
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
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   291
	if( ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
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   292
	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
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   293
	    if( result != -1 ) {
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   294
		return -2;
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	    }
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   296
	    result = i;
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   297
	}
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   298
    }
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   299
    return result;
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   300
}
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   301
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   302
/**
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 * Perform the actual itlb lookup.
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   304
 * Possible utcomes are:
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   305
 *   0..63 Single match - good, return entry found
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   306
 *   -1 No match - raise a tlb data miss exception
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   307
 *   -2 Multiple matches - raise a multi-hit exception (reset)
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   308
 * @param vpn virtual address to resolve
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   309
 * @param asid Address space identifier
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   310
 * @param use_asid whether to require an asid match on non-shared pages.
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   311
 * @return the resultant ITLB entry, or an error.
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   312
 */
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   313
static inline int mmu_itlb_lookup_vpn( uint32_t vpn, uint32_t asid, int use_asid )
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   314
{
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   315
    int result = -1;
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   316
    unsigned int i;
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   317
    if( use_asid ) {
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   318
	for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
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   319
	    if( (mmu_itlb[i].flags & TLB_VALID) &&
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   320
	        ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
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   321
		((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
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   322
		if( result != -1 ) {
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   323
		    return -2;
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   324
		}
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   325
		result = i;
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   326
	    }
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   327
	}
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   328
    } else {
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   329
	for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
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   330
	    if( (mmu_itlb[i].flags & TLB_VALID) &&
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   331
		((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
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   332
		if( result != -1 ) {
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   333
		    return -2;
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   334
		}
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   335
		result = i;
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   336
	    }
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   337
	}
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   338
    }
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   339
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   340
    switch( result ) {
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   341
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
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   342
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
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   343
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
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   344
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
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   345
    }
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   346
	
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   347
    return result;
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   348
}
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   349
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   350
static int inline mmu_itlb_update_from_utlb( int entryNo )
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   351
{
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   352
    int replace;
nkeynes@559
   353
    /* Determine entry to replace based on lrui */
nkeynes@559
   354
    if( mmu_lrui & 0x38 == 0x38 ) {
nkeynes@559
   355
	replace = 0;
nkeynes@559
   356
	mmu_lrui = mmu_lrui & 0x07;
nkeynes@559
   357
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@559
   358
	replace = 1;
nkeynes@559
   359
	mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@559
   360
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@559
   361
	replace = 2;
nkeynes@559
   362
	mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@559
   363
    } else { // Note - gets invalid entries too
nkeynes@559
   364
	replace = 3;
nkeynes@559
   365
	mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@559
   366
    } 
nkeynes@559
   367
nkeynes@559
   368
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@559
   369
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@559
   370
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@559
   371
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@559
   372
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@559
   373
    return replace;
nkeynes@559
   374
}
nkeynes@559
   375
nkeynes@559
   376
/**
nkeynes@559
   377
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@559
   378
 * lookup but ignores the valid bit.
nkeynes@559
   379
 */
nkeynes@559
   380
static inline mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@559
   381
{
nkeynes@559
   382
    int result = -1;
nkeynes@559
   383
    unsigned int i;
nkeynes@559
   384
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@559
   385
	if( ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
nkeynes@559
   386
	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@559
   387
	    if( result != -1 ) {
nkeynes@559
   388
		return -2;
nkeynes@559
   389
	    }
nkeynes@559
   390
	    result = i;
nkeynes@559
   391
	}
nkeynes@559
   392
    }
nkeynes@559
   393
    return result;
nkeynes@559
   394
}
nkeynes@559
   395
nkeynes@559
   396
#define RAISE_TLB_ERROR(code, vpn) \
nkeynes@559
   397
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@559
   398
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@559
   399
    sh4_raise_tlb_exception(code); \
nkeynes@559
   400
    return (((uint64_t)code)<<32)
nkeynes@559
   401
nkeynes@559
   402
#define RAISE_MEM_ERROR(code, vpn) \
nkeynes@559
   403
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@559
   404
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@559
   405
    sh4_raise_exception(code); \
nkeynes@559
   406
    return (((uint64_t)code)<<32)
nkeynes@559
   407
nkeynes@559
   408
#define RAISE_OTHER_ERROR(code) \
nkeynes@559
   409
    sh4_raise_exception(code); \
nkeynes@559
   410
    return (((uint64_t)EXV_EXCEPTION)<<32)
nkeynes@559
   411
nkeynes@559
   412
/**
nkeynes@559
   413
 * Abort with a non-MMU address error. Caused by user-mode code attempting
nkeynes@559
   414
 * to access privileged regions, or alignment faults.
nkeynes@559
   415
 */
nkeynes@559
   416
#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
nkeynes@559
   417
#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
nkeynes@559
   418
nkeynes@559
   419
#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
nkeynes@559
   420
#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
nkeynes@559
   421
#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
nkeynes@559
   422
#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
nkeynes@559
   423
#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
nkeynes@559
   424
#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
nkeynes@559
   425
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@559
   426
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@559
   427
    return (((uint64_t)EXC_TLB_MULTI_HIT)<<32)
nkeynes@559
   428
nkeynes@559
   429
uint64_t mmu_vma_to_phys_write( sh4addr_t addr )
nkeynes@559
   430
{
nkeynes@559
   431
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@559
   432
    if( addr & 0x80000000 ) {
nkeynes@559
   433
	if( IS_SH4_PRIVMODE() ) {
nkeynes@559
   434
	    if( addr < 0xC0000000 || addr >= 0xE0000000 ) {
nkeynes@559
   435
		/* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@559
   436
		return (uint64_t)addr;
nkeynes@559
   437
	    }
nkeynes@559
   438
	} else {
nkeynes@559
   439
	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@559
   440
		((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@559
   441
		/* Conditional user-mode access to the store-queue (no translation) */
nkeynes@559
   442
		return (uint64_t)addr;
nkeynes@559
   443
	    }
nkeynes@559
   444
	    MMU_WRITE_ADDR_ERROR();
nkeynes@559
   445
	}
nkeynes@559
   446
    }
nkeynes@559
   447
    
nkeynes@559
   448
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@559
   449
	return (uint64_t)addr;
nkeynes@559
   450
    }
nkeynes@559
   451
nkeynes@559
   452
    /* If we get this far, translation is required */
nkeynes@559
   453
nkeynes@559
   454
    int use_asid = ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE();
nkeynes@559
   455
    uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
nkeynes@559
   456
    
nkeynes@559
   457
    int entryNo = mmu_utlb_lookup_vpn( addr, asid, use_asid );
nkeynes@559
   458
nkeynes@559
   459
    switch(entryNo) {
nkeynes@559
   460
    case -1:
nkeynes@559
   461
	MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@559
   462
	break;
nkeynes@559
   463
    case -2:
nkeynes@559
   464
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@559
   465
	break;
nkeynes@559
   466
    default:
nkeynes@559
   467
	if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@559
   468
	    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@559
   469
	    /* protection violation */
nkeynes@559
   470
	    MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@559
   471
	}
nkeynes@559
   472
nkeynes@559
   473
	if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@559
   474
	    MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@559
   475
	}
nkeynes@559
   476
nkeynes@559
   477
	/* finally generate the target address */
nkeynes@559
   478
	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@559
   479
	    (addr & (~mmu_utlb[entryNo].mask));
nkeynes@559
   480
    }
nkeynes@559
   481
    return -1;
nkeynes@559
   482
nkeynes@559
   483
}
nkeynes@559
   484
nkeynes@559
   485
uint64_t mmu_vma_to_phys_exec( sh4addr_t addr )
nkeynes@559
   486
{
nkeynes@559
   487
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@559
   488
    if( addr & 0x80000000 ) {
nkeynes@559
   489
	if( IS_SH4_PRIVMODE()  ) {
nkeynes@559
   490
	    if( addr < 0xC0000000 ) {
nkeynes@559
   491
		/* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@559
   492
		return (uint64_t)addr;
nkeynes@559
   493
	    } else if( addr >= 0xE0000000 ) {
nkeynes@559
   494
		MMU_READ_ADDR_ERROR();
nkeynes@559
   495
	    }
nkeynes@559
   496
	} else {
nkeynes@559
   497
	    MMU_READ_ADDR_ERROR();
nkeynes@559
   498
	}
nkeynes@559
   499
    }
nkeynes@559
   500
    
nkeynes@559
   501
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@559
   502
	return (uint64_t)addr;
nkeynes@559
   503
    }
nkeynes@559
   504
nkeynes@559
   505
    /* If we get this far, translation is required */
nkeynes@559
   506
    int use_asid = ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE();
nkeynes@559
   507
    uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
nkeynes@559
   508
    
nkeynes@559
   509
    int entryNo = mmu_itlb_lookup_vpn( addr, asid, use_asid );
nkeynes@559
   510
    if( entryNo == -1 ) {
nkeynes@559
   511
	entryNo = mmu_utlb_lookup_vpn( addr, asid, use_asid );
nkeynes@559
   512
	if( entryNo >= 0 ) {
nkeynes@559
   513
	    entryNo = mmu_itlb_update_from_utlb( entryNo );
nkeynes@559
   514
	}
nkeynes@559
   515
    }
nkeynes@559
   516
    switch(entryNo) {
nkeynes@559
   517
    case -1:
nkeynes@559
   518
	MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@559
   519
	break;
nkeynes@559
   520
    case -2:
nkeynes@559
   521
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@559
   522
	break;
nkeynes@559
   523
    default:
nkeynes@559
   524
	if( (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@559
   525
	    !IS_SH4_PRIVMODE() ) {
nkeynes@559
   526
	    /* protection violation */
nkeynes@559
   527
	    MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@559
   528
	}
nkeynes@559
   529
nkeynes@559
   530
	/* finally generate the target address */
nkeynes@559
   531
	return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) | 
nkeynes@559
   532
	    (addr & (~mmu_itlb[entryNo].mask));
nkeynes@559
   533
    }
nkeynes@559
   534
    return -1;
nkeynes@559
   535
}
nkeynes@559
   536
nkeynes@559
   537
uint64_t mmu_vma_to_phys_read_noexc( sh4addr_t addr ) {
nkeynes@559
   538
nkeynes@559
   539
nkeynes@559
   540
}
nkeynes@559
   541
nkeynes@559
   542
nkeynes@559
   543
uint64_t mmu_vma_to_phys_read( sh4addr_t addr )
nkeynes@559
   544
{
nkeynes@559
   545
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@559
   546
    if( addr & 0x80000000 ) {
nkeynes@559
   547
	if( IS_SH4_PRIVMODE() ) {
nkeynes@559
   548
	    if( addr < 0xC0000000 || addr >= 0xE0000000 ) {
nkeynes@559
   549
		/* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@559
   550
		return (uint64_t)addr;
nkeynes@559
   551
	    }
nkeynes@559
   552
	} else {
nkeynes@559
   553
	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@559
   554
		((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@559
   555
		/* Conditional user-mode access to the store-queue (no translation) */
nkeynes@559
   556
		return (uint64_t)addr;
nkeynes@559
   557
	    }
nkeynes@559
   558
	    MMU_READ_ADDR_ERROR();
nkeynes@559
   559
	}
nkeynes@559
   560
    }
nkeynes@559
   561
    
nkeynes@559
   562
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@559
   563
	return (uint64_t)addr;
nkeynes@559
   564
    }
nkeynes@559
   565
nkeynes@559
   566
    /* If we get this far, translation is required */
nkeynes@559
   567
nkeynes@559
   568
    int use_asid = ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE();
nkeynes@559
   569
    uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
nkeynes@559
   570
    
nkeynes@559
   571
    int entryNo = mmu_utlb_lookup_vpn( addr, asid, use_asid );
nkeynes@559
   572
nkeynes@559
   573
    switch(entryNo) {
nkeynes@559
   574
    case -1:
nkeynes@559
   575
	MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@559
   576
	break;
nkeynes@559
   577
    case -2:
nkeynes@559
   578
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@559
   579
	break;
nkeynes@559
   580
    default:
nkeynes@559
   581
	if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@559
   582
	    !IS_SH4_PRIVMODE() ) {
nkeynes@559
   583
	    /* protection violation */
nkeynes@559
   584
	    MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@559
   585
	}
nkeynes@559
   586
nkeynes@559
   587
	/* finally generate the target address */
nkeynes@559
   588
	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@559
   589
	    (addr & (~mmu_utlb[entryNo].mask));
nkeynes@559
   590
    }
nkeynes@559
   591
    return -1;
nkeynes@550
   592
}
nkeynes@550
   593
nkeynes@550
   594
static void mmu_invalidate_tlb()
nkeynes@550
   595
{
nkeynes@550
   596
    int i;
nkeynes@550
   597
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@550
   598
	mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   599
    }
nkeynes@550
   600
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@550
   601
	mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   602
    }
nkeynes@550
   603
}
nkeynes@550
   604
nkeynes@550
   605
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@550
   606
nkeynes@550
   607
int32_t mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@550
   608
{
nkeynes@550
   609
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   610
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@550
   611
}
nkeynes@550
   612
int32_t mmu_itlb_data_read( sh4addr_t addr )
nkeynes@550
   613
{
nkeynes@550
   614
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   615
    return ent->ppn | ent->flags;
nkeynes@550
   616
}
nkeynes@550
   617
nkeynes@550
   618
void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   619
{
nkeynes@550
   620
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   621
    ent->vpn = val & 0xFFFFFC00;
nkeynes@550
   622
    ent->asid = val & 0x000000FF;
nkeynes@550
   623
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@550
   624
}
nkeynes@550
   625
nkeynes@550
   626
void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   627
{
nkeynes@550
   628
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   629
    ent->ppn = val & 0x1FFFFC00;
nkeynes@550
   630
    ent->flags = val & 0x00001DA;
nkeynes@559
   631
    ent->mask = get_mask_for_flags(val);
nkeynes@550
   632
}
nkeynes@550
   633
nkeynes@550
   634
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@550
   635
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@550
   636
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@550
   637
nkeynes@550
   638
int32_t mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@550
   639
{
nkeynes@550
   640
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   641
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@550
   642
	((ent->flags & TLB_DIRTY)<<7);
nkeynes@550
   643
}
nkeynes@550
   644
int32_t mmu_utlb_data_read( sh4addr_t addr )
nkeynes@550
   645
{
nkeynes@550
   646
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   647
    if( UTLB_DATA2(addr) ) {
nkeynes@550
   648
	return ent->pcmcia;
nkeynes@550
   649
    } else {
nkeynes@550
   650
	return ent->ppn | ent->flags;
nkeynes@550
   651
    }
nkeynes@550
   652
}
nkeynes@550
   653
nkeynes@550
   654
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   655
{
nkeynes@550
   656
    if( UTLB_ASSOC(addr) ) {
nkeynes@559
   657
	uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
nkeynes@559
   658
	int entryNo = mmu_utlb_lookup_assoc( val, asid );
nkeynes@559
   659
	if( entryNo >= 0 ) {
nkeynes@559
   660
	    struct utlb_entry *ent = &mmu_utlb[entryNo];
nkeynes@559
   661
	    ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@559
   662
	    ent->flags |= (val & TLB_VALID);
nkeynes@559
   663
	    ent->flags |= ((val & 0x200)>>7);
nkeynes@559
   664
	} else if( entryNo == -2 ) {
nkeynes@559
   665
	    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@559
   666
	}
nkeynes@550
   667
    } else {
nkeynes@550
   668
	struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   669
	ent->vpn = (val & 0xFFFFFC00);
nkeynes@550
   670
	ent->asid = (val & 0xFF);
nkeynes@550
   671
	ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@550
   672
	ent->flags |= (val & TLB_VALID);
nkeynes@550
   673
	ent->flags |= ((val & 0x200)>>7);
nkeynes@550
   674
    }
nkeynes@550
   675
}
nkeynes@550
   676
nkeynes@550
   677
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   678
{
nkeynes@550
   679
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   680
    if( UTLB_DATA2(addr) ) {
nkeynes@550
   681
	ent->pcmcia = val & 0x0000000F;
nkeynes@550
   682
    } else {
nkeynes@550
   683
	ent->ppn = (val & 0x1FFFFC00);
nkeynes@550
   684
	ent->flags = (val & 0x000001FF);
nkeynes@559
   685
	ent->mask = get_mask_for_flags(val);
nkeynes@550
   686
    }
nkeynes@550
   687
}
nkeynes@550
   688
nkeynes@550
   689
/* Cache access - not implemented */
nkeynes@550
   690
nkeynes@550
   691
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   692
{
nkeynes@550
   693
    return 0; // not implemented
nkeynes@550
   694
}
nkeynes@550
   695
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   696
{
nkeynes@550
   697
    return 0; // not implemented
nkeynes@550
   698
}
nkeynes@550
   699
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   700
{
nkeynes@550
   701
    return 0; // not implemented
nkeynes@550
   702
}
nkeynes@550
   703
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   704
{
nkeynes@550
   705
    return 0; // not implemented
nkeynes@550
   706
}
nkeynes@550
   707
nkeynes@550
   708
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   709
{
nkeynes@550
   710
}
nkeynes@550
   711
nkeynes@550
   712
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   713
{
nkeynes@550
   714
}
nkeynes@550
   715
nkeynes@550
   716
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   717
{
nkeynes@550
   718
}
nkeynes@550
   719
nkeynes@550
   720
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   721
{
nkeynes@550
   722
}
.