Search
lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.c
changeset 561:533f6b478071
prev559:06714bc64271
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@561
     2
 * $Id$
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359
    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359
    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@368
    21
#include <assert.h>
nkeynes@388
    22
#include <math.h>
nkeynes@368
    23
nkeynes@380
    24
#ifndef NDEBUG
nkeynes@380
    25
#define DEBUG_JUMPS 1
nkeynes@380
    26
#endif
nkeynes@380
    27
nkeynes@417
    28
#include "sh4/xltcache.h"
nkeynes@368
    29
#include "sh4/sh4core.h"
nkeynes@368
    30
#include "sh4/sh4trans.h"
nkeynes@388
    31
#include "sh4/sh4mmio.h"
nkeynes@368
    32
#include "sh4/x86op.h"
nkeynes@368
    33
#include "clock.h"
nkeynes@368
    34
nkeynes@368
    35
#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368
    36
nkeynes@559
    37
struct backpatch_record {
nkeynes@559
    38
    uint32_t *fixup_addr;
nkeynes@559
    39
    uint32_t fixup_icount;
nkeynes@559
    40
    uint32_t exc_code;
nkeynes@559
    41
};
nkeynes@559
    42
nkeynes@368
    43
/** 
nkeynes@368
    44
 * Struct to manage internal translation state. This state is not saved -
nkeynes@368
    45
 * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368
    46
 * sh4_translate_end_block()
nkeynes@368
    47
 */
nkeynes@368
    48
struct sh4_x86_state {
nkeynes@368
    49
    gboolean in_delay_slot;
nkeynes@368
    50
    gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368
    51
    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409
    52
    gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@408
    53
    uint32_t block_start_pc;
nkeynes@547
    54
    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
nkeynes@417
    55
    int tstate;
nkeynes@368
    56
nkeynes@368
    57
    /* Allocated memory for the (block-wide) back-patch list */
nkeynes@559
    58
    struct backpatch_record *backpatch_list;
nkeynes@368
    59
    uint32_t backpatch_posn;
nkeynes@368
    60
    uint32_t backpatch_size;
nkeynes@368
    61
};
nkeynes@368
    62
nkeynes@417
    63
#define TSTATE_NONE -1
nkeynes@417
    64
#define TSTATE_O    0
nkeynes@417
    65
#define TSTATE_C    2
nkeynes@417
    66
#define TSTATE_E    4
nkeynes@417
    67
#define TSTATE_NE   5
nkeynes@417
    68
#define TSTATE_G    0xF
nkeynes@417
    69
#define TSTATE_GE   0xD
nkeynes@417
    70
#define TSTATE_A    7
nkeynes@417
    71
#define TSTATE_AE   3
nkeynes@417
    72
nkeynes@417
    73
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@417
    74
#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    75
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    76
    OP(0x70+sh4_x86.tstate); OP(rel8); \
nkeynes@417
    77
    MARK_JMP(rel8,label)
nkeynes@417
    78
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@417
    79
#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    80
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    81
    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
nkeynes@417
    82
    MARK_JMP(rel8, label)
nkeynes@417
    83
nkeynes@368
    84
static struct sh4_x86_state sh4_x86;
nkeynes@368
    85
nkeynes@388
    86
static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388
    87
static uint32_t min_int = 0x80000000;
nkeynes@394
    88
static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394
    89
static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386
    90
nkeynes@368
    91
void sh4_x86_init()
nkeynes@368
    92
{
nkeynes@368
    93
    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@559
    94
    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@368
    95
}
nkeynes@368
    96
nkeynes@368
    97
nkeynes@559
    98
static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368
    99
{
nkeynes@368
   100
    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368
   101
	sh4_x86.backpatch_size <<= 1;
nkeynes@559
   102
	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
nkeynes@559
   103
					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368
   104
	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368
   105
    }
nkeynes@559
   106
    if( sh4_x86.in_delay_slot ) {
nkeynes@559
   107
	fixup_pc -= 2;
nkeynes@368
   108
    }
nkeynes@559
   109
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
nkeynes@559
   110
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@559
   111
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@559
   112
    sh4_x86.backpatch_posn++;
nkeynes@368
   113
}
nkeynes@368
   114
nkeynes@359
   115
/**
nkeynes@359
   116
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
   117
 */
nkeynes@359
   118
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
   119
{
nkeynes@359
   120
    /* mov [bp+n], reg */
nkeynes@361
   121
    OP(0x8B);
nkeynes@361
   122
    OP(0x45 + (x86reg<<3));
nkeynes@359
   123
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   124
}
nkeynes@359
   125
nkeynes@374
   126
static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368
   127
{
nkeynes@374
   128
    OP(0x0F);
nkeynes@374
   129
    OP(0xBF);
nkeynes@374
   130
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368
   131
}
nkeynes@368
   132
nkeynes@374
   133
static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368
   134
{
nkeynes@374
   135
    OP(0x0F);
nkeynes@374
   136
    OP(0xB7);
nkeynes@374
   137
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374
   138
nkeynes@368
   139
}
nkeynes@368
   140
nkeynes@380
   141
#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380
   142
#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359
   143
/**
nkeynes@359
   144
 * Emit an instruction to load an immediate value into a register
nkeynes@359
   145
 */
nkeynes@359
   146
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
   147
    /* mov #value, reg */
nkeynes@359
   148
    OP(0xB8 + x86reg);
nkeynes@359
   149
    OP32(value);
nkeynes@359
   150
}
nkeynes@359
   151
nkeynes@359
   152
/**
nkeynes@527
   153
 * Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527
   154
 */
nkeynes@527
   155
static inline void load_imm64( int x86reg, uint32_t value ) {
nkeynes@527
   156
    /* mov #value, reg */
nkeynes@527
   157
    REXW();
nkeynes@527
   158
    OP(0xB8 + x86reg);
nkeynes@527
   159
    OP64(value);
nkeynes@527
   160
}
nkeynes@527
   161
nkeynes@527
   162
nkeynes@527
   163
/**
nkeynes@359
   164
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
   165
 */
nkeynes@359
   166
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
   167
    /* mov reg, [bp+n] */
nkeynes@361
   168
    OP(0x89);
nkeynes@361
   169
    OP(0x45 + (x86reg<<3));
nkeynes@359
   170
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   171
}
nkeynes@374
   172
nkeynes@374
   173
#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374
   174
nkeynes@375
   175
/**
nkeynes@375
   176
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   177
 * register (eg for register-to-register moves)
nkeynes@375
   178
 */
nkeynes@375
   179
void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375
   180
{
nkeynes@375
   181
    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375
   182
}
nkeynes@375
   183
nkeynes@375
   184
/**
nkeynes@375
   185
 * Store an FR register (single-precision floating point) into an integer x86
nkeynes@375
   186
 * register (eg for register-to-register moves)
nkeynes@375
   187
 */
nkeynes@375
   188
void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375
   189
{
nkeynes@375
   190
    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375
   191
}
nkeynes@375
   192
nkeynes@375
   193
nkeynes@375
   194
/**
nkeynes@375
   195
 * Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375
   196
 * bankreg must have been previously loaded with FPSCR.
nkeynes@388
   197
 * NB: 12 bytes
nkeynes@375
   198
 */
nkeynes@374
   199
static inline void load_xf_bank( int bankreg )
nkeynes@374
   200
{
nkeynes@386
   201
    NOT_r32( bankreg );
nkeynes@374
   202
    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374
   203
    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
nkeynes@374
   204
    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374
   205
}
nkeynes@374
   206
nkeynes@375
   207
/**
nkeynes@386
   208
 * Update the fr_bank pointer based on the current fpscr value.
nkeynes@386
   209
 */
nkeynes@386
   210
static inline void update_fr_bank( int fpscrreg )
nkeynes@386
   211
{
nkeynes@386
   212
    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386
   213
    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
nkeynes@386
   214
    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386
   215
    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386
   216
}
nkeynes@386
   217
/**
nkeynes@377
   218
 * Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377
   219
 */
nkeynes@377
   220
static inline void push_fpul( )
nkeynes@377
   221
{
nkeynes@377
   222
    OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377
   223
}
nkeynes@377
   224
nkeynes@377
   225
/**
nkeynes@377
   226
 * Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377
   227
 */
nkeynes@377
   228
static inline void pop_fpul( )
nkeynes@377
   229
{
nkeynes@377
   230
    OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377
   231
}
nkeynes@377
   232
nkeynes@377
   233
/**
nkeynes@375
   234
 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375
   235
 * with the location of the current fp bank.
nkeynes@375
   236
 */
nkeynes@374
   237
static inline void push_fr( int bankreg, int frm ) 
nkeynes@374
   238
{
nkeynes@374
   239
    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
nkeynes@374
   240
}
nkeynes@374
   241
nkeynes@375
   242
/**
nkeynes@375
   243
 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
nkeynes@375
   244
 * with bankreg previously loaded with the location of the current fp bank.
nkeynes@375
   245
 */
nkeynes@374
   246
static inline void pop_fr( int bankreg, int frm )
nkeynes@374
   247
{
nkeynes@374
   248
    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374
   249
}
nkeynes@374
   250
nkeynes@375
   251
/**
nkeynes@375
   252
 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375
   253
 * with the location of the current fp bank.
nkeynes@375
   254
 */
nkeynes@374
   255
static inline void push_dr( int bankreg, int frm )
nkeynes@374
   256
{
nkeynes@377
   257
    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374
   258
}
nkeynes@374
   259
nkeynes@374
   260
static inline void pop_dr( int bankreg, int frm )
nkeynes@374
   261
{
nkeynes@377
   262
    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374
   263
}
nkeynes@374
   264
nkeynes@368
   265
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   266
nkeynes@416
   267
#define check_priv( ) \
nkeynes@416
   268
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   269
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   270
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   271
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   272
	if( sh4_x86.in_delay_slot ) {\
nkeynes@559
   273
	    JE_exc( EXC_SLOT_ILLEGAL );\
nkeynes@416
   274
	} else {\
nkeynes@559
   275
	    JE_exc( EXC_ILLEGAL );\
nkeynes@416
   276
	}\
nkeynes@416
   277
    }\
nkeynes@416
   278
nkeynes@416
   279
#define check_fpuen( ) \
nkeynes@416
   280
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   281
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   282
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   283
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   284
	if( sh4_x86.in_delay_slot ) {\
nkeynes@559
   285
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   286
	} else {\
nkeynes@559
   287
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   288
	}\
nkeynes@416
   289
    }
nkeynes@416
   290
nkeynes@559
   291
#define check_ralign16( x86reg ) \
nkeynes@559
   292
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@559
   293
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   294
nkeynes@559
   295
#define check_walign16( x86reg ) \
nkeynes@559
   296
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@559
   297
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   298
nkeynes@559
   299
#define check_ralign32( x86reg ) \
nkeynes@559
   300
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@559
   301
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   302
nkeynes@559
   303
#define check_walign32( x86reg ) \
nkeynes@559
   304
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@559
   305
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   306
nkeynes@361
   307
#define UNDEF()
nkeynes@361
   308
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@559
   309
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
nkeynes@559
   310
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
nkeynes@559
   311
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
nkeynes@559
   312
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
nkeynes@559
   313
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
nkeynes@559
   314
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
nkeynes@361
   315
nkeynes@559
   316
#define MEM_READ_SIZE  (CALL_FUNC1_SIZE+8)
nkeynes@559
   317
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE+8)
nkeynes@559
   318
nkeynes@559
   319
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   320
nkeynes@388
   321
extern uint16_t *sh4_icache;
nkeynes@388
   322
extern uint32_t sh4_icache_addr;
nkeynes@388
   323
nkeynes@539
   324
/****** Import appropriate calling conventions ******/
nkeynes@539
   325
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   326
#include "sh4/ia64abi.h"
nkeynes@539
   327
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   328
#ifdef APPLE_BUILD
nkeynes@539
   329
#include "sh4/ia32mac.h"
nkeynes@539
   330
#else
nkeynes@539
   331
#include "sh4/ia32abi.h"
nkeynes@539
   332
#endif
nkeynes@539
   333
#endif
nkeynes@539
   334
nkeynes@539
   335
nkeynes@359
   336
/**
nkeynes@359
   337
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   338
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   339
 * 
nkeynes@359
   340
 *
nkeynes@359
   341
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   342
 * (eg a branch or 
nkeynes@359
   343
 */
nkeynes@526
   344
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   345
{
nkeynes@388
   346
    uint32_t ir;
nkeynes@388
   347
    /* Read instruction */
nkeynes@388
   348
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   349
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   350
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   351
    } else {
nkeynes@559
   352
	uint64_t phys = mmu_vma_to_phys_exec(pc);
nkeynes@559
   353
	sh4_icache = (uint16_t *)mem_get_page((uint32_t)phys);
nkeynes@527
   354
	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   355
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   356
	     * region, fallback on the full-blown memory read
nkeynes@388
   357
	     */
nkeynes@388
   358
	    sh4_icache = NULL;
nkeynes@388
   359
	    ir = sh4_read_word(pc);
nkeynes@388
   360
	} else {
nkeynes@388
   361
	    sh4_icache_addr = pageaddr;
nkeynes@388
   362
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   363
	}
nkeynes@388
   364
    }
nkeynes@388
   365
nkeynes@359
   366
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   367
            case 0x0:
nkeynes@359
   368
                switch( ir&0xF ) {
nkeynes@359
   369
                    case 0x2:
nkeynes@359
   370
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   371
                            case 0x0:
nkeynes@359
   372
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   373
                                    case 0x0:
nkeynes@359
   374
                                        { /* STC SR, Rn */
nkeynes@359
   375
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   376
                                        check_priv();
nkeynes@374
   377
                                        call_func0(sh4_read_sr);
nkeynes@368
   378
                                        store_reg( R_EAX, Rn );
nkeynes@417
   379
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   380
                                        }
nkeynes@359
   381
                                        break;
nkeynes@359
   382
                                    case 0x1:
nkeynes@359
   383
                                        { /* STC GBR, Rn */
nkeynes@359
   384
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   385
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   386
                                        store_reg( R_EAX, Rn );
nkeynes@359
   387
                                        }
nkeynes@359
   388
                                        break;
nkeynes@359
   389
                                    case 0x2:
nkeynes@359
   390
                                        { /* STC VBR, Rn */
nkeynes@359
   391
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   392
                                        check_priv();
nkeynes@359
   393
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   394
                                        store_reg( R_EAX, Rn );
nkeynes@417
   395
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   396
                                        }
nkeynes@359
   397
                                        break;
nkeynes@359
   398
                                    case 0x3:
nkeynes@359
   399
                                        { /* STC SSR, Rn */
nkeynes@359
   400
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   401
                                        check_priv();
nkeynes@359
   402
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   403
                                        store_reg( R_EAX, Rn );
nkeynes@417
   404
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   405
                                        }
nkeynes@359
   406
                                        break;
nkeynes@359
   407
                                    case 0x4:
nkeynes@359
   408
                                        { /* STC SPC, Rn */
nkeynes@359
   409
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   410
                                        check_priv();
nkeynes@359
   411
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   412
                                        store_reg( R_EAX, Rn );
nkeynes@417
   413
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   414
                                        }
nkeynes@359
   415
                                        break;
nkeynes@359
   416
                                    default:
nkeynes@359
   417
                                        UNDEF();
nkeynes@359
   418
                                        break;
nkeynes@359
   419
                                }
nkeynes@359
   420
                                break;
nkeynes@359
   421
                            case 0x1:
nkeynes@359
   422
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   423
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   424
                                check_priv();
nkeynes@374
   425
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   426
                                store_reg( R_EAX, Rn );
nkeynes@417
   427
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   428
                                }
nkeynes@359
   429
                                break;
nkeynes@359
   430
                        }
nkeynes@359
   431
                        break;
nkeynes@359
   432
                    case 0x3:
nkeynes@359
   433
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   434
                            case 0x0:
nkeynes@359
   435
                                { /* BSRF Rn */
nkeynes@359
   436
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   437
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   438
                            	SLOTILLEGAL();
nkeynes@374
   439
                                } else {
nkeynes@408
   440
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   441
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   442
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   443
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   444
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   445
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   446
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   447
                            	exit_block_pcset(pc+2);
nkeynes@409
   448
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   449
                            	return 4;
nkeynes@374
   450
                                }
nkeynes@359
   451
                                }
nkeynes@359
   452
                                break;
nkeynes@359
   453
                            case 0x2:
nkeynes@359
   454
                                { /* BRAF Rn */
nkeynes@359
   455
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   456
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   457
                            	SLOTILLEGAL();
nkeynes@374
   458
                                } else {
nkeynes@408
   459
                            	load_reg( R_EAX, Rn );
nkeynes@408
   460
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   461
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   462
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   463
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   464
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   465
                            	exit_block_pcset(pc+2);
nkeynes@409
   466
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   467
                            	return 4;
nkeynes@374
   468
                                }
nkeynes@359
   469
                                }
nkeynes@359
   470
                                break;
nkeynes@359
   471
                            case 0x8:
nkeynes@359
   472
                                { /* PREF @Rn */
nkeynes@359
   473
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   474
                                load_reg( R_EAX, Rn );
nkeynes@532
   475
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   476
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   477
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
   478
                                JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
   479
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
   480
                                JMP_TARGET(end);
nkeynes@417
   481
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   482
                                }
nkeynes@359
   483
                                break;
nkeynes@359
   484
                            case 0x9:
nkeynes@359
   485
                                { /* OCBI @Rn */
nkeynes@359
   486
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   487
                                }
nkeynes@359
   488
                                break;
nkeynes@359
   489
                            case 0xA:
nkeynes@359
   490
                                { /* OCBP @Rn */
nkeynes@359
   491
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   492
                                }
nkeynes@359
   493
                                break;
nkeynes@359
   494
                            case 0xB:
nkeynes@359
   495
                                { /* OCBWB @Rn */
nkeynes@359
   496
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   497
                                }
nkeynes@359
   498
                                break;
nkeynes@359
   499
                            case 0xC:
nkeynes@359
   500
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   501
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   502
                                load_reg( R_EAX, 0 );
nkeynes@361
   503
                                load_reg( R_ECX, Rn );
nkeynes@374
   504
                                check_walign32( R_ECX );
nkeynes@361
   505
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   506
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   507
                                }
nkeynes@359
   508
                                break;
nkeynes@359
   509
                            default:
nkeynes@359
   510
                                UNDEF();
nkeynes@359
   511
                                break;
nkeynes@359
   512
                        }
nkeynes@359
   513
                        break;
nkeynes@359
   514
                    case 0x4:
nkeynes@359
   515
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   516
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   517
                        load_reg( R_EAX, 0 );
nkeynes@359
   518
                        load_reg( R_ECX, Rn );
nkeynes@359
   519
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   520
                        load_reg( R_EAX, Rm );
nkeynes@359
   521
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   522
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   523
                        }
nkeynes@359
   524
                        break;
nkeynes@359
   525
                    case 0x5:
nkeynes@359
   526
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   527
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   528
                        load_reg( R_EAX, 0 );
nkeynes@361
   529
                        load_reg( R_ECX, Rn );
nkeynes@361
   530
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   531
                        check_walign16( R_ECX );
nkeynes@361
   532
                        load_reg( R_EAX, Rm );
nkeynes@361
   533
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   534
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   535
                        }
nkeynes@359
   536
                        break;
nkeynes@359
   537
                    case 0x6:
nkeynes@359
   538
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   539
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   540
                        load_reg( R_EAX, 0 );
nkeynes@361
   541
                        load_reg( R_ECX, Rn );
nkeynes@361
   542
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   543
                        check_walign32( R_ECX );
nkeynes@361
   544
                        load_reg( R_EAX, Rm );
nkeynes@361
   545
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   546
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   547
                        }
nkeynes@359
   548
                        break;
nkeynes@359
   549
                    case 0x7:
nkeynes@359
   550
                        { /* MUL.L Rm, Rn */
nkeynes@359
   551
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   552
                        load_reg( R_EAX, Rm );
nkeynes@361
   553
                        load_reg( R_ECX, Rn );
nkeynes@361
   554
                        MUL_r32( R_ECX );
nkeynes@361
   555
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   556
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   557
                        }
nkeynes@359
   558
                        break;
nkeynes@359
   559
                    case 0x8:
nkeynes@359
   560
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   561
                            case 0x0:
nkeynes@359
   562
                                { /* CLRT */
nkeynes@374
   563
                                CLC();
nkeynes@374
   564
                                SETC_t();
nkeynes@417
   565
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   566
                                }
nkeynes@359
   567
                                break;
nkeynes@359
   568
                            case 0x1:
nkeynes@359
   569
                                { /* SETT */
nkeynes@374
   570
                                STC();
nkeynes@374
   571
                                SETC_t();
nkeynes@417
   572
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   573
                                }
nkeynes@359
   574
                                break;
nkeynes@359
   575
                            case 0x2:
nkeynes@359
   576
                                { /* CLRMAC */
nkeynes@374
   577
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   578
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   579
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   580
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   581
                                }
nkeynes@359
   582
                                break;
nkeynes@359
   583
                            case 0x3:
nkeynes@359
   584
                                { /* LDTLB */
nkeynes@553
   585
                                call_func0( MMU_ldtlb );
nkeynes@359
   586
                                }
nkeynes@359
   587
                                break;
nkeynes@359
   588
                            case 0x4:
nkeynes@359
   589
                                { /* CLRS */
nkeynes@374
   590
                                CLC();
nkeynes@374
   591
                                SETC_sh4r(R_S);
nkeynes@417
   592
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   593
                                }
nkeynes@359
   594
                                break;
nkeynes@359
   595
                            case 0x5:
nkeynes@359
   596
                                { /* SETS */
nkeynes@374
   597
                                STC();
nkeynes@374
   598
                                SETC_sh4r(R_S);
nkeynes@417
   599
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   600
                                }
nkeynes@359
   601
                                break;
nkeynes@359
   602
                            default:
nkeynes@359
   603
                                UNDEF();
nkeynes@359
   604
                                break;
nkeynes@359
   605
                        }
nkeynes@359
   606
                        break;
nkeynes@359
   607
                    case 0x9:
nkeynes@359
   608
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   609
                            case 0x0:
nkeynes@359
   610
                                { /* NOP */
nkeynes@359
   611
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   612
                                }
nkeynes@359
   613
                                break;
nkeynes@359
   614
                            case 0x1:
nkeynes@359
   615
                                { /* DIV0U */
nkeynes@361
   616
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   617
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   618
                                store_spreg( R_EAX, R_M );
nkeynes@361
   619
                                store_spreg( R_EAX, R_T );
nkeynes@417
   620
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   621
                                }
nkeynes@359
   622
                                break;
nkeynes@359
   623
                            case 0x2:
nkeynes@359
   624
                                { /* MOVT Rn */
nkeynes@359
   625
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   626
                                load_spreg( R_EAX, R_T );
nkeynes@359
   627
                                store_reg( R_EAX, Rn );
nkeynes@359
   628
                                }
nkeynes@359
   629
                                break;
nkeynes@359
   630
                            default:
nkeynes@359
   631
                                UNDEF();
nkeynes@359
   632
                                break;
nkeynes@359
   633
                        }
nkeynes@359
   634
                        break;
nkeynes@359
   635
                    case 0xA:
nkeynes@359
   636
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   637
                            case 0x0:
nkeynes@359
   638
                                { /* STS MACH, Rn */
nkeynes@359
   639
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   640
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   641
                                store_reg( R_EAX, Rn );
nkeynes@359
   642
                                }
nkeynes@359
   643
                                break;
nkeynes@359
   644
                            case 0x1:
nkeynes@359
   645
                                { /* STS MACL, Rn */
nkeynes@359
   646
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   647
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   648
                                store_reg( R_EAX, Rn );
nkeynes@359
   649
                                }
nkeynes@359
   650
                                break;
nkeynes@359
   651
                            case 0x2:
nkeynes@359
   652
                                { /* STS PR, Rn */
nkeynes@359
   653
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   654
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   655
                                store_reg( R_EAX, Rn );
nkeynes@359
   656
                                }
nkeynes@359
   657
                                break;
nkeynes@359
   658
                            case 0x3:
nkeynes@359
   659
                                { /* STC SGR, Rn */
nkeynes@359
   660
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   661
                                check_priv();
nkeynes@359
   662
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   663
                                store_reg( R_EAX, Rn );
nkeynes@417
   664
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   665
                                }
nkeynes@359
   666
                                break;
nkeynes@359
   667
                            case 0x5:
nkeynes@359
   668
                                { /* STS FPUL, Rn */
nkeynes@359
   669
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   670
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   671
                                store_reg( R_EAX, Rn );
nkeynes@359
   672
                                }
nkeynes@359
   673
                                break;
nkeynes@359
   674
                            case 0x6:
nkeynes@359
   675
                                { /* STS FPSCR, Rn */
nkeynes@359
   676
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   677
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   678
                                store_reg( R_EAX, Rn );
nkeynes@359
   679
                                }
nkeynes@359
   680
                                break;
nkeynes@359
   681
                            case 0xF:
nkeynes@359
   682
                                { /* STC DBR, Rn */
nkeynes@359
   683
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   684
                                check_priv();
nkeynes@359
   685
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   686
                                store_reg( R_EAX, Rn );
nkeynes@417
   687
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   688
                                }
nkeynes@359
   689
                                break;
nkeynes@359
   690
                            default:
nkeynes@359
   691
                                UNDEF();
nkeynes@359
   692
                                break;
nkeynes@359
   693
                        }
nkeynes@359
   694
                        break;
nkeynes@359
   695
                    case 0xB:
nkeynes@359
   696
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   697
                            case 0x0:
nkeynes@359
   698
                                { /* RTS */
nkeynes@374
   699
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   700
                            	SLOTILLEGAL();
nkeynes@374
   701
                                } else {
nkeynes@408
   702
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
   703
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   704
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
   705
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   706
                            	exit_block_pcset(pc+2);
nkeynes@409
   707
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   708
                            	return 4;
nkeynes@374
   709
                                }
nkeynes@359
   710
                                }
nkeynes@359
   711
                                break;
nkeynes@359
   712
                            case 0x1:
nkeynes@359
   713
                                { /* SLEEP */
nkeynes@388
   714
                                check_priv();
nkeynes@388
   715
                                call_func0( sh4_sleep );
nkeynes@417
   716
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
   717
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
   718
                                return 2;
nkeynes@359
   719
                                }
nkeynes@359
   720
                                break;
nkeynes@359
   721
                            case 0x2:
nkeynes@359
   722
                                { /* RTE */
nkeynes@374
   723
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   724
                            	SLOTILLEGAL();
nkeynes@374
   725
                                } else {
nkeynes@408
   726
                            	check_priv();
nkeynes@408
   727
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
   728
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   729
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   730
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   731
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   732
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   733
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   734
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   735
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   736
                            	exit_block_pcset(pc+2);
nkeynes@409
   737
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   738
                            	return 4;
nkeynes@374
   739
                                }
nkeynes@359
   740
                                }
nkeynes@359
   741
                                break;
nkeynes@359
   742
                            default:
nkeynes@359
   743
                                UNDEF();
nkeynes@359
   744
                                break;
nkeynes@359
   745
                        }
nkeynes@359
   746
                        break;
nkeynes@359
   747
                    case 0xC:
nkeynes@359
   748
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   749
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   750
                        load_reg( R_EAX, 0 );
nkeynes@359
   751
                        load_reg( R_ECX, Rm );
nkeynes@359
   752
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   753
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   754
                        store_reg( R_EAX, Rn );
nkeynes@417
   755
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   756
                        }
nkeynes@359
   757
                        break;
nkeynes@359
   758
                    case 0xD:
nkeynes@359
   759
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   760
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   761
                        load_reg( R_EAX, 0 );
nkeynes@361
   762
                        load_reg( R_ECX, Rm );
nkeynes@361
   763
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   764
                        check_ralign16( R_ECX );
nkeynes@361
   765
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   766
                        store_reg( R_EAX, Rn );
nkeynes@417
   767
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   768
                        }
nkeynes@359
   769
                        break;
nkeynes@359
   770
                    case 0xE:
nkeynes@359
   771
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   772
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   773
                        load_reg( R_EAX, 0 );
nkeynes@361
   774
                        load_reg( R_ECX, Rm );
nkeynes@361
   775
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   776
                        check_ralign32( R_ECX );
nkeynes@361
   777
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   778
                        store_reg( R_EAX, Rn );
nkeynes@417
   779
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   780
                        }
nkeynes@359
   781
                        break;
nkeynes@359
   782
                    case 0xF:
nkeynes@359
   783
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   784
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   785
                        load_reg( R_ECX, Rm );
nkeynes@386
   786
                        check_ralign32( R_ECX );
nkeynes@386
   787
                        load_reg( R_ECX, Rn );
nkeynes@386
   788
                        check_ralign32( R_ECX );
nkeynes@386
   789
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   790
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   791
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
   792
                        load_reg( R_ECX, Rm );
nkeynes@386
   793
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   794
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   795
                        POP_realigned_r32( R_ECX );
nkeynes@386
   796
                        IMUL_r32( R_ECX );
nkeynes@386
   797
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   798
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   799
                    
nkeynes@386
   800
                        load_spreg( R_ECX, R_S );
nkeynes@386
   801
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   802
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   803
                        call_func0( signsat48 );
nkeynes@386
   804
                        JMP_TARGET( nosat );
nkeynes@417
   805
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   806
                        }
nkeynes@359
   807
                        break;
nkeynes@359
   808
                    default:
nkeynes@359
   809
                        UNDEF();
nkeynes@359
   810
                        break;
nkeynes@359
   811
                }
nkeynes@359
   812
                break;
nkeynes@359
   813
            case 0x1:
nkeynes@359
   814
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   815
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   816
                load_reg( R_ECX, Rn );
nkeynes@361
   817
                load_reg( R_EAX, Rm );
nkeynes@361
   818
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   819
                check_walign32( R_ECX );
nkeynes@361
   820
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   821
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   822
                }
nkeynes@359
   823
                break;
nkeynes@359
   824
            case 0x2:
nkeynes@359
   825
                switch( ir&0xF ) {
nkeynes@359
   826
                    case 0x0:
nkeynes@359
   827
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   828
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   829
                        load_reg( R_EAX, Rm );
nkeynes@359
   830
                        load_reg( R_ECX, Rn );
nkeynes@359
   831
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   832
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   833
                        }
nkeynes@359
   834
                        break;
nkeynes@359
   835
                    case 0x1:
nkeynes@359
   836
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   837
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   838
                        load_reg( R_ECX, Rn );
nkeynes@374
   839
                        check_walign16( R_ECX );
nkeynes@386
   840
                        load_reg( R_EAX, Rm );
nkeynes@386
   841
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   842
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   843
                        }
nkeynes@359
   844
                        break;
nkeynes@359
   845
                    case 0x2:
nkeynes@359
   846
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   847
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   848
                        load_reg( R_EAX, Rm );
nkeynes@361
   849
                        load_reg( R_ECX, Rn );
nkeynes@374
   850
                        check_walign32(R_ECX);
nkeynes@361
   851
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   852
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   853
                        }
nkeynes@359
   854
                        break;
nkeynes@359
   855
                    case 0x4:
nkeynes@359
   856
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   857
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   858
                        load_reg( R_EAX, Rm );
nkeynes@359
   859
                        load_reg( R_ECX, Rn );
nkeynes@386
   860
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   861
                        store_reg( R_ECX, Rn );
nkeynes@359
   862
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   863
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   864
                        }
nkeynes@359
   865
                        break;
nkeynes@359
   866
                    case 0x5:
nkeynes@359
   867
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   868
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   869
                        load_reg( R_ECX, Rn );
nkeynes@374
   870
                        check_walign16( R_ECX );
nkeynes@361
   871
                        load_reg( R_EAX, Rm );
nkeynes@361
   872
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
   873
                        store_reg( R_ECX, Rn );
nkeynes@361
   874
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   875
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   876
                        }
nkeynes@359
   877
                        break;
nkeynes@359
   878
                    case 0x6:
nkeynes@359
   879
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   880
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   881
                        load_reg( R_EAX, Rm );
nkeynes@361
   882
                        load_reg( R_ECX, Rn );
nkeynes@374
   883
                        check_walign32( R_ECX );
nkeynes@361
   884
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   885
                        store_reg( R_ECX, Rn );
nkeynes@361
   886
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   887
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   888
                        }
nkeynes@359
   889
                        break;
nkeynes@359
   890
                    case 0x7:
nkeynes@359
   891
                        { /* DIV0S Rm, Rn */
nkeynes@359
   892
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   893
                        load_reg( R_EAX, Rm );
nkeynes@386
   894
                        load_reg( R_ECX, Rn );
nkeynes@361
   895
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   896
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   897
                        store_spreg( R_EAX, R_M );
nkeynes@361
   898
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   899
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   900
                        SETNE_t();
nkeynes@417
   901
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   902
                        }
nkeynes@359
   903
                        break;
nkeynes@359
   904
                    case 0x8:
nkeynes@359
   905
                        { /* TST Rm, Rn */
nkeynes@359
   906
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   907
                        load_reg( R_EAX, Rm );
nkeynes@361
   908
                        load_reg( R_ECX, Rn );
nkeynes@361
   909
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   910
                        SETE_t();
nkeynes@417
   911
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   912
                        }
nkeynes@359
   913
                        break;
nkeynes@359
   914
                    case 0x9:
nkeynes@359
   915
                        { /* AND Rm, Rn */
nkeynes@359
   916
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   917
                        load_reg( R_EAX, Rm );
nkeynes@359
   918
                        load_reg( R_ECX, Rn );
nkeynes@359
   919
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   920
                        store_reg( R_ECX, Rn );
nkeynes@417
   921
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   922
                        }
nkeynes@359
   923
                        break;
nkeynes@359
   924
                    case 0xA:
nkeynes@359
   925
                        { /* XOR Rm, Rn */
nkeynes@359
   926
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   927
                        load_reg( R_EAX, Rm );
nkeynes@359
   928
                        load_reg( R_ECX, Rn );
nkeynes@359
   929
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   930
                        store_reg( R_ECX, Rn );
nkeynes@417
   931
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   932
                        }
nkeynes@359
   933
                        break;
nkeynes@359
   934
                    case 0xB:
nkeynes@359
   935
                        { /* OR Rm, Rn */
nkeynes@359
   936
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   937
                        load_reg( R_EAX, Rm );
nkeynes@359
   938
                        load_reg( R_ECX, Rn );
nkeynes@359
   939
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   940
                        store_reg( R_ECX, Rn );
nkeynes@417
   941
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   942
                        }
nkeynes@359
   943
                        break;
nkeynes@359
   944
                    case 0xC:
nkeynes@359
   945
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   946
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   947
                        load_reg( R_EAX, Rm );
nkeynes@368
   948
                        load_reg( R_ECX, Rn );
nkeynes@368
   949
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   950
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   951
                        JE_rel8(13, target1);
nkeynes@368
   952
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   953
                        JE_rel8(9, target2);
nkeynes@368
   954
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   955
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   956
                        JE_rel8(2, target3);
nkeynes@368
   957
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   958
                        JMP_TARGET(target1);
nkeynes@380
   959
                        JMP_TARGET(target2);
nkeynes@380
   960
                        JMP_TARGET(target3);
nkeynes@368
   961
                        SETE_t();
nkeynes@417
   962
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   963
                        }
nkeynes@359
   964
                        break;
nkeynes@359
   965
                    case 0xD:
nkeynes@359
   966
                        { /* XTRCT Rm, Rn */
nkeynes@359
   967
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   968
                        load_reg( R_EAX, Rm );
nkeynes@394
   969
                        load_reg( R_ECX, Rn );
nkeynes@394
   970
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   971
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   972
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   973
                        store_reg( R_ECX, Rn );
nkeynes@417
   974
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   975
                        }
nkeynes@359
   976
                        break;
nkeynes@359
   977
                    case 0xE:
nkeynes@359
   978
                        { /* MULU.W Rm, Rn */
nkeynes@359
   979
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   980
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   981
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   982
                        MUL_r32( R_ECX );
nkeynes@374
   983
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   984
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   985
                        }
nkeynes@359
   986
                        break;
nkeynes@359
   987
                    case 0xF:
nkeynes@359
   988
                        { /* MULS.W Rm, Rn */
nkeynes@359
   989
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   990
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   991
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   992
                        MUL_r32( R_ECX );
nkeynes@374
   993
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   994
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   995
                        }
nkeynes@359
   996
                        break;
nkeynes@359
   997
                    default:
nkeynes@359
   998
                        UNDEF();
nkeynes@359
   999
                        break;
nkeynes@359
  1000
                }
nkeynes@359
  1001
                break;
nkeynes@359
  1002
            case 0x3:
nkeynes@359
  1003
                switch( ir&0xF ) {
nkeynes@359
  1004
                    case 0x0:
nkeynes@359
  1005
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1006
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1007
                        load_reg( R_EAX, Rm );
nkeynes@359
  1008
                        load_reg( R_ECX, Rn );
nkeynes@359
  1009
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1010
                        SETE_t();
nkeynes@417
  1011
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1012
                        }
nkeynes@359
  1013
                        break;
nkeynes@359
  1014
                    case 0x2:
nkeynes@359
  1015
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1016
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1017
                        load_reg( R_EAX, Rm );
nkeynes@359
  1018
                        load_reg( R_ECX, Rn );
nkeynes@359
  1019
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
                        SETAE_t();
nkeynes@417
  1021
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1022
                        }
nkeynes@359
  1023
                        break;
nkeynes@359
  1024
                    case 0x3:
nkeynes@359
  1025
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1026
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1027
                        load_reg( R_EAX, Rm );
nkeynes@359
  1028
                        load_reg( R_ECX, Rn );
nkeynes@359
  1029
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1030
                        SETGE_t();
nkeynes@417
  1031
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1032
                        }
nkeynes@359
  1033
                        break;
nkeynes@359
  1034
                    case 0x4:
nkeynes@359
  1035
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1036
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1037
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1038
                        load_reg( R_EAX, Rn );
nkeynes@417
  1039
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1040
                    	LDC_t();
nkeynes@417
  1041
                        }
nkeynes@386
  1042
                        RCL1_r32( R_EAX );
nkeynes@386
  1043
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1044
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1045
                        JE_rel8(5, mqequal);
nkeynes@386
  1046
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1047
                        JMP_rel8(3, end);
nkeynes@380
  1048
                        JMP_TARGET(mqequal);
nkeynes@386
  1049
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1050
                        JMP_TARGET(end);
nkeynes@386
  1051
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1052
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1053
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1054
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1055
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1056
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1057
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1058
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1059
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1060
                        }
nkeynes@359
  1061
                        break;
nkeynes@359
  1062
                    case 0x5:
nkeynes@359
  1063
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1064
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1065
                        load_reg( R_EAX, Rm );
nkeynes@361
  1066
                        load_reg( R_ECX, Rn );
nkeynes@361
  1067
                        MUL_r32(R_ECX);
nkeynes@361
  1068
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1069
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1070
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
                        }
nkeynes@359
  1072
                        break;
nkeynes@359
  1073
                    case 0x6:
nkeynes@359
  1074
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1075
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1076
                        load_reg( R_EAX, Rm );
nkeynes@359
  1077
                        load_reg( R_ECX, Rn );
nkeynes@359
  1078
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1079
                        SETA_t();
nkeynes@417
  1080
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1081
                        }
nkeynes@359
  1082
                        break;
nkeynes@359
  1083
                    case 0x7:
nkeynes@359
  1084
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1085
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1086
                        load_reg( R_EAX, Rm );
nkeynes@359
  1087
                        load_reg( R_ECX, Rn );
nkeynes@359
  1088
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1089
                        SETG_t();
nkeynes@417
  1090
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1091
                        }
nkeynes@359
  1092
                        break;
nkeynes@359
  1093
                    case 0x8:
nkeynes@359
  1094
                        { /* SUB Rm, Rn */
nkeynes@359
  1095
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1096
                        load_reg( R_EAX, Rm );
nkeynes@359
  1097
                        load_reg( R_ECX, Rn );
nkeynes@359
  1098
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1099
                        store_reg( R_ECX, Rn );
nkeynes@417
  1100
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1101
                        }
nkeynes@359
  1102
                        break;
nkeynes@359
  1103
                    case 0xA:
nkeynes@359
  1104
                        { /* SUBC Rm, Rn */
nkeynes@359
  1105
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1106
                        load_reg( R_EAX, Rm );
nkeynes@359
  1107
                        load_reg( R_ECX, Rn );
nkeynes@417
  1108
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1109
                    	LDC_t();
nkeynes@417
  1110
                        }
nkeynes@359
  1111
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1112
                        store_reg( R_ECX, Rn );
nkeynes@394
  1113
                        SETC_t();
nkeynes@417
  1114
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1115
                        }
nkeynes@359
  1116
                        break;
nkeynes@359
  1117
                    case 0xB:
nkeynes@359
  1118
                        { /* SUBV Rm, Rn */
nkeynes@359
  1119
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1120
                        load_reg( R_EAX, Rm );
nkeynes@359
  1121
                        load_reg( R_ECX, Rn );
nkeynes@359
  1122
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1123
                        store_reg( R_ECX, Rn );
nkeynes@359
  1124
                        SETO_t();
nkeynes@417
  1125
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1126
                        }
nkeynes@359
  1127
                        break;
nkeynes@359
  1128
                    case 0xC:
nkeynes@359
  1129
                        { /* ADD Rm, Rn */
nkeynes@359
  1130
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1131
                        load_reg( R_EAX, Rm );
nkeynes@359
  1132
                        load_reg( R_ECX, Rn );
nkeynes@359
  1133
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1134
                        store_reg( R_ECX, Rn );
nkeynes@417
  1135
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1136
                        }
nkeynes@359
  1137
                        break;
nkeynes@359
  1138
                    case 0xD:
nkeynes@359
  1139
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1140
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1141
                        load_reg( R_EAX, Rm );
nkeynes@361
  1142
                        load_reg( R_ECX, Rn );
nkeynes@361
  1143
                        IMUL_r32(R_ECX);
nkeynes@361
  1144
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1145
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1146
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
                        }
nkeynes@359
  1148
                        break;
nkeynes@359
  1149
                    case 0xE:
nkeynes@359
  1150
                        { /* ADDC Rm, Rn */
nkeynes@359
  1151
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1152
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1153
                    	LDC_t();
nkeynes@417
  1154
                        }
nkeynes@359
  1155
                        load_reg( R_EAX, Rm );
nkeynes@359
  1156
                        load_reg( R_ECX, Rn );
nkeynes@359
  1157
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1158
                        store_reg( R_ECX, Rn );
nkeynes@359
  1159
                        SETC_t();
nkeynes@417
  1160
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1161
                        }
nkeynes@359
  1162
                        break;
nkeynes@359
  1163
                    case 0xF:
nkeynes@359
  1164
                        { /* ADDV Rm, Rn */
nkeynes@359
  1165
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1166
                        load_reg( R_EAX, Rm );
nkeynes@359
  1167
                        load_reg( R_ECX, Rn );
nkeynes@359
  1168
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1169
                        store_reg( R_ECX, Rn );
nkeynes@359
  1170
                        SETO_t();
nkeynes@417
  1171
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1172
                        }
nkeynes@359
  1173
                        break;
nkeynes@359
  1174
                    default:
nkeynes@359
  1175
                        UNDEF();
nkeynes@359
  1176
                        break;
nkeynes@359
  1177
                }
nkeynes@359
  1178
                break;
nkeynes@359
  1179
            case 0x4:
nkeynes@359
  1180
                switch( ir&0xF ) {
nkeynes@359
  1181
                    case 0x0:
nkeynes@359
  1182
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1183
                            case 0x0:
nkeynes@359
  1184
                                { /* SHLL Rn */
nkeynes@359
  1185
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1186
                                load_reg( R_EAX, Rn );
nkeynes@359
  1187
                                SHL1_r32( R_EAX );
nkeynes@397
  1188
                                SETC_t();
nkeynes@359
  1189
                                store_reg( R_EAX, Rn );
nkeynes@417
  1190
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1191
                                }
nkeynes@359
  1192
                                break;
nkeynes@359
  1193
                            case 0x1:
nkeynes@359
  1194
                                { /* DT Rn */
nkeynes@359
  1195
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1196
                                load_reg( R_EAX, Rn );
nkeynes@386
  1197
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1198
                                store_reg( R_EAX, Rn );
nkeynes@359
  1199
                                SETE_t();
nkeynes@417
  1200
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1201
                                }
nkeynes@359
  1202
                                break;
nkeynes@359
  1203
                            case 0x2:
nkeynes@359
  1204
                                { /* SHAL Rn */
nkeynes@359
  1205
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1206
                                load_reg( R_EAX, Rn );
nkeynes@359
  1207
                                SHL1_r32( R_EAX );
nkeynes@397
  1208
                                SETC_t();
nkeynes@359
  1209
                                store_reg( R_EAX, Rn );
nkeynes@417
  1210
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1211
                                }
nkeynes@359
  1212
                                break;
nkeynes@359
  1213
                            default:
nkeynes@359
  1214
                                UNDEF();
nkeynes@359
  1215
                                break;
nkeynes@359
  1216
                        }
nkeynes@359
  1217
                        break;
nkeynes@359
  1218
                    case 0x1:
nkeynes@359
  1219
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1220
                            case 0x0:
nkeynes@359
  1221
                                { /* SHLR Rn */
nkeynes@359
  1222
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1223
                                load_reg( R_EAX, Rn );
nkeynes@359
  1224
                                SHR1_r32( R_EAX );
nkeynes@397
  1225
                                SETC_t();
nkeynes@359
  1226
                                store_reg( R_EAX, Rn );
nkeynes@417
  1227
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1228
                                }
nkeynes@359
  1229
                                break;
nkeynes@359
  1230
                            case 0x1:
nkeynes@359
  1231
                                { /* CMP/PZ Rn */
nkeynes@359
  1232
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1233
                                load_reg( R_EAX, Rn );
nkeynes@359
  1234
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1235
                                SETGE_t();
nkeynes@417
  1236
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1237
                                }
nkeynes@359
  1238
                                break;
nkeynes@359
  1239
                            case 0x2:
nkeynes@359
  1240
                                { /* SHAR Rn */
nkeynes@359
  1241
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1242
                                load_reg( R_EAX, Rn );
nkeynes@359
  1243
                                SAR1_r32( R_EAX );
nkeynes@397
  1244
                                SETC_t();
nkeynes@359
  1245
                                store_reg( R_EAX, Rn );
nkeynes@417
  1246
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1247
                                }
nkeynes@359
  1248
                                break;
nkeynes@359
  1249
                            default:
nkeynes@359
  1250
                                UNDEF();
nkeynes@359
  1251
                                break;
nkeynes@359
  1252
                        }
nkeynes@359
  1253
                        break;
nkeynes@359
  1254
                    case 0x2:
nkeynes@359
  1255
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1256
                            case 0x0:
nkeynes@359
  1257
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1258
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1259
                                load_reg( R_ECX, Rn );
nkeynes@395
  1260
                                check_walign32( R_ECX );
nkeynes@386
  1261
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1262
                                store_reg( R_ECX, Rn );
nkeynes@359
  1263
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1264
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1265
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1266
                                }
nkeynes@359
  1267
                                break;
nkeynes@359
  1268
                            case 0x1:
nkeynes@359
  1269
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1270
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1271
                                load_reg( R_ECX, Rn );
nkeynes@395
  1272
                                check_walign32( R_ECX );
nkeynes@386
  1273
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1274
                                store_reg( R_ECX, Rn );
nkeynes@359
  1275
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1276
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1277
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1278
                                }
nkeynes@359
  1279
                                break;
nkeynes@359
  1280
                            case 0x2:
nkeynes@359
  1281
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1282
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1283
                                load_reg( R_ECX, Rn );
nkeynes@395
  1284
                                check_walign32( R_ECX );
nkeynes@386
  1285
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1286
                                store_reg( R_ECX, Rn );
nkeynes@359
  1287
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1288
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1289
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1290
                                }
nkeynes@359
  1291
                                break;
nkeynes@359
  1292
                            case 0x3:
nkeynes@359
  1293
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1294
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1295
                                check_priv();
nkeynes@359
  1296
                                load_reg( R_ECX, Rn );
nkeynes@395
  1297
                                check_walign32( R_ECX );
nkeynes@386
  1298
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1299
                                store_reg( R_ECX, Rn );
nkeynes@359
  1300
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1301
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1302
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1303
                                }
nkeynes@359
  1304
                                break;
nkeynes@359
  1305
                            case 0x5:
nkeynes@359
  1306
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1307
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1308
                                load_reg( R_ECX, Rn );
nkeynes@395
  1309
                                check_walign32( R_ECX );
nkeynes@386
  1310
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1311
                                store_reg( R_ECX, Rn );
nkeynes@359
  1312
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1313
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1314
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1315
                                }
nkeynes@359
  1316
                                break;
nkeynes@359
  1317
                            case 0x6:
nkeynes@359
  1318
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1319
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1320
                                load_reg( R_ECX, Rn );
nkeynes@395
  1321
                                check_walign32( R_ECX );
nkeynes@386
  1322
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1323
                                store_reg( R_ECX, Rn );
nkeynes@359
  1324
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1325
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1326
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1327
                                }
nkeynes@359
  1328
                                break;
nkeynes@359
  1329
                            case 0xF:
nkeynes@359
  1330
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1331
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1332
                                check_priv();
nkeynes@359
  1333
                                load_reg( R_ECX, Rn );
nkeynes@395
  1334
                                check_walign32( R_ECX );
nkeynes@386
  1335
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1336
                                store_reg( R_ECX, Rn );
nkeynes@359
  1337
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1338
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1339
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1340
                                }
nkeynes@359
  1341
                                break;
nkeynes@359
  1342
                            default:
nkeynes@359
  1343
                                UNDEF();
nkeynes@359
  1344
                                break;
nkeynes@359
  1345
                        }
nkeynes@359
  1346
                        break;
nkeynes@359
  1347
                    case 0x3:
nkeynes@359
  1348
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1349
                            case 0x0:
nkeynes@359
  1350
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1351
                                    case 0x0:
nkeynes@359
  1352
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1353
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1354
                                        check_priv();
nkeynes@395
  1355
                                        call_func0( sh4_read_sr );
nkeynes@374
  1356
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1357
                                        check_walign32( R_ECX );
nkeynes@386
  1358
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1359
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1360
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1361
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1362
                                        }
nkeynes@359
  1363
                                        break;
nkeynes@359
  1364
                                    case 0x1:
nkeynes@359
  1365
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1366
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1367
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1368
                                        check_walign32( R_ECX );
nkeynes@386
  1369
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1370
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1371
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1372
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1373
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1374
                                        }
nkeynes@359
  1375
                                        break;
nkeynes@359
  1376
                                    case 0x2:
nkeynes@359
  1377
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1378
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1379
                                        check_priv();
nkeynes@359
  1380
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1381
                                        check_walign32( R_ECX );
nkeynes@386
  1382
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1383
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1384
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1385
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1386
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1387
                                        }
nkeynes@359
  1388
                                        break;
nkeynes@359
  1389
                                    case 0x3:
nkeynes@359
  1390
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1391
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1392
                                        check_priv();
nkeynes@359
  1393
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1394
                                        check_walign32( R_ECX );
nkeynes@386
  1395
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1396
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1397
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1398
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1399
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1400
                                        }
nkeynes@359
  1401
                                        break;
nkeynes@359
  1402
                                    case 0x4:
nkeynes@359
  1403
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1404
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1405
                                        check_priv();
nkeynes@359
  1406
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1407
                                        check_walign32( R_ECX );
nkeynes@386
  1408
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1409
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1410
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1411
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1412
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1413
                                        }
nkeynes@359
  1414
                                        break;
nkeynes@359
  1415
                                    default:
nkeynes@359
  1416
                                        UNDEF();
nkeynes@359
  1417
                                        break;
nkeynes@359
  1418
                                }
nkeynes@359
  1419
                                break;
nkeynes@359
  1420
                            case 0x1:
nkeynes@359
  1421
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1422
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1423
                                check_priv();
nkeynes@374
  1424
                                load_reg( R_ECX, Rn );
nkeynes@395
  1425
                                check_walign32( R_ECX );
nkeynes@386
  1426
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1427
                                store_reg( R_ECX, Rn );
nkeynes@374
  1428
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1429
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1430
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1431
                                }
nkeynes@359
  1432
                                break;
nkeynes@359
  1433
                        }
nkeynes@359
  1434
                        break;
nkeynes@359
  1435
                    case 0x4:
nkeynes@359
  1436
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1437
                            case 0x0:
nkeynes@359
  1438
                                { /* ROTL Rn */
nkeynes@359
  1439
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1440
                                load_reg( R_EAX, Rn );
nkeynes@359
  1441
                                ROL1_r32( R_EAX );
nkeynes@359
  1442
                                store_reg( R_EAX, Rn );
nkeynes@359
  1443
                                SETC_t();
nkeynes@417
  1444
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1445
                                }
nkeynes@359
  1446
                                break;
nkeynes@359
  1447
                            case 0x2:
nkeynes@359
  1448
                                { /* ROTCL Rn */
nkeynes@359
  1449
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1450
                                load_reg( R_EAX, Rn );
nkeynes@417
  1451
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1452
                            	LDC_t();
nkeynes@417
  1453
                                }
nkeynes@359
  1454
                                RCL1_r32( R_EAX );
nkeynes@359
  1455
                                store_reg( R_EAX, Rn );
nkeynes@359
  1456
                                SETC_t();
nkeynes@417
  1457
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1458
                                }
nkeynes@359
  1459
                                break;
nkeynes@359
  1460
                            default:
nkeynes@359
  1461
                                UNDEF();
nkeynes@359
  1462
                                break;
nkeynes@359
  1463
                        }
nkeynes@359
  1464
                        break;
nkeynes@359
  1465
                    case 0x5:
nkeynes@359
  1466
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1467
                            case 0x0:
nkeynes@359
  1468
                                { /* ROTR Rn */
nkeynes@359
  1469
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1470
                                load_reg( R_EAX, Rn );
nkeynes@359
  1471
                                ROR1_r32( R_EAX );
nkeynes@359
  1472
                                store_reg( R_EAX, Rn );
nkeynes@359
  1473
                                SETC_t();
nkeynes@417
  1474
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1475
                                }
nkeynes@359
  1476
                                break;
nkeynes@359
  1477
                            case 0x1:
nkeynes@359
  1478
                                { /* CMP/PL Rn */
nkeynes@359
  1479
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1480
                                load_reg( R_EAX, Rn );
nkeynes@359
  1481
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1482
                                SETG_t();
nkeynes@417
  1483
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1484
                                }
nkeynes@359
  1485
                                break;
nkeynes@359
  1486
                            case 0x2:
nkeynes@359
  1487
                                { /* ROTCR Rn */
nkeynes@359
  1488
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1489
                                load_reg( R_EAX, Rn );
nkeynes@417
  1490
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1491
                            	LDC_t();
nkeynes@417
  1492
                                }
nkeynes@359
  1493
                                RCR1_r32( R_EAX );
nkeynes@359
  1494
                                store_reg( R_EAX, Rn );
nkeynes@359
  1495
                                SETC_t();
nkeynes@417
  1496
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1497
                                }
nkeynes@359
  1498
                                break;
nkeynes@359
  1499
                            default:
nkeynes@359
  1500
                                UNDEF();
nkeynes@359
  1501
                                break;
nkeynes@359
  1502
                        }
nkeynes@359
  1503
                        break;
nkeynes@359
  1504
                    case 0x6:
nkeynes@359
  1505
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1506
                            case 0x0:
nkeynes@359
  1507
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1508
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1509
                                load_reg( R_EAX, Rm );
nkeynes@395
  1510
                                check_ralign32( R_EAX );
nkeynes@359
  1511
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1512
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1513
                                store_reg( R_EAX, Rm );
nkeynes@359
  1514
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1515
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1516
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1517
                                }
nkeynes@359
  1518
                                break;
nkeynes@359
  1519
                            case 0x1:
nkeynes@359
  1520
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1521
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1522
                                load_reg( R_EAX, Rm );
nkeynes@395
  1523
                                check_ralign32( R_EAX );
nkeynes@359
  1524
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1525
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1526
                                store_reg( R_EAX, Rm );
nkeynes@359
  1527
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1528
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1529
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1530
                                }
nkeynes@359
  1531
                                break;
nkeynes@359
  1532
                            case 0x2:
nkeynes@359
  1533
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1534
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1535
                                load_reg( R_EAX, Rm );
nkeynes@395
  1536
                                check_ralign32( R_EAX );
nkeynes@359
  1537
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1538
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1539
                                store_reg( R_EAX, Rm );
nkeynes@359
  1540
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1541
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1542
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1543
                                }
nkeynes@359
  1544
                                break;
nkeynes@359
  1545
                            case 0x3:
nkeynes@359
  1546
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1547
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1548
                                check_priv();
nkeynes@359
  1549
                                load_reg( R_EAX, Rm );
nkeynes@395
  1550
                                check_ralign32( R_EAX );
nkeynes@359
  1551
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1552
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1553
                                store_reg( R_EAX, Rm );
nkeynes@359
  1554
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1555
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1556
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1557
                                }
nkeynes@359
  1558
                                break;
nkeynes@359
  1559
                            case 0x5:
nkeynes@359
  1560
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1561
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1562
                                load_reg( R_EAX, Rm );
nkeynes@395
  1563
                                check_ralign32( R_EAX );
nkeynes@359
  1564
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1565
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1566
                                store_reg( R_EAX, Rm );
nkeynes@359
  1567
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1568
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1569
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1570
                                }
nkeynes@359
  1571
                                break;
nkeynes@359
  1572
                            case 0x6:
nkeynes@359
  1573
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1574
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1575
                                load_reg( R_EAX, Rm );
nkeynes@395
  1576
                                check_ralign32( R_EAX );
nkeynes@359
  1577
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1578
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1579
                                store_reg( R_EAX, Rm );
nkeynes@359
  1580
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1581
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1582
                                update_fr_bank( R_EAX );
nkeynes@417
  1583
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1584
                                }
nkeynes@359
  1585
                                break;
nkeynes@359
  1586
                            case 0xF:
nkeynes@359
  1587
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1588
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1589
                                check_priv();
nkeynes@359
  1590
                                load_reg( R_EAX, Rm );
nkeynes@395
  1591
                                check_ralign32( R_EAX );
nkeynes@359
  1592
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1593
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1594
                                store_reg( R_EAX, Rm );
nkeynes@359
  1595
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1596
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1597
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1598
                                }
nkeynes@359
  1599
                                break;
nkeynes@359
  1600
                            default:
nkeynes@359
  1601
                                UNDEF();
nkeynes@359
  1602
                                break;
nkeynes@359
  1603
                        }
nkeynes@359
  1604
                        break;
nkeynes@359
  1605
                    case 0x7:
nkeynes@359
  1606
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1607
                            case 0x0:
nkeynes@359
  1608
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1609
                                    case 0x0:
nkeynes@359
  1610
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1611
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1612
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1613
                                    	SLOTILLEGAL();
nkeynes@386
  1614
                                        } else {
nkeynes@559
  1615
                                    	check_priv();
nkeynes@386
  1616
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1617
                                    	check_ralign32( R_EAX );
nkeynes@386
  1618
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1619
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1620
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1621
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1622
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1623
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1624
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1625
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1626
                                        }
nkeynes@359
  1627
                                        }
nkeynes@359
  1628
                                        break;
nkeynes@359
  1629
                                    case 0x1:
nkeynes@359
  1630
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1631
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1632
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1633
                                        check_ralign32( R_EAX );
nkeynes@359
  1634
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1635
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1636
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1637
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1638
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1639
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1640
                                        }
nkeynes@359
  1641
                                        break;
nkeynes@359
  1642
                                    case 0x2:
nkeynes@359
  1643
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1644
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1645
                                        check_priv();
nkeynes@359
  1646
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1647
                                        check_ralign32( R_EAX );
nkeynes@359
  1648
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1649
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1650
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1651
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1652
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1653
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1654
                                        }
nkeynes@359
  1655
                                        break;
nkeynes@359
  1656
                                    case 0x3:
nkeynes@359
  1657
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1658
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1659
                                        check_priv();
nkeynes@359
  1660
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1661
                                        check_ralign32( R_EAX );
nkeynes@359
  1662
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1663
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1664
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1665
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1666
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1667
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1668
                                        }
nkeynes@359
  1669
                                        break;
nkeynes@359
  1670
                                    case 0x4:
nkeynes@359
  1671
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1672
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1673
                                        check_priv();
nkeynes@359
  1674
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1675
                                        check_ralign32( R_EAX );
nkeynes@359
  1676
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1677
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1678
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1679
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1680
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1681
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1682
                                        }
nkeynes@359
  1683
                                        break;
nkeynes@359
  1684
                                    default:
nkeynes@359
  1685
                                        UNDEF();
nkeynes@359
  1686
                                        break;
nkeynes@359
  1687
                                }
nkeynes@359
  1688
                                break;
nkeynes@359
  1689
                            case 0x1:
nkeynes@359
  1690
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1691
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1692
                                check_priv();
nkeynes@374
  1693
                                load_reg( R_EAX, Rm );
nkeynes@395
  1694
                                check_ralign32( R_EAX );
nkeynes@374
  1695
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1696
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1697
                                store_reg( R_EAX, Rm );
nkeynes@374
  1698
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1699
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1700
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1701
                                }
nkeynes@359
  1702
                                break;
nkeynes@359
  1703
                        }
nkeynes@359
  1704
                        break;
nkeynes@359
  1705
                    case 0x8:
nkeynes@359
  1706
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1707
                            case 0x0:
nkeynes@359
  1708
                                { /* SHLL2 Rn */
nkeynes@359
  1709
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1710
                                load_reg( R_EAX, Rn );
nkeynes@359
  1711
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1712
                                store_reg( R_EAX, Rn );
nkeynes@417
  1713
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1714
                                }
nkeynes@359
  1715
                                break;
nkeynes@359
  1716
                            case 0x1:
nkeynes@359
  1717
                                { /* SHLL8 Rn */
nkeynes@359
  1718
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1719
                                load_reg( R_EAX, Rn );
nkeynes@359
  1720
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1721
                                store_reg( R_EAX, Rn );
nkeynes@417
  1722
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1723
                                }
nkeynes@359
  1724
                                break;
nkeynes@359
  1725
                            case 0x2:
nkeynes@359
  1726
                                { /* SHLL16 Rn */
nkeynes@359
  1727
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1728
                                load_reg( R_EAX, Rn );
nkeynes@359
  1729
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1730
                                store_reg( R_EAX, Rn );
nkeynes@417
  1731
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1732
                                }
nkeynes@359
  1733
                                break;
nkeynes@359
  1734
                            default:
nkeynes@359
  1735
                                UNDEF();
nkeynes@359
  1736
                                break;
nkeynes@359
  1737
                        }
nkeynes@359
  1738
                        break;
nkeynes@359
  1739
                    case 0x9:
nkeynes@359
  1740
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1741
                            case 0x0:
nkeynes@359
  1742
                                { /* SHLR2 Rn */
nkeynes@359
  1743
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1744
                                load_reg( R_EAX, Rn );
nkeynes@359
  1745
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1746
                                store_reg( R_EAX, Rn );
nkeynes@417
  1747
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1748
                                }
nkeynes@359
  1749
                                break;
nkeynes@359
  1750
                            case 0x1:
nkeynes@359
  1751
                                { /* SHLR8 Rn */
nkeynes@359
  1752
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1753
                                load_reg( R_EAX, Rn );
nkeynes@359
  1754
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1755
                                store_reg( R_EAX, Rn );
nkeynes@417
  1756
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1757
                                }
nkeynes@359
  1758
                                break;
nkeynes@359
  1759
                            case 0x2:
nkeynes@359
  1760
                                { /* SHLR16 Rn */
nkeynes@359
  1761
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1762
                                load_reg( R_EAX, Rn );
nkeynes@359
  1763
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1764
                                store_reg( R_EAX, Rn );
nkeynes@417
  1765
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1766
                                }
nkeynes@359
  1767
                                break;
nkeynes@359
  1768
                            default:
nkeynes@359
  1769
                                UNDEF();
nkeynes@359
  1770
                                break;
nkeynes@359
  1771
                        }
nkeynes@359
  1772
                        break;
nkeynes@359
  1773
                    case 0xA:
nkeynes@359
  1774
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1775
                            case 0x0:
nkeynes@359
  1776
                                { /* LDS Rm, MACH */
nkeynes@359
  1777
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1778
                                load_reg( R_EAX, Rm );
nkeynes@359
  1779
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1780
                                }
nkeynes@359
  1781
                                break;
nkeynes@359
  1782
                            case 0x1:
nkeynes@359
  1783
                                { /* LDS Rm, MACL */
nkeynes@359
  1784
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1785
                                load_reg( R_EAX, Rm );
nkeynes@359
  1786
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1787
                                }
nkeynes@359
  1788
                                break;
nkeynes@359
  1789
                            case 0x2:
nkeynes@359
  1790
                                { /* LDS Rm, PR */
nkeynes@359
  1791
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1792
                                load_reg( R_EAX, Rm );
nkeynes@359
  1793
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1794
                                }
nkeynes@359
  1795
                                break;
nkeynes@359
  1796
                            case 0x3:
nkeynes@359
  1797
                                { /* LDC Rm, SGR */
nkeynes@359
  1798
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1799
                                check_priv();
nkeynes@359
  1800
                                load_reg( R_EAX, Rm );
nkeynes@359
  1801
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1802
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1803
                                }
nkeynes@359
  1804
                                break;
nkeynes@359
  1805
                            case 0x5:
nkeynes@359
  1806
                                { /* LDS Rm, FPUL */
nkeynes@359
  1807
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1808
                                load_reg( R_EAX, Rm );
nkeynes@359
  1809
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1810
                                }
nkeynes@359
  1811
                                break;
nkeynes@359
  1812
                            case 0x6:
nkeynes@359
  1813
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1814
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1815
                                load_reg( R_EAX, Rm );
nkeynes@359
  1816
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1817
                                update_fr_bank( R_EAX );
nkeynes@417
  1818
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1819
                                }
nkeynes@359
  1820
                                break;
nkeynes@359
  1821
                            case 0xF:
nkeynes@359
  1822
                                { /* LDC Rm, DBR */
nkeynes@359
  1823
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1824
                                check_priv();
nkeynes@359
  1825
                                load_reg( R_EAX, Rm );
nkeynes@359
  1826
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1827
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1828
                                }
nkeynes@359
  1829
                                break;
nkeynes@359
  1830
                            default:
nkeynes@359
  1831
                                UNDEF();
nkeynes@359
  1832
                                break;
nkeynes@359
  1833
                        }
nkeynes@359
  1834
                        break;
nkeynes@359
  1835
                    case 0xB:
nkeynes@359
  1836
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1837
                            case 0x0:
nkeynes@359
  1838
                                { /* JSR @Rn */
nkeynes@359
  1839
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1840
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1841
                            	SLOTILLEGAL();
nkeynes@374
  1842
                                } else {
nkeynes@374
  1843
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1844
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1845
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1846
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1847
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1848
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1849
                            	exit_block_pcset(pc+2);
nkeynes@409
  1850
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1851
                            	return 4;
nkeynes@374
  1852
                                }
nkeynes@359
  1853
                                }
nkeynes@359
  1854
                                break;
nkeynes@359
  1855
                            case 0x1:
nkeynes@359
  1856
                                { /* TAS.B @Rn */
nkeynes@359
  1857
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1858
                                load_reg( R_ECX, Rn );
nkeynes@361
  1859
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1860
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1861
                                SETE_t();
nkeynes@361
  1862
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1863
                                load_reg( R_ECX, Rn );
nkeynes@361
  1864
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1865
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1866
                                }
nkeynes@359
  1867
                                break;
nkeynes@359
  1868
                            case 0x2:
nkeynes@359
  1869
                                { /* JMP @Rn */
nkeynes@359
  1870
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1871
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1872
                            	SLOTILLEGAL();
nkeynes@374
  1873
                                } else {
nkeynes@408
  1874
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1875
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1876
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1877
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1878
                            	exit_block_pcset(pc+2);
nkeynes@409
  1879
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1880
                            	return 4;
nkeynes@374
  1881
                                }
nkeynes@359
  1882
                                }
nkeynes@359
  1883
                                break;
nkeynes@359
  1884
                            default:
nkeynes@359
  1885
                                UNDEF();
nkeynes@359
  1886
                                break;
nkeynes@359
  1887
                        }
nkeynes@359
  1888
                        break;
nkeynes@359
  1889
                    case 0xC:
nkeynes@359
  1890
                        { /* SHAD Rm, Rn */
nkeynes@359
  1891
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1892
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1893
                        load_reg( R_EAX, Rn );
nkeynes@361
  1894
                        load_reg( R_ECX, Rm );
nkeynes@361
  1895
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1896
                        JGE_rel8(16, doshl);
nkeynes@361
  1897
                                        
nkeynes@361
  1898
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1899
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1900
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1901
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1902
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1903
                    
nkeynes@386
  1904
                        JMP_TARGET(emptysar);
nkeynes@386
  1905
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1906
                        JMP_rel8(5, end2);
nkeynes@386
  1907
                    
nkeynes@380
  1908
                        JMP_TARGET(doshl);
nkeynes@361
  1909
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1910
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1911
                        JMP_TARGET(end);
nkeynes@386
  1912
                        JMP_TARGET(end2);
nkeynes@361
  1913
                        store_reg( R_EAX, Rn );
nkeynes@417
  1914
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1915
                        }
nkeynes@359
  1916
                        break;
nkeynes@359
  1917
                    case 0xD:
nkeynes@359
  1918
                        { /* SHLD Rm, Rn */
nkeynes@359
  1919
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1920
                        load_reg( R_EAX, Rn );
nkeynes@368
  1921
                        load_reg( R_ECX, Rm );
nkeynes@386
  1922
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1923
                        JGE_rel8(15, doshl);
nkeynes@368
  1924
                    
nkeynes@386
  1925
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1926
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1927
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1928
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1929
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1930
                    
nkeynes@386
  1931
                        JMP_TARGET(emptyshr);
nkeynes@386
  1932
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1933
                        JMP_rel8(5, end2);
nkeynes@386
  1934
                    
nkeynes@386
  1935
                        JMP_TARGET(doshl);
nkeynes@386
  1936
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1937
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1938
                        JMP_TARGET(end);
nkeynes@386
  1939
                        JMP_TARGET(end2);
nkeynes@368
  1940
                        store_reg( R_EAX, Rn );
nkeynes@417
  1941
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1942
                        }
nkeynes@359
  1943
                        break;
nkeynes@359
  1944
                    case 0xE:
nkeynes@359
  1945
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1946
                            case 0x0:
nkeynes@359
  1947
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1948
                                    case 0x0:
nkeynes@359
  1949
                                        { /* LDC Rm, SR */
nkeynes@359
  1950
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1951
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1952
                                    	SLOTILLEGAL();
nkeynes@386
  1953
                                        } else {
nkeynes@386
  1954
                                    	check_priv();
nkeynes@386
  1955
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1956
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1957
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1958
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1959
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1960
                                        }
nkeynes@359
  1961
                                        }
nkeynes@359
  1962
                                        break;
nkeynes@359
  1963
                                    case 0x1:
nkeynes@359
  1964
                                        { /* LDC Rm, GBR */
nkeynes@359
  1965
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1966
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1967
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1968
                                        }
nkeynes@359
  1969
                                        break;
nkeynes@359
  1970
                                    case 0x2:
nkeynes@359
  1971
                                        { /* LDC Rm, VBR */
nkeynes@359
  1972
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1973
                                        check_priv();
nkeynes@359
  1974
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1975
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1976
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1977
                                        }
nkeynes@359
  1978
                                        break;
nkeynes@359
  1979
                                    case 0x3:
nkeynes@359
  1980
                                        { /* LDC Rm, SSR */
nkeynes@359
  1981
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1982
                                        check_priv();
nkeynes@359
  1983
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1984
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1985
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1986
                                        }
nkeynes@359
  1987
                                        break;
nkeynes@359
  1988
                                    case 0x4:
nkeynes@359
  1989
                                        { /* LDC Rm, SPC */
nkeynes@359
  1990
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1991
                                        check_priv();
nkeynes@359
  1992
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1993
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1994
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1995
                                        }
nkeynes@359
  1996
                                        break;
nkeynes@359
  1997
                                    default:
nkeynes@359
  1998
                                        UNDEF();
nkeynes@359
  1999
                                        break;
nkeynes@359
  2000
                                }
nkeynes@359
  2001
                                break;
nkeynes@359
  2002
                            case 0x1:
nkeynes@359
  2003
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2004
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2005
                                check_priv();
nkeynes@374
  2006
                                load_reg( R_EAX, Rm );
nkeynes@374
  2007
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2008
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2009
                                }
nkeynes@359
  2010
                                break;
nkeynes@359
  2011
                        }
nkeynes@359
  2012
                        break;
nkeynes@359
  2013
                    case 0xF:
nkeynes@359
  2014
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2015
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  2016
                        load_reg( R_ECX, Rm );
nkeynes@386
  2017
                        check_ralign16( R_ECX );
nkeynes@386
  2018
                        load_reg( R_ECX, Rn );
nkeynes@386
  2019
                        check_ralign16( R_ECX );
nkeynes@386
  2020
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  2021
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2022
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
  2023
                        load_reg( R_ECX, Rm );
nkeynes@386
  2024
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  2025
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2026
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2027
                        IMUL_r32( R_ECX );
nkeynes@386
  2028
                    
nkeynes@386
  2029
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2030
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2031
                        JE_rel8( 47, nosat );
nkeynes@386
  2032
                    
nkeynes@386
  2033
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2034
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2035
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2036
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2037
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2038
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2039
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2040
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2041
                    
nkeynes@386
  2042
                        JMP_TARGET(positive);
nkeynes@386
  2043
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2044
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2045
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2046
                    
nkeynes@386
  2047
                        JMP_TARGET(nosat);
nkeynes@386
  2048
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2049
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2050
                        JMP_TARGET(end);
nkeynes@386
  2051
                        JMP_TARGET(end2);
nkeynes@386
  2052
                        JMP_TARGET(end3);
nkeynes@417
  2053
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2054
                        }
nkeynes@359
  2055
                        break;
nkeynes@359
  2056
                }
nkeynes@359
  2057
                break;
nkeynes@359
  2058
            case 0x5:
nkeynes@359
  2059
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2060
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2061
                load_reg( R_ECX, Rm );
nkeynes@361
  2062
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  2063
                check_ralign32( R_ECX );
nkeynes@361
  2064
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2065
                store_reg( R_EAX, Rn );
nkeynes@417
  2066
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2067
                }
nkeynes@359
  2068
                break;
nkeynes@359
  2069
            case 0x6:
nkeynes@359
  2070
                switch( ir&0xF ) {
nkeynes@359
  2071
                    case 0x0:
nkeynes@359
  2072
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2073
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2074
                        load_reg( R_ECX, Rm );
nkeynes@359
  2075
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2076
                        store_reg( R_EAX, Rn );
nkeynes@417
  2077
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2078
                        }
nkeynes@359
  2079
                        break;
nkeynes@359
  2080
                    case 0x1:
nkeynes@359
  2081
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2082
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2083
                        load_reg( R_ECX, Rm );
nkeynes@374
  2084
                        check_ralign16( R_ECX );
nkeynes@361
  2085
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2086
                        store_reg( R_EAX, Rn );
nkeynes@417
  2087
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2088
                        }
nkeynes@359
  2089
                        break;
nkeynes@359
  2090
                    case 0x2:
nkeynes@359
  2091
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2092
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2093
                        load_reg( R_ECX, Rm );
nkeynes@374
  2094
                        check_ralign32( R_ECX );
nkeynes@361
  2095
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2096
                        store_reg( R_EAX, Rn );
nkeynes@417
  2097
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2098
                        }
nkeynes@359
  2099
                        break;
nkeynes@359
  2100
                    case 0x3:
nkeynes@359
  2101
                        { /* MOV Rm, Rn */
nkeynes@359
  2102
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2103
                        load_reg( R_EAX, Rm );
nkeynes@359
  2104
                        store_reg( R_EAX, Rn );
nkeynes@359
  2105
                        }
nkeynes@359
  2106
                        break;
nkeynes@359
  2107
                    case 0x4:
nkeynes@359
  2108
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2109
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2110
                        load_reg( R_ECX, Rm );
nkeynes@359
  2111
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2112
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2113
                        store_reg( R_EAX, Rm );
nkeynes@359
  2114
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2115
                        store_reg( R_EAX, Rn );
nkeynes@417
  2116
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2117
                        }
nkeynes@359
  2118
                        break;
nkeynes@359
  2119
                    case 0x5:
nkeynes@359
  2120
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2121
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2122
                        load_reg( R_EAX, Rm );
nkeynes@374
  2123
                        check_ralign16( R_EAX );
nkeynes@361
  2124
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2125
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2126
                        store_reg( R_EAX, Rm );
nkeynes@361
  2127
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2128
                        store_reg( R_EAX, Rn );
nkeynes@417
  2129
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2130
                        }
nkeynes@359
  2131
                        break;
nkeynes@359
  2132
                    case 0x6:
nkeynes@359
  2133
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2134
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2135
                        load_reg( R_EAX, Rm );
nkeynes@386
  2136
                        check_ralign32( R_EAX );
nkeynes@361
  2137
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2138
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2139
                        store_reg( R_EAX, Rm );
nkeynes@361
  2140
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2141
                        store_reg( R_EAX, Rn );
nkeynes@417
  2142
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2143
                        }
nkeynes@359
  2144
                        break;
nkeynes@359
  2145
                    case 0x7:
nkeynes@359
  2146
                        { /* NOT Rm, Rn */
nkeynes@359
  2147
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2148
                        load_reg( R_EAX, Rm );
nkeynes@359
  2149
                        NOT_r32( R_EAX );
nkeynes@359
  2150
                        store_reg( R_EAX, Rn );
nkeynes@417
  2151
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2152
                        }
nkeynes@359
  2153
                        break;
nkeynes@359
  2154
                    case 0x8:
nkeynes@359
  2155
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2156
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2157
                        load_reg( R_EAX, Rm );
nkeynes@359
  2158
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2159
                        store_reg( R_EAX, Rn );
nkeynes@359
  2160
                        }
nkeynes@359
  2161
                        break;
nkeynes@359
  2162
                    case 0x9:
nkeynes@359
  2163
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2164
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2165
                        load_reg( R_EAX, Rm );
nkeynes@359
  2166
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2167
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2168
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2169
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2170
                        store_reg( R_ECX, Rn );
nkeynes@417
  2171
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2172
                        }
nkeynes@359
  2173
                        break;
nkeynes@359
  2174
                    case 0xA:
nkeynes@359
  2175
                        { /* NEGC Rm, Rn */
nkeynes@359
  2176
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2177
                        load_reg( R_EAX, Rm );
nkeynes@359
  2178
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2179
                        LDC_t();
nkeynes@359
  2180
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2181
                        store_reg( R_ECX, Rn );
nkeynes@359
  2182
                        SETC_t();
nkeynes@417
  2183
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2184
                        }
nkeynes@359
  2185
                        break;
nkeynes@359
  2186
                    case 0xB:
nkeynes@359
  2187
                        { /* NEG Rm, Rn */
nkeynes@359
  2188
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2189
                        load_reg( R_EAX, Rm );
nkeynes@359
  2190
                        NEG_r32( R_EAX );
nkeynes@359
  2191
                        store_reg( R_EAX, Rn );
nkeynes@417
  2192
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2193
                        }
nkeynes@359
  2194
                        break;
nkeynes@359
  2195
                    case 0xC:
nkeynes@359
  2196
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2197
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2198
                        load_reg( R_EAX, Rm );
nkeynes@361
  2199
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2200
                        store_reg( R_EAX, Rn );
nkeynes@359
  2201
                        }
nkeynes@359
  2202
                        break;
nkeynes@359
  2203
                    case 0xD:
nkeynes@359
  2204
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2205
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2206
                        load_reg( R_EAX, Rm );
nkeynes@361
  2207
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2208
                        store_reg( R_EAX, Rn );
nkeynes@359
  2209
                        }
nkeynes@359
  2210
                        break;
nkeynes@359
  2211
                    case 0xE:
nkeynes@359
  2212
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2213
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2214
                        load_reg( R_EAX, Rm );
nkeynes@359
  2215
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2216
                        store_reg( R_EAX, Rn );
nkeynes@359
  2217
                        }
nkeynes@359
  2218
                        break;
nkeynes@359
  2219
                    case 0xF:
nkeynes@359
  2220
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2221
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2222
                        load_reg( R_EAX, Rm );
nkeynes@361
  2223
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2224
                        store_reg( R_EAX, Rn );
nkeynes@359
  2225
                        }
nkeynes@359
  2226
                        break;
nkeynes@359
  2227
                }
nkeynes@359
  2228
                break;
nkeynes@359
  2229
            case 0x7:
nkeynes@359
  2230
                { /* ADD #imm, Rn */
nkeynes@359
  2231
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2232
                load_reg( R_EAX, Rn );
nkeynes@359
  2233
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2234
                store_reg( R_EAX, Rn );
nkeynes@417
  2235
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2236
                }
nkeynes@359
  2237
                break;
nkeynes@359
  2238
            case 0x8:
nkeynes@359
  2239
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2240
                    case 0x0:
nkeynes@359
  2241
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2242
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2243
                        load_reg( R_EAX, 0 );
nkeynes@359
  2244
                        load_reg( R_ECX, Rn );
nkeynes@359
  2245
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2246
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2247
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2248
                        }
nkeynes@359
  2249
                        break;
nkeynes@359
  2250
                    case 0x1:
nkeynes@359
  2251
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2252
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2253
                        load_reg( R_ECX, Rn );
nkeynes@361
  2254
                        load_reg( R_EAX, 0 );
nkeynes@361
  2255
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2256
                        check_walign16( R_ECX );
nkeynes@361
  2257
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2258
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2259
                        }
nkeynes@359
  2260
                        break;
nkeynes@359
  2261
                    case 0x4:
nkeynes@359
  2262
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2263
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2264
                        load_reg( R_ECX, Rm );
nkeynes@359
  2265
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2266
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2267
                        store_reg( R_EAX, 0 );
nkeynes@417
  2268
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2269
                        }
nkeynes@359
  2270
                        break;
nkeynes@359
  2271
                    case 0x5:
nkeynes@359
  2272
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2273
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2274
                        load_reg( R_ECX, Rm );
nkeynes@361
  2275
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2276
                        check_ralign16( R_ECX );
nkeynes@361
  2277
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2278
                        store_reg( R_EAX, 0 );
nkeynes@417
  2279
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2280
                        }
nkeynes@359
  2281
                        break;
nkeynes@359
  2282
                    case 0x8:
nkeynes@359
  2283
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2284
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2285
                        load_reg( R_EAX, 0 );
nkeynes@359
  2286
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2287
                        SETE_t();
nkeynes@417
  2288
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2289
                        }
nkeynes@359
  2290
                        break;
nkeynes@359
  2291
                    case 0x9:
nkeynes@359
  2292
                        { /* BT disp */
nkeynes@359
  2293
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2294
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2295
                    	SLOTILLEGAL();
nkeynes@374
  2296
                        } else {
nkeynes@527
  2297
                    	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2298
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2299
                    	JMP_TARGET(nottaken);
nkeynes@408
  2300
                    	return 2;
nkeynes@374
  2301
                        }
nkeynes@359
  2302
                        }
nkeynes@359
  2303
                        break;
nkeynes@359
  2304
                    case 0xB:
nkeynes@359
  2305
                        { /* BF disp */
nkeynes@359
  2306
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2307
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2308
                    	SLOTILLEGAL();
nkeynes@374
  2309
                        } else {
nkeynes@527
  2310
                    	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2311
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2312
                    	JMP_TARGET(nottaken);
nkeynes@408
  2313
                    	return 2;
nkeynes@374
  2314
                        }
nkeynes@359
  2315
                        }
nkeynes@359
  2316
                        break;
nkeynes@359
  2317
                    case 0xD:
nkeynes@359
  2318
                        { /* BT/S disp */
nkeynes@359
  2319
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2320
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2321
                    	SLOTILLEGAL();
nkeynes@374
  2322
                        } else {
nkeynes@408
  2323
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2324
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2325
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2326
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2327
                    	}
nkeynes@417
  2328
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2329
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2330
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2331
                    	// not taken
nkeynes@408
  2332
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2333
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2334
                    	return 4;
nkeynes@374
  2335
                        }
nkeynes@359
  2336
                        }
nkeynes@359
  2337
                        break;
nkeynes@359
  2338
                    case 0xF:
nkeynes@359
  2339
                        { /* BF/S disp */
nkeynes@359
  2340
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2341
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2342
                    	SLOTILLEGAL();
nkeynes@374
  2343
                        } else {
nkeynes@408
  2344
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2345
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2346
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2347
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2348
                    	}
nkeynes@417
  2349
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2350
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2351
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2352
                    	// not taken
nkeynes@408
  2353
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2354
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2355
                    	return 4;
nkeynes@374
  2356
                        }
nkeynes@359
  2357
                        }
nkeynes@359
  2358
                        break;
nkeynes@359
  2359
                    default:
nkeynes@359
  2360
                        UNDEF();
nkeynes@359
  2361
                        break;
nkeynes@359
  2362
                }
nkeynes@359
  2363
                break;
nkeynes@359
  2364
            case 0x9:
nkeynes@359
  2365
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2366
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2367
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2368
            	SLOTILLEGAL();
nkeynes@374
  2369
                } else {
nkeynes@374
  2370
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2371
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2372
            	store_reg( R_EAX, Rn );
nkeynes@417
  2373
            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2374
                }
nkeynes@359
  2375
                }
nkeynes@359
  2376
                break;
nkeynes@359
  2377
            case 0xA:
nkeynes@359
  2378
                { /* BRA disp */
nkeynes@359
  2379
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2380
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2381
            	SLOTILLEGAL();
nkeynes@374
  2382
                } else {
nkeynes@374
  2383
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2384
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2385
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2386
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2387
            	return 4;
nkeynes@374
  2388
                }
nkeynes@359
  2389
                }
nkeynes@359
  2390
                break;
nkeynes@359
  2391
            case 0xB:
nkeynes@359
  2392
                { /* BSR disp */
nkeynes@359
  2393
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2394
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2395
            	SLOTILLEGAL();
nkeynes@374
  2396
                } else {
nkeynes@374
  2397
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2398
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2399
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2400
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2401
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2402
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2403
            	return 4;
nkeynes@374
  2404
                }
nkeynes@359
  2405
                }
nkeynes@359
  2406
                break;
nkeynes@359
  2407
            case 0xC:
nkeynes@359
  2408
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2409
                    case 0x0:
nkeynes@359
  2410
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2411
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2412
                        load_reg( R_EAX, 0 );
nkeynes@359
  2413
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2414
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2415
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2416
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2417
                        }
nkeynes@359
  2418
                        break;
nkeynes@359
  2419
                    case 0x1:
nkeynes@359
  2420
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2421
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2422
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2423
                        load_reg( R_EAX, 0 );
nkeynes@361
  2424
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2425
                        check_walign16( R_ECX );
nkeynes@361
  2426
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2427
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2428
                        }
nkeynes@359
  2429
                        break;
nkeynes@359
  2430
                    case 0x2:
nkeynes@359
  2431
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2432
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2433
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2434
                        load_reg( R_EAX, 0 );
nkeynes@361
  2435
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2436
                        check_walign32( R_ECX );
nkeynes@361
  2437
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2438
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2439
                        }
nkeynes@359
  2440
                        break;
nkeynes@359
  2441
                    case 0x3:
nkeynes@359
  2442
                        { /* TRAPA #imm */
nkeynes@359
  2443
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2444
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2445
                    	SLOTILLEGAL();
nkeynes@374
  2446
                        } else {
nkeynes@533
  2447
                    	load_imm32( R_ECX, pc+2 );
nkeynes@533
  2448
                    	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  2449
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2450
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2451
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2452
                    	exit_block_pcset(pc);
nkeynes@409
  2453
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2454
                    	return 2;
nkeynes@374
  2455
                        }
nkeynes@359
  2456
                        }
nkeynes@359
  2457
                        break;
nkeynes@359
  2458
                    case 0x4:
nkeynes@359
  2459
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2460
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2461
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2462
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2463
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2464
                        store_reg( R_EAX, 0 );
nkeynes@417
  2465
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2466
                        }
nkeynes@359
  2467
                        break;
nkeynes@359
  2468
                    case 0x5:
nkeynes@359
  2469
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2470
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2471
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2472
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2473
                        check_ralign16( R_ECX );
nkeynes@361
  2474
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2475
                        store_reg( R_EAX, 0 );
nkeynes@417
  2476
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2477
                        }
nkeynes@359
  2478
                        break;
nkeynes@359
  2479
                    case 0x6:
nkeynes@359
  2480
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2481
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2482
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2483
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2484
                        check_ralign32( R_ECX );
nkeynes@361
  2485
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2486
                        store_reg( R_EAX, 0 );
nkeynes@417
  2487
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2488
                        }
nkeynes@359
  2489
                        break;
nkeynes@359
  2490
                    case 0x7:
nkeynes@359
  2491
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2492
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2493
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2494
                    	SLOTILLEGAL();
nkeynes@374
  2495
                        } else {
nkeynes@374
  2496
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2497
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2498
                        }
nkeynes@359
  2499
                        }
nkeynes@359
  2500
                        break;
nkeynes@359
  2501
                    case 0x8:
nkeynes@359
  2502
                        { /* TST #imm, R0 */
nkeynes@359
  2503
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2504
                        load_reg( R_EAX, 0 );
nkeynes@368
  2505
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2506
                        SETE_t();
nkeynes@417
  2507
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2508
                        }
nkeynes@359
  2509
                        break;
nkeynes@359
  2510
                    case 0x9:
nkeynes@359
  2511
                        { /* AND #imm, R0 */
nkeynes@359
  2512
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2513
                        load_reg( R_EAX, 0 );
nkeynes@359
  2514
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2515
                        store_reg( R_EAX, 0 );
nkeynes@417
  2516
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2517
                        }
nkeynes@359
  2518
                        break;
nkeynes@359
  2519
                    case 0xA:
nkeynes@359
  2520
                        { /* XOR #imm, R0 */
nkeynes@359
  2521
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2522
                        load_reg( R_EAX, 0 );
nkeynes@359
  2523
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2524
                        store_reg( R_EAX, 0 );
nkeynes@417
  2525
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
                        }
nkeynes@359
  2527
                        break;
nkeynes@359
  2528
                    case 0xB:
nkeynes@359
  2529
                        { /* OR #imm, R0 */
nkeynes@359
  2530
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2531
                        load_reg( R_EAX, 0 );
nkeynes@359
  2532
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2533
                        store_reg( R_EAX, 0 );
nkeynes@417
  2534
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2535
                        }
nkeynes@359
  2536
                        break;
nkeynes@359
  2537
                    case 0xC:
nkeynes@359
  2538
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2539
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2540
                        load_reg( R_EAX, 0);
nkeynes@368
  2541
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2542
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2543
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  2544
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2545
                        SETE_t();
nkeynes@417
  2546
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2547
                        }
nkeynes@359
  2548
                        break;
nkeynes@359
  2549
                    case 0xD:
nkeynes@359
  2550
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2551
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2552
                        load_reg( R_EAX, 0 );
nkeynes@359
  2553
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2554
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2555
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2556
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2557
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2558
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2559
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2560
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2561
                        }
nkeynes@359
  2562
                        break;
nkeynes@359
  2563
                    case 0xE:
nkeynes@359
  2564
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2565
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2566
                        load_reg( R_EAX, 0 );
nkeynes@359
  2567
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2568
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2569
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2570
                        MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
  2571
                        POP_realigned_r32(R_ECX);
nkeynes@359
  2572
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2573
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2574
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2575
                        }
nkeynes@359
  2576
                        break;
nkeynes@359
  2577
                    case 0xF:
nkeynes@359
  2578
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2579
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2580
                        load_reg( R_EAX, 0 );
nkeynes@374
  2581
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2582
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2583
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2584
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2585
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2586
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2587
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2588
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2589
                        }
nkeynes@359
  2590
                        break;
nkeynes@359
  2591
                }
nkeynes@359
  2592
                break;
nkeynes@359
  2593
            case 0xD:
nkeynes@359
  2594
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2595
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2596
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2597
            	SLOTILLEGAL();
nkeynes@374
  2598
                } else {
nkeynes@388
  2599
            	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@559
  2600
            	sh4ptr_t ptr = sh4_get_region_by_vma(target);
nkeynes@388
  2601
            	if( ptr != NULL ) {
nkeynes@527
  2602
            	    MOV_moff32_EAX( ptr );
nkeynes@388
  2603
            	} else {
nkeynes@388
  2604
            	    load_imm32( R_ECX, target );
nkeynes@388
  2605
            	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  2606
            	}
nkeynes@386
  2607
            	store_reg( R_EAX, Rn );
nkeynes@417
  2608
            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2609
                }
nkeynes@359
  2610
                }
nkeynes@359
  2611
                break;
nkeynes@359
  2612
            case 0xE:
nkeynes@359
  2613
                { /* MOV #imm, Rn */
nkeynes@359
  2614
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2615
                load_imm32( R_EAX, imm );
nkeynes@359
  2616
                store_reg( R_EAX, Rn );
nkeynes@359
  2617
                }
nkeynes@359
  2618
                break;
nkeynes@359
  2619
            case 0xF:
nkeynes@359
  2620
                switch( ir&0xF ) {
nkeynes@359
  2621
                    case 0x0:
nkeynes@359
  2622
                        { /* FADD FRm, FRn */
nkeynes@359
  2623
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2624
                        check_fpuen();
nkeynes@377
  2625
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2626
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2627
                        load_fr_bank( R_EDX );
nkeynes@380
  2628
                        JNE_rel8(13,doubleprec);
nkeynes@377
  2629
                        push_fr(R_EDX, FRm);
nkeynes@377
  2630
                        push_fr(R_EDX, FRn);
nkeynes@377
  2631
                        FADDP_st(1);
nkeynes@377
  2632
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2633
                        JMP_rel8(11,end);
nkeynes@380
  2634
                        JMP_TARGET(doubleprec);
nkeynes@377
  2635
                        push_dr(R_EDX, FRm);
nkeynes@377
  2636
                        push_dr(R_EDX, FRn);
nkeynes@377
  2637
                        FADDP_st(1);
nkeynes@377
  2638
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2639
                        JMP_TARGET(end);
nkeynes@417
  2640
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2641
                        }
nkeynes@359
  2642
                        break;
nkeynes@359
  2643
                    case 0x1:
nkeynes@359
  2644
                        { /* FSUB FRm, FRn */
nkeynes@359
  2645
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2646
                        check_fpuen();
nkeynes@377
  2647
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2648
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2649
                        load_fr_bank( R_EDX );
nkeynes@380
  2650
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2651
                        push_fr(R_EDX, FRn);
nkeynes@377
  2652
                        push_fr(R_EDX, FRm);
nkeynes@388
  2653
                        FSUBP_st(1);
nkeynes@377
  2654
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2655
                        JMP_rel8(11, end);
nkeynes@380
  2656
                        JMP_TARGET(doubleprec);
nkeynes@377
  2657
                        push_dr(R_EDX, FRn);
nkeynes@377
  2658
                        push_dr(R_EDX, FRm);
nkeynes@388
  2659
                        FSUBP_st(1);
nkeynes@377
  2660
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2661
                        JMP_TARGET(end);
nkeynes@417
  2662
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2663
                        }
nkeynes@359
  2664
                        break;
nkeynes@359
  2665
                    case 0x2:
nkeynes@359
  2666
                        { /* FMUL FRm, FRn */
nkeynes@359
  2667
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2668
                        check_fpuen();
nkeynes@377
  2669
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2670
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2671
                        load_fr_bank( R_EDX );
nkeynes@380
  2672
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2673
                        push_fr(R_EDX, FRm);
nkeynes@377
  2674
                        push_fr(R_EDX, FRn);
nkeynes@377
  2675
                        FMULP_st(1);
nkeynes@377
  2676
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2677
                        JMP_rel8(11, end);
nkeynes@380
  2678
                        JMP_TARGET(doubleprec);
nkeynes@377
  2679
                        push_dr(R_EDX, FRm);
nkeynes@377
  2680
                        push_dr(R_EDX, FRn);
nkeynes@377
  2681
                        FMULP_st(1);
nkeynes@377
  2682
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2683
                        JMP_TARGET(end);
nkeynes@417
  2684
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2685
                        }
nkeynes@359
  2686
                        break;
nkeynes@359
  2687
                    case 0x3:
nkeynes@359
  2688
                        { /* FDIV FRm, FRn */
nkeynes@359
  2689
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2690
                        check_fpuen();
nkeynes@377
  2691
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2692
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2693
                        load_fr_bank( R_EDX );
nkeynes@380
  2694
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2695
                        push_fr(R_EDX, FRn);
nkeynes@377
  2696
                        push_fr(R_EDX, FRm);
nkeynes@377
  2697
                        FDIVP_st(1);
nkeynes@377
  2698
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2699
                        JMP_rel8(11, end);
nkeynes@380
  2700
                        JMP_TARGET(doubleprec);
nkeynes@377
  2701
                        push_dr(R_EDX, FRn);
nkeynes@377
  2702
                        push_dr(R_EDX, FRm);
nkeynes@377
  2703
                        FDIVP_st(1);
nkeynes@377
  2704
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2705
                        JMP_TARGET(end);
nkeynes@417
  2706
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2707
                        }
nkeynes@359
  2708
                        break;
nkeynes@359
  2709
                    case 0x4:
nkeynes@359
  2710
                        { /* FCMP/EQ FRm, FRn */