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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 561:533f6b478071
prev559:06714bc64271
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
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last change Enable Id keyword on all source files
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_READ_SIZE  (CALL_FUNC1_SIZE+8)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE+8)
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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extern uint16_t *sh4_icache;
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extern uint32_t sh4_icache_addr;
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/****** Import appropriate calling conventions ******/
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#if SH4_TRANSLATOR == TARGET_X86_64
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#include "sh4/ia64abi.h"
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#else /* SH4_TRANSLATOR == TARGET_X86 */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
nkeynes@539
   333
#endif
nkeynes@539
   334
nkeynes@539
   335
nkeynes@359
   336
/**
nkeynes@359
   337
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   338
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   339
 * 
nkeynes@359
   340
 *
nkeynes@359
   341
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   342
 * (eg a branch or 
nkeynes@359
   343
 */
nkeynes@526
   344
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   345
{
nkeynes@388
   346
    uint32_t ir;
nkeynes@388
   347
    /* Read instruction */
nkeynes@388
   348
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   349
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   350
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   351
    } else {
nkeynes@559
   352
	uint64_t phys = mmu_vma_to_phys_exec(pc);
nkeynes@559
   353
	sh4_icache = (uint16_t *)mem_get_page((uint32_t)phys);
nkeynes@527
   354
	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   355
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   356
	     * region, fallback on the full-blown memory read
nkeynes@388
   357
	     */
nkeynes@388
   358
	    sh4_icache = NULL;
nkeynes@388
   359
	    ir = sh4_read_word(pc);
nkeynes@388
   360
	} else {
nkeynes@388
   361
	    sh4_icache_addr = pageaddr;
nkeynes@388
   362
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   363
	}
nkeynes@388
   364
    }
nkeynes@388
   365
nkeynes@359
   366
%%
nkeynes@359
   367
/* ALU operations */
nkeynes@359
   368
ADD Rm, Rn {:
nkeynes@359
   369
    load_reg( R_EAX, Rm );
nkeynes@359
   370
    load_reg( R_ECX, Rn );
nkeynes@359
   371
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   372
    store_reg( R_ECX, Rn );
nkeynes@417
   373
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   374
:}
nkeynes@359
   375
ADD #imm, Rn {:  
nkeynes@359
   376
    load_reg( R_EAX, Rn );
nkeynes@359
   377
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   378
    store_reg( R_EAX, Rn );
nkeynes@417
   379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   380
:}
nkeynes@359
   381
ADDC Rm, Rn {:
nkeynes@417
   382
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   383
	LDC_t();
nkeynes@417
   384
    }
nkeynes@359
   385
    load_reg( R_EAX, Rm );
nkeynes@359
   386
    load_reg( R_ECX, Rn );
nkeynes@359
   387
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   388
    store_reg( R_ECX, Rn );
nkeynes@359
   389
    SETC_t();
nkeynes@417
   390
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   391
:}
nkeynes@359
   392
ADDV Rm, Rn {:
nkeynes@359
   393
    load_reg( R_EAX, Rm );
nkeynes@359
   394
    load_reg( R_ECX, Rn );
nkeynes@359
   395
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   396
    store_reg( R_ECX, Rn );
nkeynes@359
   397
    SETO_t();
nkeynes@417
   398
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   399
:}
nkeynes@359
   400
AND Rm, Rn {:
nkeynes@359
   401
    load_reg( R_EAX, Rm );
nkeynes@359
   402
    load_reg( R_ECX, Rn );
nkeynes@359
   403
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   404
    store_reg( R_ECX, Rn );
nkeynes@417
   405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   406
:}
nkeynes@359
   407
AND #imm, R0 {:  
nkeynes@359
   408
    load_reg( R_EAX, 0 );
nkeynes@359
   409
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   410
    store_reg( R_EAX, 0 );
nkeynes@417
   411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   412
:}
nkeynes@359
   413
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   414
    load_reg( R_EAX, 0 );
nkeynes@359
   415
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   416
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   417
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   418
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   419
    POP_realigned_r32(R_ECX);
nkeynes@386
   420
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   421
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   423
:}
nkeynes@359
   424
CMP/EQ Rm, Rn {:  
nkeynes@359
   425
    load_reg( R_EAX, Rm );
nkeynes@359
   426
    load_reg( R_ECX, Rn );
nkeynes@359
   427
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   428
    SETE_t();
nkeynes@417
   429
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   430
:}
nkeynes@359
   431
CMP/EQ #imm, R0 {:  
nkeynes@359
   432
    load_reg( R_EAX, 0 );
nkeynes@359
   433
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   434
    SETE_t();
nkeynes@417
   435
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   436
:}
nkeynes@359
   437
CMP/GE Rm, Rn {:  
nkeynes@359
   438
    load_reg( R_EAX, Rm );
nkeynes@359
   439
    load_reg( R_ECX, Rn );
nkeynes@359
   440
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   441
    SETGE_t();
nkeynes@417
   442
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   443
:}
nkeynes@359
   444
CMP/GT Rm, Rn {: 
nkeynes@359
   445
    load_reg( R_EAX, Rm );
nkeynes@359
   446
    load_reg( R_ECX, Rn );
nkeynes@359
   447
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   448
    SETG_t();
nkeynes@417
   449
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   450
:}
nkeynes@359
   451
CMP/HI Rm, Rn {:  
nkeynes@359
   452
    load_reg( R_EAX, Rm );
nkeynes@359
   453
    load_reg( R_ECX, Rn );
nkeynes@359
   454
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   455
    SETA_t();
nkeynes@417
   456
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   457
:}
nkeynes@359
   458
CMP/HS Rm, Rn {: 
nkeynes@359
   459
    load_reg( R_EAX, Rm );
nkeynes@359
   460
    load_reg( R_ECX, Rn );
nkeynes@359
   461
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   462
    SETAE_t();
nkeynes@417
   463
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   464
 :}
nkeynes@359
   465
CMP/PL Rn {: 
nkeynes@359
   466
    load_reg( R_EAX, Rn );
nkeynes@359
   467
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   468
    SETG_t();
nkeynes@417
   469
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   470
:}
nkeynes@359
   471
CMP/PZ Rn {:  
nkeynes@359
   472
    load_reg( R_EAX, Rn );
nkeynes@359
   473
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   474
    SETGE_t();
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   476
:}
nkeynes@361
   477
CMP/STR Rm, Rn {:  
nkeynes@368
   478
    load_reg( R_EAX, Rm );
nkeynes@368
   479
    load_reg( R_ECX, Rn );
nkeynes@368
   480
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   481
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   482
    JE_rel8(13, target1);
nkeynes@368
   483
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   484
    JE_rel8(9, target2);
nkeynes@368
   485
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   486
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   487
    JE_rel8(2, target3);
nkeynes@368
   488
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   489
    JMP_TARGET(target1);
nkeynes@380
   490
    JMP_TARGET(target2);
nkeynes@380
   491
    JMP_TARGET(target3);
nkeynes@368
   492
    SETE_t();
nkeynes@417
   493
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   494
:}
nkeynes@361
   495
DIV0S Rm, Rn {:
nkeynes@361
   496
    load_reg( R_EAX, Rm );
nkeynes@386
   497
    load_reg( R_ECX, Rn );
nkeynes@361
   498
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   499
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   500
    store_spreg( R_EAX, R_M );
nkeynes@361
   501
    store_spreg( R_ECX, R_Q );
nkeynes@361
   502
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   503
    SETNE_t();
nkeynes@417
   504
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   505
:}
nkeynes@361
   506
DIV0U {:  
nkeynes@361
   507
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   508
    store_spreg( R_EAX, R_Q );
nkeynes@361
   509
    store_spreg( R_EAX, R_M );
nkeynes@361
   510
    store_spreg( R_EAX, R_T );
nkeynes@417
   511
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   512
:}
nkeynes@386
   513
DIV1 Rm, Rn {:
nkeynes@386
   514
    load_spreg( R_ECX, R_M );
nkeynes@386
   515
    load_reg( R_EAX, Rn );
nkeynes@417
   516
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   517
	LDC_t();
nkeynes@417
   518
    }
nkeynes@386
   519
    RCL1_r32( R_EAX );
nkeynes@386
   520
    SETC_r8( R_DL ); // Q'
nkeynes@386
   521
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   522
    JE_rel8(5, mqequal);
nkeynes@386
   523
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   524
    JMP_rel8(3, end);
nkeynes@380
   525
    JMP_TARGET(mqequal);
nkeynes@386
   526
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   527
    JMP_TARGET(end);
nkeynes@386
   528
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   529
    SETC_r8(R_AL); // tmp1
nkeynes@386
   530
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   531
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   532
    store_spreg( R_ECX, R_Q );
nkeynes@386
   533
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   534
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   535
    store_spreg( R_EAX, R_T );
nkeynes@417
   536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   537
:}
nkeynes@361
   538
DMULS.L Rm, Rn {:  
nkeynes@361
   539
    load_reg( R_EAX, Rm );
nkeynes@361
   540
    load_reg( R_ECX, Rn );
nkeynes@361
   541
    IMUL_r32(R_ECX);
nkeynes@361
   542
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   543
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   544
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   545
:}
nkeynes@361
   546
DMULU.L Rm, Rn {:  
nkeynes@361
   547
    load_reg( R_EAX, Rm );
nkeynes@361
   548
    load_reg( R_ECX, Rn );
nkeynes@361
   549
    MUL_r32(R_ECX);
nkeynes@361
   550
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   551
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   552
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   553
:}
nkeynes@359
   554
DT Rn {:  
nkeynes@359
   555
    load_reg( R_EAX, Rn );
nkeynes@382
   556
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   557
    store_reg( R_EAX, Rn );
nkeynes@359
   558
    SETE_t();
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   560
:}
nkeynes@359
   561
EXTS.B Rm, Rn {:  
nkeynes@359
   562
    load_reg( R_EAX, Rm );
nkeynes@359
   563
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   564
    store_reg( R_EAX, Rn );
nkeynes@359
   565
:}
nkeynes@361
   566
EXTS.W Rm, Rn {:  
nkeynes@361
   567
    load_reg( R_EAX, Rm );
nkeynes@361
   568
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   569
    store_reg( R_EAX, Rn );
nkeynes@361
   570
:}
nkeynes@361
   571
EXTU.B Rm, Rn {:  
nkeynes@361
   572
    load_reg( R_EAX, Rm );
nkeynes@361
   573
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   574
    store_reg( R_EAX, Rn );
nkeynes@361
   575
:}
nkeynes@361
   576
EXTU.W Rm, Rn {:  
nkeynes@361
   577
    load_reg( R_EAX, Rm );
nkeynes@361
   578
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   579
    store_reg( R_EAX, Rn );
nkeynes@361
   580
:}
nkeynes@386
   581
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   582
    load_reg( R_ECX, Rm );
nkeynes@386
   583
    check_ralign32( R_ECX );
nkeynes@386
   584
    load_reg( R_ECX, Rn );
nkeynes@386
   585
    check_ralign32( R_ECX );
nkeynes@386
   586
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   587
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   588
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   589
    load_reg( R_ECX, Rm );
nkeynes@386
   590
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   591
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   592
    POP_realigned_r32( R_ECX );
nkeynes@386
   593
    IMUL_r32( R_ECX );
nkeynes@386
   594
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   595
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   596
nkeynes@386
   597
    load_spreg( R_ECX, R_S );
nkeynes@386
   598
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   599
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   600
    call_func0( signsat48 );
nkeynes@386
   601
    JMP_TARGET( nosat );
nkeynes@417
   602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   603
:}
nkeynes@386
   604
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   605
    load_reg( R_ECX, Rm );
nkeynes@386
   606
    check_ralign16( R_ECX );
nkeynes@386
   607
    load_reg( R_ECX, Rn );
nkeynes@386
   608
    check_ralign16( R_ECX );
nkeynes@386
   609
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   610
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   611
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   612
    load_reg( R_ECX, Rm );
nkeynes@386
   613
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   614
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   615
    POP_realigned_r32( R_ECX );
nkeynes@386
   616
    IMUL_r32( R_ECX );
nkeynes@386
   617
nkeynes@386
   618
    load_spreg( R_ECX, R_S );
nkeynes@386
   619
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   620
    JE_rel8( 47, nosat );
nkeynes@386
   621
nkeynes@386
   622
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   623
    JNO_rel8( 51, end );            // 2
nkeynes@386
   624
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   625
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   626
    JS_rel8( 13, positive );        // 2
nkeynes@386
   627
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   628
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   629
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   630
nkeynes@386
   631
    JMP_TARGET(positive);
nkeynes@386
   632
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   633
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   634
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   635
nkeynes@386
   636
    JMP_TARGET(nosat);
nkeynes@386
   637
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   638
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   639
    JMP_TARGET(end);
nkeynes@386
   640
    JMP_TARGET(end2);
nkeynes@386
   641
    JMP_TARGET(end3);
nkeynes@417
   642
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   643
:}
nkeynes@359
   644
MOVT Rn {:  
nkeynes@359
   645
    load_spreg( R_EAX, R_T );
nkeynes@359
   646
    store_reg( R_EAX, Rn );
nkeynes@359
   647
:}
nkeynes@361
   648
MUL.L Rm, Rn {:  
nkeynes@361
   649
    load_reg( R_EAX, Rm );
nkeynes@361
   650
    load_reg( R_ECX, Rn );
nkeynes@361
   651
    MUL_r32( R_ECX );
nkeynes@361
   652
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   653
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   654
:}
nkeynes@374
   655
MULS.W Rm, Rn {:
nkeynes@374
   656
    load_reg16s( R_EAX, Rm );
nkeynes@374
   657
    load_reg16s( R_ECX, Rn );
nkeynes@374
   658
    MUL_r32( R_ECX );
nkeynes@374
   659
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   660
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   661
:}
nkeynes@374
   662
MULU.W Rm, Rn {:  
nkeynes@374
   663
    load_reg16u( R_EAX, Rm );
nkeynes@374
   664
    load_reg16u( R_ECX, Rn );
nkeynes@374
   665
    MUL_r32( R_ECX );
nkeynes@374
   666
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   667
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   668
:}
nkeynes@359
   669
NEG Rm, Rn {:
nkeynes@359
   670
    load_reg( R_EAX, Rm );
nkeynes@359
   671
    NEG_r32( R_EAX );
nkeynes@359
   672
    store_reg( R_EAX, Rn );
nkeynes@417
   673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   674
:}
nkeynes@359
   675
NEGC Rm, Rn {:  
nkeynes@359
   676
    load_reg( R_EAX, Rm );
nkeynes@359
   677
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   678
    LDC_t();
nkeynes@359
   679
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   680
    store_reg( R_ECX, Rn );
nkeynes@359
   681
    SETC_t();
nkeynes@417
   682
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   683
:}
nkeynes@359
   684
NOT Rm, Rn {:  
nkeynes@359
   685
    load_reg( R_EAX, Rm );
nkeynes@359
   686
    NOT_r32( R_EAX );
nkeynes@359
   687
    store_reg( R_EAX, Rn );
nkeynes@417
   688
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   689
:}
nkeynes@359
   690
OR Rm, Rn {:  
nkeynes@359
   691
    load_reg( R_EAX, Rm );
nkeynes@359
   692
    load_reg( R_ECX, Rn );
nkeynes@359
   693
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   694
    store_reg( R_ECX, Rn );
nkeynes@417
   695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   696
:}
nkeynes@359
   697
OR #imm, R0 {:
nkeynes@359
   698
    load_reg( R_EAX, 0 );
nkeynes@359
   699
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   700
    store_reg( R_EAX, 0 );
nkeynes@417
   701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   702
:}
nkeynes@374
   703
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   704
    load_reg( R_EAX, 0 );
nkeynes@374
   705
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   706
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   707
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   708
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   709
    POP_realigned_r32(R_ECX);
nkeynes@386
   710
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   711
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   712
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   713
:}
nkeynes@359
   714
ROTCL Rn {:
nkeynes@359
   715
    load_reg( R_EAX, Rn );
nkeynes@417
   716
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   717
	LDC_t();
nkeynes@417
   718
    }
nkeynes@359
   719
    RCL1_r32( R_EAX );
nkeynes@359
   720
    store_reg( R_EAX, Rn );
nkeynes@359
   721
    SETC_t();
nkeynes@417
   722
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   723
:}
nkeynes@359
   724
ROTCR Rn {:  
nkeynes@359
   725
    load_reg( R_EAX, Rn );
nkeynes@417
   726
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   727
	LDC_t();
nkeynes@417
   728
    }
nkeynes@359
   729
    RCR1_r32( R_EAX );
nkeynes@359
   730
    store_reg( R_EAX, Rn );
nkeynes@359
   731
    SETC_t();
nkeynes@417
   732
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   733
:}
nkeynes@359
   734
ROTL Rn {:  
nkeynes@359
   735
    load_reg( R_EAX, Rn );
nkeynes@359
   736
    ROL1_r32( R_EAX );
nkeynes@359
   737
    store_reg( R_EAX, Rn );
nkeynes@359
   738
    SETC_t();
nkeynes@417
   739
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   740
:}
nkeynes@359
   741
ROTR Rn {:  
nkeynes@359
   742
    load_reg( R_EAX, Rn );
nkeynes@359
   743
    ROR1_r32( R_EAX );
nkeynes@359
   744
    store_reg( R_EAX, Rn );
nkeynes@359
   745
    SETC_t();
nkeynes@417
   746
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   747
:}
nkeynes@359
   748
SHAD Rm, Rn {:
nkeynes@359
   749
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   750
    load_reg( R_EAX, Rn );
nkeynes@361
   751
    load_reg( R_ECX, Rm );
nkeynes@361
   752
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   753
    JGE_rel8(16, doshl);
nkeynes@361
   754
                    
nkeynes@361
   755
    NEG_r32( R_ECX );      // 2
nkeynes@361
   756
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   757
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   758
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   759
    JMP_rel8(10, end);          // 2
nkeynes@386
   760
nkeynes@386
   761
    JMP_TARGET(emptysar);
nkeynes@386
   762
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   763
    JMP_rel8(5, end2);
nkeynes@382
   764
nkeynes@380
   765
    JMP_TARGET(doshl);
nkeynes@361
   766
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   767
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   768
    JMP_TARGET(end);
nkeynes@386
   769
    JMP_TARGET(end2);
nkeynes@361
   770
    store_reg( R_EAX, Rn );
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   772
:}
nkeynes@359
   773
SHLD Rm, Rn {:  
nkeynes@368
   774
    load_reg( R_EAX, Rn );
nkeynes@368
   775
    load_reg( R_ECX, Rm );
nkeynes@382
   776
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   777
    JGE_rel8(15, doshl);
nkeynes@368
   778
nkeynes@382
   779
    NEG_r32( R_ECX );      // 2
nkeynes@382
   780
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   781
    JE_rel8( 4, emptyshr );
nkeynes@382
   782
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   783
    JMP_rel8(9, end);          // 2
nkeynes@386
   784
nkeynes@386
   785
    JMP_TARGET(emptyshr);
nkeynes@386
   786
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   787
    JMP_rel8(5, end2);
nkeynes@382
   788
nkeynes@382
   789
    JMP_TARGET(doshl);
nkeynes@382
   790
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   791
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   792
    JMP_TARGET(end);
nkeynes@386
   793
    JMP_TARGET(end2);
nkeynes@368
   794
    store_reg( R_EAX, Rn );
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   796
:}
nkeynes@359
   797
SHAL Rn {: 
nkeynes@359
   798
    load_reg( R_EAX, Rn );
nkeynes@359
   799
    SHL1_r32( R_EAX );
nkeynes@397
   800
    SETC_t();
nkeynes@359
   801
    store_reg( R_EAX, Rn );
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   803
:}
nkeynes@359
   804
SHAR Rn {:  
nkeynes@359
   805
    load_reg( R_EAX, Rn );
nkeynes@359
   806
    SAR1_r32( R_EAX );
nkeynes@397
   807
    SETC_t();
nkeynes@359
   808
    store_reg( R_EAX, Rn );
nkeynes@417
   809
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   810
:}
nkeynes@359
   811
SHLL Rn {:  
nkeynes@359
   812
    load_reg( R_EAX, Rn );
nkeynes@359
   813
    SHL1_r32( R_EAX );
nkeynes@397
   814
    SETC_t();
nkeynes@359
   815
    store_reg( R_EAX, Rn );
nkeynes@417
   816
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   817
:}
nkeynes@359
   818
SHLL2 Rn {:
nkeynes@359
   819
    load_reg( R_EAX, Rn );
nkeynes@359
   820
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   821
    store_reg( R_EAX, Rn );
nkeynes@417
   822
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   823
:}
nkeynes@359
   824
SHLL8 Rn {:  
nkeynes@359
   825
    load_reg( R_EAX, Rn );
nkeynes@359
   826
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   827
    store_reg( R_EAX, Rn );
nkeynes@417
   828
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   829
:}
nkeynes@359
   830
SHLL16 Rn {:  
nkeynes@359
   831
    load_reg( R_EAX, Rn );
nkeynes@359
   832
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   833
    store_reg( R_EAX, Rn );
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   835
:}
nkeynes@359
   836
SHLR Rn {:  
nkeynes@359
   837
    load_reg( R_EAX, Rn );
nkeynes@359
   838
    SHR1_r32( R_EAX );
nkeynes@397
   839
    SETC_t();
nkeynes@359
   840
    store_reg( R_EAX, Rn );
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   842
:}
nkeynes@359
   843
SHLR2 Rn {:  
nkeynes@359
   844
    load_reg( R_EAX, Rn );
nkeynes@359
   845
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   846
    store_reg( R_EAX, Rn );
nkeynes@417
   847
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   848
:}
nkeynes@359
   849
SHLR8 Rn {:  
nkeynes@359
   850
    load_reg( R_EAX, Rn );
nkeynes@359
   851
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   852
    store_reg( R_EAX, Rn );
nkeynes@417
   853
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   854
:}
nkeynes@359
   855
SHLR16 Rn {:  
nkeynes@359
   856
    load_reg( R_EAX, Rn );
nkeynes@359
   857
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, Rn );
nkeynes@417
   859
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   860
:}
nkeynes@359
   861
SUB Rm, Rn {:  
nkeynes@359
   862
    load_reg( R_EAX, Rm );
nkeynes@359
   863
    load_reg( R_ECX, Rn );
nkeynes@359
   864
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   865
    store_reg( R_ECX, Rn );
nkeynes@417
   866
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   867
:}
nkeynes@359
   868
SUBC Rm, Rn {:  
nkeynes@359
   869
    load_reg( R_EAX, Rm );
nkeynes@359
   870
    load_reg( R_ECX, Rn );
nkeynes@417
   871
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   872
	LDC_t();
nkeynes@417
   873
    }
nkeynes@359
   874
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   875
    store_reg( R_ECX, Rn );
nkeynes@394
   876
    SETC_t();
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   878
:}
nkeynes@359
   879
SUBV Rm, Rn {:  
nkeynes@359
   880
    load_reg( R_EAX, Rm );
nkeynes@359
   881
    load_reg( R_ECX, Rn );
nkeynes@359
   882
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   883
    store_reg( R_ECX, Rn );
nkeynes@359
   884
    SETO_t();
nkeynes@417
   885
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   886
:}
nkeynes@359
   887
SWAP.B Rm, Rn {:  
nkeynes@359
   888
    load_reg( R_EAX, Rm );
nkeynes@359
   889
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   890
    store_reg( R_EAX, Rn );
nkeynes@359
   891
:}
nkeynes@359
   892
SWAP.W Rm, Rn {:  
nkeynes@359
   893
    load_reg( R_EAX, Rm );
nkeynes@359
   894
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   895
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   896
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   897
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   898
    store_reg( R_ECX, Rn );
nkeynes@417
   899
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   900
:}
nkeynes@361
   901
TAS.B @Rn {:  
nkeynes@361
   902
    load_reg( R_ECX, Rn );
nkeynes@361
   903
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   904
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   905
    SETE_t();
nkeynes@361
   906
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   907
    load_reg( R_ECX, Rn );
nkeynes@361
   908
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   909
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   910
:}
nkeynes@361
   911
TST Rm, Rn {:  
nkeynes@361
   912
    load_reg( R_EAX, Rm );
nkeynes@361
   913
    load_reg( R_ECX, Rn );
nkeynes@361
   914
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   915
    SETE_t();
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   917
:}
nkeynes@368
   918
TST #imm, R0 {:  
nkeynes@368
   919
    load_reg( R_EAX, 0 );
nkeynes@368
   920
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   921
    SETE_t();
nkeynes@417
   922
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   923
:}
nkeynes@368
   924
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   925
    load_reg( R_EAX, 0);
nkeynes@368
   926
    load_reg( R_ECX, R_GBR);
nkeynes@368
   927
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   928
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
   929
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   930
    SETE_t();
nkeynes@417
   931
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   932
:}
nkeynes@359
   933
XOR Rm, Rn {:  
nkeynes@359
   934
    load_reg( R_EAX, Rm );
nkeynes@359
   935
    load_reg( R_ECX, Rn );
nkeynes@359
   936
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   937
    store_reg( R_ECX, Rn );
nkeynes@417
   938
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   939
:}
nkeynes@359
   940
XOR #imm, R0 {:  
nkeynes@359
   941
    load_reg( R_EAX, 0 );
nkeynes@359
   942
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   943
    store_reg( R_EAX, 0 );
nkeynes@417
   944
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   945
:}
nkeynes@359
   946
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   947
    load_reg( R_EAX, 0 );
nkeynes@359
   948
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   949
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   950
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   951
    MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
   952
    POP_realigned_r32(R_ECX);
nkeynes@359
   953
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   954
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   955
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   956
:}
nkeynes@361
   957
XTRCT Rm, Rn {:
nkeynes@361
   958
    load_reg( R_EAX, Rm );
nkeynes@394
   959
    load_reg( R_ECX, Rn );
nkeynes@394
   960
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   961
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   962
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   963
    store_reg( R_ECX, Rn );
nkeynes@417
   964
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
:}
nkeynes@359
   966
nkeynes@359
   967
/* Data move instructions */
nkeynes@359
   968
MOV Rm, Rn {:  
nkeynes@359
   969
    load_reg( R_EAX, Rm );
nkeynes@359
   970
    store_reg( R_EAX, Rn );
nkeynes@359
   971
:}
nkeynes@359
   972
MOV #imm, Rn {:  
nkeynes@359
   973
    load_imm32( R_EAX, imm );
nkeynes@359
   974
    store_reg( R_EAX, Rn );
nkeynes@359
   975
:}
nkeynes@359
   976
MOV.B Rm, @Rn {:  
nkeynes@359
   977
    load_reg( R_EAX, Rm );
nkeynes@359
   978
    load_reg( R_ECX, Rn );
nkeynes@359
   979
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   980
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   981
:}
nkeynes@359
   982
MOV.B Rm, @-Rn {:  
nkeynes@359
   983
    load_reg( R_EAX, Rm );
nkeynes@359
   984
    load_reg( R_ECX, Rn );
nkeynes@382
   985
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   986
    store_reg( R_ECX, Rn );
nkeynes@359
   987
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   988
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   989
:}
nkeynes@359
   990
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   991
    load_reg( R_EAX, 0 );
nkeynes@359
   992
    load_reg( R_ECX, Rn );
nkeynes@359
   993
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
    load_reg( R_EAX, Rm );
nkeynes@359
   995
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   997
:}
nkeynes@359
   998
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   999
    load_reg( R_EAX, 0 );
nkeynes@359
  1000
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1001
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1002
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1003
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1004
:}
nkeynes@359
  1005
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1006
    load_reg( R_EAX, 0 );
nkeynes@359
  1007
    load_reg( R_ECX, Rn );
nkeynes@359
  1008
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1009
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1011
:}
nkeynes@359
  1012
MOV.B @Rm, Rn {:  
nkeynes@359
  1013
    load_reg( R_ECX, Rm );
nkeynes@359
  1014
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1015
    store_reg( R_EAX, Rn );
nkeynes@417
  1016
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1017
:}
nkeynes@359
  1018
MOV.B @Rm+, Rn {:  
nkeynes@359
  1019
    load_reg( R_ECX, Rm );
nkeynes@359
  1020
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1021
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1022
    store_reg( R_EAX, Rm );
nkeynes@359
  1023
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1024
    store_reg( R_EAX, Rn );
nkeynes@417
  1025
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1026
:}
nkeynes@359
  1027
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1028
    load_reg( R_EAX, 0 );
nkeynes@359
  1029
    load_reg( R_ECX, Rm );
nkeynes@359
  1030
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1031
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1032
    store_reg( R_EAX, Rn );
nkeynes@417
  1033
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1034
:}
nkeynes@359
  1035
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1036
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1037
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1038
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1039
    store_reg( R_EAX, 0 );
nkeynes@417
  1040
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1041
:}
nkeynes@359
  1042
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1043
    load_reg( R_ECX, Rm );
nkeynes@359
  1044
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1045
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1046
    store_reg( R_EAX, 0 );
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1048
:}
nkeynes@374
  1049
MOV.L Rm, @Rn {:
nkeynes@361
  1050
    load_reg( R_EAX, Rm );
nkeynes@361
  1051
    load_reg( R_ECX, Rn );
nkeynes@374
  1052
    check_walign32(R_ECX);
nkeynes@361
  1053
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1054
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1055
:}
nkeynes@361
  1056
MOV.L Rm, @-Rn {:  
nkeynes@361
  1057
    load_reg( R_EAX, Rm );
nkeynes@361
  1058
    load_reg( R_ECX, Rn );
nkeynes@374
  1059
    check_walign32( R_ECX );
nkeynes@361
  1060
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1061
    store_reg( R_ECX, Rn );
nkeynes@361
  1062
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1063
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1064
:}
nkeynes@361
  1065
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1066
    load_reg( R_EAX, 0 );
nkeynes@361
  1067
    load_reg( R_ECX, Rn );
nkeynes@361
  1068
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1069
    check_walign32( R_ECX );
nkeynes@361
  1070
    load_reg( R_EAX, Rm );
nkeynes@361
  1071
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1072
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1073
:}
nkeynes@361
  1074
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1075
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1076
    load_reg( R_EAX, 0 );
nkeynes@361
  1077
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1078
    check_walign32( R_ECX );
nkeynes@361
  1079
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1080
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1081
:}
nkeynes@361
  1082
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1083
    load_reg( R_ECX, Rn );
nkeynes@361
  1084
    load_reg( R_EAX, Rm );
nkeynes@361
  1085
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1086
    check_walign32( R_ECX );
nkeynes@361
  1087
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1088
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1089
:}
nkeynes@361
  1090
MOV.L @Rm, Rn {:  
nkeynes@361
  1091
    load_reg( R_ECX, Rm );
nkeynes@374
  1092
    check_ralign32( R_ECX );
nkeynes@361
  1093
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1094
    store_reg( R_EAX, Rn );
nkeynes@417
  1095
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1096
:}
nkeynes@361
  1097
MOV.L @Rm+, Rn {:  
nkeynes@361
  1098
    load_reg( R_EAX, Rm );
nkeynes@382
  1099
    check_ralign32( R_EAX );
nkeynes@361
  1100
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1101
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1102
    store_reg( R_EAX, Rm );
nkeynes@361
  1103
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1104
    store_reg( R_EAX, Rn );
nkeynes@417
  1105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1106
:}
nkeynes@361
  1107
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1108
    load_reg( R_EAX, 0 );
nkeynes@361
  1109
    load_reg( R_ECX, Rm );
nkeynes@361
  1110
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1111
    check_ralign32( R_ECX );
nkeynes@361
  1112
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1113
    store_reg( R_EAX, Rn );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1115
:}
nkeynes@361
  1116
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1117
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1118
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1119
    check_ralign32( R_ECX );
nkeynes@361
  1120
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1121
    store_reg( R_EAX, 0 );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1123
:}
nkeynes@361
  1124
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1125
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1126
	SLOTILLEGAL();
nkeynes@374
  1127
    } else {
nkeynes@388
  1128
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@559
  1129
	sh4ptr_t ptr = sh4_get_region_by_vma(target);
nkeynes@388
  1130
	if( ptr != NULL ) {
nkeynes@527
  1131
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1132
	} else {
nkeynes@388
  1133
	    load_imm32( R_ECX, target );
nkeynes@388
  1134
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1135
	}
nkeynes@382
  1136
	store_reg( R_EAX, Rn );
nkeynes@417
  1137
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1138
    }
nkeynes@361
  1139
:}
nkeynes@361
  1140
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1141
    load_reg( R_ECX, Rm );
nkeynes@361
  1142
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1143
    check_ralign32( R_ECX );
nkeynes@361
  1144
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1145
    store_reg( R_EAX, Rn );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1147
:}
nkeynes@361
  1148
MOV.W Rm, @Rn {:  
nkeynes@361
  1149
    load_reg( R_ECX, Rn );
nkeynes@374
  1150
    check_walign16( R_ECX );
nkeynes@382
  1151
    load_reg( R_EAX, Rm );
nkeynes@382
  1152
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1154
:}
nkeynes@361
  1155
MOV.W Rm, @-Rn {:  
nkeynes@361
  1156
    load_reg( R_ECX, Rn );
nkeynes@374
  1157
    check_walign16( R_ECX );
nkeynes@361
  1158
    load_reg( R_EAX, Rm );
nkeynes@361
  1159
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1160
    store_reg( R_ECX, Rn );
nkeynes@361
  1161
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1163
:}
nkeynes@361
  1164
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1165
    load_reg( R_EAX, 0 );
nkeynes@361
  1166
    load_reg( R_ECX, Rn );
nkeynes@361
  1167
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1168
    check_walign16( R_ECX );
nkeynes@361
  1169
    load_reg( R_EAX, Rm );
nkeynes@361
  1170
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1171
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1172
:}
nkeynes@361
  1173
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1174
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1175
    load_reg( R_EAX, 0 );
nkeynes@361
  1176
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1177
    check_walign16( R_ECX );
nkeynes@361
  1178
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1179
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1180
:}
nkeynes@361
  1181
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1182
    load_reg( R_ECX, Rn );
nkeynes@361
  1183
    load_reg( R_EAX, 0 );
nkeynes@361
  1184
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1185
    check_walign16( R_ECX );
nkeynes@361
  1186
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1187
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1188
:}
nkeynes@361
  1189
MOV.W @Rm, Rn {:  
nkeynes@361
  1190
    load_reg( R_ECX, Rm );
nkeynes@374
  1191
    check_ralign16( R_ECX );
nkeynes@361
  1192
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1193
    store_reg( R_EAX, Rn );
nkeynes@417
  1194
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1195
:}
nkeynes@361
  1196
MOV.W @Rm+, Rn {:  
nkeynes@361
  1197
    load_reg( R_EAX, Rm );
nkeynes@374
  1198
    check_ralign16( R_EAX );
nkeynes@361
  1199
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1200
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1201
    store_reg( R_EAX, Rm );
nkeynes@361
  1202
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1203
    store_reg( R_EAX, Rn );
nkeynes@417
  1204
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1205
:}
nkeynes@361
  1206
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1207
    load_reg( R_EAX, 0 );
nkeynes@361
  1208
    load_reg( R_ECX, Rm );
nkeynes@361
  1209
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1210
    check_ralign16( R_ECX );
nkeynes@361
  1211
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1212
    store_reg( R_EAX, Rn );
nkeynes@417
  1213
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1214
:}
nkeynes@361
  1215
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1216
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1217
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1218
    check_ralign16( R_ECX );
nkeynes@361
  1219
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1220
    store_reg( R_EAX, 0 );
nkeynes@417
  1221
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1222
:}
nkeynes@361
  1223
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1224
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1225
	SLOTILLEGAL();
nkeynes@374
  1226
    } else {
nkeynes@374
  1227
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1228
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1229
	store_reg( R_EAX, Rn );
nkeynes@417
  1230
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1231
    }
nkeynes@361
  1232
:}
nkeynes@361
  1233
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1234
    load_reg( R_ECX, Rm );
nkeynes@361
  1235
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1236
    check_ralign16( R_ECX );
nkeynes@361
  1237
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1238
    store_reg( R_EAX, 0 );
nkeynes@417
  1239
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1240
:}
nkeynes@361
  1241
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1242
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1243
	SLOTILLEGAL();
nkeynes@374
  1244
    } else {
nkeynes@374
  1245
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1246
	store_reg( R_ECX, 0 );
nkeynes@374
  1247
    }
nkeynes@361
  1248
:}
nkeynes@361
  1249
MOVCA.L R0, @Rn {:  
nkeynes@361
  1250
    load_reg( R_EAX, 0 );
nkeynes@361
  1251
    load_reg( R_ECX, Rn );
nkeynes@374
  1252
    check_walign32( R_ECX );
nkeynes@361
  1253
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1255
:}
nkeynes@359
  1256
nkeynes@359
  1257
/* Control transfer instructions */
nkeynes@374
  1258
BF disp {:
nkeynes@374
  1259
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1260
	SLOTILLEGAL();
nkeynes@374
  1261
    } else {
nkeynes@527
  1262
	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1263
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1264
	JMP_TARGET(nottaken);
nkeynes@408
  1265
	return 2;
nkeynes@374
  1266
    }
nkeynes@374
  1267
:}
nkeynes@374
  1268
BF/S disp {:
nkeynes@374
  1269
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1270
	SLOTILLEGAL();
nkeynes@374
  1271
    } else {
nkeynes@408
  1272
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1273
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1274
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1275
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1276
	}
nkeynes@417
  1277
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1278
	sh4_translate_instruction(pc+2);
nkeynes@408
  1279
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1280
	// not taken
nkeynes@408
  1281
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1282
	sh4_translate_instruction(pc+2);
nkeynes@408
  1283
	return 4;
nkeynes@374
  1284
    }
nkeynes@374
  1285
:}
nkeynes@374
  1286
BRA disp {:  
nkeynes@374
  1287
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1288
	SLOTILLEGAL();
nkeynes@374
  1289
    } else {
nkeynes@374
  1290
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1291
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1292
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1293
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1294
	return 4;
nkeynes@374
  1295
    }
nkeynes@374
  1296
:}
nkeynes@374
  1297
BRAF Rn {:  
nkeynes@374
  1298
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1299
	SLOTILLEGAL();
nkeynes@374
  1300
    } else {
nkeynes@408
  1301
	load_reg( R_EAX, Rn );
nkeynes@408
  1302
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1303
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1304
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1305
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1306
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1307
	exit_block_pcset(pc+2);
nkeynes@409
  1308
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1309
	return 4;
nkeynes@374
  1310
    }
nkeynes@374
  1311
:}
nkeynes@374
  1312
BSR disp {:  
nkeynes@374
  1313
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1314
	SLOTILLEGAL();
nkeynes@374
  1315
    } else {
nkeynes@374
  1316
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1317
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1318
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1319
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1320
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1321
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1322
	return 4;
nkeynes@374
  1323
    }
nkeynes@374
  1324
:}
nkeynes@374
  1325
BSRF Rn {:  
nkeynes@374
  1326
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1327
	SLOTILLEGAL();
nkeynes@374
  1328
    } else {
nkeynes@408
  1329
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1330
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1331
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1332
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1333
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1334
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1335
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1336
	exit_block_pcset(pc+2);
nkeynes@409
  1337
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1338
	return 4;
nkeynes@374
  1339
    }
nkeynes@374
  1340
:}
nkeynes@374
  1341
BT disp {:
nkeynes@374
  1342
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1343
	SLOTILLEGAL();
nkeynes@374
  1344
    } else {
nkeynes@527
  1345
	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1346
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1347
	JMP_TARGET(nottaken);
nkeynes@408
  1348
	return 2;
nkeynes@374
  1349
    }
nkeynes@374
  1350
:}
nkeynes@374
  1351
BT/S disp {:
nkeynes@374
  1352
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1353
	SLOTILLEGAL();
nkeynes@374
  1354
    } else {
nkeynes@408
  1355
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1356
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1357
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1358
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1359
	}
nkeynes@417
  1360
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1361
	sh4_translate_instruction(pc+2);
nkeynes@408
  1362
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1363
	// not taken
nkeynes@408
  1364
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1365
	sh4_translate_instruction(pc+2);
nkeynes@408
  1366
	return 4;
nkeynes@374
  1367
    }
nkeynes@374
  1368
:}
nkeynes@374
  1369
JMP @Rn {:  
nkeynes@374
  1370
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1371
	SLOTILLEGAL();
nkeynes@374
  1372
    } else {
nkeynes@408
  1373
	load_reg( R_ECX, Rn );
nkeynes@408
  1374
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1375
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1376
	sh4_translate_instruction(pc+2);
nkeynes@408
  1377
	exit_block_pcset(pc+2);
nkeynes@409
  1378
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1379
	return 4;
nkeynes@374
  1380
    }
nkeynes@374
  1381
:}
nkeynes@374
  1382
JSR @Rn {:  
nkeynes@374
  1383
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1384
	SLOTILLEGAL();
nkeynes@374
  1385
    } else {
nkeynes@374
  1386
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1387
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1388
	load_reg( R_ECX, Rn );
nkeynes@408
  1389
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1390
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1391
	sh4_translate_instruction(pc+2);
nkeynes@408
  1392
	exit_block_pcset(pc+2);
nkeynes@409
  1393
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1394
	return 4;
nkeynes@374
  1395
    }
nkeynes@374
  1396
:}
nkeynes@374
  1397
RTE {:  
nkeynes@374
  1398
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1399
	SLOTILLEGAL();
nkeynes@374
  1400
    } else {
nkeynes@408
  1401
	check_priv();
nkeynes@408
  1402
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1403
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1404
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1405
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1406
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1407
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1408
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1409
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1410
	sh4_translate_instruction(pc+2);
nkeynes@408
  1411
	exit_block_pcset(pc+2);
nkeynes@409
  1412
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1413
	return 4;
nkeynes@374
  1414
    }
nkeynes@374
  1415
:}
nkeynes@374
  1416
RTS {:  
nkeynes@374
  1417
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1418
	SLOTILLEGAL();
nkeynes@374
  1419
    } else {
nkeynes@408
  1420
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1421
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1422
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1423
	sh4_translate_instruction(pc+2);
nkeynes@408
  1424
	exit_block_pcset(pc+2);
nkeynes@409
  1425
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1426
	return 4;
nkeynes@374
  1427
    }
nkeynes@374
  1428
:}
nkeynes@374
  1429
TRAPA #imm {:  
nkeynes@374
  1430
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1431
	SLOTILLEGAL();
nkeynes@374
  1432
    } else {
nkeynes@533
  1433
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1434
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1435
	load_imm32( R_EAX, imm );
nkeynes@527
  1436
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1437
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1438
	exit_block_pcset(pc);
nkeynes@409
  1439
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1440
	return 2;
nkeynes@374
  1441
    }
nkeynes@374
  1442
:}
nkeynes@374
  1443
UNDEF {:  
nkeynes@374
  1444
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1445
	SLOTILLEGAL();
nkeynes@374
  1446
    } else {
nkeynes@559
  1447
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1448
	return 2;
nkeynes@374
  1449
    }
nkeynes@368
  1450
:}
nkeynes@374
  1451
nkeynes@374
  1452
CLRMAC {:  
nkeynes@374
  1453
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1454
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1455
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1456
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1457
:}
nkeynes@374
  1458
CLRS {:
nkeynes@374
  1459
    CLC();
nkeynes@374
  1460
    SETC_sh4r(R_S);
nkeynes@417
  1461
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1462
:}
nkeynes@374
  1463
CLRT {:  
nkeynes@374
  1464
    CLC();
nkeynes@374
  1465
    SETC_t();
nkeynes@417
  1466
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1467
:}
nkeynes@374
  1468
SETS {:  
nkeynes@374
  1469
    STC();
nkeynes@374
  1470
    SETC_sh4r(R_S);
nkeynes@417
  1471
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1472
:}
nkeynes@374
  1473
SETT {:  
nkeynes@374
  1474
    STC();
nkeynes@374
  1475
    SETC_t();
nkeynes@417
  1476
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1477
:}
nkeynes@359
  1478
nkeynes@375
  1479
/* Floating point moves */
nkeynes@375
  1480
FMOV FRm, FRn {:  
nkeynes@375
  1481
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1482
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1483
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1484
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1485
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1486
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1487
     */
nkeynes@377
  1488
    check_fpuen();
nkeynes@375
  1489
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1490
    load_fr_bank( R_EDX );
nkeynes@375
  1491
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1492
    JNE_rel8(8, doublesize);
nkeynes@375
  1493
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1494
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1495
    if( FRm&1 ) {
nkeynes@386
  1496
	JMP_rel8(24, end);
nkeynes@380
  1497
	JMP_TARGET(doublesize);
nkeynes@375
  1498
	load_xf_bank( R_ECX ); 
nkeynes@375
  1499
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1500
	if( FRn&1 ) {
nkeynes@375
  1501
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1502
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1503
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1504
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1505
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1506
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1507
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1508
	}
nkeynes@380
  1509
	JMP_TARGET(end);
nkeynes@375
  1510
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1511
	if( FRn&1 ) {
nkeynes@386
  1512
	    JMP_rel8(24, end);
nkeynes@375
  1513
	    load_xf_bank( R_ECX );
nkeynes@375
  1514
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1515
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1516
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1517
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1518
	    JMP_TARGET(end);
nkeynes@375
  1519
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1520
	    JMP_rel8(12, end);
nkeynes@375
  1521
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1522
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1523
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1524
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1525
	    JMP_TARGET(end);
nkeynes@375
  1526
	}
nkeynes@375
  1527
    }
nkeynes@417
  1528
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1529
:}
nkeynes@416
  1530
FMOV FRm, @Rn {: 
nkeynes@559
  1531
    check_fpuen();
nkeynes@416
  1532
    load_reg( R_ECX, Rn );
nkeynes@416
  1533
    check_walign32( R_ECX );
nkeynes@416
  1534
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1535
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1536
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1537
    load_fr_bank( R_EDX );
nkeynes@416
  1538
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1539
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1540
    if( FRm&1 ) {
nkeynes@527
  1541
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1542
	JMP_TARGET(doublesize);
nkeynes@416
  1543
	load_xf_bank( R_EDX );
nkeynes@416
  1544
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1545
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1546
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1547
	JMP_TARGET(end);
nkeynes@375
  1548
    } else {
nkeynes@527
  1549
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1550
	JMP_TARGET(doublesize);
nkeynes@416
  1551
	load_fr_bank( R_EDX );
nkeynes@416
  1552
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1553
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1554
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1555
	JMP_TARGET(end);
nkeynes@375
  1556
    }
nkeynes@417
  1557
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1558
:}
nkeynes@375
  1559
FMOV @Rm, FRn {:  
nkeynes@559
  1560
    check_fpuen();
nkeynes@416
  1561
    load_reg( R_ECX, Rm );
nkeynes@416
  1562
    check_ralign32( R_ECX );
nkeynes@416
  1563
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1564
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1565
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1566
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1567
    load_fr_bank( R_EDX );
nkeynes@416
  1568
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1569
    if( FRn&1 ) {
nkeynes@527
  1570
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1571
	JMP_TARGET(doublesize);
nkeynes@416
  1572
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1573
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1574
	load_xf_bank( R_EDX );
nkeynes@416
  1575
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1576
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1577
	JMP_TARGET(end);
nkeynes@375
  1578
    } else {
nkeynes@527
  1579
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1580
	JMP_TARGET(doublesize);
nkeynes@416
  1581
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1582
	load_fr_bank( R_EDX );
nkeynes@416
  1583
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1584
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1585
	JMP_TARGET(end);
nkeynes@375
  1586
    }
nkeynes@417
  1587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1588
:}
nkeynes@377
  1589
FMOV FRm, @-Rn {:  
nkeynes@559
  1590
    check_fpuen();
nkeynes@416
  1591
    load_reg( R_ECX, Rn );
nkeynes@416
  1592
    check_walign32( R_ECX );
nkeynes@416
  1593
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1594
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1595
    JNE_rel8(14 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1596
    load_fr_bank( R_EDX );
nkeynes@416
  1597
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1598
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1599
    store_reg( R_ECX, Rn );
nkeynes@416
  1600
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1601
    if( FRm&1 ) {
nkeynes@527
  1602
	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1603
	JMP_TARGET(doublesize);
nkeynes@416
  1604
	load_xf_bank( R_EDX );
nkeynes@416
  1605
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1606
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1607
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1608
	store_reg( R_ECX, Rn );
nkeynes@416
  1609
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1610
	JMP_TARGET(end);
nkeynes@377
  1611
    } else {
nkeynes@527
  1612
	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1613
	JMP_TARGET(doublesize);
nkeynes@416
  1614
	load_fr_bank( R_EDX );
nkeynes@416
  1615
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1616
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1617
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1618
	store_reg( R_ECX, Rn );
nkeynes@416
  1619
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1620
	JMP_TARGET(end);
nkeynes@377
  1621
    }
nkeynes@417
  1622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1623
:}
nkeynes@416
  1624
FMOV @Rm+, FRn {:
nkeynes@559
  1625
    check_fpuen();
nkeynes@416
  1626
    load_reg( R_ECX, Rm );
nkeynes@416
  1627
    check_ralign32( R_ECX );
nkeynes@416
  1628
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1629
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1630
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1631
    JNE_rel8(14 + MEM_READ_SIZE, doublesize);
nkeynes@377
  1632
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1633
    store_reg( R_EAX, Rm );
nkeynes@416
  1634
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1635
    load_fr_bank( R_EDX );
nkeynes@416
  1636
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1637
    if( FRn&1 ) {
nkeynes@527
  1638
	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1639
	JMP_TARGET(doublesize);
nkeynes@377
  1640
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1641
	store_reg(R_EAX, Rm);
nkeynes@416
  1642
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1643
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1644
	load_xf_bank( R_EDX );
nkeynes@416
  1645
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1646
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1647
	JMP_TARGET(end);
nkeynes@377
  1648
    } else {
nkeynes@527
  1649
	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@377
  1650
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1651
	store_reg(R_EAX, Rm);
nkeynes@416
  1652
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1653
	load_fr_bank( R_EDX );
nkeynes@416
  1654
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1655
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1656
	JMP_TARGET(end);
nkeynes@377
  1657
    }
nkeynes@417
  1658
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1659
:}
nkeynes@377
  1660
FMOV FRm, @(R0, Rn) {:  
nkeynes@559
  1661
    check_fpuen();
nkeynes@416
  1662
    load_reg( R_ECX, Rn );
nkeynes@416
  1663
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1664
    check_walign32( R_ECX );
nkeynes@416
  1665
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1666
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1667
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1668
    load_fr_bank( R_EDX );
nkeynes@416
  1669
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1670
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1671
    if( FRm&1 ) {
nkeynes@527
  1672
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1673
	JMP_TARGET(doublesize);
nkeynes@416
  1674
	load_xf_bank( R_EDX );
nkeynes@416
  1675
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1676
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1677
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1678
	JMP_TARGET(end);
nkeynes@377
  1679
    } else {
nkeynes@527
  1680
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1681
	JMP_TARGET(doublesize);
nkeynes@416
  1682
	load_fr_bank( R_EDX );
nkeynes@416
  1683
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1684
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1685
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1686
	JMP_TARGET(end);
nkeynes@377
  1687
    }
nkeynes@417
  1688
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1689
:}
nkeynes@377
  1690
FMOV @(R0, Rm), FRn {:  
nkeynes@559
  1691
    check_fpuen();
nkeynes@416
  1692
    load_reg( R_ECX, Rm );
nkeynes@416
  1693
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1694
    check_ralign32( R_ECX );
nkeynes@416
  1695
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1696
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1697
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1698
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1699
    load_fr_bank( R_EDX );
nkeynes@416
  1700
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1701
    if( FRn&1 ) {
nkeynes@527
  1702
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1703
	JMP_TARGET(doublesize);
nkeynes@416
  1704
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1705
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1706
	load_xf_bank( R_EDX );
nkeynes@416
  1707
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1708
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1709
	JMP_TARGET(end);
nkeynes@377
  1710
    } else {
nkeynes@527
  1711
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1712
	JMP_TARGET(doublesize);
nkeynes@416
  1713
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1714
	load_fr_bank( R_EDX );
nkeynes@416
  1715
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1716
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1717
	JMP_TARGET(end);
nkeynes@377
  1718
    }
nkeynes@417
  1719
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1720
:}
nkeynes@377
  1721
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1722
    check_fpuen();
nkeynes@377
  1723
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1724
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1725
    JNE_rel8(8, end);
nkeynes@377
  1726
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1727
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1728
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1729
    JMP_TARGET(end);
nkeynes@417
  1730
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1731
:}
nkeynes@377
  1732
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1733
    check_fpuen();
nkeynes@377
  1734
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1735
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1736
    JNE_rel8(11, end);
nkeynes@377
  1737
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1738
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1739
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1740
    JMP_TARGET(end);
nkeynes@417
  1741
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1742
:}
nkeynes@377
  1743
nkeynes@377
  1744
FLOAT FPUL, FRn {:  
nkeynes@377
  1745
    check_fpuen();
nkeynes@377
  1746
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1747
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1748
    FILD_sh4r(R_FPUL);
nkeynes@377
  1749
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1750
    JNE_rel8(5, doubleprec);
nkeynes@377
  1751
    pop_fr( R_EDX, FRn );
nkeynes@380
  1752
    JMP_rel8(3, end);
nkeynes@380
  1753
    JMP_TARGET(doubleprec);
nkeynes@377
  1754
    pop_dr( R_EDX, FRn );
nkeynes@380
  1755
    JMP_TARGET(end);
nkeynes@417
  1756
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1757
:}
nkeynes@377
  1758
FTRC FRm, FPUL {:  
nkeynes@377
  1759
    check_fpuen();
nkeynes@388
  1760
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1761
    load_fr_bank( R_EDX );
nkeynes@388
  1762
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1763
    JNE_rel8(5, doubleprec);
nkeynes@388
  1764
    push_fr( R_EDX, FRm );
nkeynes@388
  1765
    JMP_rel8(3, doop);
nkeynes@388
  1766
    JMP_TARGET(doubleprec);
nkeynes@388
  1767
    push_dr( R_EDX, FRm );
nkeynes@388
  1768
    JMP_TARGET( doop );
nkeynes@388
  1769
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1770
    FILD_r32ind( R_ECX );
nkeynes@388
  1771
    FCOMIP_st(1);
nkeynes@394
  1772
    JNA_rel8( 32, sat );
nkeynes@388
  1773
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1774
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1775
    FCOMIP_st(1);                   // 2
nkeynes@394
  1776
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1777
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1778
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1779
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1780
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1781
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1782
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1783
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1784
nkeynes@388
  1785
    JMP_TARGET(sat);
nkeynes@388
  1786
    JMP_TARGET(sat2);
nkeynes@388
  1787
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1788
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1789
    FPOP_st();
nkeynes@388
  1790
    JMP_TARGET(end);
nkeynes@417
  1791
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1792
:}
nkeynes@377
  1793
FLDS FRm, FPUL {:  
nkeynes@377
  1794
    check_fpuen();
nkeynes@377
  1795
    load_fr_bank( R_ECX );
nkeynes@377
  1796
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1797
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1799
:}
nkeynes@377
  1800
FSTS FPUL, FRn {:  
nkeynes@377
  1801
    check_fpuen();
nkeynes@377
  1802
    load_fr_bank( R_ECX );
nkeynes@377
  1803
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1804
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1806
:}
nkeynes@377
  1807
FCNVDS FRm, FPUL {:  
nkeynes@377
  1808
    check_fpuen();
nkeynes@377
  1809
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1810
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1811
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1812
    load_fr_bank( R_ECX );
nkeynes@377
  1813
    push_dr( R_ECX, FRm );
nkeynes@377
  1814
    pop_fpul();
nkeynes@380
  1815
    JMP_TARGET(end);
nkeynes@417
  1816
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1817
:}
nkeynes@377
  1818
FCNVSD FPUL, FRn {:  
nkeynes@377
  1819
    check_fpuen();
nkeynes@377
  1820
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1821
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1822
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1823
    load_fr_bank( R_ECX );
nkeynes@377
  1824
    push_fpul();
nkeynes@377
  1825
    pop_dr( R_ECX, FRn );
nkeynes@380
  1826
    JMP_TARGET(end);
nkeynes@417
  1827
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1828
:}
nkeynes@375
  1829
nkeynes@359
  1830
/* Floating point instructions */
nkeynes@374
  1831
FABS FRn {:  
nkeynes@377
  1832
    check_fpuen();
nkeynes@374
  1833
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1834
    load_fr_bank( R_EDX );
nkeynes@374
  1835
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1836
    JNE_rel8(10, doubleprec);
nkeynes@374
  1837
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1838
    FABS_st0(); // 2
nkeynes@374
  1839
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1840
    JMP_rel8(8,end); // 2
nkeynes@380
  1841
    JMP_TARGET(doubleprec);
nkeynes@374
  1842
    push_dr(R_EDX, FRn);
nkeynes@374
  1843
    FABS_st0();
nkeynes@374
  1844
    pop_dr(R_EDX, FRn);
nkeynes@380
  1845
    JMP_TARGET(end);
nkeynes@417
  1846
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1847
:}
nkeynes@377
  1848
FADD FRm, FRn {:  
nkeynes@377
  1849
    check_fpuen();
nkeynes@375
  1850
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1851
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1852
    load_fr_bank( R_EDX );
nkeynes@380
  1853
    JNE_rel8(13,doubleprec);
nkeynes@377
  1854
    push_fr(R_EDX, FRm);
nkeynes@377
  1855
    push_fr(R_EDX, FRn);
nkeynes@377
  1856
    FADDP_st(1);
nkeynes@377
  1857
    pop_fr(R_EDX, FRn);
nkeynes@380
  1858
    JMP_rel8(11,end);
nkeynes@380
  1859
    JMP_TARGET(doubleprec);
nkeynes@377
  1860
    push_dr(R_EDX, FRm);
nkeynes@377
  1861
    push_dr(R_EDX, FRn);
nkeynes@377
  1862
    FADDP_st(1);
nkeynes@377
  1863
    pop_dr(R_EDX, FRn);
nkeynes@380
  1864
    JMP_TARGET(end);
nkeynes@417
  1865
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1866
:}
nkeynes@377
  1867
FDIV FRm, FRn {:  
nkeynes@377
  1868
    check_fpuen();
nkeynes@375
  1869
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1870
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1871
    load_fr_bank( R_EDX );
nkeynes@380
  1872
    JNE_rel8(13, doubleprec);
nkeynes@377
  1873
    push_fr(R_EDX, FRn);
nkeynes@377
  1874
    push_fr(R_EDX, FRm);
nkeynes@377
  1875
    FDIVP_st(1);
nkeynes@377
  1876
    pop_fr(R_EDX, FRn);
nkeynes@380
  1877
    JMP_rel8(11, end);
nkeynes@380
  1878
    JMP_TARGET(doubleprec);
nkeynes@377
  1879
    push_dr(R_EDX, FRn);
nkeynes@377
  1880
    push_dr(R_EDX, FRm);
nkeynes@377
  1881
    FDIVP_st(1);
nkeynes@377
  1882
    pop_dr(R_EDX, FRn);
nkeynes@380
  1883
    JMP_TARGET(end);
nkeynes@417
  1884
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1885
:}
nkeynes@375
  1886
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1887
    check_fpuen();
nkeynes@375
  1888
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1889
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1890
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1891
    JNE_rel8(18, doubleprec);
nkeynes@375
  1892
    push_fr( R_EDX, 0 );
nkeynes@375
  1893
    push_fr( R_EDX, FRm );
nkeynes@375
  1894
    FMULP_st(1);
nkeynes@375
  1895
    push_fr( R_EDX, FRn );
nkeynes@375
  1896
    FADDP_st(1);
nkeynes@375
  1897
    pop_fr( R_EDX, FRn );
nkeynes@380
  1898
    JMP_rel8(16, end);
nkeynes@380
  1899
    JMP_TARGET(doubleprec);
nkeynes@375
  1900
    push_dr( R_EDX, 0 );
nkeynes@375
  1901
    push_dr( R_EDX, FRm );
nkeynes@375
  1902
    FMULP_st(1);
nkeynes@375
  1903
    push_dr( R_EDX, FRn );
nkeynes@375
  1904
    FADDP_st(1);
nkeynes@375
  1905
    pop_dr( R_EDX, FRn );
nkeynes@380
  1906
    JMP_TARGET(end);
nkeynes@417
  1907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1908
:}
nkeynes@375
  1909
nkeynes@377
  1910
FMUL FRm, FRn {:  
nkeynes@377
  1911
    check_fpuen();
nkeynes@377
  1912
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1913
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1914
    load_fr_bank( R_EDX );
nkeynes@380
  1915
    JNE_rel8(13, doubleprec);
nkeynes@377
  1916
    push_fr(R_EDX, FRm);
nkeynes@377
  1917
    push_fr(R_EDX, FRn);
nkeynes@377
  1918
    FMULP_st(1);
nkeynes@377
  1919
    pop_fr(R_EDX, FRn);
nkeynes@380
  1920
    JMP_rel8(11, end);
nkeynes@380
  1921
    JMP_TARGET(doubleprec);
nkeynes@377
  1922
    push_dr(R_EDX, FRm);
nkeynes@377
  1923
    push_dr(R_EDX, FRn);
nkeynes@377
  1924
    FMULP_st(1);
nkeynes@377
  1925
    pop_dr(R_EDX, FRn);
nkeynes@380
  1926
    JMP_TARGET(end);
nkeynes@417
  1927
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1928
:}
nkeynes@377
  1929
FNEG FRn {:  
nkeynes@377
  1930
    check_fpuen();
nkeynes@377
  1931
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1932
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1933
    load_fr_bank( R_EDX );
nkeynes@380
  1934
    JNE_rel8(10, doubleprec);
nkeynes@377
  1935
    push_fr(R_EDX, FRn);
nkeynes@377
  1936
    FCHS_st0();
nkeynes@377
  1937
    pop_fr(R_EDX, FRn);
nkeynes@380
  1938
    JMP_rel8(8, end);
nkeynes@380
  1939
    JMP_TARGET(doubleprec);
nkeynes@377
  1940
    push_dr(R_EDX, FRn);
nkeynes@377
  1941
    FCHS_st0();
nkeynes@377
  1942
    pop_dr(R_EDX, FRn);
nkeynes@380
  1943
    JMP_TARGET(end);
nkeynes@417
  1944
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1945
:}
nkeynes@377
  1946
FSRRA FRn {:  
nkeynes@377
  1947
    check_fpuen();
nkeynes@377
  1948
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1949
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1950
    load_fr_bank( R_EDX );
nkeynes@380
  1951
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1952
    FLD1_st0();
nkeynes@377
  1953
    push_fr(R_EDX, FRn);
nkeynes@377
  1954
    FSQRT_st0();
nkeynes@377
  1955
    FDIVP_st(1);
nkeynes@377
  1956
    pop_fr(R_EDX, FRn);
nkeynes@380
  1957
    JMP_TARGET(end);
nkeynes@417
  1958
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1959
:}
nkeynes@377
  1960
FSQRT FRn {:  
nkeynes@377
  1961
    check_fpuen();
nkeynes@377
  1962
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1963
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1964
    load_fr_bank( R_EDX );
nkeynes@380
  1965
    JNE_rel8(10, doubleprec);
nkeynes@377
  1966
    push_fr(R_EDX, FRn);
nkeynes@377
  1967
    FSQRT_st0();
nkeynes@377
  1968
    pop_fr(R_EDX, FRn);
nkeynes@380
  1969
    JMP_rel8(8, end);
nkeynes@380
  1970
    JMP_TARGET(doubleprec);
nkeynes@377
  1971
    push_dr(R_EDX, FRn);
nkeynes@377
  1972
    FSQRT_st0();
nkeynes@377
  1973
    pop_dr(R_EDX, FRn);
nkeynes@380
  1974
    JMP_TARGET(end);
nkeynes@417
  1975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1976
:}
nkeynes@377
  1977
FSUB FRm, FRn {:  
nkeynes@377
  1978
    check_fpuen();
nkeynes@377
  1979
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1980
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1981
    load_fr_bank( R_EDX );
nkeynes@380
  1982
    JNE_rel8(13, doubleprec);
nkeynes@377
  1983
    push_fr(R_EDX, FRn);
nkeynes@377
  1984
    push_fr(R_EDX, FRm);
nkeynes@388
  1985
    FSUBP_st(1);
nkeynes@377
  1986
    pop_fr(R_EDX, FRn);
nkeynes@380
  1987
    JMP_rel8(11, end);
nkeynes@380
  1988
    JMP_TARGET(doubleprec);
nkeynes@377
  1989
    push_dr(R_EDX, FRn);
nkeynes@377
  1990
    push_dr(R_EDX, FRm);
nkeynes@388
  1991
    FSUBP_st(1);
nkeynes@377
  1992
    pop_dr(R_EDX, FRn);
nkeynes@380
  1993
    JMP_TARGET(end);
nkeynes@417
  1994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1995
:}
nkeynes@377
  1996
nkeynes@377
  1997
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1998
    check_fpuen();
nkeynes@377
  1999
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2000
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2001
    load_fr_bank( R_EDX );
nkeynes@380
  2002
    JNE_rel8(8, doubleprec);
nkeynes@377
  2003
    push_fr(R_EDX, FRm);
nkeynes@377
  2004
    push_fr(R_EDX, FRn);
nkeynes@380
  2005
    JMP_rel8(6, end);
nkeynes@380
  2006
    JMP_TARGET(doubleprec);
nkeynes@377
  2007
    push_dr(R_EDX, FRm);
nkeynes@377
  2008
    push_dr(R_EDX, FRn);
nkeynes@382
  2009
    JMP_TARGET(end);
nkeynes@377
  2010
    FCOMIP_st(1);
nkeynes@377
  2011
    SETE_t();
nkeynes@377
  2012
    FPOP_st();
nkeynes@417
  2013
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2014
:}
nkeynes@377
  2015
FCMP/GT FRm, FRn {:  
nkeynes@377
  2016
    check_fpuen();
nkeynes@377
  2017
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2018
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2019
    load_fr_bank( R_EDX );
nkeynes@380
  2020
    JNE_rel8(8, doubleprec);
nkeynes@377
  2021
    push_fr(R_EDX, FRm);
nkeynes@377
  2022
    push_fr(R_EDX, FRn);
nkeynes@380
  2023
    JMP_rel8(6, end);
nkeynes@380
  2024
    JMP_TARGET(doubleprec);
nkeynes@377
  2025
    push_dr(R_EDX, FRm);
nkeynes@377
  2026
    push_dr(R_EDX, FRn);
nkeynes@380
  2027
    JMP_TARGET(end);
nkeynes@377
  2028
    FCOMIP_st(1);
nkeynes@377
  2029
    SETA_t();
nkeynes@377
  2030
    FPOP_st();
nkeynes@417
  2031
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2032
:}
nkeynes@377
  2033
nkeynes@377
  2034
FSCA FPUL, FRn {:  
nkeynes@377
  2035
    check_fpuen();
nkeynes@388
  2036
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2037
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2038
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2039
    load_fr_bank( R_ECX );
nkeynes@388
  2040
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2041
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2042
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2043
    JMP_TARGET(doubleprec);
nkeynes@417
  2044
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2045
:}
nkeynes@377
  2046
FIPR FVm, FVn {:  
nkeynes@377
  2047
    check_fpuen();
nkeynes@388
  2048
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2049
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2050
    JNE_rel8(44, doubleprec);
nkeynes@388
  2051
    
nkeynes@388
  2052
    load_fr_bank( R_ECX );
nkeynes@388
  2053
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2054
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2055
    FMULP_st(1);
nkeynes@388
  2056
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2057
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2058
    FMULP_st(1);
nkeynes@388
  2059
    FADDP_st(1);
nkeynes@388
  2060
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2061
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2062
    FMULP_st(1);
nkeynes@388
  2063
    FADDP_st(1);
nkeynes@388
  2064
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2065
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2066
    FMULP_st(1);
nkeynes@388
  2067
    FADDP_st(1);
nkeynes@388
  2068
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2069
    JMP_TARGET(doubleprec);
nkeynes@417
  2070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2071
:}
nkeynes@377
  2072
FTRV XMTRX, FVn {:  
nkeynes@377
  2073
    check_fpuen();
nkeynes@388
  2074
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2075
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2076
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2077
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2078
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2079
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2080
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2081
    JMP_TARGET(doubleprec);
nkeynes@417
  2082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2083
:}
nkeynes@377
  2084
nkeynes@377
  2085
FRCHG {:  
nkeynes@377
  2086
    check_fpuen();
nkeynes@377
  2087
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2088
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2089
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2090
    update_fr_bank( R_ECX );
nkeynes@417
  2091
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2092
:}
nkeynes@377
  2093
FSCHG {:  
nkeynes@377
  2094
    check_fpuen();
nkeynes@377
  2095
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2096
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2097
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2098
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2099
:}
nkeynes@359
  2100
nkeynes@359
  2101
/* Processor control instructions */
nkeynes@368
  2102
LDC Rm, SR {:
nkeynes@386
  2103
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2104
	SLOTILLEGAL();
nkeynes@386
  2105
    } else {
nkeynes@386
  2106
	check_priv();
nkeynes@386
  2107
	load_reg( R_EAX, Rm );
nkeynes@386
  2108
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2109
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2110
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2111
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2112
    }
nkeynes@368
  2113
:}
nkeynes@359
  2114
LDC Rm, GBR {: 
nkeynes@359
  2115
    load_reg( R_EAX, Rm );
nkeynes@359
  2116
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2117
:}
nkeynes@359
  2118
LDC Rm, VBR {:  
nkeynes@386
  2119
    check_priv();
nkeynes@359
  2120
    load_reg( R_EAX, Rm );
nkeynes@359
  2121
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2123
:}
nkeynes@359
  2124
LDC Rm, SSR {:  
nkeynes@386
  2125
    check_priv();
nkeynes@359
  2126
    load_reg( R_EAX, Rm );
nkeynes@359
  2127
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2128
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2129
:}
nkeynes@359
  2130
LDC Rm, SGR {:  
nkeynes@386
  2131
    check_priv();
nkeynes@359
  2132
    load_reg( R_EAX, Rm );
nkeynes@359
  2133
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2134
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2135
:}
nkeynes@359
  2136
LDC Rm, SPC {:  
nkeynes@386
  2137
    check_priv();
nkeynes@359
  2138
    load_reg( R_EAX, Rm );
nkeynes@359
  2139
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2140
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2141
:}
nkeynes@359
  2142
LDC Rm, DBR {:  
nkeynes@386
  2143
    check_priv();
nkeynes@359
  2144
    load_reg( R_EAX, Rm );
nkeynes@359
  2145
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2147
:}
nkeynes@374
  2148
LDC Rm, Rn_BANK {:  
nkeynes@386
  2149
    check_priv();
nkeynes@374
  2150
    load_reg( R_EAX, Rm );
nkeynes@374
  2151
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2152
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2153
:}
nkeynes@359
  2154
LDC.L @Rm+, GBR {:  
nkeynes@359
  2155
    load_reg( R_EAX, Rm );
nkeynes@395
  2156
    check_ralign32( R_EAX );
nkeynes@359
  2157
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2158
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2159
    store_reg( R_EAX, Rm );
nkeynes@359
  2160
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2161
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2163
:}
nkeynes@368
  2164
LDC.L @Rm+, SR {:
nkeynes@386
  2165
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2166
	SLOTILLEGAL();
nkeynes@386
  2167
    } else {
nkeynes@559
  2168
	check_priv();
nkeynes@386
  2169
	load_reg( R_EAX, Rm );
nkeynes@395
  2170
	check_ralign32( R_EAX );
nkeynes@386
  2171
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2172
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2173
	store_reg( R_EAX, Rm );
nkeynes@386
  2174
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2175
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2176
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2177
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2178
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2179
    }
nkeynes@359
  2180
:}
nkeynes@359
  2181
LDC.L @Rm+, VBR {:  
nkeynes@559
  2182
    check_priv();
nkeynes@359
  2183
    load_reg( R_EAX, Rm );
nkeynes@395
  2184
    check_ralign32( R_EAX );
nkeynes@359
  2185
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2186
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2187
    store_reg( R_EAX, Rm );
nkeynes@359
  2188
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2189
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2191
:}
nkeynes@359
  2192
LDC.L @Rm+, SSR {:
nkeynes@559
  2193
    check_priv();
nkeynes@359
  2194
    load_reg( R_EAX, Rm );
nkeynes@416
  2195
    check_ralign32( R_EAX );
nkeynes@359
  2196
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2197
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2198
    store_reg( R_EAX, Rm );
nkeynes@359
  2199
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2200
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2201
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2202
:}
nkeynes@359
  2203
LDC.L @Rm+, SGR {:  
nkeynes@559
  2204
    check_priv();
nkeynes@359
  2205
    load_reg( R_EAX, Rm );
nkeynes@395
  2206
    check_ralign32( R_EAX );
nkeynes@359
  2207
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2208
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2209
    store_reg( R_EAX, Rm );
nkeynes@359
  2210
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2211
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2212
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2213
:}
nkeynes@359
  2214
LDC.L @Rm+, SPC {:  
nkeynes@559
  2215
    check_priv();
nkeynes@359
  2216
    load_reg( R_EAX, Rm );
nkeynes@395
  2217
    check_ralign32( R_EAX );
nkeynes@359
  2218
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2219
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2220
    store_reg( R_EAX, Rm );
nkeynes@359
  2221
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2222
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2223
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2224
:}
nkeynes@359
  2225
LDC.L @Rm+, DBR {:  
nkeynes@559
  2226
    check_priv();
nkeynes@359
  2227
    load_reg( R_EAX, Rm );
nkeynes@395
  2228
    check_ralign32( R_EAX );
nkeynes@359
  2229
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2230
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2231
    store_reg( R_EAX, Rm );
nkeynes@359
  2232
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2233
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2235
:}
nkeynes@359
  2236
LDC.L @Rm+, Rn_BANK {:  
nkeynes@559
  2237
    check_priv();
nkeynes@374
  2238
    load_reg( R_EAX, Rm );
nkeynes@395
  2239
    check_ralign32( R_EAX );
nkeynes@374
  2240
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2241
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2242
    store_reg( R_EAX, Rm );
nkeynes@374
  2243
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2244
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2246
:}
nkeynes@359
  2247
LDS Rm, FPSCR {:  
nkeynes@359
  2248
    load_reg( R_EAX, Rm );
nkeynes@359
  2249
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2250
    update_fr_bank( R_EAX );
nkeynes@417
  2251
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2252
:}
nkeynes@359
  2253
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2254
    load_reg( R_EAX, Rm );
nkeynes@395
  2255
    check_ralign32( R_EAX );
nkeynes@359
  2256
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2257
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2258
    store_reg( R_EAX, Rm );
nkeynes@359
  2259
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2260
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2261
    update_fr_bank( R_EAX );
nkeynes@417
  2262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2263
:}
nkeynes@359
  2264
LDS Rm, FPUL {:  
nkeynes@359
  2265
    load_reg( R_EAX, Rm );
nkeynes@359
  2266
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2267
:}
nkeynes@359
  2268
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2269
    load_reg( R_EAX, Rm );
nkeynes@395
  2270
    check_ralign32( R_EAX );
nkeynes@359
  2271
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2272
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2273
    store_reg( R_EAX, Rm );
nkeynes@359
  2274
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2275
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2276
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2277
:}
nkeynes@359
  2278
LDS Rm, MACH {: 
nkeynes@359
  2279
    load_reg( R_EAX, Rm );
nkeynes@359
  2280
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2281
:}
nkeynes@359
  2282
LDS.L @Rm+, MACH {:  
nkeynes@359
  2283
    load_reg( R_EAX, Rm );
nkeynes@395
  2284
    check_ralign32( R_EAX );
nkeynes@359
  2285
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2286
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2287
    store_reg( R_EAX, Rm );
nkeynes@359
  2288
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2289
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2290
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2291
:}
nkeynes@359
  2292
LDS Rm, MACL {:  
nkeynes@359
  2293
    load_reg( R_EAX, Rm );
nkeynes@359
  2294
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2295
:}
nkeynes@359
  2296
LDS.L @Rm+, MACL {:  
nkeynes@359
  2297
    load_reg( R_EAX, Rm );
nkeynes@395
  2298
    check_ralign32( R_EAX );
nkeynes@359
  2299
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2300
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2301
    store_reg( R_EAX, Rm );
nkeynes@359
  2302
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2303
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2304
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2305
:}
nkeynes@359
  2306
LDS Rm, PR {:  
nkeynes@359
  2307
    load_reg( R_EAX, Rm );
nkeynes@359
  2308
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2309
:}
nkeynes@359
  2310
LDS.L @Rm+, PR {:  
nkeynes@359
  2311
    load_reg( R_EAX, Rm );
nkeynes@395
  2312
    check_ralign32( R_EAX );
nkeynes@359
  2313
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2314
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2315
    store_reg( R_EAX, Rm );
nkeynes@359
  2316
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2317
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2318
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2319
:}
nkeynes@550
  2320
LDTLB {:  
nkeynes@553
  2321
    call_func0( MMU_ldtlb );
nkeynes@550
  2322
:}
nkeynes@359
  2323
OCBI @Rn {:  :}
nkeynes@359
  2324
OCBP @Rn {:  :}
nkeynes@359
  2325
OCBWB @Rn {:  :}
nkeynes@374
  2326
PREF @Rn {:
nkeynes@374
  2327
    load_reg( R_EAX, Rn );
nkeynes@532
  2328
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2329
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2330
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
  2331
    JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
  2332
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
  2333
    JMP_TARGET(end);
nkeynes@417
  2334
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2335
:}
nkeynes@388
  2336
SLEEP {: 
nkeynes@388
  2337
    check_priv();
nkeynes@388
  2338
    call_func0( sh4_sleep );
nkeynes@417
  2339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2340
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2341
    return 2;
nkeynes@388
  2342
:}
nkeynes@386
  2343
STC SR, Rn {:
nkeynes@386
  2344
    check_priv();
nkeynes@386
  2345
    call_func0(sh4_read_sr);
nkeynes@386
  2346
    store_reg( R_EAX, Rn );
nkeynes@417
  2347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2348
:}
nkeynes@359
  2349
STC GBR, Rn {:  
nkeynes@359
  2350
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2351
    store_reg( R_EAX, Rn );
nkeynes@359
  2352
:}
nkeynes@359
  2353
STC VBR, Rn {:  
nkeynes@386
  2354
    check_priv();
nkeynes@359
  2355
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2356
    store_reg( R_EAX, Rn );
nkeynes@417
  2357
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2358
:}
nkeynes@359
  2359
STC SSR, Rn {:  
nkeynes@386
  2360
    check_priv();
nkeynes@359
  2361
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2362
    store_reg( R_EAX, Rn );
nkeynes@417
  2363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2364
:}
nkeynes@359
  2365
STC SPC, Rn {:  
nkeynes@386
  2366
    check_priv();
nkeynes@359
  2367
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2368
    store_reg( R_EAX, Rn );
nkeynes@417
  2369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2370
:}
nkeynes@359
  2371
STC SGR, Rn {:  
nkeynes@386
  2372
    check_priv();
nkeynes@359
  2373
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2374
    store_reg( R_EAX, Rn );
nkeynes@417
  2375
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2376
:}
nkeynes@359
  2377
STC DBR, Rn {:  
nkeynes@386
  2378
    check_priv();
nkeynes@359
  2379
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2380
    store_reg( R_EAX, Rn );
nkeynes@417
  2381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2382
:}
nkeynes@374
  2383
STC Rm_BANK, Rn {:
nkeynes@386
  2384
    check_priv();
nkeynes@374
  2385
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2386
    store_reg( R_EAX, Rn );
nkeynes@417
  2387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2388
:}
nkeynes@374
  2389
STC.L SR, @-Rn {:
nkeynes@559
  2390
    check_priv();
nkeynes@395
  2391
    call_func0( sh4_read_sr );
nkeynes@368
  2392
    load_reg( R_ECX, Rn );
nkeynes@395
  2393
    check_walign32( R_ECX );
nkeynes@382
  2394
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2395
    store_reg( R_ECX, Rn );
nkeynes@368
  2396
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2398
:}
nkeynes@359
  2399
STC.L VBR, @-Rn {:  
nkeynes@559
  2400
    check_priv();
nkeynes@359
  2401
    load_reg( R_ECX, Rn );
nkeynes@395
  2402
    check_walign32( R_ECX );
nkeynes@382
  2403
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2404
    store_reg( R_ECX, Rn );
nkeynes@359
  2405
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2406
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2408
:}
nkeynes@359
  2409
STC.L SSR, @-Rn {:  
nkeynes@559
  2410
    check_priv();
nkeynes@359
  2411
    load_reg( R_ECX, Rn );
nkeynes@395
  2412
    check_walign32( R_ECX );
nkeynes@382
  2413
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2414
    store_reg( R_ECX, Rn );
nkeynes@359
  2415
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2416
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2418
:}
nkeynes@416
  2419
STC.L SPC, @-Rn {:
nkeynes@559
  2420
    check_priv();
nkeynes@359
  2421
    load_reg( R_ECX, Rn );
nkeynes@395
  2422
    check_walign32( R_ECX );
nkeynes@382
  2423
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2424
    store_reg( R_ECX, Rn );
nkeynes@359
  2425
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2426
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2428
:}
nkeynes@359
  2429
STC.L SGR, @-Rn {:  
nkeynes@559
  2430
    check_priv();
nkeynes@359
  2431
    load_reg( R_ECX, Rn );
nkeynes@395
  2432
    check_walign32( R_ECX );
nkeynes@382
  2433
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2434
    store_reg( R_ECX, Rn );
nkeynes@359
  2435
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2436
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2437
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2438
:}
nkeynes@359
  2439
STC.L DBR, @-Rn {:  
nkeynes@559
  2440
    check_priv();
nkeynes@359
  2441
    load_reg( R_ECX, Rn );
nkeynes@395
  2442
    check_walign32( R_ECX );
nkeynes@382
  2443
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2444
    store_reg( R_ECX, Rn );
nkeynes@359
  2445
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2446
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2448
:}
nkeynes@374
  2449
STC.L Rm_BANK, @-Rn {:  
nkeynes@559
  2450
    check_priv();
nkeynes@374
  2451
    load_reg( R_ECX, Rn );
nkeynes@395
  2452
    check_walign32( R_ECX );
nkeynes@382
  2453
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2454
    store_reg( R_ECX, Rn );
nkeynes@374
  2455
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2456
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2458
:}
nkeynes@359
  2459
STC.L GBR, @-Rn {:  
nkeynes@359
  2460
    load_reg( R_ECX, Rn );
nkeynes@395
  2461
    check_walign32( R_ECX );
nkeynes@382
  2462
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2463
    store_reg( R_ECX, Rn );
nkeynes@359
  2464
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2465
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2467
:}
nkeynes@359
  2468
STS FPSCR, Rn {:  
nkeynes@359
  2469
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2470
    store_reg( R_EAX, Rn );
nkeynes@359
  2471
:}
nkeynes@359
  2472
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2473
    load_reg( R_ECX, Rn );
nkeynes@395
  2474
    check_walign32( R_ECX );
nkeynes@382
  2475
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2476
    store_reg( R_ECX, Rn );
nkeynes@359
  2477
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2478
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2480
:}
nkeynes@359
  2481
STS FPUL, Rn {:  
nkeynes@359
  2482
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2483
    store_reg( R_EAX, Rn );
nkeynes@359
  2484
:}
nkeynes@359
  2485
STS.L FPUL, @-Rn {:  
nkeynes@359
  2486
    load_reg( R_ECX, Rn );
nkeynes@395
  2487
    check_walign32( R_ECX );
nkeynes@382
  2488
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2489
    store_reg( R_ECX, Rn );
nkeynes@359
  2490
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2491
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2492
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2493
:}
nkeynes@359
  2494
STS MACH, Rn {:  
nkeynes@359
  2495
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2496
    store_reg( R_EAX, Rn );
nkeynes@359
  2497
:}
nkeynes@359
  2498
STS.L MACH, @-Rn {:  
nkeynes@359
  2499
    load_reg( R_ECX, Rn );
nkeynes@395
  2500
    check_walign32( R_ECX );
nkeynes@382
  2501
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2502
    store_reg( R_ECX, Rn );
nkeynes@359
  2503
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2504
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2505
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2506
:}
nkeynes@359
  2507
STS MACL, Rn {:  
nkeynes@359
  2508
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2509
    store_reg( R_EAX, Rn );
nkeynes@359
  2510
:}
nkeynes@359
  2511
STS.L MACL, @-Rn {:  
nkeynes@359
  2512
    load_reg( R_ECX, Rn );
nkeynes@395
  2513
    check_walign32( R_ECX );
nkeynes@382
  2514
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2515
    store_reg( R_ECX, Rn );
nkeynes@359
  2516
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2517
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2518
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2519
:}
nkeynes@359
  2520
STS PR, Rn {:  
nkeynes@359
  2521
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2522
    store_reg( R_EAX, Rn );
nkeynes@359
  2523
:}
nkeynes@359
  2524
STS.L PR, @-Rn {:  
nkeynes@359
  2525
    load_reg( R_ECX, Rn );
nkeynes@395
  2526
    check_walign32( R_ECX );
nkeynes@382
  2527
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2528
    store_reg( R_ECX, Rn );
nkeynes@359
  2529
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2530
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2531
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2532
:}
nkeynes@359
  2533
nkeynes@359
  2534
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2535
%%
nkeynes@416
  2536
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2537
    return 0;
nkeynes@359
  2538
}
.