Search
lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/mmu.c
changeset 948:545c85cc56f1
prev946:d41ee7994db7
next951:63483914846f
author nkeynes
date Wed Jan 07 04:39:04 2009 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Introduce sh4_finalize_instruction to clean-up on instruction exits
Remove the sh4_flush_icache special cases, now works through the
general case.
file annotate diff log raw
nkeynes@550
     1
/**
nkeynes@586
     2
 * $Id$
nkeynes@826
     3
 *
nkeynes@939
     4
 * SH4 MMU implementation based on address space page maps. This module
nkeynes@939
     5
 * is responsible for all address decoding functions. 
nkeynes@550
     6
 *
nkeynes@550
     7
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@550
     8
 *
nkeynes@550
     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@550
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@550
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@550
    12
 * (at your option) any later version.
nkeynes@550
    13
 *
nkeynes@550
    14
 * This program is distributed in the hope that it will be useful,
nkeynes@550
    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@550
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@550
    17
 * GNU General Public License for more details.
nkeynes@550
    18
 */
nkeynes@550
    19
#define MODULE sh4_module
nkeynes@550
    20
nkeynes@550
    21
#include <stdio.h>
nkeynes@915
    22
#include <assert.h>
nkeynes@550
    23
#include "sh4/sh4mmio.h"
nkeynes@550
    24
#include "sh4/sh4core.h"
nkeynes@669
    25
#include "sh4/sh4trans.h"
nkeynes@934
    26
#include "dreamcast.h"
nkeynes@550
    27
#include "mem.h"
nkeynes@931
    28
#include "mmu.h"
nkeynes@550
    29
nkeynes@586
    30
#define RAISE_TLB_ERROR(code, vpn) \
nkeynes@586
    31
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@586
    32
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@586
    33
    sh4_raise_tlb_exception(code);
nkeynes@586
    34
#define RAISE_MEM_ERROR(code, vpn) \
nkeynes@586
    35
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@586
    36
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@586
    37
    sh4_raise_exception(code);
nkeynes@939
    38
#define RAISE_TLB_MULTIHIT_ERROR(vpn) \
nkeynes@939
    39
    sh4_raise_reset(EXC_TLB_MULTI_HIT); \
nkeynes@586
    40
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@586
    41
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
nkeynes@586
    42
nkeynes@939
    43
/* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
nkeynes@939
    44
#define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
nkeynes@586
    45
nkeynes@939
    46
/* Primary address space (used directly by SH4 cores) */
nkeynes@939
    47
mem_region_fn_t *sh4_address_space;
nkeynes@939
    48
mem_region_fn_t *sh4_user_address_space;
nkeynes@550
    49
nkeynes@939
    50
/* Accessed from the UTLB accessor methods */
nkeynes@939
    51
uint32_t mmu_urc;
nkeynes@939
    52
uint32_t mmu_urb;
nkeynes@939
    53
nkeynes@939
    54
/* Module globals */
nkeynes@550
    55
static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
nkeynes@550
    56
static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
nkeynes@939
    57
static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
nkeynes@550
    58
static uint32_t mmu_lrui;
nkeynes@586
    59
static uint32_t mmu_asid; // current asid
nkeynes@946
    60
static struct utlb_default_regions *mmu_user_storequeue_regions;
nkeynes@550
    61
nkeynes@939
    62
/* Structures for 1K page handling */
nkeynes@939
    63
static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
nkeynes@939
    64
static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
nkeynes@939
    65
static int mmu_utlb_1k_free_index;
nkeynes@915
    66
nkeynes@550
    67
nkeynes@939
    68
/* Function prototypes */
nkeynes@550
    69
static void mmu_invalidate_tlb();
nkeynes@939
    70
static void mmu_utlb_register_all();
nkeynes@939
    71
static void mmu_utlb_remove_entry(int);
nkeynes@939
    72
static void mmu_utlb_insert_entry(int);
nkeynes@939
    73
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
nkeynes@939
    74
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
nkeynes@939
    75
static void mmu_set_tlb_enabled( int tlb_on );
nkeynes@939
    76
static void mmu_set_tlb_asid( uint32_t asid );
nkeynes@946
    77
static void mmu_set_storequeue_protected( int protected, int tlb_on );
nkeynes@939
    78
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
nkeynes@943
    79
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
nkeynes@943
    80
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
nkeynes@939
    81
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
nkeynes@939
    82
static void mmu_utlb_1k_init();
nkeynes@939
    83
static struct utlb_1k_entry *mmu_utlb_1k_alloc();
nkeynes@939
    84
static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
nkeynes@550
    85
nkeynes@946
    86
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
nkeynes@939
    87
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
nkeynes@939
    88
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
nkeynes@939
    89
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
nkeynes@939
    90
static uint32_t get_tlb_size_mask( uint32_t flags );
nkeynes@939
    91
static uint32_t get_tlb_size_pages( uint32_t flags );
nkeynes@586
    92
nkeynes@946
    93
#define DEFAULT_REGIONS 0
nkeynes@946
    94
#define DEFAULT_STOREQUEUE_REGIONS 1
nkeynes@946
    95
#define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
nkeynes@946
    96
nkeynes@946
    97
static struct utlb_default_regions mmu_default_regions[3] = {
nkeynes@946
    98
        { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
nkeynes@946
    99
        { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
nkeynes@946
   100
        { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
nkeynes@946
   101
nkeynes@946
   102
#define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
nkeynes@550
   103
nkeynes@939
   104
/*********************** Module public functions ****************************/
nkeynes@550
   105
nkeynes@939
   106
/**
nkeynes@939
   107
 * Allocate memory for the address space maps, and initialize them according
nkeynes@939
   108
 * to the default (reset) values. (TLB is disabled by default)
nkeynes@939
   109
 */
nkeynes@939
   110
                           
nkeynes@826
   111
void MMU_init()
nkeynes@550
   112
{
nkeynes@939
   113
    sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
nkeynes@939
   114
    sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
nkeynes@946
   115
    mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@939
   116
    
nkeynes@939
   117
    mmu_set_tlb_enabled(0);
nkeynes@939
   118
    mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
nkeynes@946
   119
    mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
nkeynes@939
   120
    
nkeynes@939
   121
    /* Setup P4 tlb/cache access regions */
nkeynes@939
   122
    mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@939
   123
    mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
nkeynes@939
   124
    mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
nkeynes@939
   125
    mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
nkeynes@939
   126
    mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
nkeynes@939
   127
    mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
nkeynes@939
   128
    mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
nkeynes@939
   129
    mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
nkeynes@939
   130
    mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
nkeynes@939
   131
    mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
nkeynes@939
   132
    mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
nkeynes@939
   133
    
nkeynes@939
   134
    /* Setup P4 control region */
nkeynes@939
   135
    mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
nkeynes@939
   136
    mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
nkeynes@939
   137
    mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
nkeynes@939
   138
    mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
nkeynes@939
   139
    mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
nkeynes@939
   140
    mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
nkeynes@939
   141
    mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
nkeynes@939
   142
    mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
nkeynes@939
   143
    mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
nkeynes@939
   144
    mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
nkeynes@939
   145
    mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
nkeynes@939
   146
    mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
nkeynes@939
   147
    mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
nkeynes@939
   148
    
nkeynes@939
   149
    register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
nkeynes@939
   150
    mmu_utlb_1k_init();
nkeynes@939
   151
    
nkeynes@939
   152
    /* Ensure the code regions are executable */
nkeynes@939
   153
    mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
nkeynes@939
   154
    mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
nkeynes@550
   155
}
nkeynes@550
   156
nkeynes@550
   157
void MMU_reset()
nkeynes@550
   158
{
nkeynes@550
   159
    mmio_region_MMU_write( CCR, 0 );
nkeynes@586
   160
    mmio_region_MMU_write( MMUCR, 0 );
nkeynes@550
   161
}
nkeynes@550
   162
nkeynes@550
   163
void MMU_save_state( FILE *f )
nkeynes@550
   164
{
nkeynes@550
   165
    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
nkeynes@550
   166
    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
nkeynes@586
   167
    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
nkeynes@586
   168
    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
nkeynes@586
   169
    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
nkeynes@586
   170
    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
nkeynes@550
   171
}
nkeynes@550
   172
nkeynes@550
   173
int MMU_load_state( FILE *f )
nkeynes@550
   174
{
nkeynes@550
   175
    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
nkeynes@736
   176
        return 1;
nkeynes@550
   177
    }
nkeynes@550
   178
    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
nkeynes@736
   179
        return 1;
nkeynes@550
   180
    }
nkeynes@586
   181
    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
nkeynes@736
   182
        return 1;
nkeynes@586
   183
    }
nkeynes@586
   184
    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
nkeynes@736
   185
        return 1;
nkeynes@586
   186
    }
nkeynes@586
   187
    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
nkeynes@736
   188
        return 1;
nkeynes@586
   189
    }
nkeynes@586
   190
    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
nkeynes@736
   191
        return 1;
nkeynes@586
   192
    }
nkeynes@939
   193
nkeynes@939
   194
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@939
   195
    mmu_set_tlb_enabled(mmucr&MMUCR_AT);
nkeynes@946
   196
    mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
nkeynes@550
   197
    return 0;
nkeynes@550
   198
}
nkeynes@550
   199
nkeynes@550
   200
/**
nkeynes@550
   201
 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
nkeynes@550
   202
 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
nkeynes@550
   203
 */
nkeynes@550
   204
void MMU_ldtlb()
nkeynes@550
   205
{
nkeynes@939
   206
    mmu_urc %= mmu_urb;
nkeynes@915
   207
    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
nkeynes@915
   208
        mmu_utlb_remove_entry( mmu_urc );
nkeynes@550
   209
    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
nkeynes@550
   210
    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
nkeynes@550
   211
    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
nkeynes@550
   212
    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
nkeynes@550
   213
    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
nkeynes@939
   214
    mmu_utlb[mmu_urc].mask = get_tlb_size_mask(mmu_utlb[mmu_urc].flags);
nkeynes@915
   215
    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
nkeynes@915
   216
        mmu_utlb_insert_entry( mmu_urc );
nkeynes@550
   217
}
nkeynes@550
   218
nkeynes@939
   219
nkeynes@939
   220
MMIO_REGION_READ_FN( MMU, reg )
nkeynes@939
   221
{
nkeynes@939
   222
    reg &= 0xFFF;
nkeynes@939
   223
    switch( reg ) {
nkeynes@939
   224
    case MMUCR:
nkeynes@939
   225
        mmu_urc %= mmu_urb;
nkeynes@939
   226
        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
nkeynes@939
   227
    default:
nkeynes@939
   228
        return MMIO_READ( MMU, reg );
nkeynes@939
   229
    }
nkeynes@939
   230
}
nkeynes@939
   231
nkeynes@939
   232
MMIO_REGION_WRITE_FN( MMU, reg, val )
nkeynes@939
   233
{
nkeynes@939
   234
    uint32_t tmp;
nkeynes@939
   235
    reg &= 0xFFF;
nkeynes@939
   236
    switch(reg) {
nkeynes@939
   237
    case SH4VER:
nkeynes@939
   238
        return;
nkeynes@939
   239
    case PTEH:
nkeynes@939
   240
        val &= 0xFFFFFCFF;
nkeynes@939
   241
        if( (val & 0xFF) != mmu_asid ) {
nkeynes@939
   242
            mmu_set_tlb_asid( val&0xFF );
nkeynes@939
   243
            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
nkeynes@939
   244
        }
nkeynes@939
   245
        break;
nkeynes@939
   246
    case PTEL:
nkeynes@939
   247
        val &= 0x1FFFFDFF;
nkeynes@939
   248
        break;
nkeynes@939
   249
    case PTEA:
nkeynes@939
   250
        val &= 0x0000000F;
nkeynes@939
   251
        break;
nkeynes@939
   252
    case TRA:
nkeynes@939
   253
        val &= 0x000003FC;
nkeynes@939
   254
        break;
nkeynes@939
   255
    case EXPEVT:
nkeynes@939
   256
    case INTEVT:
nkeynes@939
   257
        val &= 0x00000FFF;
nkeynes@939
   258
        break;
nkeynes@939
   259
    case MMUCR:
nkeynes@939
   260
        if( val & MMUCR_TI ) {
nkeynes@939
   261
            mmu_invalidate_tlb();
nkeynes@939
   262
        }
nkeynes@939
   263
        mmu_urc = (val >> 10) & 0x3F;
nkeynes@939
   264
        mmu_urb = (val >> 18) & 0x3F;
nkeynes@939
   265
        if( mmu_urb == 0 ) {
nkeynes@939
   266
            mmu_urb = 0x40;
nkeynes@939
   267
        }
nkeynes@939
   268
        mmu_lrui = (val >> 26) & 0x3F;
nkeynes@939
   269
        val &= 0x00000301;
nkeynes@939
   270
        tmp = MMIO_READ( MMU, MMUCR );
nkeynes@939
   271
        if( (val ^ tmp) & (MMUCR_SQMD) ) {
nkeynes@946
   272
            mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
nkeynes@939
   273
        }
nkeynes@939
   274
        if( (val ^ tmp) & (MMUCR_AT) ) {
nkeynes@939
   275
            // AT flag has changed state - flush the xlt cache as all bets
nkeynes@939
   276
            // are off now. We also need to force an immediate exit from the
nkeynes@939
   277
            // current block
nkeynes@939
   278
            mmu_set_tlb_enabled( val & MMUCR_AT );
nkeynes@939
   279
            MMIO_WRITE( MMU, MMUCR, val );
nkeynes@948
   280
            sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
nkeynes@948
   281
            xlat_flush_cache(); // If we're not running, flush the cache anyway
nkeynes@939
   282
        }
nkeynes@939
   283
        break;
nkeynes@939
   284
    case CCR:
nkeynes@939
   285
        CCN_set_cache_control( val );
nkeynes@939
   286
        val &= 0x81A7;
nkeynes@939
   287
        break;
nkeynes@939
   288
    case MMUUNK1:
nkeynes@939
   289
        /* Note that if the high bit is set, this appears to reset the machine.
nkeynes@939
   290
         * Not emulating this behaviour yet until we know why...
nkeynes@939
   291
         */
nkeynes@939
   292
        val &= 0x00010007;
nkeynes@939
   293
        break;
nkeynes@939
   294
    case QACR0:
nkeynes@939
   295
    case QACR1:
nkeynes@939
   296
        val &= 0x0000001C;
nkeynes@939
   297
        break;
nkeynes@939
   298
    case PMCR1:
nkeynes@939
   299
        PMM_write_control(0, val);
nkeynes@939
   300
        val &= 0x0000C13F;
nkeynes@939
   301
        break;
nkeynes@939
   302
    case PMCR2:
nkeynes@939
   303
        PMM_write_control(1, val);
nkeynes@939
   304
        val &= 0x0000C13F;
nkeynes@939
   305
        break;
nkeynes@939
   306
    default:
nkeynes@939
   307
        break;
nkeynes@939
   308
    }
nkeynes@939
   309
    MMIO_WRITE( MMU, reg, val );
nkeynes@939
   310
}
nkeynes@939
   311
nkeynes@939
   312
/********************** 1K Page handling ***********************/
nkeynes@939
   313
/* Since we use 4K pages as our native page size, 1K pages need a bit of extra
nkeynes@939
   314
 * effort to manage - we justify this on the basis that most programs won't
nkeynes@939
   315
 * actually use 1K pages, so we may as well optimize for the common case.
nkeynes@939
   316
 * 
nkeynes@939
   317
 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
nkeynes@939
   318
 * redirects requests to the 'real' page entry. These are allocated on an
nkeynes@939
   319
 * as-needed basis, and returned to the pool when all subpages are empty.
nkeynes@939
   320
 */ 
nkeynes@939
   321
static void mmu_utlb_1k_init()
nkeynes@939
   322
{
nkeynes@939
   323
    int i;
nkeynes@939
   324
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   325
        mmu_utlb_1k_free_list[i] = i;
nkeynes@939
   326
        mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
nkeynes@939
   327
    }
nkeynes@939
   328
    mmu_utlb_1k_free_index = 0;
nkeynes@939
   329
}
nkeynes@939
   330
nkeynes@939
   331
static struct utlb_1k_entry *mmu_utlb_1k_alloc()
nkeynes@939
   332
{
nkeynes@939
   333
    assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
nkeynes@939
   334
    struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_index++];
nkeynes@939
   335
    return entry;
nkeynes@939
   336
}    
nkeynes@939
   337
nkeynes@939
   338
static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
nkeynes@939
   339
{
nkeynes@939
   340
    unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
nkeynes@939
   341
    assert( entryNo < UTLB_ENTRY_COUNT );
nkeynes@939
   342
    assert( mmu_utlb_1k_free_index > 0 );
nkeynes@939
   343
    mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
nkeynes@939
   344
}
nkeynes@939
   345
nkeynes@939
   346
nkeynes@939
   347
/********************** Address space maintenance *************************/
nkeynes@939
   348
nkeynes@939
   349
/**
nkeynes@939
   350
 * MMU accessor functions just increment URC - fixup here if necessary
nkeynes@939
   351
 */
nkeynes@939
   352
static inline void mmu_urc_fixup()
nkeynes@939
   353
{
nkeynes@939
   354
   mmu_urc %= mmu_urb; 
nkeynes@939
   355
}
nkeynes@939
   356
nkeynes@939
   357
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   358
{
nkeynes@939
   359
    int count = (end - start) >> 12;
nkeynes@939
   360
    mem_region_fn_t *ptr = &sh4_address_space[start>>12];
nkeynes@939
   361
    while( count-- > 0 ) {
nkeynes@939
   362
        *ptr++ = fn;
nkeynes@939
   363
    }
nkeynes@939
   364
}
nkeynes@939
   365
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   366
{
nkeynes@939
   367
    int count = (end - start) >> 12;
nkeynes@939
   368
    mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
nkeynes@939
   369
    while( count-- > 0 ) {
nkeynes@939
   370
        *ptr++ = fn;
nkeynes@939
   371
    }
nkeynes@939
   372
}
nkeynes@939
   373
nkeynes@939
   374
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
nkeynes@939
   375
{
nkeynes@939
   376
    int i;
nkeynes@939
   377
    if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
nkeynes@939
   378
        /* TLB on */
nkeynes@939
   379
        sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
nkeynes@939
   380
        sh4_address_space[(page|0xA0000000)>>12] = fn;
nkeynes@939
   381
        /* Scan UTLB and update any direct-referencing entries */
nkeynes@939
   382
    } else {
nkeynes@939
   383
        /* Direct map to U0, P0, P1, P2, P3 */
nkeynes@939
   384
        for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
nkeynes@939
   385
            sh4_address_space[(page|i)>>12] = fn;
nkeynes@939
   386
        }
nkeynes@939
   387
        for( i=0; i < 0x80000000; i+= 0x20000000 ) {
nkeynes@939
   388
            sh4_user_address_space[(page|i)>>12] = fn;
nkeynes@939
   389
        }
nkeynes@939
   390
    }
nkeynes@939
   391
}
nkeynes@939
   392
nkeynes@939
   393
static void mmu_set_tlb_enabled( int tlb_on )
nkeynes@939
   394
{
nkeynes@939
   395
    mem_region_fn_t *ptr, *uptr;
nkeynes@939
   396
    int i;
nkeynes@939
   397
    
nkeynes@946
   398
    /* Reset the storequeue area */
nkeynes@946
   399
nkeynes@939
   400
    if( tlb_on ) {
nkeynes@939
   401
        mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@939
   402
        mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
nkeynes@939
   403
        mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@946
   404
        
nkeynes@946
   405
        /* Default SQ prefetch goes to TLB miss (?) */
nkeynes@946
   406
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
nkeynes@946
   407
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@939
   408
        mmu_utlb_register_all();
nkeynes@939
   409
    } else {
nkeynes@939
   410
        for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   411
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   412
        }
nkeynes@939
   413
        for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   414
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   415
        }
nkeynes@946
   416
nkeynes@946
   417
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   418
        if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   419
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
nkeynes@946
   420
        } else {
nkeynes@946
   421
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   422
        }
nkeynes@939
   423
    }
nkeynes@946
   424
    
nkeynes@939
   425
}
nkeynes@939
   426
nkeynes@946
   427
/**
nkeynes@946
   428
 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
nkeynes@946
   429
 * anything expects to do this frequently.
nkeynes@946
   430
 */
nkeynes@946
   431
static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
nkeynes@939
   432
{
nkeynes@946
   433
    mem_region_fn_t nontlb_region;
nkeynes@946
   434
    int i;
nkeynes@946
   435
nkeynes@939
   436
    if( protected ) {
nkeynes@946
   437
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
nkeynes@946
   438
        nontlb_region = &p4_region_storequeue_sqmd;
nkeynes@939
   439
    } else {
nkeynes@946
   440
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   441
        nontlb_region = &p4_region_storequeue; 
nkeynes@939
   442
    }
nkeynes@946
   443
nkeynes@946
   444
    if( tlb_on ) {
nkeynes@946
   445
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@946
   446
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@946
   447
            if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   448
                mmu_utlb_insert_entry(i);
nkeynes@946
   449
            }
nkeynes@946
   450
        }
nkeynes@946
   451
    } else {
nkeynes@946
   452
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
nkeynes@946
   453
    }
nkeynes@946
   454
    
nkeynes@939
   455
}
nkeynes@939
   456
nkeynes@939
   457
static void mmu_set_tlb_asid( uint32_t asid )
nkeynes@939
   458
{
nkeynes@939
   459
    /* Scan for pages that need to be remapped */
nkeynes@939
   460
    int i;
nkeynes@939
   461
    if( IS_SV_ENABLED() ) {
nkeynes@939
   462
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   463
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   464
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   465
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   466
                        if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   467
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   468
                            mmu_utlb_remap_pages( FALSE, TRUE, i );
nkeynes@939
   469
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   470
                        mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   471
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   472
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   473
                    }
nkeynes@939
   474
                }
nkeynes@939
   475
            }
nkeynes@939
   476
        }
nkeynes@939
   477
    } else {
nkeynes@939
   478
        // Remap both Priv+user pages
nkeynes@939
   479
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   480
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   481
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   482
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   483
                        if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   484
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   485
                            mmu_utlb_remap_pages( TRUE, TRUE, i );
nkeynes@939
   486
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   487
                        mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   488
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   489
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   490
                    }
nkeynes@939
   491
                }
nkeynes@939
   492
            }
nkeynes@939
   493
        }
nkeynes@939
   494
    }
nkeynes@939
   495
    
nkeynes@939
   496
    mmu_asid = asid;
nkeynes@939
   497
}
nkeynes@939
   498
nkeynes@939
   499
static uint32_t get_tlb_size_mask( uint32_t flags )
nkeynes@939
   500
{
nkeynes@939
   501
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   502
    case TLB_SIZE_1K: return MASK_1K;
nkeynes@939
   503
    case TLB_SIZE_4K: return MASK_4K;
nkeynes@939
   504
    case TLB_SIZE_64K: return MASK_64K;
nkeynes@939
   505
    case TLB_SIZE_1M: return MASK_1M;
nkeynes@939
   506
    default: return 0; /* Unreachable */
nkeynes@939
   507
    }
nkeynes@939
   508
}
nkeynes@939
   509
static uint32_t get_tlb_size_pages( uint32_t flags )
nkeynes@939
   510
{
nkeynes@939
   511
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   512
    case TLB_SIZE_1K: return 0;
nkeynes@939
   513
    case TLB_SIZE_4K: return 1;
nkeynes@939
   514
    case TLB_SIZE_64K: return 16;
nkeynes@939
   515
    case TLB_SIZE_1M: return 256;
nkeynes@939
   516
    default: return 0; /* Unreachable */
nkeynes@939
   517
    }
nkeynes@939
   518
}
nkeynes@939
   519
nkeynes@939
   520
/**
nkeynes@939
   521
 * Add a new TLB entry mapping to the address space table. If any of the pages
nkeynes@939
   522
 * are already mapped, they are mapped to the TLB multi-hit page instead.
nkeynes@939
   523
 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
nkeynes@939
   524
 */ 
nkeynes@939
   525
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
nkeynes@939
   526
{
nkeynes@939
   527
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   528
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   529
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   530
    struct utlb_default_regions *userdefs = privdefs;    
nkeynes@946
   531
    
nkeynes@939
   532
    gboolean mapping_ok = TRUE;
nkeynes@939
   533
    int i;
nkeynes@939
   534
    
nkeynes@939
   535
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   536
        /* Storequeue mapping */
nkeynes@946
   537
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   538
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   539
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   540
        user_page = NULL; /* No user access to P3 region */
nkeynes@939
   541
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   542
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   543
    }
nkeynes@939
   544
nkeynes@939
   545
    if( npages == 0 ) {
nkeynes@939
   546
        struct utlb_1k_entry *ent;
nkeynes@939
   547
        int i, idx = (start_addr >> 10) & 0x03;
nkeynes@939
   548
        if( IS_1K_PAGE_ENTRY(*ptr) ) {
nkeynes@939
   549
            ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   550
        } else {
nkeynes@939
   551
            ent = mmu_utlb_1k_alloc();
nkeynes@939
   552
            /* New 1K struct - init to previous contents of region */
nkeynes@939
   553
            for( i=0; i<4; i++ ) {
nkeynes@939
   554
                ent->subpages[i] = *ptr;
nkeynes@939
   555
                ent->user_subpages[i] = *uptr;
nkeynes@939
   556
            }
nkeynes@939
   557
            *ptr = &ent->fn;
nkeynes@939
   558
            *uptr = &ent->user_fn;
nkeynes@939
   559
        }
nkeynes@939
   560
        
nkeynes@939
   561
        if( priv_page != NULL ) {
nkeynes@946
   562
            if( ent->subpages[idx] == privdefs->tlb_miss ) {
nkeynes@939
   563
                ent->subpages[idx] = priv_page;
nkeynes@939
   564
            } else {
nkeynes@939
   565
                mapping_ok = FALSE;
nkeynes@946
   566
                ent->subpages[idx] = privdefs->tlb_multihit;
nkeynes@939
   567
            }
nkeynes@939
   568
        }
nkeynes@939
   569
        if( user_page != NULL ) {
nkeynes@946
   570
            if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
nkeynes@939
   571
                ent->user_subpages[idx] = user_page;
nkeynes@939
   572
            } else {
nkeynes@939
   573
                mapping_ok = FALSE;
nkeynes@946
   574
                ent->user_subpages[idx] = userdefs->tlb_multihit;
nkeynes@939
   575
            }
nkeynes@939
   576
        }
nkeynes@939
   577
        
nkeynes@939
   578
    } else {
nkeynes@943
   579
        if( priv_page != NULL ) {
nkeynes@946
   580
            /* Privileged mapping only */
nkeynes@946
   581
            for( i=0; i<npages; i++ ) {
nkeynes@946
   582
                if( *ptr == privdefs->tlb_miss ) {
nkeynes@946
   583
                    *ptr++ = priv_page;
nkeynes@946
   584
                } else {
nkeynes@946
   585
                    mapping_ok = FALSE;
nkeynes@946
   586
                    *ptr++ = privdefs->tlb_multihit;
nkeynes@939
   587
                }
nkeynes@939
   588
            }
nkeynes@946
   589
        }
nkeynes@946
   590
        if( user_page != NULL ) {
nkeynes@943
   591
            /* User mapping only (eg ASID change remap w/ SV=1) */
nkeynes@939
   592
            for( i=0; i<npages; i++ ) {
nkeynes@946
   593
                if( *uptr == userdefs->tlb_miss ) {
nkeynes@939
   594
                    *uptr++ = user_page;
nkeynes@939
   595
                } else {
nkeynes@939
   596
                    mapping_ok = FALSE;
nkeynes@946
   597
                    *uptr++ = userdefs->tlb_multihit;
nkeynes@939
   598
                }
nkeynes@939
   599
            }        
nkeynes@939
   600
        }
nkeynes@939
   601
    }
nkeynes@946
   602
nkeynes@939
   603
    return mapping_ok;
nkeynes@939
   604
}
nkeynes@939
   605
nkeynes@939
   606
/**
nkeynes@943
   607
 * Remap any pages within the region covered by entryNo, but not including 
nkeynes@943
   608
 * entryNo itself. This is used to reestablish pages that were previously
nkeynes@943
   609
 * covered by a multi-hit exception region when one of the pages is removed.
nkeynes@943
   610
 */
nkeynes@943
   611
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
nkeynes@943
   612
{
nkeynes@943
   613
    int mask = mmu_utlb[entryNo].mask;
nkeynes@943
   614
    uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
nkeynes@943
   615
    int i;
nkeynes@943
   616
    
nkeynes@943
   617
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@943
   618
        if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
nkeynes@943
   619
            /* Overlapping region */
nkeynes@943
   620
            mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
nkeynes@943
   621
            mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
nkeynes@943
   622
            uint32_t start_addr;
nkeynes@943
   623
            int npages;
nkeynes@943
   624
nkeynes@943
   625
            if( mmu_utlb[i].mask >= mask ) {
nkeynes@943
   626
                /* entry is no larger than the area we're replacing - map completely */
nkeynes@943
   627
                start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
nkeynes@943
   628
                npages = get_tlb_size_pages( mmu_utlb[i].flags );
nkeynes@943
   629
            } else {
nkeynes@943
   630
                /* Otherwise map subset - region covered by removed page */
nkeynes@943
   631
                start_addr = remap_addr;
nkeynes@943
   632
                npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
nkeynes@943
   633
            }
nkeynes@943
   634
nkeynes@943
   635
            if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
nkeynes@943
   636
                mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
nkeynes@943
   637
            } else if( IS_SV_ENABLED() ) {
nkeynes@943
   638
                mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
nkeynes@943
   639
            }
nkeynes@943
   640
nkeynes@943
   641
        }
nkeynes@943
   642
    }
nkeynes@943
   643
}
nkeynes@943
   644
nkeynes@943
   645
/**
nkeynes@939
   646
 * Remove a previous TLB mapping (replacing them with the TLB miss region).
nkeynes@939
   647
 * @return FALSE if any pages were previously mapped to the TLB multihit page, 
nkeynes@939
   648
 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
nkeynes@939
   649
 */
nkeynes@943
   650
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
nkeynes@939
   651
{
nkeynes@939
   652
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   653
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   654
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   655
    struct utlb_default_regions *userdefs = privdefs;
nkeynes@946
   656
nkeynes@939
   657
    gboolean unmapping_ok = TRUE;
nkeynes@939
   658
    int i;
nkeynes@939
   659
    
nkeynes@939
   660
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   661
        /* Storequeue mapping */
nkeynes@946
   662
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   663
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   664
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   665
        unmap_user = FALSE;
nkeynes@939
   666
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   667
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   668
    }
nkeynes@939
   669
nkeynes@939
   670
    if( npages == 0 ) { // 1K page
nkeynes@939
   671
        assert( IS_1K_PAGE_ENTRY( *ptr ) );
nkeynes@939
   672
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   673
        int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
nkeynes@946
   674
        if( ent->subpages[idx] == privdefs->tlb_multihit ) {
nkeynes@939
   675
            unmapping_ok = FALSE;
nkeynes@939
   676
        }
nkeynes@943
   677
        if( unmap_priv )
nkeynes@946
   678
            ent->subpages[idx] = privdefs->tlb_miss;
nkeynes@943
   679
        if( unmap_user )
nkeynes@946
   680
            ent->user_subpages[idx] = userdefs->tlb_miss;
nkeynes@939
   681
nkeynes@939
   682
        /* If all 4 subpages have the same content, merge them together and
nkeynes@939
   683
         * release the 1K entry
nkeynes@939
   684
         */
nkeynes@939
   685
        mem_region_fn_t priv_page = ent->subpages[0];
nkeynes@939
   686
        mem_region_fn_t user_page = ent->user_subpages[0];
nkeynes@939
   687
        for( i=1; i<4; i++ ) {
nkeynes@939
   688
            if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
nkeynes@939
   689
                mergeable = 0;
nkeynes@939
   690
                break;
nkeynes@939
   691
            }
nkeynes@939
   692
        }
nkeynes@939
   693
        if( mergeable ) {
nkeynes@939
   694
            mmu_utlb_1k_free(ent);
nkeynes@939
   695
            *ptr = priv_page;
nkeynes@939
   696
            *uptr = user_page;
nkeynes@939
   697
        }
nkeynes@939
   698
    } else {
nkeynes@943
   699
        if( unmap_priv ) {
nkeynes@946
   700
            /* Privileged (un)mapping */
nkeynes@939
   701
            for( i=0; i<npages; i++ ) {
nkeynes@946
   702
                if( *ptr == privdefs->tlb_multihit ) {
nkeynes@939
   703
                    unmapping_ok = FALSE;
nkeynes@939
   704
                }
nkeynes@946
   705
                *ptr++ = privdefs->tlb_miss;
nkeynes@946
   706
            }
nkeynes@946
   707
        }
nkeynes@946
   708
        if( unmap_user ) {
nkeynes@946
   709
            /* User (un)mapping */
nkeynes@946
   710
            for( i=0; i<npages; i++ ) {
nkeynes@946
   711
                if( *uptr == userdefs->tlb_multihit ) {
nkeynes@946
   712
                    unmapping_ok = FALSE;
nkeynes@946
   713
                }
nkeynes@946
   714
                *uptr++ = userdefs->tlb_miss;
nkeynes@943
   715
            }            
nkeynes@939
   716
        }
nkeynes@939
   717
    }
nkeynes@943
   718
    
nkeynes@939
   719
    return unmapping_ok;
nkeynes@939
   720
}
nkeynes@939
   721
nkeynes@939
   722
static void mmu_utlb_insert_entry( int entry )
nkeynes@939
   723
{
nkeynes@939
   724
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   725
    mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
nkeynes@939
   726
    mem_region_fn_t upage;
nkeynes@939
   727
    sh4addr_t start_addr = ent->vpn & ent->mask;
nkeynes@939
   728
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   729
nkeynes@946
   730
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   731
        /* Store queue mappings are a bit different - normal access is fixed to
nkeynes@946
   732
         * the store queue register block, and we only map prefetches through
nkeynes@946
   733
         * the TLB 
nkeynes@946
   734
         */
nkeynes@946
   735
        mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
nkeynes@946
   736
nkeynes@946
   737
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   738
            upage = mmu_user_storequeue_regions->tlb_prot;
nkeynes@946
   739
        } else if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   740
            upage = &p4_region_storequeue_sqmd;
nkeynes@946
   741
        } else {
nkeynes@946
   742
            upage = page;
nkeynes@946
   743
        }
nkeynes@946
   744
nkeynes@946
   745
    }  else {
nkeynes@946
   746
nkeynes@946
   747
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   748
            upage = &mem_region_tlb_protected;
nkeynes@946
   749
        } else {        
nkeynes@946
   750
            upage = page;
nkeynes@946
   751
        }
nkeynes@946
   752
nkeynes@946
   753
        if( (ent->flags & TLB_WRITABLE) == 0 ) {
nkeynes@946
   754
            page->write_long = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   755
            page->write_word = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   756
            page->write_byte = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   757
            page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
nkeynes@946
   758
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   759
        } else if( (ent->flags & TLB_DIRTY) == 0 ) {
nkeynes@946
   760
            page->write_long = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   761
            page->write_word = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   762
            page->write_byte = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   763
            page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
nkeynes@946
   764
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   765
        } else {
nkeynes@946
   766
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
nkeynes@946
   767
        }
nkeynes@939
   768
    }
nkeynes@946
   769
    
nkeynes@939
   770
    mmu_utlb_pages[entry].user_fn = upage;
nkeynes@939
   771
nkeynes@939
   772
    /* Is page visible? */
nkeynes@939
   773
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
nkeynes@939
   774
        mmu_utlb_map_pages( page, upage, start_addr, npages );
nkeynes@939
   775
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   776
        mmu_utlb_map_pages( page, NULL, start_addr, npages );
nkeynes@939
   777
    }
nkeynes@939
   778
}
nkeynes@939
   779
nkeynes@939
   780
static void mmu_utlb_remove_entry( int entry )
nkeynes@939
   781
{
nkeynes@939
   782
    int i, j;
nkeynes@939
   783
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   784
    sh4addr_t start_addr = ent->vpn&ent->mask;
nkeynes@939
   785
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   786
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@939
   787
    gboolean unmap_user;
nkeynes@939
   788
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   789
    
nkeynes@939
   790
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
nkeynes@939
   791
        unmap_user = TRUE;
nkeynes@939
   792
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   793
        unmap_user = FALSE;
nkeynes@939
   794
    } else {
nkeynes@939
   795
        return; // Not mapped
nkeynes@939
   796
    }
nkeynes@939
   797
    
nkeynes@943
   798
    gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
nkeynes@939
   799
    
nkeynes@939
   800
    if( !clean_unmap ) {
nkeynes@943
   801
        mmu_utlb_remap_pages( TRUE, unmap_user, entry );
nkeynes@939
   802
    }
nkeynes@939
   803
}
nkeynes@939
   804
nkeynes@939
   805
static void mmu_utlb_register_all()
nkeynes@939
   806
{
nkeynes@939
   807
    int i;
nkeynes@939
   808
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   809
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@939
   810
            mmu_utlb_insert_entry( i );
nkeynes@939
   811
    }
nkeynes@939
   812
}
nkeynes@939
   813
nkeynes@550
   814
static void mmu_invalidate_tlb()
nkeynes@550
   815
{
nkeynes@550
   816
    int i;
nkeynes@550
   817
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   818
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   819
    }
nkeynes@939
   820
    if( IS_TLB_ENABLED() ) {
nkeynes@939
   821
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   822
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   823
                mmu_utlb_remove_entry( i );
nkeynes@939
   824
            }
nkeynes@939
   825
        }
nkeynes@939
   826
    }
nkeynes@550
   827
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   828
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   829
    }
nkeynes@550
   830
}
nkeynes@550
   831
nkeynes@586
   832
/******************************************************************************/
nkeynes@586
   833
/*                        MMU TLB address translation                         */
nkeynes@586
   834
/******************************************************************************/
nkeynes@586
   835
nkeynes@586
   836
/**
nkeynes@939
   837
 * Translate a 32-bit address into a UTLB entry number. Does not check for
nkeynes@939
   838
 * page protection etc.
nkeynes@939
   839
 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
nkeynes@586
   840
 */
nkeynes@939
   841
int mmu_utlb_entry_for_vpn( uint32_t vpn )
nkeynes@939
   842
{
nkeynes@939
   843
    mem_region_fn_t fn = sh4_address_space[vpn>>12];
nkeynes@939
   844
    if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@939
   845
        return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@939
   846
    } else if( fn == &mem_region_tlb_multihit ) {
nkeynes@939
   847
        return -2;
nkeynes@939
   848
    } else {
nkeynes@939
   849
        return -1;
nkeynes@939
   850
    }
nkeynes@939
   851
}
nkeynes@939
   852
nkeynes@586
   853
nkeynes@586
   854
/**
nkeynes@586
   855
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   856
 * Possible utcomes are:
nkeynes@586
   857
 *   0..63 Single match - good, return entry found
nkeynes@586
   858
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   859
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   860
 * @param vpn virtual address to resolve
nkeynes@586
   861
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   862
 */
nkeynes@586
   863
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   864
{
nkeynes@586
   865
    int result = -1;
nkeynes@586
   866
    unsigned int i;
nkeynes@586
   867
nkeynes@586
   868
    mmu_urc++;
nkeynes@586
   869
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   870
        mmu_urc = 0;
nkeynes@586
   871
    }
nkeynes@586
   872
nkeynes@586
   873
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   874
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   875
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   876
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   877
            if( result != -1 ) {
nkeynes@736
   878
                return -2;
nkeynes@736
   879
            }
nkeynes@736
   880
            result = i;
nkeynes@736
   881
        }
nkeynes@586
   882
    }
nkeynes@586
   883
    return result;
nkeynes@586
   884
}
nkeynes@586
   885
nkeynes@586
   886
/**
nkeynes@586
   887
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   888
 * Possible utcomes are:
nkeynes@586
   889
 *   0..63 Single match - good, return entry found
nkeynes@586
   890
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   891
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   892
 * @param vpn virtual address to resolve
nkeynes@586
   893
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   894
 */
nkeynes@586
   895
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   896
{
nkeynes@586
   897
    int result = -1;
nkeynes@586
   898
    unsigned int i;
nkeynes@586
   899
nkeynes@586
   900
    mmu_urc++;
nkeynes@586
   901
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   902
        mmu_urc = 0;
nkeynes@586
   903
    }
nkeynes@586
   904
nkeynes@586
   905
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   906
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   907
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   908
            if( result != -1 ) {
nkeynes@736
   909
                return -2;
nkeynes@736
   910
            }
nkeynes@736
   911
            result = i;
nkeynes@736
   912
        }
nkeynes@586
   913
    }
nkeynes@586
   914
nkeynes@586
   915
    return result;
nkeynes@586
   916
}
nkeynes@586
   917
nkeynes@586
   918
/**
nkeynes@586
   919
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   920
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   921
 */
nkeynes@586
   922
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   923
{
nkeynes@586
   924
    int replace;
nkeynes@586
   925
    /* Determine entry to replace based on lrui */
nkeynes@586
   926
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   927
        replace = 0;
nkeynes@736
   928
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   929
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   930
        replace = 1;
nkeynes@736
   931
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   932
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   933
        replace = 2;
nkeynes@736
   934
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   935
    } else { // Note - gets invalid entries too
nkeynes@736
   936
        replace = 3;
nkeynes@736
   937
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   938
    }
nkeynes@586
   939
nkeynes@586
   940
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   941
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   942
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   943
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   944
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   945
    return replace;
nkeynes@586
   946
}
nkeynes@586
   947
nkeynes@586
   948
/**
nkeynes@586
   949
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   950
 * Possible utcomes are:
nkeynes@586
   951
 *   0..63 Single match - good, return entry found
nkeynes@586
   952
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   953
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   954
 * @param vpn virtual address to resolve
nkeynes@586
   955
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   956
 */
nkeynes@586
   957
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   958
{
nkeynes@586
   959
    int result = -1;
nkeynes@586
   960
    unsigned int i;
nkeynes@586
   961
nkeynes@586
   962
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   963
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   964
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   965
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   966
            if( result != -1 ) {
nkeynes@736
   967
                return -2;
nkeynes@736
   968
            }
nkeynes@736
   969
            result = i;
nkeynes@736
   970
        }
nkeynes@586
   971
    }
nkeynes@586
   972
nkeynes@586
   973
    if( result == -1 ) {
nkeynes@939
   974
        int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
nkeynes@736
   975
        if( utlbEntry < 0 ) {
nkeynes@736
   976
            return utlbEntry;
nkeynes@736
   977
        } else {
nkeynes@736
   978
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   979
        }
nkeynes@586
   980
    }
nkeynes@586
   981
nkeynes@586
   982
    switch( result ) {
nkeynes@586
   983
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   984
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   985
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   986
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   987
    }
nkeynes@736
   988
nkeynes@586
   989
    return result;
nkeynes@586
   990
}
nkeynes@586
   991
nkeynes@586
   992
/**
nkeynes@586
   993
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   994
 * Possible utcomes are:
nkeynes@586
   995
 *   0..63 Single match - good, return entry found
nkeynes@586
   996
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   997
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   998
 * @param vpn virtual address to resolve
nkeynes@586
   999
 * @return the resultant ITLB entry, or an error.
nkeynes@586
  1000
 */
nkeynes@586
  1001
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
  1002
{
nkeynes@586
  1003
    int result = -1;
nkeynes@586
  1004
    unsigned int i;
nkeynes@586
  1005
nkeynes@586
  1006
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
  1007
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
  1008
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
  1009
            if( result != -1 ) {
nkeynes@736
  1010
                return -2;
nkeynes@736
  1011
            }
nkeynes@736
  1012
            result = i;
nkeynes@736
  1013
        }
nkeynes@586
  1014
    }
nkeynes@586
  1015
nkeynes@586
  1016
    if( result == -1 ) {
nkeynes@736
  1017
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
  1018
        if( utlbEntry < 0 ) {
nkeynes@736
  1019
            return utlbEntry;
nkeynes@736
  1020
        } else {
nkeynes@736
  1021
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1022
        }
nkeynes@586
  1023
    }
nkeynes@586
  1024
nkeynes@586
  1025
    switch( result ) {
nkeynes@586
  1026
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1027
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1028
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1029
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1030
    }
nkeynes@736
  1031
nkeynes@586
  1032
    return result;
nkeynes@586
  1033
}
nkeynes@927
  1034
nkeynes@586
  1035
/**
nkeynes@586
  1036
 * Update the icache for an untranslated address
nkeynes@586
  1037
 */
nkeynes@905
  1038
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
  1039
{
nkeynes@586
  1040
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
  1041
        /* Main ram */
nkeynes@736
  1042
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
  1043
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
  1044
        sh4_icache.mask = 0xFF000000;
nkeynes@934
  1045
        sh4_icache.page = dc_main_ram;
nkeynes@586
  1046
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
  1047
        /* BIOS ROM */
nkeynes@736
  1048
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
  1049
        sh4_icache.page_ppa = 0;
nkeynes@736
  1050
        sh4_icache.mask = 0xFFE00000;
nkeynes@934
  1051
        sh4_icache.page = dc_boot_rom;
nkeynes@586
  1052
    } else {
nkeynes@736
  1053
        /* not supported */
nkeynes@736
  1054
        sh4_icache.page_vma = -1;
nkeynes@586
  1055
    }
nkeynes@586
  1056
}
nkeynes@586
  1057
nkeynes@586
  1058
/**
nkeynes@586
  1059
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
  1060
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
  1061
 * will be invalidated instead.
nkeynes@586
  1062
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
  1063
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
  1064
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
  1065
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
  1066
 * the icache.
nkeynes@586
  1067
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
  1068
 * if an exception was raised.
nkeynes@586
  1069
 */
nkeynes@905
  1070
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
  1071
{
nkeynes@586
  1072
    int entryNo;
nkeynes@586
  1073
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
  1074
        if( addr & 0x80000000 ) {
nkeynes@736
  1075
            if( addr < 0xC0000000 ) {
nkeynes@736
  1076
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1077
                mmu_update_icache_phys(addr);
nkeynes@736
  1078
                return TRUE;
nkeynes@736
  1079
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@939
  1080
                RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1081
                return FALSE;
nkeynes@736
  1082
            }
nkeynes@736
  1083
        }
nkeynes@586
  1084
nkeynes@736
  1085
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1086
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1087
            mmu_update_icache_phys(addr);
nkeynes@736
  1088
            return TRUE;
nkeynes@736
  1089
        }
nkeynes@736
  1090
nkeynes@826
  1091
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1092
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1093
        else
nkeynes@807
  1094
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1095
    } else {
nkeynes@736
  1096
        if( addr & 0x80000000 ) {
nkeynes@939
  1097
            RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1098
            return FALSE;
nkeynes@736
  1099
        }
nkeynes@586
  1100
nkeynes@736
  1101
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1102
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1103
            mmu_update_icache_phys(addr);
nkeynes@736
  1104
            return TRUE;
nkeynes@736
  1105
        }
nkeynes@736
  1106
nkeynes@807
  1107
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1108
nkeynes@736
  1109
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@939
  1110
            RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@736
  1111
            return FALSE;
nkeynes@736
  1112
        }
nkeynes@586
  1113
    }
nkeynes@586
  1114
nkeynes@586
  1115
    switch(entryNo) {
nkeynes@586
  1116
    case -1:
nkeynes@939
  1117
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@736
  1118
    return FALSE;
nkeynes@586
  1119
    case -2:
nkeynes@939
  1120
    RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@736
  1121
    return FALSE;
nkeynes@586
  1122
    default:
nkeynes@736
  1123
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1124
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1125
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1126
            sh4_icache.page_vma = -1;
nkeynes@736
  1127
        } else {
nkeynes@736
  1128
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1129
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1130
        }
nkeynes@736
  1131
        return TRUE;
nkeynes@586
  1132
    }
nkeynes@586
  1133
}
nkeynes@586
  1134
nkeynes@597
  1135
/**
nkeynes@826
  1136
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1137
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1138
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1139
 * on translation failure.
nkeynes@597
  1140
 */
nkeynes@905
  1141
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1142
{
nkeynes@597
  1143
    if( vma & 0x80000000 ) {
nkeynes@736
  1144
        if( vma < 0xC0000000 ) {
nkeynes@736
  1145
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1146
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1147
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1148
            /* Not translatable */
nkeynes@736
  1149
            return MMU_VMA_ERROR;
nkeynes@736
  1150
        }
nkeynes@597
  1151
    }
nkeynes@597
  1152
nkeynes@597
  1153
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1154
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1155
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1156
    }
nkeynes@736
  1157
nkeynes@597
  1158
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1159
    if( entryNo == -2 ) {
nkeynes@736
  1160
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1161
    }
nkeynes@597
  1162
    if( entryNo < 0 ) {
nkeynes@736
  1163
        return MMU_VMA_ERROR;
nkeynes@597
  1164
    } else {
nkeynes@826
  1165
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1166
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1167
    }
nkeynes@597
  1168
}
nkeynes@597
  1169
nkeynes@939
  1170
/********************** TLB Direct-Access Regions ***************************/
nkeynes@939
  1171
#ifdef HAVE_FRAME_ADDRESS
nkeynes@939
  1172
#define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
nkeynes@939
  1173
#else
nkeynes@939
  1174
#define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
nkeynes@939
  1175
#endif
nkeynes@939
  1176
nkeynes@939
  1177
nkeynes@939
  1178
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@939
  1179
nkeynes@939
  1180
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@939
  1181
{
nkeynes@939
  1182
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1183
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@939
  1184
}
nkeynes@939
  1185
nkeynes@939
  1186
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1187
{
nkeynes@939
  1188
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1189
    ent->vpn = val & 0xFFFFFC00;
nkeynes@939
  1190
    ent->asid = val & 0x000000FF;
nkeynes@939
  1191
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@939
  1192
}
nkeynes@939
  1193
nkeynes@939
  1194
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@939
  1195
{
nkeynes@939
  1196
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1197
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@939
  1198
}
nkeynes@939
  1199
nkeynes@939
  1200
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1201
{
nkeynes@939
  1202
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1203
    ent->ppn = val & 0x1FFFFC00;
nkeynes@939
  1204
    ent->flags = val & 0x00001DA;
nkeynes@939
  1205
    ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1206
    if( ent->ppn >= 0x1C000000 )
nkeynes@939
  1207
        ent->ppn |= 0xE0000000;
nkeynes@939
  1208
}
nkeynes@939
  1209
nkeynes@939
  1210
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@939
  1211
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@939
  1212
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@939
  1213
nkeynes@939
  1214
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@939
  1215
{
nkeynes@939
  1216
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1217
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@939
  1218
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@939
  1219
}
nkeynes@939
  1220
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@939
  1221
{
nkeynes@939
  1222
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1223
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1224
        return ent->pcmcia;
nkeynes@939
  1225
    } else {
nkeynes@939
  1226
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@939
  1227
    }
nkeynes@939
  1228
}
nkeynes@939
  1229
nkeynes@939
  1230
/**
nkeynes@939
  1231
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@939
  1232
 * lookup but ignores the valid bit.
nkeynes@939
  1233
 */
nkeynes@939
  1234
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1235
{
nkeynes@939
  1236
    int result = -1;
nkeynes@939
  1237
    unsigned int i;
nkeynes@939
  1238
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1239
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@939
  1240
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@939
  1241
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@939
  1242
            if( result != -1 ) {
nkeynes@939
  1243
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@939
  1244
                return -2;
nkeynes@939
  1245
            }
nkeynes@939
  1246
            result = i;
nkeynes@939
  1247
        }
nkeynes@939
  1248
    }
nkeynes@939
  1249
    return result;
nkeynes@939
  1250
}
nkeynes@939
  1251
nkeynes@939
  1252
/**
nkeynes@939
  1253
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@939
  1254
 * lookup but ignores the valid bit.
nkeynes@939
  1255
 */
nkeynes@939
  1256
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1257
{
nkeynes@939
  1258
    int result = -1;
nkeynes@939
  1259
    unsigned int i;
nkeynes@939
  1260
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1261
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@939
  1262
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@939
  1263
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@939
  1264
            if( result != -1 ) {
nkeynes@939
  1265
                return -2;
nkeynes@939
  1266
            }
nkeynes@939
  1267
            result = i;
nkeynes@939
  1268
        }
nkeynes@939
  1269
    }
nkeynes@939
  1270
    return result;
nkeynes@939
  1271
}
nkeynes@939
  1272
nkeynes@939
  1273
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1274
{
nkeynes@939
  1275
    if( UTLB_ASSOC(addr) ) {
nkeynes@939
  1276
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1277
        if( utlb >= 0 ) {
nkeynes@939
  1278
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@939
  1279
            uint32_t old_flags = ent->flags;
nkeynes@939
  1280
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@939
  1281
            ent->flags |= (val & TLB_VALID);
nkeynes@939
  1282
            ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1283
            if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
nkeynes@939
  1284
                if( old_flags & TLB_VALID )
nkeynes@939
  1285
                    mmu_utlb_remove_entry( utlb );
nkeynes@939
  1286
                if( ent->flags & TLB_VALID )
nkeynes@939
  1287
                    mmu_utlb_insert_entry( utlb );
nkeynes@939
  1288
            }
nkeynes@939
  1289
        }
nkeynes@939
  1290
nkeynes@939
  1291
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1292
        if( itlb >= 0 ) {
nkeynes@939
  1293
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@939
  1294
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@939
  1295
        }
nkeynes@939
  1296
nkeynes@939
  1297
        if( itlb == -2 || utlb == -2 ) {
nkeynes@939
  1298
            RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@939
  1299
            EXCEPTION_EXIT();
nkeynes@939
  1300
            return;
nkeynes@939
  1301
        }
nkeynes@939
  1302
    } else {
nkeynes@939
  1303
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1304
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1305
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1306
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@939
  1307
        ent->asid = (val & 0xFF);
nkeynes@939
  1308
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@939
  1309
        ent->flags |= (val & TLB_VALID);
nkeynes@939
  1310
        ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1311
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1312
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1313
    }
nkeynes@939
  1314
}
nkeynes@939
  1315
nkeynes@939
  1316
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1317
{
nkeynes@939
  1318
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1319
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1320
        ent->pcmcia = val & 0x0000000F;
nkeynes@939
  1321
    } else {
nkeynes@939
  1322
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1323
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1324
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@939
  1325
        ent->flags = (val & 0x000001FF);
nkeynes@939
  1326
        ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1327
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1328
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1329
    }
nkeynes@939
  1330
}
nkeynes@939
  1331
nkeynes@939
  1332
struct mem_region_fn p4_region_itlb_addr = {
nkeynes@939
  1333
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1334
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1335
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@946
  1336
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1337
        unmapped_prefetch };
nkeynes@939
  1338
struct mem_region_fn p4_region_itlb_data = {
nkeynes@939
  1339
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1340
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1341
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@946
  1342
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1343
        unmapped_prefetch };
nkeynes@939
  1344
struct mem_region_fn p4_region_utlb_addr = {
nkeynes@939
  1345
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1346
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1347
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@946
  1348
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1349
        unmapped_prefetch };
nkeynes@939
  1350
struct mem_region_fn p4_region_utlb_data = {
nkeynes@939
  1351
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1352
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1353
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@946
  1354
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1355
        unmapped_prefetch };
nkeynes@939
  1356
nkeynes@939
  1357
/********************** Error regions **************************/
nkeynes@939
  1358
nkeynes@939
  1359
static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
nkeynes@939
  1360
{
nkeynes@939
  1361
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1362
    EXCEPTION_EXIT();
nkeynes@939
  1363
}
nkeynes@939
  1364
nkeynes@939
  1365
static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
nkeynes@939
  1366
{
nkeynes@939
  1367
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1368
    EXCEPTION_EXIT();
nkeynes@939
  1369
}
nkeynes@939
  1370
nkeynes@939
  1371
static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1372
{
nkeynes@939
  1373
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@939
  1374
    EXCEPTION_EXIT();
nkeynes@939
  1375
}
nkeynes@939
  1376
nkeynes@939
  1377
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
nkeynes@939
  1378
{
nkeynes@939
  1379
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1380
    EXCEPTION_EXIT();
nkeynes@939
  1381
}
nkeynes@939
  1382
nkeynes@939
  1383
static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1384
{
nkeynes@939
  1385
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1386
    EXCEPTION_EXIT();
nkeynes@939
  1387
}
nkeynes@939
  1388
nkeynes@939
  1389
static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1390
{
nkeynes@939
  1391
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@939
  1392
    EXCEPTION_EXIT();
nkeynes@939
  1393
}    
nkeynes@939
  1394
nkeynes@939
  1395
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
nkeynes@939
  1396
{
nkeynes@939
  1397
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1398
    EXCEPTION_EXIT();
nkeynes@939
  1399
}
nkeynes@939
  1400
nkeynes@939
  1401
static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1402
{
nkeynes@939
  1403
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1404
    EXCEPTION_EXIT();
nkeynes@939
  1405
}
nkeynes@939
  1406
nkeynes@939
  1407
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1408
{
nkeynes@939
  1409
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@939
  1410
    EXCEPTION_EXIT();
nkeynes@939
  1411
}
nkeynes@939
  1412
nkeynes@939
  1413
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1414
{
nkeynes@939
  1415
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@939
  1416
    EXCEPTION_EXIT();
nkeynes@939
  1417
}
nkeynes@939
  1418
    
nkeynes@939
  1419
static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
nkeynes@939
  1420
{
nkeynes@939
  1421
    MMIO_WRITE(MMU, TEA, addr);
nkeynes@939
  1422
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (addr&0xFFFFFC00)));
nkeynes@939
  1423
    sh4_raise_reset(EXC_TLB_MULTI_HIT);
nkeynes@939
  1424
    EXCEPTION_EXIT();
nkeynes@939
  1425
}
nkeynes@939
  1426
nkeynes@939
  1427
static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1428
{
nkeynes@939
  1429
    MMIO_WRITE(MMU, TEA, addr);
nkeynes@939
  1430
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (addr&0xFFFFFC00)));
nkeynes@939
  1431
    sh4_raise_reset(EXC_TLB_MULTI_HIT);
nkeynes@939
  1432
    EXCEPTION_EXIT();
nkeynes@939
  1433
}
nkeynes@939
  1434
static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1435
{
nkeynes@939
  1436
    MMIO_WRITE(MMU, TEA, addr);
nkeynes@939
  1437
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (addr&0xFFFFFC00)));
nkeynes@939
  1438
    sh4_raise_reset(EXC_TLB_MULTI_HIT);
nkeynes@939
  1439
    EXCEPTION_EXIT();
nkeynes@939
  1440
}
nkeynes@939
  1441
nkeynes@939
  1442
/**
nkeynes@939
  1443
 * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
nkeynes@939
  1444
 */
nkeynes@939
  1445
struct mem_region_fn mem_region_address_error = {
nkeynes@939
  1446
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1447
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1448
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1449
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1450
        unmapped_prefetch };
nkeynes@939
  1451
nkeynes@939
  1452
struct mem_region_fn mem_region_tlb_miss = {
nkeynes@939
  1453
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1454
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1455
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@946
  1456
        (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
nkeynes@946
  1457
        unmapped_prefetch };
nkeynes@939
  1458
nkeynes@946
  1459
struct mem_region_fn mem_region_tlb_protected = {
nkeynes@939
  1460
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1461
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1462
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@946
  1463
        (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
nkeynes@946
  1464
        unmapped_prefetch };
nkeynes@939
  1465
nkeynes@939
  1466
struct mem_region_fn mem_region_tlb_multihit = {
nkeynes@939
  1467
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1468
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1469
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@946
  1470
        (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
nkeynes@946
  1471
        (mem_prefetch_fn_t)tlb_multi_hit_read };
nkeynes@939
  1472
        
nkeynes@946
  1473
nkeynes@946
  1474
/* Store-queue regions */
nkeynes@946
  1475
/* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
nkeynes@946
  1476
 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
nkeynes@946
  1477
 * some cases), in contrast to the ordinary fields above.
nkeynes@946
  1478
 * 
nkeynes@946
  1479
 * There is probably a simpler way to do this.
nkeynes@946
  1480
 */
nkeynes@946
  1481
nkeynes@946
  1482
struct mem_region_fn p4_region_storequeue = { 
nkeynes@946
  1483
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1484
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1485
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1486
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1487
        ccn_storequeue_prefetch }; 
nkeynes@946
  1488
nkeynes@946
  1489
struct mem_region_fn p4_region_storequeue_miss = { 
nkeynes@946
  1490
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1491
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1492
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1493
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1494
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1495
nkeynes@946
  1496
struct mem_region_fn p4_region_storequeue_multihit = { 
nkeynes@946
  1497
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1498
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1499
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1500
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1501
        (mem_prefetch_fn_t)tlb_multi_hit_read }; 
nkeynes@946
  1502
nkeynes@946
  1503
struct mem_region_fn p4_region_storequeue_protected = {
nkeynes@946
  1504
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1505
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1506
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1507
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1508
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1509
nkeynes@946
  1510
struct mem_region_fn p4_region_storequeue_sqmd = {
nkeynes@946
  1511
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1512
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1513
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1514
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1515
        (mem_prefetch_fn_t)address_error_read };        
nkeynes@939
  1516
        
nkeynes@946
  1517
struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
nkeynes@946
  1518
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1519
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1520
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1521
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1522
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1523
nkeynes@946
  1524
struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
nkeynes@946
  1525
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1526
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1527
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1528
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1529
        (mem_prefetch_fn_t)tlb_multi_hit_read };        
nkeynes@946
  1530
        
nkeynes@946
  1531
struct mem_region_fn p4_region_storequeue_sqmd_protected = {
nkeynes@946
  1532
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1533
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1534
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1535
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1536
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1537
.