filename | src/sh4/sh4core.h |
changeset | 948:545c85cc56f1 |
prev | 946:d41ee7994db7 |
next | 951:63483914846f |
author | nkeynes |
date | Wed Jan 07 04:39:04 2009 +0000 (15 years ago) |
branch | lxdream-mem |
permissions | -rw-r--r-- |
last change | Introduce sh4_finalize_instruction to clean-up on instruction exits Remove the sh4_flush_icache special cases, now works through the general case. |
file | annotate | diff | log | raw |
nkeynes@10 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@10 | 3 | * |
nkeynes@945 | 4 | * This file defines the internal functions used by the SH4 core, |
nkeynes@10 | 5 | * |
nkeynes@945 | 6 | * Copyright (c) 2005-2008 Nathan Keynes. |
nkeynes@10 | 7 | * |
nkeynes@10 | 8 | * This program is free software; you can redistribute it and/or modify |
nkeynes@10 | 9 | * it under the terms of the GNU General Public License as published by |
nkeynes@10 | 10 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@10 | 11 | * (at your option) any later version. |
nkeynes@10 | 12 | * |
nkeynes@10 | 13 | * This program is distributed in the hope that it will be useful, |
nkeynes@10 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@10 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@10 | 16 | * GNU General Public License for more details. |
nkeynes@1 | 17 | */ |
nkeynes@30 | 18 | |
nkeynes@736 | 19 | #ifndef lxdream_sh4core_H |
nkeynes@736 | 20 | #define lxdream_sh4core_H 1 |
nkeynes@1 | 21 | |
nkeynes@27 | 22 | #include <glib/gtypes.h> |
nkeynes@1 | 23 | #include <stdint.h> |
nkeynes@23 | 24 | #include <stdio.h> |
nkeynes@378 | 25 | #include "mem.h" |
nkeynes@586 | 26 | #include "sh4/sh4.h" |
nkeynes@1 | 27 | |
nkeynes@1 | 28 | #ifdef __cplusplus |
nkeynes@1 | 29 | extern "C" { |
nkeynes@1 | 30 | #endif |
nkeynes@1 | 31 | |
nkeynes@586 | 32 | /* Breakpoint data structure */ |
nkeynes@586 | 33 | extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@586 | 34 | extern int sh4_breakpoint_count; |
nkeynes@591 | 35 | extern gboolean sh4_starting; |
nkeynes@27 | 36 | |
nkeynes@27 | 37 | /** |
nkeynes@586 | 38 | * Cached direct pointer to the current instruction page. If AT is on, this |
nkeynes@586 | 39 | * is derived from the ITLB, otherwise this will be the entire memory region. |
nkeynes@586 | 40 | * This is actually a fairly useful optimization, as we can make a lot of |
nkeynes@586 | 41 | * assumptions about the "current page" that we can't make in general for |
nkeynes@586 | 42 | * arbitrary virtual addresses. |
nkeynes@27 | 43 | */ |
nkeynes@586 | 44 | struct sh4_icache_struct { |
nkeynes@586 | 45 | sh4ptr_t page; // Page pointer (NULL if no page) |
nkeynes@586 | 46 | sh4vma_t page_vma; // virtual address of the page. |
nkeynes@586 | 47 | sh4addr_t page_ppa; // physical address of the page |
nkeynes@586 | 48 | uint32_t mask; // page mask |
nkeynes@586 | 49 | }; |
nkeynes@586 | 50 | extern struct sh4_icache_struct sh4_icache; |
nkeynes@586 | 51 | |
nkeynes@27 | 52 | /** |
nkeynes@586 | 53 | * Test if a given address is contained in the current icache entry |
nkeynes@27 | 54 | */ |
nkeynes@586 | 55 | #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask)) |
nkeynes@27 | 56 | /** |
nkeynes@586 | 57 | * Return a pointer for the given vma, under the assumption that it is |
nkeynes@586 | 58 | * actually contained in the current icache entry. |
nkeynes@27 | 59 | */ |
nkeynes@586 | 60 | #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma)) |
nkeynes@27 | 61 | /** |
nkeynes@586 | 62 | * Return the physical (external) address for the given vma, assuming that it is |
nkeynes@586 | 63 | * actually contained in the current icache entry. |
nkeynes@27 | 64 | */ |
nkeynes@586 | 65 | #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma)) |
nkeynes@27 | 66 | |
nkeynes@589 | 67 | /** |
nkeynes@589 | 68 | * Return the virtual (vma) address for the first address past the end of the |
nkeynes@589 | 69 | * cache entry. Assumes that there is in fact a current icache entry. |
nkeynes@589 | 70 | */ |
nkeynes@589 | 71 | #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1) |
nkeynes@589 | 72 | |
nkeynes@740 | 73 | |
nkeynes@740 | 74 | /** |
nkeynes@948 | 75 | * SH4 vm-exit flag - exit the current block but continue normally |
nkeynes@740 | 76 | */ |
nkeynes@740 | 77 | #define CORE_EXIT_CONTINUE 1 |
nkeynes@740 | 78 | |
nkeynes@740 | 79 | /** |
nkeynes@740 | 80 | * SH4 vm-exit flag - exit the current block and halt immediately (eg fatal error) |
nkeynes@740 | 81 | */ |
nkeynes@740 | 82 | #define CORE_EXIT_HALT 2 |
nkeynes@740 | 83 | |
nkeynes@740 | 84 | /** |
nkeynes@740 | 85 | * SH4 vm-exit flag - exit the current block and halt immediately for a system |
nkeynes@740 | 86 | * breakpoint. |
nkeynes@740 | 87 | */ |
nkeynes@740 | 88 | #define CORE_EXIT_BREAKPOINT 3 |
nkeynes@740 | 89 | |
nkeynes@740 | 90 | /** |
nkeynes@740 | 91 | * SH4 vm-exit flag - exit the current block and continue after performing a full |
nkeynes@740 | 92 | * system reset (dreamcast_reset()) |
nkeynes@740 | 93 | */ |
nkeynes@740 | 94 | #define CORE_EXIT_SYSRESET 4 |
nkeynes@740 | 95 | |
nkeynes@740 | 96 | /** |
nkeynes@740 | 97 | * SH4 vm-exit flag - exit the current block and continue after the next IRQ. |
nkeynes@740 | 98 | */ |
nkeynes@740 | 99 | #define CORE_EXIT_SLEEP 5 |
nkeynes@740 | 100 | |
nkeynes@740 | 101 | /** |
nkeynes@939 | 102 | * SH4 vm-exit flag - exit the current block and flush all instruction caches (ie |
nkeynes@740 | 103 | * if address translation has changed) |
nkeynes@740 | 104 | */ |
nkeynes@740 | 105 | #define CORE_EXIT_FLUSH_ICACHE 6 |
nkeynes@740 | 106 | |
nkeynes@939 | 107 | /** |
nkeynes@939 | 108 | * SH4 vm-exit flag - exit the current block following a taken exception. sh4r.spc |
nkeynes@939 | 109 | * is fixed up by recovery rather than sh4r.pc. |
nkeynes@939 | 110 | */ |
nkeynes@939 | 111 | #define CORE_EXIT_EXCEPTION 7 |
nkeynes@939 | 112 | |
nkeynes@740 | 113 | typedef uint32_t (*sh4_run_slice_fn)(uint32_t); |
nkeynes@740 | 114 | |
nkeynes@586 | 115 | /* SH4 module functions */ |
nkeynes@1 | 116 | void sh4_init( void ); |
nkeynes@1 | 117 | void sh4_reset( void ); |
nkeynes@1 | 118 | void sh4_run( void ); |
nkeynes@1 | 119 | void sh4_stop( void ); |
nkeynes@617 | 120 | uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator |
nkeynes@617 | 121 | uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator |
nkeynes@617 | 122 | uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep |
nkeynes@586 | 123 | |
nkeynes@740 | 124 | /** |
nkeynes@740 | 125 | * Immediately exit from the currently executing instruction with the given |
nkeynes@740 | 126 | * exit code. This method does not return. |
nkeynes@740 | 127 | */ |
nkeynes@740 | 128 | void sh4_core_exit( int exit_code ); |
nkeynes@740 | 129 | |
nkeynes@740 | 130 | /** |
nkeynes@740 | 131 | * Exit the current block at the end of the current instruction, flush the |
nkeynes@740 | 132 | * translation cache (completely) and return control to sh4_xlat_run_slice. |
nkeynes@740 | 133 | * |
nkeynes@740 | 134 | * As a special case, if the current instruction is actually the last |
nkeynes@740 | 135 | * instruction in the block (ie it's in a delay slot), this function |
nkeynes@740 | 136 | * returns to allow normal completion of the translation block. Otherwise |
nkeynes@740 | 137 | * this function never returns. |
nkeynes@740 | 138 | * |
nkeynes@740 | 139 | * Must only be invoked (indirectly) from within translated code. |
nkeynes@740 | 140 | */ |
nkeynes@740 | 141 | void sh4_flush_icache(); |
nkeynes@740 | 142 | |
nkeynes@586 | 143 | /* SH4 peripheral module functions */ |
nkeynes@586 | 144 | void CPG_reset( void ); |
nkeynes@586 | 145 | void DMAC_reset( void ); |
nkeynes@586 | 146 | void DMAC_run_slice( uint32_t ); |
nkeynes@586 | 147 | void DMAC_save_state( FILE * ); |
nkeynes@586 | 148 | int DMAC_load_state( FILE * ); |
nkeynes@586 | 149 | void INTC_reset( void ); |
nkeynes@586 | 150 | void INTC_save_state( FILE *f ); |
nkeynes@586 | 151 | int INTC_load_state( FILE *f ); |
nkeynes@586 | 152 | void MMU_reset( void ); |
nkeynes@586 | 153 | void MMU_save_state( FILE *f ); |
nkeynes@586 | 154 | int MMU_load_state( FILE *f ); |
nkeynes@586 | 155 | void MMU_ldtlb(); |
nkeynes@931 | 156 | void CCN_save_state( FILE *f ); |
nkeynes@931 | 157 | int CCN_load_state( FILE *f ); |
nkeynes@586 | 158 | void SCIF_reset( void ); |
nkeynes@586 | 159 | void SCIF_run_slice( uint32_t ); |
nkeynes@586 | 160 | void SCIF_save_state( FILE *f ); |
nkeynes@586 | 161 | int SCIF_load_state( FILE *f ); |
nkeynes@586 | 162 | void SCIF_update_line_speed(void); |
nkeynes@669 | 163 | void TMU_init( void ); |
nkeynes@586 | 164 | void TMU_reset( void ); |
nkeynes@586 | 165 | void TMU_run_slice( uint32_t ); |
nkeynes@586 | 166 | void TMU_save_state( FILE * ); |
nkeynes@586 | 167 | int TMU_load_state( FILE * ); |
nkeynes@586 | 168 | void TMU_update_clocks( void ); |
nkeynes@841 | 169 | void PMM_reset( void ); |
nkeynes@841 | 170 | void PMM_write_control( int, uint32_t ); |
nkeynes@841 | 171 | void PMM_save_state( FILE * ); |
nkeynes@841 | 172 | int PMM_load_state( FILE * ); |
nkeynes@841 | 173 | uint32_t PMM_run_slice( uint32_t ); |
nkeynes@759 | 174 | uint32_t sh4_translate_run_slice(uint32_t); |
nkeynes@759 | 175 | uint32_t sh4_emulate_run_slice(uint32_t); |
nkeynes@586 | 176 | |
nkeynes@586 | 177 | /* SH4 instruction support methods */ |
nkeynes@929 | 178 | mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t address ); |
nkeynes@929 | 179 | void FASTCALL sh7750_decode_address_copy( sh4addr_t address, mem_region_fn_t result ); |
nkeynes@905 | 180 | void FASTCALL sh4_sleep( void ); |
nkeynes@905 | 181 | void FASTCALL sh4_fsca( uint32_t angle, float *fr ); |
nkeynes@905 | 182 | void FASTCALL sh4_ftrv( float *fv ); |
nkeynes@905 | 183 | uint32_t FASTCALL sh4_read_sr(void); |
nkeynes@905 | 184 | void FASTCALL sh4_write_sr(uint32_t val); |
nkeynes@905 | 185 | void FASTCALL sh4_write_fpscr(uint32_t val); |
nkeynes@905 | 186 | void FASTCALL sh4_switch_fr_banks(void); |
nkeynes@905 | 187 | void FASTCALL signsat48(void); |
nkeynes@597 | 188 | gboolean sh4_has_page( sh4vma_t vma ); |
nkeynes@378 | 189 | |
nkeynes@586 | 190 | /* SH4 Memory */ |
nkeynes@603 | 191 | #define MMU_VMA_ERROR 0x80000000 |
nkeynes@586 | 192 | /** |
nkeynes@586 | 193 | * Update the sh4_icache structure to contain the specified vma. If the vma |
nkeynes@586 | 194 | * cannot be resolved, an MMU exception is raised and the function returns |
nkeynes@586 | 195 | * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly. |
nkeynes@586 | 196 | * Note: If the vma resolves to a non-memory area, sh4_icache will be |
nkeynes@586 | 197 | * invalidated, but the function will still return TRUE. |
nkeynes@586 | 198 | * @return FALSE if an MMU exception was raised, otherwise TRUE. |
nkeynes@586 | 199 | */ |
nkeynes@905 | 200 | gboolean FASTCALL mmu_update_icache( sh4vma_t addr ); |
nkeynes@23 | 201 | |
nkeynes@905 | 202 | int64_t FASTCALL sh4_read_quad( sh4addr_t addr ); |
nkeynes@905 | 203 | int32_t FASTCALL sh4_read_long( sh4addr_t addr ); |
nkeynes@905 | 204 | int32_t FASTCALL sh4_read_word( sh4addr_t addr ); |
nkeynes@905 | 205 | int32_t FASTCALL sh4_read_byte( sh4addr_t addr ); |
nkeynes@905 | 206 | void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val ); |
nkeynes@905 | 207 | void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val ); |
nkeynes@905 | 208 | void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val ); |
nkeynes@905 | 209 | void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val ); |
nkeynes@527 | 210 | int32_t sh4_read_phys_word( sh4addr_t addr ); |
nkeynes@911 | 211 | void FASTCALL sh4_flush_store_queue( sh4addr_t addr ); |
nkeynes@939 | 212 | void FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr, void *exc ); |
nkeynes@10 | 213 | |
nkeynes@586 | 214 | /* SH4 Exceptions */ |
nkeynes@586 | 215 | #define EXC_POWER_RESET 0x000 /* reset vector */ |
nkeynes@586 | 216 | #define EXC_MANUAL_RESET 0x020 /* reset vector */ |
nkeynes@586 | 217 | #define EXC_TLB_MISS_READ 0x040 /* TLB vector */ |
nkeynes@586 | 218 | #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */ |
nkeynes@586 | 219 | #define EXC_INIT_PAGE_WRITE 0x080 |
nkeynes@586 | 220 | #define EXC_TLB_PROT_READ 0x0A0 |
nkeynes@586 | 221 | #define EXC_TLB_PROT_WRITE 0x0C0 |
nkeynes@586 | 222 | #define EXC_DATA_ADDR_READ 0x0E0 |
nkeynes@586 | 223 | #define EXC_DATA_ADDR_WRITE 0x100 |
nkeynes@586 | 224 | #define EXC_TLB_MULTI_HIT 0x140 |
nkeynes@586 | 225 | #define EXC_SLOT_ILLEGAL 0x1A0 |
nkeynes@586 | 226 | #define EXC_ILLEGAL 0x180 |
nkeynes@586 | 227 | #define EXC_TRAP 0x160 |
nkeynes@586 | 228 | #define EXC_FPU_DISABLED 0x800 |
nkeynes@586 | 229 | #define EXC_SLOT_FPU_DISABLED 0x820 |
nkeynes@374 | 230 | |
nkeynes@586 | 231 | #define EXV_EXCEPTION 0x100 /* General exception vector */ |
nkeynes@586 | 232 | #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */ |
nkeynes@586 | 233 | #define EXV_INTERRUPT 0x600 /* External interrupt vector */ |
nkeynes@586 | 234 | |
nkeynes@905 | 235 | gboolean FASTCALL sh4_raise_exception( int ); |
nkeynes@905 | 236 | gboolean FASTCALL sh4_raise_reset( int ); |
nkeynes@905 | 237 | gboolean FASTCALL sh4_raise_trap( int ); |
nkeynes@905 | 238 | gboolean FASTCALL sh4_raise_slot_exception( int, int ); |
nkeynes@905 | 239 | gboolean FASTCALL sh4_raise_tlb_exception( int ); |
nkeynes@905 | 240 | void FASTCALL sh4_accept_interrupt( void ); |
nkeynes@1 | 241 | |
nkeynes@948 | 242 | /** |
nkeynes@948 | 243 | * Complete the current instruction as part of a core exit. Prevents the |
nkeynes@948 | 244 | * system from being left in an inconsistent state when an exit is |
nkeynes@948 | 245 | * triggered during a memory write. |
nkeynes@948 | 246 | */ |
nkeynes@948 | 247 | void sh4_finalize_instruction( void ); |
nkeynes@948 | 248 | |
nkeynes@1 | 249 | /* Status Register (SR) bits */ |
nkeynes@1 | 250 | #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ |
nkeynes@1 | 251 | #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */ |
nkeynes@1 | 252 | #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */ |
nkeynes@1 | 253 | #define SR_FD 0x00008000 /* FPU disable */ |
nkeynes@1 | 254 | #define SR_M 0x00000200 |
nkeynes@1 | 255 | #define SR_Q 0x00000100 |
nkeynes@1 | 256 | #define SR_IMASK 0x000000F0 /* Interrupt mask level */ |
nkeynes@1 | 257 | #define SR_S 0x00000002 /* Saturation operation for MAC instructions */ |
nkeynes@1 | 258 | #define SR_T 0x00000001 /* True/false or carry/borrow */ |
nkeynes@1 | 259 | #define SR_MASK 0x700083F3 |
nkeynes@1 | 260 | #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */ |
nkeynes@586 | 261 | #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */ |
nkeynes@1 | 262 | |
nkeynes@1 | 263 | #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD) |
nkeynes@1 | 264 | #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4) |
nkeynes@265 | 265 | #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot) |
nkeynes@1 | 266 | |
nkeynes@1 | 267 | #define FPSCR_FR 0x00200000 /* FPU register bank */ |
nkeynes@1 | 268 | #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */ |
nkeynes@1 | 269 | #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */ |
nkeynes@1 | 270 | #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */ |
nkeynes@1 | 271 | #define FPSCR_CAUSE 0x0003F000 |
nkeynes@1 | 272 | #define FPSCR_ENABLE 0x00000F80 |
nkeynes@1 | 273 | #define FPSCR_FLAG 0x0000007C |
nkeynes@1 | 274 | #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */ |
nkeynes@823 | 275 | #define FPSCR_MASK 0x003FFFFF |
nkeynes@1 | 276 | |
nkeynes@1 | 277 | #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR) |
nkeynes@1 | 278 | #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ) |
nkeynes@1 | 279 | #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0) |
nkeynes@1 | 280 | |
nkeynes@669 | 281 | #define FR(x) sh4r.fr[0][(x)^1] |
nkeynes@669 | 282 | #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1]) |
nkeynes@669 | 283 | #define XF(x) sh4r.fr[1][(x)^1] |
nkeynes@669 | 284 | #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1]) |
nkeynes@669 | 285 | #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1]) |
nkeynes@669 | 286 | #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E]) |
nkeynes@669 | 287 | #define FPULf (sh4r.fpul.f) |
nkeynes@669 | 288 | #define FPULi (sh4r.fpul.i) |
nkeynes@359 | 289 | |
nkeynes@939 | 290 | /**************** SH4 internal memory regions *****************/ |
nkeynes@939 | 291 | extern struct mem_region_fn p4_region_itlb_addr; |
nkeynes@939 | 292 | extern struct mem_region_fn p4_region_itlb_data; |
nkeynes@939 | 293 | extern struct mem_region_fn p4_region_utlb_addr; |
nkeynes@939 | 294 | extern struct mem_region_fn p4_region_utlb_data; |
nkeynes@939 | 295 | extern struct mem_region_fn p4_region_icache_addr; |
nkeynes@939 | 296 | extern struct mem_region_fn p4_region_icache_data; |
nkeynes@939 | 297 | extern struct mem_region_fn p4_region_ocache_addr; |
nkeynes@939 | 298 | extern struct mem_region_fn p4_region_ocache_data; |
nkeynes@946 | 299 | |
nkeynes@939 | 300 | |
nkeynes@1 | 301 | |
nkeynes@1 | 302 | #ifdef __cplusplus |
nkeynes@1 | 303 | } |
nkeynes@1 | 304 | #endif |
nkeynes@359 | 305 | |
nkeynes@736 | 306 | #endif /* !lxdream_sh4core_H */ |
nkeynes@736 | 307 |
.