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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 948:545c85cc56f1
prev946:d41ee7994db7
next951:63483914846f
author nkeynes
date Wed Jan 07 04:39:04 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Introduce sh4_finalize_instruction to clean-up on instruction exits
Remove the sh4_flush_icache special cases, now works through the
general case.
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <assert.h>
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#include <math.h>
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#include "dream.h"
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#include "dreamcast.h"
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#include "eventq.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4stat.h"
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#include "sh4/mmu.h"
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#define SH4_CALLTRACE 1
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#define MAX_INT 0x7FFFFFFF
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#define MIN_INT 0x80000000
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#define MAX_INTF 2147483647.0
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#define MIN_INTF -2147483648.0
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/********************** SH4 Module Definition ****************************/
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uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
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{
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    int i;
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    if( sh4_breakpoint_count == 0 ) {
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	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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		if( sh4r.event_types & PENDING_EVENT ) {
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		    event_execute();
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		}
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		/* Eventq execute may (quite likely) deliver an immediate IRQ */
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		if( sh4r.event_types & PENDING_IRQ ) {
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		    sh4_accept_interrupt();
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		}
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	    }
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	    if( !sh4_execute_instruction() ) {
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		break;
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	    }
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	}
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    } else {
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	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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		if( sh4r.event_types & PENDING_EVENT ) {
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		    event_execute();
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		}
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		/* Eventq execute may (quite likely) deliver an immediate IRQ */
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		if( sh4r.event_types & PENDING_IRQ ) {
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		    sh4_accept_interrupt();
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		}
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	    }
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	    if( !sh4_execute_instruction() )
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		break;
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#ifdef ENABLE_DEBUG_MODE
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	    for( i=0; i<sh4_breakpoint_count; i++ ) {
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		if( sh4_breakpoints[i].address == sh4r.pc ) {
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		    break;
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		}
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	    }
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	    if( i != sh4_breakpoint_count ) {
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	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
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	    }
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#endif	
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	}
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    return nanosecs;
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}
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/********************** SH4 emulation core  ****************************/
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#if(SH4_CALLTRACE == 1)
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#define MAX_CALLSTACK 32
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static struct call_stack {
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    sh4addr_t call_addr;
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    sh4addr_t target_addr;
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    sh4addr_t stack_pointer;
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} call_stack[MAX_CALLSTACK];
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static int call_stack_depth = 0;
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int sh4_call_trace_on = 0;
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static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
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{
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    if( call_stack_depth < MAX_CALLSTACK ) {
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	call_stack[call_stack_depth].call_addr = source;
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	call_stack[call_stack_depth].target_addr = dest;
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	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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    }
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    call_stack_depth++;
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}
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static inline void trace_return( sh4addr_t source, sh4addr_t dest )
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{
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    if( call_stack_depth > 0 ) {
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	call_stack_depth--;
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    }
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}
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void fprint_stack_trace( FILE *f )
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{
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    int i = call_stack_depth -1;
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    if( i >= MAX_CALLSTACK )
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	i = MAX_CALLSTACK - 1;
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    for( ; i >= 0; i-- ) {
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	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
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		 (call_stack_depth - i), call_stack[i].call_addr,
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		 call_stack[i].target_addr, call_stack[i].stack_pointer );
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    }
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}
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#define TRACE_CALL( source, dest ) trace_call(source, dest)
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#define TRACE_RETURN( source, dest ) trace_return(source, dest)
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#else
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#define TRACE_CALL( dest, rts ) 
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#define TRACE_RETURN( source, dest )
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#endif
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#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
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#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
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#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
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#define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
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#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
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#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
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#define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
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#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
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#define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
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#define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
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#ifdef HAVE_FRAME_ADDRESS
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static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
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#define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
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#define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
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#define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
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#define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
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#define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
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#define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
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#define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
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#define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
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#else
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#define INIT_EXCEPTIONS(label)
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#define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
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#define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
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#define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
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#define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
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#define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
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#define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
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#define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
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#endif
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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	CHECKRALIGN64(addr); \
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        if( reg & 1 ) { \
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            MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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            MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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        CHECKRALIGN32(addr); \
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        MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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    }
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#define MEM_FP_WRITE( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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        CHECKWALIGN64(addr); \
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        if( reg & 1 ) { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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    	CHECKWALIGN32(addr); \
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        MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
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    }
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#define UNDEF(ir)
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#define UNIMP(ir)
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/**
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 * Perform instruction-completion following core exit of a partially completed
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 * instruction. NOTE: This is only allowed on memory writes, operation is not
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 * guaranteed in any other case.
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 */
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void sh4_finalize_instruction( void )
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{
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    unsigned short ir;
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    uint32_t tmp;
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    assert( IS_IN_ICACHE(sh4r.pc) );
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    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
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   234
    
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    /**
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     * Note - we can't take an exit on a control transfer instruction itself,
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     * which means the exit must have happened in the delay slot. So for these
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     * cases, finalize the delay slot instruction, and re-execute the control transfer.
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     *
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     * For delay slots which modify the argument used in the branch instruction,
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     * we pretty much just assume that that can't have already happened in an exit case.
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     */
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   243
    
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   244
%%
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BRA disp {: 
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    sh4r.pc += 2; 
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   247
    sh4_finalize_instruction(); 
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    sh4r.pc += disp;
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   249
    sh4r.slice_cycle += sh4_cpu_period;
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:}
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   251
BRAF Rn {: 
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    sh4r.pc += 2; 
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    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction(); 
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   255
    sh4r.pc += tmp;
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   256
    sh4r.slice_cycle += sh4_cpu_period;
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   257
:}
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   258
BSR disp {: 
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   259
    /* Note: PR is already set */ 
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   260
    sh4r.pc += 2;
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   261
    sh4_finalize_instruction();
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   262
    sh4r.pc += disp;
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   263
    sh4r.slice_cycle += sh4_cpu_period;
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   264
:}
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   265
BSRF Rn {:
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   266
    /* Note: PR is already set */ 
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   267
    sh4r.pc += 2;
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   268
    tmp = sh4r.r[Rn];
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   269
    sh4_finalize_instruction();
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   270
    sh4r.pc += tmp;
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   271
    sh4r.slice_cycle += sh4_cpu_period;
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   272
:}
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   273
BF/S disp {: 
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   274
    sh4r.pc += 2;
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   275
    sh4_finalize_instruction();
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   276
    if( !sh4r.t ) {
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   277
        sh4r.pc += disp;
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   278
    }
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   279
    sh4r.slice_cycle += sh4_cpu_period;
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   280
:}
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   281
BT/S disp {: 
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   282
    sh4r.pc += 2;
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   283
    sh4_finalize_instruction();
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   284
    if( sh4r.t ) {
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   285
        sh4r.pc += disp;
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   286
    }
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   287
    sh4r.slice_cycle += sh4_cpu_period;
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   288
:}
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   289
JMP @Rn {:
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   290
    sh4r.pc += 2;
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   291
    tmp = sh4r.r[Rn];
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   292
    sh4_finalize_instruction();
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   293
    sh4r.pc = tmp;
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   294
    sh4r.new_pc = tmp + 2;
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   295
    sh4r.slice_cycle += 2*sh4_cpu_period;
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   296
    return;
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   297
:}
nkeynes@948
   298
JSR @Rn {: 
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   299
    /* Note: PR is already set */ 
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   300
    sh4r.pc += 2;
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   301
    tmp = sh4r.r[Rn];
nkeynes@948
   302
    sh4_finalize_instruction();
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   303
    sh4r.pc = tmp;
nkeynes@948
   304
    sh4r.new_pc = tmp + 2;
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   305
    sh4r.slice_cycle += 2*sh4_cpu_period;
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   306
    return;
nkeynes@948
   307
:}
nkeynes@948
   308
RTS {: 
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   309
    sh4r.pc += 2;
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   310
    sh4_finalize_instruction();
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   311
    sh4r.pc = sh4r.pr;
nkeynes@948
   312
    sh4r.new_pc = sh4r.pr + 2;
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   313
    sh4r.slice_cycle += 2*sh4_cpu_period;
nkeynes@948
   314
    return;
nkeynes@948
   315
:}
nkeynes@948
   316
RTE {: 
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   317
    /* SR is already set */
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   318
    sh4r.pc += 2;
nkeynes@948
   319
    sh4_finalize_instruction();
nkeynes@948
   320
    sh4r.pc = sh4r.spc;
nkeynes@948
   321
    sh4r.new_pc = sh4r.pr + 2;
nkeynes@948
   322
    sh4r.slice_cycle += 2*sh4_cpu_period;
nkeynes@948
   323
    return;
nkeynes@948
   324
:}
nkeynes@948
   325
MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
nkeynes@948
   326
MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
nkeynes@948
   327
MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
nkeynes@948
   328
MOV.B @Rm+, Rn {: sh4r.r[Rm] ++; :}
nkeynes@948
   329
MOV.W @Rm+, Rn {: sh4r.r[Rm] += 2; :}
nkeynes@948
   330
MOV.L @Rm+, Rn {: sh4r.r[Rm] += 4; :}
nkeynes@948
   331
%%
nkeynes@948
   332
    sh4r.pc += 2;
nkeynes@948
   333
    sh4r.new_pc = sh4r.pc+2;
nkeynes@948
   334
    sh4r.slice_cycle += sh4_cpu_period;
nkeynes@948
   335
}
nkeynes@948
   336
nkeynes@948
   337
#undef UNDEF(ir)
nkeynes@948
   338
#undef UNIMP(ir)
nkeynes@948
   339
nkeynes@948
   340
#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
nkeynes@948
   341
#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
nkeynes@948
   342
nkeynes@948
   343
nkeynes@359
   344
gboolean sh4_execute_instruction( void )
nkeynes@359
   345
{
nkeynes@359
   346
    uint32_t pc;
nkeynes@359
   347
    unsigned short ir;
nkeynes@359
   348
    uint32_t tmp;
nkeynes@359
   349
    float ftmp;
nkeynes@359
   350
    double dtmp;
nkeynes@586
   351
    int64_t memtmp; // temporary holder for memory reads
nkeynes@927
   352
nkeynes@927
   353
    INIT_EXCEPTIONS(except)
nkeynes@359
   354
    
nkeynes@359
   355
#define R0 sh4r.r[0]
nkeynes@359
   356
    pc = sh4r.pc;
nkeynes@359
   357
    if( pc > 0xFFFFFF00 ) {
nkeynes@359
   358
	/* SYSCALL Magic */
nkeynes@359
   359
	syscall_invoke( pc );
nkeynes@359
   360
	sh4r.in_delay_slot = 0;
nkeynes@359
   361
	pc = sh4r.pc = sh4r.pr;
nkeynes@359
   362
	sh4r.new_pc = sh4r.pc + 2;
nkeynes@671
   363
        return TRUE;
nkeynes@359
   364
    }
nkeynes@359
   365
    CHECKRALIGN16(pc);
nkeynes@359
   366
nkeynes@671
   367
#ifdef ENABLE_SH4STATS
nkeynes@671
   368
    sh4_stats_add_by_pc(sh4r.pc);
nkeynes@671
   369
#endif
nkeynes@671
   370
nkeynes@359
   371
    /* Read instruction */
nkeynes@586
   372
    if( !IS_IN_ICACHE(pc) ) {
nkeynes@586
   373
	if( !mmu_update_icache(pc) ) {
nkeynes@586
   374
	    // Fault - look for the fault handler
nkeynes@586
   375
	    if( !mmu_update_icache(sh4r.pc) ) {
nkeynes@586
   376
		// double fault - halt
nkeynes@586
   377
		ERROR( "Double fault - halting" );
nkeynes@740
   378
		sh4_core_exit(CORE_EXIT_HALT);
nkeynes@586
   379
		return FALSE;
nkeynes@586
   380
	    }
nkeynes@359
   381
	}
nkeynes@586
   382
	pc = sh4r.pc;
nkeynes@359
   383
    }
nkeynes@586
   384
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   385
    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
nkeynes@948
   386
    
nkeynes@948
   387
    /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
nkeynes@948
   388
     * be visible until after the instruction has executed (for exception 
nkeynes@948
   389
     * correctness)
nkeynes@948
   390
     */
nkeynes@948
   391
    if( sh4r.in_delay_slot ) {
nkeynes@948
   392
    	sh4r.pc -= 2;
nkeynes@948
   393
    }
nkeynes@359
   394
%%
nkeynes@359
   395
AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
nkeynes@359
   396
AND #imm, R0 {: R0 &= imm; :}
nkeynes@586
   397
 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
nkeynes@359
   398
NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
nkeynes@359
   399
OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
nkeynes@359
   400
OR #imm, R0  {: R0 |= imm; :}
nkeynes@586
   401
 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
nkeynes@359
   402
TAS.B @Rn {:
nkeynes@586
   403
    MEM_READ_BYTE( sh4r.r[Rn], tmp );
nkeynes@359
   404
    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@359
   405
    MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
nkeynes@359
   406
:}
nkeynes@359
   407
TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
nkeynes@359
   408
TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
nkeynes@586
   409
 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
nkeynes@359
   410
XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
nkeynes@359
   411
XOR #imm, R0 {: R0 ^= imm; :}
nkeynes@586
   412
 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
nkeynes@359
   413
XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   414
nkeynes@359
   415
ROTL Rn {:
nkeynes@359
   416
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   417
    sh4r.r[Rn] <<= 1;
nkeynes@359
   418
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   419
:}
nkeynes@359
   420
ROTR Rn {:
nkeynes@359
   421
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   422
    sh4r.r[Rn] >>= 1;
nkeynes@359
   423
    sh4r.r[Rn] |= (sh4r.t << 31);
nkeynes@359
   424
:}
nkeynes@359
   425
ROTCL Rn {:
nkeynes@359
   426
    tmp = sh4r.r[Rn] >> 31;
nkeynes@359
   427
    sh4r.r[Rn] <<= 1;
nkeynes@359
   428
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   429
    sh4r.t = tmp;
nkeynes@359
   430
:}
nkeynes@359
   431
ROTCR Rn {:
nkeynes@359
   432
    tmp = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   433
    sh4r.r[Rn] >>= 1;
nkeynes@359
   434
    sh4r.r[Rn] |= (sh4r.t << 31 );
nkeynes@359
   435
    sh4r.t = tmp;
nkeynes@359
   436
:}
nkeynes@359
   437
SHAD Rm, Rn {:
nkeynes@359
   438
    tmp = sh4r.r[Rm];
nkeynes@359
   439
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   440
    else if( (tmp & 0x1F) == 0 )  
nkeynes@359
   441
        sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
nkeynes@359
   442
    else 
nkeynes@359
   443
	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
nkeynes@359
   444
:}
nkeynes@359
   445
SHLD Rm, Rn {:
nkeynes@359
   446
    tmp = sh4r.r[Rm];
nkeynes@359
   447
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   448
    else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
nkeynes@359
   449
    else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
nkeynes@359
   450
:}
nkeynes@359
   451
SHAL Rn {:
nkeynes@359
   452
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   453
    sh4r.r[Rn] <<= 1;
nkeynes@359
   454
:}
nkeynes@359
   455
SHAR Rn {:
nkeynes@359
   456
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   457
    sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
nkeynes@359
   458
:}
nkeynes@359
   459
SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
nkeynes@359
   460
SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
nkeynes@359
   461
SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
nkeynes@359
   462
SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
nkeynes@359
   463
SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
nkeynes@359
   464
SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
nkeynes@359
   465
SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
nkeynes@359
   466
SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
nkeynes@359
   467
nkeynes@359
   468
EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
nkeynes@359
   469
EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
nkeynes@359
   470
EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
nkeynes@359
   471
EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
nkeynes@359
   472
SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
nkeynes@359
   473
SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   474
nkeynes@359
   475
CLRT {: sh4r.t = 0; :}
nkeynes@359
   476
SETT {: sh4r.t = 1; :}
nkeynes@359
   477
CLRMAC {: sh4r.mac = 0; :}
nkeynes@550
   478
LDTLB {: MMU_ldtlb(); :}
nkeynes@359
   479
CLRS {: sh4r.s = 0; :}
nkeynes@359
   480
SETS {: sh4r.s = 1; :}
nkeynes@359
   481
MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
nkeynes@359
   482
NOP {: /* NOP */ :}
nkeynes@359
   483
nkeynes@359
   484
PREF @Rn {:
nkeynes@946
   485
    MEM_PREFETCH(sh4r.r[Rn]);
nkeynes@359
   486
:}
nkeynes@359
   487
OCBI @Rn {: :}
nkeynes@359
   488
OCBP @Rn {: :}
nkeynes@359
   489
OCBWB @Rn {: :}
nkeynes@359
   490
MOVCA.L R0, @Rn {:
nkeynes@359
   491
    tmp = sh4r.r[Rn];
nkeynes@359
   492
    CHECKWALIGN32(tmp);
nkeynes@359
   493
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   494
:}
nkeynes@359
   495
MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   496
MOV.W Rm, @(R0, Rn) {: 
nkeynes@359
   497
    CHECKWALIGN16( R0 + sh4r.r[Rn] );
nkeynes@359
   498
    MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   499
:}
nkeynes@359
   500
MOV.L Rm, @(R0, Rn) {:
nkeynes@359
   501
    CHECKWALIGN32( R0 + sh4r.r[Rn] );
nkeynes@359
   502
    MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   503
:}
nkeynes@586
   504
MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   505
MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
nkeynes@586
   506
    MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   507
:}
nkeynes@359
   508
MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
nkeynes@586
   509
    MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   510
:}
nkeynes@359
   511
MOV.L Rm, @(disp, Rn) {:
nkeynes@359
   512
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   513
    CHECKWALIGN32( tmp );
nkeynes@359
   514
    MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
nkeynes@359
   515
:}
nkeynes@359
   516
MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   517
MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   518
MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@587
   519
 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
nkeynes@587
   520
 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
nkeynes@587
   521
 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
nkeynes@359
   522
MOV.L @(disp, Rm), Rn {:
nkeynes@359
   523
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   524
    CHECKRALIGN32( tmp );
nkeynes@586
   525
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   526
:}
nkeynes@586
   527
MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   528
 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   529
 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   530
MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
nkeynes@586
   531
 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
nkeynes@586
   532
 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
nkeynes@586
   533
 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
nkeynes@359
   534
MOV.L @(disp, PC), Rn {:
nkeynes@359
   535
    CHECKSLOTILLEGAL();
nkeynes@359
   536
    tmp = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@586
   537
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   538
:}
nkeynes@359
   539
MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   540
MOV.W R0, @(disp, GBR) {:
nkeynes@359
   541
    tmp = sh4r.gbr + disp;
nkeynes@359
   542
    CHECKWALIGN16( tmp );
nkeynes@359
   543
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   544
:}
nkeynes@359
   545
MOV.L R0, @(disp, GBR) {:
nkeynes@359
   546
    tmp = sh4r.gbr + disp;
nkeynes@359
   547
    CHECKWALIGN32( tmp );
nkeynes@359
   548
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   549
:}
nkeynes@586
   550
 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   551
MOV.W @(disp, GBR), R0 {: 
nkeynes@359
   552
    tmp = sh4r.gbr + disp;
nkeynes@359
   553
    CHECKRALIGN16( tmp );
nkeynes@586
   554
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   555
:}
nkeynes@359
   556
MOV.L @(disp, GBR), R0 {:
nkeynes@359
   557
    tmp = sh4r.gbr + disp;
nkeynes@359
   558
    CHECKRALIGN32( tmp );
nkeynes@586
   559
    MEM_READ_LONG( tmp, R0 );
nkeynes@359
   560
:}
nkeynes@359
   561
MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
nkeynes@359
   562
MOV.W R0, @(disp, Rn) {: 
nkeynes@359
   563
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   564
    CHECKWALIGN16( tmp );
nkeynes@359
   565
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   566
:}
nkeynes@586
   567
 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
nkeynes@359
   568
MOV.W @(disp, Rm), R0 {: 
nkeynes@359
   569
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   570
    CHECKRALIGN16( tmp );
nkeynes@586
   571
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   572
:}
nkeynes@359
   573
MOV.W @(disp, PC), Rn {:
nkeynes@359
   574
    CHECKSLOTILLEGAL();
nkeynes@359
   575
    tmp = pc + 4 + disp;
nkeynes@586
   576
    MEM_READ_WORD( tmp, sh4r.r[Rn] );
nkeynes@359
   577
:}
nkeynes@359
   578
MOVA @(disp, PC), R0 {:
nkeynes@359
   579
    CHECKSLOTILLEGAL();
nkeynes@359
   580
    R0 = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@359
   581
:}
nkeynes@359
   582
MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
nkeynes@359
   583
nkeynes@732
   584
FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
nkeynes@732
   585
FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
nkeynes@732
   586
FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
nkeynes@732
   587
FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
nkeynes@732
   588
FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
nkeynes@732
   589
 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
nkeynes@732
   590
FMOV FRm, FRn {: 
nkeynes@732
   591
    if( IS_FPU_DOUBLESIZE() )
nkeynes@732
   592
	DR(FRn) = DR(FRm);
nkeynes@732
   593
    else
nkeynes@732
   594
	FR(FRn) = FR(FRm);
nkeynes@732
   595
:}
nkeynes@732
   596
nkeynes@359
   597
CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
nkeynes@359
   598
CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
nkeynes@359
   599
CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   600
CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   601
CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   602
CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   603
CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
nkeynes@359
   604
CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
nkeynes@359
   605
CMP/STR Rm, Rn {: 
nkeynes@359
   606
    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@359
   607
    tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
nkeynes@359
   608
    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@359
   609
             (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@359
   610
:}
nkeynes@359
   611
nkeynes@359
   612
ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
nkeynes@359
   613
ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
nkeynes@359
   614
ADDC Rm, Rn {:
nkeynes@359
   615
    tmp = sh4r.r[Rn];
nkeynes@359
   616
    sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
nkeynes@359
   617
    sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@359
   618
:}
nkeynes@359
   619
ADDV Rm, Rn {:
nkeynes@359
   620
    tmp = sh4r.r[Rn] + sh4r.r[Rm];
nkeynes@359
   621
    sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@359
   622
    sh4r.r[Rn] = tmp;
nkeynes@359
   623
:}
nkeynes@359
   624
DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
nkeynes@359
   625
DIV0S Rm, Rn {: 
nkeynes@359
   626
    sh4r.q = sh4r.r[Rn]>>31;
nkeynes@359
   627
    sh4r.m = sh4r.r[Rm]>>31;
nkeynes@359
   628
    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@359
   629
:}
nkeynes@359
   630
DIV1 Rm, Rn {:
nkeynes@384
   631
    /* This is derived from the sh4 manual with some simplifications */
nkeynes@359
   632
    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@359
   633
nkeynes@359
   634
    dir = sh4r.q ^ sh4r.m;
nkeynes@359
   635
    sh4r.q = (sh4r.r[Rn] >> 31);
nkeynes@359
   636
    tmp2 = sh4r.r[Rm];
nkeynes@359
   637
    sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
nkeynes@359
   638
    tmp0 = sh4r.r[Rn];
nkeynes@359
   639
    if( dir ) {
nkeynes@359
   640
         sh4r.r[Rn] += tmp2;
nkeynes@359
   641
         tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
nkeynes@359
   642
    } else {
nkeynes@359
   643
         sh4r.r[Rn] -= tmp2;
nkeynes@359
   644
         tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
nkeynes@359
   645
    }
nkeynes@359
   646
    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@359
   647
    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@359
   648
:}
nkeynes@359
   649
DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
nkeynes@359
   650
DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
nkeynes@359
   651
DT Rn {:
nkeynes@359
   652
    sh4r.r[Rn] --;
nkeynes@359
   653
    sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
nkeynes@359
   654
:}
nkeynes@359
   655
MAC.W @Rm+, @Rn+ {:
nkeynes@587
   656
    int32_t stmp;
nkeynes@587
   657
    if( Rm == Rn ) {
nkeynes@587
   658
	CHECKRALIGN16(sh4r.r[Rn]);
nkeynes@587
   659
	MEM_READ_WORD( sh4r.r[Rn], tmp );
nkeynes@587
   660
	stmp = SIGNEXT16(tmp);
nkeynes@587
   661
	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
nkeynes@587
   662
	stmp *= SIGNEXT16(tmp);
nkeynes@587
   663
	sh4r.r[Rn] += 4;
nkeynes@587
   664
    } else {
nkeynes@587
   665
	CHECKRALIGN16( sh4r.r[Rn] );
nkeynes@587
   666
	CHECKRALIGN16( sh4r.r[Rm] );
nkeynes@587
   667
	MEM_READ_WORD(sh4r.r[Rn], tmp);
nkeynes@587
   668
	stmp = SIGNEXT16(tmp);
nkeynes@587
   669
	MEM_READ_WORD(sh4r.r[Rm], tmp);
nkeynes@587
   670
	stmp = stmp * SIGNEXT16(tmp);
nkeynes@587
   671
	sh4r.r[Rn] += 2;
nkeynes@587
   672
	sh4r.r[Rm] += 2;
nkeynes@587
   673
    }
nkeynes@359
   674
    if( sh4r.s ) {
nkeynes@359
   675
	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
nkeynes@359
   676
	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
nkeynes@359
   677
	    sh4r.mac = 0x000000017FFFFFFFLL;
nkeynes@359
   678
	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
nkeynes@359
   679
	    sh4r.mac = 0x0000000180000000LL;
nkeynes@359
   680
	} else {
nkeynes@359
   681
	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   682
		((uint32_t)(sh4r.mac + stmp));
nkeynes@359
   683
	}
nkeynes@359
   684
    } else {
nkeynes@359
   685
	sh4r.mac += SIGNEXT32(stmp);
nkeynes@359
   686
    }
nkeynes@359
   687
:}
nkeynes@359
   688
MAC.L @Rm+, @Rn+ {:
nkeynes@587
   689
    int64_t tmpl;
nkeynes@587
   690
    if( Rm == Rn ) {
nkeynes@587
   691
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   692
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   693
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   694
	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
nkeynes@587
   695
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   696
	sh4r.r[Rn] += 8;
nkeynes@587
   697
    } else {
nkeynes@587
   698
	CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@587
   699
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   700
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   701
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   702
	MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@587
   703
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   704
	sh4r.r[Rn] += 4;
nkeynes@587
   705
	sh4r.r[Rm] += 4;
nkeynes@587
   706
    }
nkeynes@359
   707
    if( sh4r.s ) {
nkeynes@359
   708
        /* 48-bit Saturation. Yuch */
nkeynes@359
   709
        if( tmpl < (int64_t)0xFFFF800000000000LL )
nkeynes@359
   710
            tmpl = 0xFFFF800000000000LL;
nkeynes@359
   711
        else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@359
   712
            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@359
   713
    }
nkeynes@359
   714
    sh4r.mac = tmpl;
nkeynes@359
   715
:}
nkeynes@359
   716
MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   717
                        (sh4r.r[Rm] * sh4r.r[Rn]); :}
nkeynes@359
   718
MULU.W Rm, Rn {:
nkeynes@359
   719
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   720
               (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
nkeynes@359
   721
:}
nkeynes@359
   722
MULS.W Rm, Rn {:
nkeynes@359
   723
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   724
               (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
nkeynes@359
   725
:}
nkeynes@359
   726
NEGC Rm, Rn {:
nkeynes@359
   727
    tmp = 0 - sh4r.r[Rm];
nkeynes@359
   728
    sh4r.r[Rn] = tmp - sh4r.t;
nkeynes@359
   729
    sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
nkeynes@359
   730
:}
nkeynes@359
   731
NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
nkeynes@359
   732
SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
nkeynes@359
   733
SUBC Rm, Rn {: 
nkeynes@359
   734
    tmp = sh4r.r[Rn];
nkeynes@359
   735
    sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
nkeynes@359
   736
    sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
nkeynes@359
   737
:}
nkeynes@359
   738
nkeynes@359
   739
BRAF Rn {:
nkeynes@359
   740
     CHECKSLOTILLEGAL();
nkeynes@359
   741
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   742
     sh4r.in_delay_slot = 1;
nkeynes@359
   743
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   744
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   745
     return TRUE;
nkeynes@359
   746
:}
nkeynes@359
   747
BSRF Rn {:
nkeynes@359
   748
     CHECKSLOTILLEGAL();
nkeynes@359
   749
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   750
     sh4r.in_delay_slot = 1;
nkeynes@359
   751
     sh4r.pr = sh4r.pc + 4;
nkeynes@359
   752
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   753
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   754
     TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   755
     return TRUE;
nkeynes@359
   756
:}
nkeynes@359
   757
BT disp {:
nkeynes@359
   758
    CHECKSLOTILLEGAL();
nkeynes@359
   759
    if( sh4r.t ) {
nkeynes@359
   760
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   761
        sh4r.pc += disp + 4;
nkeynes@359
   762
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   763
        return TRUE;
nkeynes@359
   764
    }
nkeynes@359
   765
:}
nkeynes@359
   766
BF disp {:
nkeynes@359
   767
    CHECKSLOTILLEGAL();
nkeynes@359
   768
    if( !sh4r.t ) {
nkeynes@359
   769
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   770
        sh4r.pc += disp + 4;
nkeynes@359
   771
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   772
        return TRUE;
nkeynes@359
   773
    }
nkeynes@359
   774
:}
nkeynes@359
   775
BT/S disp {:
nkeynes@359
   776
    CHECKSLOTILLEGAL();
nkeynes@359
   777
    if( sh4r.t ) {
nkeynes@359
   778
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   779
        sh4r.in_delay_slot = 1;
nkeynes@359
   780
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   781
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   782
        sh4r.in_delay_slot = 1;
nkeynes@359
   783
        return TRUE;
nkeynes@359
   784
    }
nkeynes@359
   785
:}
nkeynes@359
   786
BF/S disp {:
nkeynes@359
   787
    CHECKSLOTILLEGAL();
nkeynes@359
   788
    if( !sh4r.t ) {
nkeynes@359
   789
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   790
        sh4r.in_delay_slot = 1;
nkeynes@359
   791
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   792
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   793
        return TRUE;
nkeynes@359
   794
    }
nkeynes@359
   795
:}
nkeynes@359
   796
BRA disp {:
nkeynes@359
   797
    CHECKSLOTILLEGAL();
nkeynes@359
   798
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   799
    sh4r.in_delay_slot = 1;
nkeynes@359
   800
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   801
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   802
    return TRUE;
nkeynes@359
   803
:}
nkeynes@359
   804
BSR disp {:
nkeynes@359
   805
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   806
    CHECKSLOTILLEGAL();
nkeynes@359
   807
    sh4r.in_delay_slot = 1;
nkeynes@359
   808
    sh4r.pr = pc + 4;
nkeynes@359
   809
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   810
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   811
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   812
    return TRUE;
nkeynes@359
   813
:}
nkeynes@359
   814
TRAPA #imm {:
nkeynes@359
   815
    CHECKSLOTILLEGAL();
nkeynes@359
   816
    sh4r.pc += 2;
nkeynes@586
   817
    sh4_raise_trap( imm );
nkeynes@586
   818
    return TRUE;
nkeynes@359
   819
:}
nkeynes@359
   820
RTS {: 
nkeynes@359
   821
    CHECKSLOTILLEGAL();
nkeynes@359
   822
    CHECKDEST( sh4r.pr );
nkeynes@359
   823
    sh4r.in_delay_slot = 1;
nkeynes@359
   824
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   825
    sh4r.new_pc = sh4r.pr;
nkeynes@359
   826
    TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@359
   827
    return TRUE;
nkeynes@359
   828
:}
nkeynes@359
   829
SLEEP {:
nkeynes@359
   830
    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@359
   831
	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@359
   832
    } else {
nkeynes@359
   833
	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@359
   834
    }
nkeynes@359
   835
    return FALSE; /* Halt CPU */
nkeynes@359
   836
:}
nkeynes@359
   837
RTE {:
nkeynes@359
   838
    CHECKPRIV();
nkeynes@359
   839
    CHECKDEST( sh4r.spc );
nkeynes@359
   840
    CHECKSLOTILLEGAL();
nkeynes@359
   841
    sh4r.in_delay_slot = 1;
nkeynes@359
   842
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   843
    sh4r.new_pc = sh4r.spc;
nkeynes@374
   844
    sh4_write_sr( sh4r.ssr );
nkeynes@359
   845
    return TRUE;
nkeynes@359
   846
:}
nkeynes@359
   847
JMP @Rn {:
nkeynes@359
   848
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   849
    CHECKSLOTILLEGAL();
nkeynes@359
   850
    sh4r.in_delay_slot = 1;
nkeynes@359
   851
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   852
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   853
    return TRUE;
nkeynes@359
   854
:}
nkeynes@359
   855
JSR @Rn {:
nkeynes@359
   856
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   857
    CHECKSLOTILLEGAL();
nkeynes@359
   858
    sh4r.in_delay_slot = 1;
nkeynes@359
   859
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   860
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   861
    sh4r.pr = pc + 4;
nkeynes@359
   862
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   863
    return TRUE;
nkeynes@359
   864
:}
nkeynes@359
   865
STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
nkeynes@359
   866
STS.L MACH, @-Rn {:
nkeynes@587
   867
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   868
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
nkeynes@359
   869
    sh4r.r[Rn] -= 4;
nkeynes@359
   870
:}
nkeynes@359
   871
STC.L SR, @-Rn {:
nkeynes@359
   872
    CHECKPRIV();
nkeynes@587
   873
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   874
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
nkeynes@359
   875
    sh4r.r[Rn] -= 4;
nkeynes@359
   876
:}
nkeynes@359
   877
LDS.L @Rm+, MACH {:
nkeynes@359
   878
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   879
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   880
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@586
   881
	(((uint64_t)tmp)<<32);
nkeynes@359
   882
    sh4r.r[Rm] += 4;
nkeynes@359
   883
:}
nkeynes@359
   884
LDC.L @Rm+, SR {:
nkeynes@359
   885
    CHECKSLOTILLEGAL();
nkeynes@359
   886
    CHECKPRIV();
nkeynes@359
   887
    CHECKWALIGN32( sh4r.r[Rm] );
nkeynes@586
   888
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@586
   889
    sh4_write_sr( tmp );
nkeynes@359
   890
    sh4r.r[Rm] +=4;
nkeynes@359
   891
:}
nkeynes@359
   892
LDS Rm, MACH {:
nkeynes@359
   893
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@359
   894
               (((uint64_t)sh4r.r[Rm])<<32);
nkeynes@359
   895
:}
nkeynes@359
   896
LDC Rm, SR {:
nkeynes@359
   897
    CHECKSLOTILLEGAL();
nkeynes@359
   898
    CHECKPRIV();
nkeynes@374
   899
    sh4_write_sr( sh4r.r[Rm] );
nkeynes@359
   900
:}
nkeynes@359
   901
LDC Rm, SGR {:
nkeynes@359
   902
    CHECKPRIV();
nkeynes@359
   903
    sh4r.sgr = sh4r.r[Rm];
nkeynes@359
   904
:}
nkeynes@359
   905
LDC.L @Rm+, SGR {:
nkeynes@359
   906
    CHECKPRIV();
nkeynes@359
   907
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   908
    MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
nkeynes@359
   909
    sh4r.r[Rm] +=4;
nkeynes@359
   910
:}
nkeynes@359
   911
STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
nkeynes@359
   912
STS.L MACL, @-Rn {:
nkeynes@587
   913
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   914
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
nkeynes@359
   915
    sh4r.r[Rn] -= 4;
nkeynes@359
   916
:}
nkeynes@359
   917
STC.L GBR, @-Rn {:
nkeynes@587
   918
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   919
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
nkeynes@359
   920
    sh4r.r[Rn] -= 4;
nkeynes@359
   921
:}
nkeynes@359
   922
LDS.L @Rm+, MACL {:
nkeynes@359
   923
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   924
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   925
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@586
   926
               (uint64_t)((uint32_t)tmp);
nkeynes@359
   927
    sh4r.r[Rm] += 4;
nkeynes@359
   928
:}
nkeynes@359
   929
LDC.L @Rm+, GBR {:
nkeynes@359
   930
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   931
    MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
nkeynes@359
   932
    sh4r.r[Rm] +=4;
nkeynes@359
   933
:}
nkeynes@359
   934
LDS Rm, MACL {:
nkeynes@359
   935
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   936
               (uint64_t)((uint32_t)(sh4r.r[Rm]));
nkeynes@359
   937
:}
nkeynes@359
   938
LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
nkeynes@359
   939
STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
nkeynes@359
   940
STS.L PR, @-Rn {:
nkeynes@587
   941
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   942
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
nkeynes@359
   943
    sh4r.r[Rn] -= 4;
nkeynes@359
   944
:}
nkeynes@359
   945
STC.L VBR, @-Rn {:
nkeynes@359
   946
    CHECKPRIV();
nkeynes@587
   947
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   948
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
nkeynes@359
   949
    sh4r.r[Rn] -= 4;
nkeynes@359
   950
:}
nkeynes@359
   951
LDS.L @Rm+, PR {:
nkeynes@359
   952
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   953
    MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
nkeynes@359
   954
    sh4r.r[Rm] += 4;
nkeynes@359
   955
:}
nkeynes@359
   956
LDC.L @Rm+, VBR {:
nkeynes@359
   957
    CHECKPRIV();
nkeynes@359
   958
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   959
    MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
nkeynes@359
   960
    sh4r.r[Rm] +=4;
nkeynes@359
   961
:}
nkeynes@359
   962
LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
nkeynes@359
   963
LDC Rm, VBR {:
nkeynes@359
   964
    CHECKPRIV();
nkeynes@359
   965
    sh4r.vbr = sh4r.r[Rm];
nkeynes@359
   966
:}
nkeynes@359
   967
STC SGR, Rn {:
nkeynes@359
   968
    CHECKPRIV();
nkeynes@359
   969
    sh4r.r[Rn] = sh4r.sgr;
nkeynes@359
   970
:}
nkeynes@359
   971
STC.L SGR, @-Rn {:
nkeynes@359
   972
    CHECKPRIV();
nkeynes@587
   973
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   974
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
nkeynes@359
   975
    sh4r.r[Rn] -= 4;
nkeynes@359
   976
:}
nkeynes@359
   977
STC.L SSR, @-Rn {:
nkeynes@359
   978
    CHECKPRIV();
nkeynes@587
   979
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   980
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
nkeynes@359
   981
    sh4r.r[Rn] -= 4;
nkeynes@359
   982
:}
nkeynes@359
   983
LDC.L @Rm+, SSR {:
nkeynes@359
   984
    CHECKPRIV();
nkeynes@359
   985
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   986
    MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
nkeynes@359
   987
    sh4r.r[Rm] +=4;
nkeynes@359
   988
:}
nkeynes@359
   989
LDC Rm, SSR {:
nkeynes@359
   990
    CHECKPRIV();
nkeynes@359
   991
    sh4r.ssr = sh4r.r[Rm];
nkeynes@359
   992
:}
nkeynes@359
   993
STC.L SPC, @-Rn {:
nkeynes@359
   994
    CHECKPRIV();
nkeynes@587
   995
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   996
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
nkeynes@359
   997
    sh4r.r[Rn] -= 4;
nkeynes@359
   998
:}
nkeynes@359
   999
LDC.L @Rm+, SPC {:
nkeynes@359
  1000
    CHECKPRIV();
nkeynes@359
  1001
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1002
    MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
nkeynes@359
  1003
    sh4r.r[Rm] +=4;
nkeynes@359
  1004
:}
nkeynes@359
  1005
LDC Rm, SPC {:
nkeynes@359
  1006
    CHECKPRIV();
nkeynes@359
  1007
    sh4r.spc = sh4r.r[Rm];
nkeynes@359
  1008
:}
nkeynes@626
  1009
STS FPUL, Rn {: 
nkeynes@626
  1010
    CHECKFPUEN();
nkeynes@669
  1011
    sh4r.r[Rn] = FPULi; 
nkeynes@626
  1012
:}
nkeynes@359
  1013
STS.L FPUL, @-Rn {:
nkeynes@626
  1014
    CHECKFPUEN();
nkeynes@587
  1015
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@669
  1016
    MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
nkeynes@359
  1017
    sh4r.r[Rn] -= 4;
nkeynes@359
  1018
:}
nkeynes@359
  1019
LDS.L @Rm+, FPUL {:
nkeynes@626
  1020
    CHECKFPUEN();
nkeynes@359
  1021
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1022
    MEM_READ_LONG(sh4r.r[Rm], FPULi);
nkeynes@359
  1023
    sh4r.r[Rm] +=4;
nkeynes@359
  1024
:}
nkeynes@626
  1025
LDS Rm, FPUL {:
nkeynes@626
  1026
    CHECKFPUEN();
nkeynes@669
  1027
    FPULi = sh4r.r[Rm]; 
nkeynes@626
  1028
:}
nkeynes@626
  1029
STS FPSCR, Rn {: 
nkeynes@626
  1030
    CHECKFPUEN();
nkeynes@626
  1031
    sh4r.r[Rn] = sh4r.fpscr; 
nkeynes@626
  1032
:}
nkeynes@359
  1033
STS.L FPSCR, @-Rn {:
nkeynes@626
  1034
    CHECKFPUEN();
nkeynes@587
  1035
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1036
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
nkeynes@359
  1037
    sh4r.r[Rn] -= 4;
nkeynes@359
  1038
:}
nkeynes@359
  1039
LDS.L @Rm+, FPSCR {:
nkeynes@626
  1040
    CHECKFPUEN();
nkeynes@359
  1041
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1042
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
  1043
    sh4r.r[Rm] +=4;
nkeynes@669
  1044
    sh4_write_fpscr( tmp );
nkeynes@359
  1045
:}
nkeynes@374
  1046
LDS Rm, FPSCR {: 
nkeynes@626
  1047
    CHECKFPUEN();
nkeynes@669
  1048
    sh4_write_fpscr( sh4r.r[Rm] );
nkeynes@374
  1049
:}
nkeynes@359
  1050
STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
nkeynes@359
  1051
STC.L DBR, @-Rn {:
nkeynes@359
  1052
    CHECKPRIV();
nkeynes@587
  1053
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1054
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
nkeynes@359
  1055
    sh4r.r[Rn] -= 4;
nkeynes@359
  1056
:}
nkeynes@359
  1057
LDC.L @Rm+, DBR {:
nkeynes@359
  1058
    CHECKPRIV();
nkeynes@359
  1059
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1060
    MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
nkeynes@359
  1061
    sh4r.r[Rm] +=4;
nkeynes@359
  1062
:}
nkeynes@359
  1063
LDC Rm, DBR {:
nkeynes@359
  1064
    CHECKPRIV();
nkeynes@359
  1065
    sh4r.dbr = sh4r.r[Rm];
nkeynes@359
  1066
:}
nkeynes@359
  1067
STC.L Rm_BANK, @-Rn {:
nkeynes@359
  1068
    CHECKPRIV();
nkeynes@587
  1069
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1070
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
nkeynes@359
  1071
    sh4r.r[Rn] -= 4;
nkeynes@359
  1072
:}
nkeynes@359
  1073
LDC.L @Rm+, Rn_BANK {:
nkeynes@359
  1074
    CHECKPRIV();
nkeynes@359
  1075
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1076
    MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
nkeynes@359
  1077
    sh4r.r[Rm] += 4;
nkeynes@359
  1078
:}
nkeynes@359
  1079
LDC Rm, Rn_BANK {:
nkeynes@359
  1080
    CHECKPRIV();
nkeynes@359
  1081
    sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
nkeynes@359
  1082
:}
nkeynes@359
  1083
STC SR, Rn {: 
nkeynes@359
  1084
    CHECKPRIV();
nkeynes@359
  1085
    sh4r.r[Rn] = sh4_read_sr();
nkeynes@359
  1086
:}
nkeynes@359
  1087
STC GBR, Rn {:
nkeynes@359
  1088
    sh4r.r[Rn] = sh4r.gbr;
nkeynes@359
  1089
:}
nkeynes@359
  1090
STC VBR, Rn {:
nkeynes@359
  1091
    CHECKPRIV();
nkeynes@359
  1092
    sh4r.r[Rn] = sh4r.vbr;
nkeynes@359
  1093
:}
nkeynes@359
  1094
STC SSR, Rn {:
nkeynes@359
  1095
    CHECKPRIV();
nkeynes@359
  1096
    sh4r.r[Rn] = sh4r.ssr;
nkeynes@359
  1097
:}
nkeynes@359
  1098
STC SPC, Rn {:
nkeynes@359
  1099
    CHECKPRIV();
nkeynes@359
  1100
    sh4r.r[Rn] = sh4r.spc;
nkeynes@359
  1101
:}
nkeynes@359
  1102
STC Rm_BANK, Rn {:
nkeynes@359
  1103
    CHECKPRIV();
nkeynes@359
  1104
    sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
nkeynes@359
  1105
:}
nkeynes@359
  1106
nkeynes@359
  1107
FADD FRm, FRn {:
nkeynes@359
  1108
    CHECKFPUEN();
nkeynes@359
  1109
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1110
	DR(FRn) += DR(FRm);
nkeynes@359
  1111
    } else {
nkeynes@359
  1112
	FR(FRn) += FR(FRm);
nkeynes@359
  1113
    }
nkeynes@359
  1114
:}
nkeynes@359
  1115
FSUB FRm, FRn {:
nkeynes@359
  1116
    CHECKFPUEN();
nkeynes@359
  1117
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1118
	DR(FRn) -= DR(FRm);
nkeynes@359
  1119
    } else {
nkeynes@359
  1120
	FR(FRn) -= FR(FRm);
nkeynes@359
  1121
    }
nkeynes@359
  1122
:}
nkeynes@359
  1123
nkeynes@359
  1124
FMUL FRm, FRn {:
nkeynes@359
  1125
    CHECKFPUEN();
nkeynes@359
  1126
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1127
	DR(FRn) *= DR(FRm);
nkeynes@359
  1128
    } else {
nkeynes@359
  1129
	FR(FRn) *= FR(FRm);
nkeynes@359
  1130
    }
nkeynes@359
  1131
:}
nkeynes@359
  1132
nkeynes@359
  1133
FDIV FRm, FRn {:
nkeynes@359
  1134
    CHECKFPUEN();
nkeynes@359
  1135
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1136
	DR(FRn) /= DR(FRm);
nkeynes@359
  1137
    } else {
nkeynes@359
  1138
	FR(FRn) /= FR(FRm);
nkeynes@359
  1139
    }
nkeynes@359
  1140
:}
nkeynes@359
  1141
nkeynes@359
  1142
FCMP/EQ FRm, FRn {:
nkeynes@359
  1143
    CHECKFPUEN();
nkeynes@359
  1144
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1145
	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
nkeynes@359
  1146
    } else {
nkeynes@359
  1147
	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
nkeynes@359
  1148
    }
nkeynes@359
  1149
:}
nkeynes@359
  1150
nkeynes@359
  1151
FCMP/GT FRm, FRn {:
nkeynes@359
  1152
    CHECKFPUEN();
nkeynes@359
  1153
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1154
	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
nkeynes@359
  1155
    } else {
nkeynes@359
  1156
	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
nkeynes@359
  1157
    }
nkeynes@359
  1158
:}
nkeynes@359
  1159
nkeynes@359
  1160
FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
nkeynes@359
  1161
FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
nkeynes@359
  1162
FLOAT FPUL, FRn {: 
nkeynes@359
  1163
    CHECKFPUEN();
nkeynes@374
  1164
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1165
	if( FRn&1 ) { // No, really...
nkeynes@374
  1166
	    dtmp = (double)FPULi;
nkeynes@374
  1167
	    FR(FRn) = *(((float *)&dtmp)+1);
nkeynes@374
  1168
	} else {
nkeynes@374
  1169
	    DRF(FRn>>1) = (double)FPULi;
nkeynes@374
  1170
	}
nkeynes@374
  1171
    } else {
nkeynes@359
  1172
	FR(FRn) = (float)FPULi;
nkeynes@374
  1173
    }
nkeynes@359
  1174
:}
nkeynes@359
  1175
FTRC FRm, FPUL {:
nkeynes@359
  1176
    CHECKFPUEN();
nkeynes@359
  1177
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1178
	if( FRm&1 ) {
nkeynes@374
  1179
	    dtmp = 0;
nkeynes@374
  1180
	    *(((float *)&dtmp)+1) = FR(FRm);
nkeynes@374
  1181
	} else {
nkeynes@374
  1182
	    dtmp = DRF(FRm>>1);
nkeynes@374
  1183
	}
nkeynes@359
  1184
        if( dtmp >= MAX_INTF )
nkeynes@359
  1185
            FPULi = MAX_INT;
nkeynes@359
  1186
        else if( dtmp <= MIN_INTF )
nkeynes@359
  1187
            FPULi = MIN_INT;
nkeynes@359
  1188
        else 
nkeynes@359
  1189
            FPULi = (int32_t)dtmp;
nkeynes@359
  1190
    } else {
nkeynes@359
  1191
	ftmp = FR(FRm);
nkeynes@359
  1192
	if( ftmp >= MAX_INTF )
nkeynes@359
  1193
	    FPULi = MAX_INT;
nkeynes@359
  1194
	else if( ftmp <= MIN_INTF )
nkeynes@359
  1195
	    FPULi = MIN_INT;
nkeynes@359
  1196
	else
nkeynes@359
  1197
	    FPULi = (int32_t)ftmp;
nkeynes@359
  1198
    }
nkeynes@359
  1199
:}
nkeynes@359
  1200
FNEG FRn {:
nkeynes@359
  1201
    CHECKFPUEN();
nkeynes@359
  1202
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1203
	DR(FRn) = -DR(FRn);
nkeynes@359
  1204
    } else {
nkeynes@359
  1205
        FR(FRn) = -FR(FRn);
nkeynes@359
  1206
    }
nkeynes@359
  1207
:}
nkeynes@359
  1208
FABS FRn {:
nkeynes@359
  1209
    CHECKFPUEN();
nkeynes@359
  1210
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1211
	DR(FRn) = fabs(DR(FRn));
nkeynes@359
  1212
    } else {
nkeynes@359
  1213
        FR(FRn) = fabsf(FR(FRn));
nkeynes@359
  1214
    }
nkeynes@359
  1215
:}
nkeynes@359
  1216
FSQRT FRn {:
nkeynes@359
  1217
    CHECKFPUEN();
nkeynes@359
  1218
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1219
	DR(FRn) = sqrt(DR(FRn));
nkeynes@359
  1220
    } else {
nkeynes@359
  1221
        FR(FRn) = sqrtf(FR(FRn));
nkeynes@359
  1222
    }
nkeynes@359
  1223
:}
nkeynes@359
  1224
FLDI0 FRn {:
nkeynes@359
  1225
    CHECKFPUEN();
nkeynes@359
  1226
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1227
	DR(FRn) = 0.0;
nkeynes@359
  1228
    } else {
nkeynes@359
  1229
        FR(FRn) = 0.0;
nkeynes@359
  1230
    }
nkeynes@359
  1231
:}
nkeynes@359
  1232
FLDI1 FRn {:
nkeynes@359
  1233
    CHECKFPUEN();
nkeynes@359
  1234
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1235
	DR(FRn) = 1.0;
nkeynes@359
  1236
    } else {
nkeynes@359
  1237
        FR(FRn) = 1.0;
nkeynes@359
  1238
    }
nkeynes@359
  1239
:}
nkeynes@359
  1240
FMAC FR0, FRm, FRn {:
nkeynes@359
  1241
    CHECKFPUEN();
nkeynes@359
  1242
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1243
        DR(FRn) += DR(FRm)*DR(0);
nkeynes@359
  1244
    } else {
nkeynes@359
  1245
	FR(FRn) += FR(FRm)*FR(0);
nkeynes@359
  1246
    }
nkeynes@359
  1247
:}
nkeynes@374
  1248
FRCHG {: 
nkeynes@374
  1249
    CHECKFPUEN(); 
nkeynes@374
  1250
    sh4r.fpscr ^= FPSCR_FR; 
nkeynes@669
  1251
    sh4_switch_fr_banks();
nkeynes@374
  1252
:}
nkeynes@359
  1253
FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
nkeynes@359
  1254
FCNVSD FPUL, FRn {:
nkeynes@359
  1255
    CHECKFPUEN();
nkeynes@359
  1256
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1257
	DR(FRn) = (double)FPULf;
nkeynes@359
  1258
    }
nkeynes@359
  1259
:}
nkeynes@359
  1260
FCNVDS FRm, FPUL {:
nkeynes@359
  1261
    CHECKFPUEN();
nkeynes@359
  1262
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1263
	FPULf = (float)DR(FRm);
nkeynes@359
  1264
    }
nkeynes@359
  1265
:}
nkeynes@359
  1266
nkeynes@359
  1267
FSRRA FRn {:
nkeynes@359
  1268
    CHECKFPUEN();
nkeynes@359
  1269
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1270
	FR(FRn) = 1.0/sqrtf(FR(FRn));
nkeynes@359
  1271
    }
nkeynes@359
  1272
:}
nkeynes@359
  1273
FIPR FVm, FVn {:
nkeynes@359
  1274
    CHECKFPUEN();
nkeynes@359
  1275
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1276
        int tmp2 = FVn<<2;
nkeynes@359
  1277
        tmp = FVm<<2;
nkeynes@359
  1278
        FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@359
  1279
            FR(tmp+1)*FR(tmp2+1) +
nkeynes@359
  1280
            FR(tmp+2)*FR(tmp2+2) +
nkeynes@359
  1281
            FR(tmp+3)*FR(tmp2+3);
nkeynes@359
  1282
    }
nkeynes@359
  1283
:}
nkeynes@359
  1284
FSCA FPUL, FRn {:
nkeynes@359
  1285
    CHECKFPUEN();
nkeynes@359
  1286
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1287
	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
nkeynes@391
  1288
	/*
nkeynes@359
  1289
        float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
nkeynes@359
  1290
        FR(FRn) = sinf(angle);
nkeynes@359
  1291
        FR((FRn)+1) = cosf(angle);
nkeynes@391
  1292
	*/
nkeynes@359
  1293
    }
nkeynes@359
  1294
:}
nkeynes@359
  1295
FTRV XMTRX, FVn {:
nkeynes@359
  1296
    CHECKFPUEN();
nkeynes@359
  1297
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1298
	sh4_ftrv((float *)&(DRF(FVn<<1)) );
nkeynes@359
  1299
    }
nkeynes@359
  1300
:}
nkeynes@359
  1301
UNDEF {:
nkeynes@359
  1302
    UNDEF(ir);
nkeynes@359
  1303
:}
nkeynes@359
  1304
%%
nkeynes@359
  1305
    sh4r.pc = sh4r.new_pc;
nkeynes@359
  1306
    sh4r.new_pc += 2;
nkeynes@927
  1307
nkeynes@927
  1308
except:
nkeynes@359
  1309
    sh4r.in_delay_slot = 0;
nkeynes@359
  1310
    return TRUE;
nkeynes@359
  1311
}
.