nkeynes@359 | 1 | /**
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nkeynes@409 | 2 | * $Id: sh4x86.in,v 1.17 2007-09-29 05:33:02 nkeynes Exp $
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@368 | 28 | #include "sh4/sh4core.h"
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nkeynes@368 | 29 | #include "sh4/sh4trans.h"
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nkeynes@388 | 30 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 31 | #include "sh4/x86op.h"
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nkeynes@368 | 32 | #include "clock.h"
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nkeynes@368 | 33 |
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nkeynes@368 | 34 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 35 |
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nkeynes@368 | 36 | /**
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nkeynes@368 | 37 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 38 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 39 | * sh4_translate_end_block()
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nkeynes@368 | 40 | */
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nkeynes@368 | 41 | struct sh4_x86_state {
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nkeynes@368 | 42 | gboolean in_delay_slot;
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nkeynes@368 | 43 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 44 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 45 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 46 | uint32_t block_start_pc;
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nkeynes@368 | 47 |
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nkeynes@368 | 48 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@368 | 49 | uint32_t **backpatch_list;
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nkeynes@368 | 50 | uint32_t backpatch_posn;
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nkeynes@368 | 51 | uint32_t backpatch_size;
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nkeynes@368 | 52 | };
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nkeynes@368 | 53 |
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nkeynes@368 | 54 | #define EXIT_DATA_ADDR_READ 0
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nkeynes@368 | 55 | #define EXIT_DATA_ADDR_WRITE 7
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nkeynes@368 | 56 | #define EXIT_ILLEGAL 14
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nkeynes@368 | 57 | #define EXIT_SLOT_ILLEGAL 21
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nkeynes@368 | 58 | #define EXIT_FPU_DISABLED 28
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nkeynes@368 | 59 | #define EXIT_SLOT_FPU_DISABLED 35
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nkeynes@368 | 60 |
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nkeynes@368 | 61 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 62 |
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nkeynes@388 | 63 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 64 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 65 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 66 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 67 |
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nkeynes@368 | 68 | void sh4_x86_init()
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nkeynes@368 | 69 | {
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nkeynes@368 | 70 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@368 | 71 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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nkeynes@368 | 72 | }
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nkeynes@368 | 73 |
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nkeynes@368 | 74 |
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nkeynes@368 | 75 | static void sh4_x86_add_backpatch( uint8_t *ptr )
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nkeynes@368 | 76 | {
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nkeynes@368 | 77 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 78 | sh4_x86.backpatch_size <<= 1;
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nkeynes@368 | 79 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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nkeynes@368 | 80 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 81 | }
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nkeynes@368 | 82 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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nkeynes@368 | 83 | }
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nkeynes@368 | 84 |
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nkeynes@368 | 85 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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nkeynes@368 | 86 | {
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nkeynes@368 | 87 | unsigned int i;
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nkeynes@368 | 88 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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nkeynes@374 | 89 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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nkeynes@368 | 90 | }
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nkeynes@368 | 91 | }
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nkeynes@368 | 92 |
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nkeynes@359 | 93 | /**
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nkeynes@359 | 94 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 95 | */
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nkeynes@359 | 96 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 97 | {
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nkeynes@359 | 98 | /* mov [bp+n], reg */
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nkeynes@361 | 99 | OP(0x8B);
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nkeynes@361 | 100 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 101 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 102 | }
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nkeynes@359 | 103 |
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nkeynes@374 | 104 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 105 | {
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nkeynes@374 | 106 | OP(0x0F);
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nkeynes@374 | 107 | OP(0xBF);
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nkeynes@374 | 108 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 109 | }
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nkeynes@368 | 110 |
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nkeynes@374 | 111 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 112 | {
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nkeynes@374 | 113 | OP(0x0F);
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nkeynes@374 | 114 | OP(0xB7);
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nkeynes@374 | 115 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 116 |
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nkeynes@368 | 117 | }
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nkeynes@368 | 118 |
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nkeynes@380 | 119 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 120 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 121 | /**
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nkeynes@359 | 122 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 123 | */
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nkeynes@359 | 124 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 125 | /* mov #value, reg */
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nkeynes@359 | 126 | OP(0xB8 + x86reg);
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nkeynes@359 | 127 | OP32(value);
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nkeynes@359 | 128 | }
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nkeynes@359 | 129 |
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nkeynes@359 | 130 | /**
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nkeynes@359 | 131 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 132 | */
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nkeynes@359 | 133 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 134 | /* mov reg, [bp+n] */
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nkeynes@361 | 135 | OP(0x89);
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nkeynes@361 | 136 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 137 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 138 | }
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nkeynes@374 | 139 |
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nkeynes@374 | 140 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 141 |
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nkeynes@375 | 142 | /**
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nkeynes@375 | 143 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 144 | * register (eg for register-to-register moves)
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nkeynes@375 | 145 | */
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nkeynes@375 | 146 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 147 | {
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nkeynes@375 | 148 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 149 | }
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nkeynes@375 | 150 |
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nkeynes@375 | 151 | /**
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nkeynes@375 | 152 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 153 | * register (eg for register-to-register moves)
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nkeynes@375 | 154 | */
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nkeynes@375 | 155 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 156 | {
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nkeynes@375 | 157 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 158 | }
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nkeynes@375 | 159 |
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nkeynes@375 | 160 |
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nkeynes@375 | 161 | /**
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nkeynes@375 | 162 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 163 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 164 | * NB: 12 bytes
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nkeynes@375 | 165 | */
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nkeynes@374 | 166 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 167 | {
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nkeynes@386 | 168 | NOT_r32( bankreg );
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nkeynes@374 | 169 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 170 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 171 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 172 | }
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nkeynes@374 | 173 |
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nkeynes@375 | 174 | /**
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nkeynes@386 | 175 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 176 | */
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nkeynes@386 | 177 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 178 | {
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nkeynes@386 | 179 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 180 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 181 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 182 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 183 | }
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nkeynes@386 | 184 | /**
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nkeynes@377 | 185 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 186 | */
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nkeynes@377 | 187 | static inline void push_fpul( )
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nkeynes@377 | 188 | {
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nkeynes@377 | 189 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 190 | }
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nkeynes@377 | 191 |
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nkeynes@377 | 192 | /**
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nkeynes@377 | 193 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 194 | */
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nkeynes@377 | 195 | static inline void pop_fpul( )
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nkeynes@377 | 196 | {
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nkeynes@377 | 197 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 198 | }
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nkeynes@377 | 199 |
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nkeynes@377 | 200 | /**
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nkeynes@375 | 201 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 202 | * with the location of the current fp bank.
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nkeynes@375 | 203 | */
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nkeynes@374 | 204 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 205 | {
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nkeynes@374 | 206 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 207 | }
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nkeynes@374 | 208 |
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nkeynes@375 | 209 | /**
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nkeynes@375 | 210 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 211 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 212 | */
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nkeynes@374 | 213 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 214 | {
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nkeynes@374 | 215 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 216 | }
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nkeynes@374 | 217 |
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nkeynes@375 | 218 | /**
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nkeynes@375 | 219 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 220 | * with the location of the current fp bank.
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nkeynes@375 | 221 | */
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nkeynes@374 | 222 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 223 | {
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nkeynes@375 | 224 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 225 | }
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nkeynes@374 | 226 |
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nkeynes@374 | 227 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 228 | {
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nkeynes@375 | 229 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 230 | }
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nkeynes@374 | 231 |
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nkeynes@361 | 232 | /**
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nkeynes@361 | 233 | * Note: clobbers EAX to make the indirect call - this isn't usually
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nkeynes@361 | 234 | * a problem since the callee will usually clobber it anyway.
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nkeynes@361 | 235 | */
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nkeynes@361 | 236 | static inline void call_func0( void *ptr )
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nkeynes@361 | 237 | {
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nkeynes@361 | 238 | load_imm32(R_EAX, (uint32_t)ptr);
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nkeynes@368 | 239 | CALL_r32(R_EAX);
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nkeynes@361 | 240 | }
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nkeynes@361 | 241 |
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nkeynes@361 | 242 | static inline void call_func1( void *ptr, int arg1 )
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nkeynes@361 | 243 | {
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nkeynes@361 | 244 | PUSH_r32(arg1);
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nkeynes@361 | 245 | call_func0(ptr);
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nkeynes@377 | 246 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@361 | 247 | }
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nkeynes@361 | 248 |
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nkeynes@361 | 249 | static inline void call_func2( void *ptr, int arg1, int arg2 )
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nkeynes@361 | 250 | {
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nkeynes@361 | 251 | PUSH_r32(arg2);
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nkeynes@361 | 252 | PUSH_r32(arg1);
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nkeynes@361 | 253 | call_func0(ptr);
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nkeynes@377 | 254 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 255 | }
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nkeynes@375 | 256 |
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nkeynes@375 | 257 | /**
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nkeynes@375 | 258 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
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nkeynes@375 | 259 | * the second in arg2b
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nkeynes@375 | 260 | * NB: 30 bytes
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nkeynes@375 | 261 | */
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nkeynes@375 | 262 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 263 | {
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nkeynes@375 | 264 | ADD_imm8s_r32( 4, addr );
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nkeynes@386 | 265 | PUSH_r32(arg2b);
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nkeynes@375 | 266 | PUSH_r32(addr);
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nkeynes@375 | 267 | ADD_imm8s_r32( -4, addr );
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nkeynes@386 | 268 | PUSH_r32(arg2a);
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nkeynes@375 | 269 | PUSH_r32(addr);
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nkeynes@375 | 270 | call_func0(sh4_write_long);
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nkeynes@377 | 271 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 272 | call_func0(sh4_write_long);
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nkeynes@377 | 273 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 274 | }
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nkeynes@375 | 275 |
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nkeynes@375 | 276 | /**
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nkeynes@375 | 277 | * Read a double (64-bit) value from memory, writing the first word into arg2a
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nkeynes@375 | 278 | * and the second into arg2b. The addr must not be in EAX
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nkeynes@375 | 279 | * NB: 27 bytes
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nkeynes@375 | 280 | */
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nkeynes@375 | 281 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 282 | {
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nkeynes@375 | 283 | PUSH_r32(addr);
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nkeynes@375 | 284 | call_func0(sh4_read_long);
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nkeynes@375 | 285 | POP_r32(addr);
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nkeynes@375 | 286 | PUSH_r32(R_EAX);
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nkeynes@375 | 287 | ADD_imm8s_r32( 4, addr );
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nkeynes@375 | 288 | PUSH_r32(addr);
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nkeynes@375 | 289 | call_func0(sh4_read_long);
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nkeynes@377 | 290 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@375 | 291 | MOV_r32_r32( R_EAX, arg2b );
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nkeynes@375 | 292 | POP_r32(arg2a);
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nkeynes@361 | 293 | }
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nkeynes@361 | 294 |
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nkeynes@368 | 295 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@368 | 296 | static void check_priv( )
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nkeynes@368 | 297 | {
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nkeynes@368 | 298 | if( !sh4_x86.priv_checked ) {
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nkeynes@368 | 299 | sh4_x86.priv_checked = TRUE;
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nkeynes@368 | 300 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 301 | AND_imm32_r32( SR_MD, R_EAX );
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nkeynes@368 | 302 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 303 | JE_exit( EXIT_SLOT_ILLEGAL );
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nkeynes@368 | 304 | } else {
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nkeynes@368 | 305 | JE_exit( EXIT_ILLEGAL );
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nkeynes@368 | 306 | }
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nkeynes@368 | 307 | }
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nkeynes@368 | 308 | }
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nkeynes@368 | 309 |
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nkeynes@368 | 310 | static void check_fpuen( )
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nkeynes@368 | 311 | {
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nkeynes@368 | 312 | if( !sh4_x86.fpuen_checked ) {
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nkeynes@368 | 313 | sh4_x86.fpuen_checked = TRUE;
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nkeynes@368 | 314 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 315 | AND_imm32_r32( SR_FD, R_EAX );
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nkeynes@368 | 316 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 317 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
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nkeynes@368 | 318 | } else {
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nkeynes@368 | 319 | JNE_exit(EXIT_FPU_DISABLED);
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nkeynes@368 | 320 | }
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nkeynes@368 | 321 | }
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nkeynes@368 | 322 | }
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nkeynes@368 | 323 |
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nkeynes@368 | 324 | static void check_ralign16( int x86reg )
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nkeynes@368 | 325 | {
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nkeynes@368 | 326 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 327 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 328 | }
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nkeynes@368 | 329 |
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nkeynes@368 | 330 | static void check_walign16( int x86reg )
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nkeynes@368 | 331 | {
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nkeynes@368 | 332 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 333 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 334 | }
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nkeynes@368 | 335 |
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nkeynes@368 | 336 | static void check_ralign32( int x86reg )
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nkeynes@368 | 337 | {
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nkeynes@368 | 338 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 339 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 340 | }
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nkeynes@368 | 341 | static void check_walign32( int x86reg )
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nkeynes@368 | 342 | {
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nkeynes@368 | 343 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 344 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 345 | }
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nkeynes@368 | 346 |
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nkeynes@361 | 347 | #define UNDEF()
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nkeynes@361 | 348 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 349 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 350 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 351 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 352 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 353 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 354 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 355 |
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nkeynes@386 | 356 | #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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nkeynes@368 | 357 |
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nkeynes@368 | 358 |
|
nkeynes@359 | 359 |
|
nkeynes@359 | 360 | /**
|
nkeynes@359 | 361 | * Emit the 'start of block' assembly. Sets up the stack frame and save
|
nkeynes@359 | 362 | * SI/DI as required
|
nkeynes@359 | 363 | */
|
nkeynes@408 | 364 | void sh4_translate_begin_block( sh4addr_t pc )
|
nkeynes@368 | 365 | {
|
nkeynes@368 | 366 | PUSH_r32(R_EBP);
|
nkeynes@359 | 367 | /* mov &sh4r, ebp */
|
nkeynes@359 | 368 | load_imm32( R_EBP, (uint32_t)&sh4r );
|
nkeynes@368 | 369 | PUSH_r32(R_ESI);
|
nkeynes@380 | 370 | XOR_r32_r32(R_ESI, R_ESI);
|
nkeynes@368 | 371 |
|
nkeynes@368 | 372 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@368 | 373 | sh4_x86.priv_checked = FALSE;
|
nkeynes@368 | 374 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@409 | 375 | sh4_x86.branch_taken = FALSE;
|
nkeynes@368 | 376 | sh4_x86.backpatch_posn = 0;
|
nkeynes@408 | 377 | sh4_x86.block_start_pc = pc;
|
nkeynes@368 | 378 | }
|
nkeynes@359 | 379 |
|
nkeynes@368 | 380 | /**
|
nkeynes@408 | 381 | * Exit the block to an absolute PC
|
nkeynes@408 | 382 | * Bytes: 30
|
nkeynes@368 | 383 | */
|
nkeynes@408 | 384 | void exit_block( sh4addr_t pc, sh4addr_t endpc )
|
nkeynes@368 | 385 | {
|
nkeynes@408 | 386 | load_imm32( R_ECX, pc ); // 5
|
nkeynes@408 | 387 | store_spreg( R_ECX, REG_OFFSET(pc) ); // 3
|
nkeynes@408 | 388 | MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
|
nkeynes@408 | 389 | AND_imm8s_r32( 0xFC, R_EAX ); // 3
|
nkeynes@408 | 390 | load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@408 | 391 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@374 | 392 | POP_r32(R_ESI);
|
nkeynes@374 | 393 | POP_r32(R_EBP);
|
nkeynes@368 | 394 | RET();
|
nkeynes@359 | 395 | }
|
nkeynes@359 | 396 |
|
nkeynes@359 | 397 | /**
|
nkeynes@408 | 398 | * Exit the block with sh4r.pc already written
|
nkeynes@408 | 399 | * Bytes: 16
|
nkeynes@408 | 400 | */
|
nkeynes@408 | 401 | void exit_block_pcset( pc )
|
nkeynes@408 | 402 | {
|
nkeynes@408 | 403 | XOR_r32_r32( R_EAX, R_EAX ); // 2
|
nkeynes@408 | 404 | load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@408 | 405 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@408 | 406 | POP_r32(R_ESI);
|
nkeynes@408 | 407 | POP_r32(R_EBP);
|
nkeynes@408 | 408 | RET();
|
nkeynes@408 | 409 | }
|
nkeynes@408 | 410 |
|
nkeynes@408 | 411 | /**
|
nkeynes@408 | 412 | * Write the block trailer (exception handling block)
|
nkeynes@359 | 413 | */
|
nkeynes@359 | 414 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@409 | 415 | if( sh4_x86.branch_taken == FALSE ) {
|
nkeynes@409 | 416 | // Didn't exit unconditionally already, so write the termination here
|
nkeynes@409 | 417 | exit_block( pc, pc );
|
nkeynes@409 | 418 | }
|
nkeynes@388 | 419 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@388 | 420 | uint8_t *end_ptr = xlat_output;
|
nkeynes@388 | 421 | // Exception termination. Jump block for various exception codes:
|
nkeynes@388 | 422 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@388 | 423 | JMP_rel8( 33, target1 );
|
nkeynes@388 | 424 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@388 | 425 | JMP_rel8( 26, target2 );
|
nkeynes@388 | 426 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@388 | 427 | JMP_rel8( 19, target3 );
|
nkeynes@388 | 428 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@388 | 429 | JMP_rel8( 12, target4 );
|
nkeynes@388 | 430 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@388 | 431 | JMP_rel8( 5, target5 );
|
nkeynes@388 | 432 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@388 | 433 | // target
|
nkeynes@388 | 434 | JMP_TARGET(target1);
|
nkeynes@388 | 435 | JMP_TARGET(target2);
|
nkeynes@388 | 436 | JMP_TARGET(target3);
|
nkeynes@388 | 437 | JMP_TARGET(target4);
|
nkeynes@388 | 438 | JMP_TARGET(target5);
|
nkeynes@388 | 439 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 440 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 441 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 442 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 443 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@388 | 444 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 445 | MUL_r32( R_ESI );
|
nkeynes@388 | 446 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@388 | 447 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 448 |
|
nkeynes@388 | 449 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
|
nkeynes@388 | 450 | CALL_r32( R_EAX ); // 2
|
nkeynes@388 | 451 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@408 | 452 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@388 | 453 | POP_r32(R_ESI);
|
nkeynes@388 | 454 | POP_r32(R_EBP);
|
nkeynes@388 | 455 | RET();
|
nkeynes@368 | 456 |
|
nkeynes@388 | 457 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@388 | 458 | }
|
nkeynes@368 | 459 |
|
nkeynes@359 | 460 | }
|
nkeynes@359 | 461 |
|
nkeynes@388 | 462 |
|
nkeynes@388 | 463 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 464 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 465 |
|
nkeynes@359 | 466 | /**
|
nkeynes@359 | 467 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 468 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 469 | *
|
nkeynes@359 | 470 | *
|
nkeynes@359 | 471 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 472 | * (eg a branch or
|
nkeynes@359 | 473 | */
|
nkeynes@408 | 474 | uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
|
nkeynes@359 | 475 | {
|
nkeynes@388 | 476 | uint32_t ir;
|
nkeynes@388 | 477 | /* Read instruction */
|
nkeynes@388 | 478 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 479 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 480 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 481 | } else {
|
nkeynes@388 | 482 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@388 | 483 | if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 484 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 485 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 486 | */
|
nkeynes@388 | 487 | sh4_icache = NULL;
|
nkeynes@388 | 488 | ir = sh4_read_word(pc);
|
nkeynes@388 | 489 | } else {
|
nkeynes@388 | 490 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 491 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 492 | }
|
nkeynes@388 | 493 | }
|
nkeynes@388 | 494 |
|
nkeynes@359 | 495 | %%
|
nkeynes@359 | 496 | /* ALU operations */
|
nkeynes@359 | 497 | ADD Rm, Rn {:
|
nkeynes@359 | 498 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 499 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 500 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 501 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 502 | :}
|
nkeynes@359 | 503 | ADD #imm, Rn {:
|
nkeynes@359 | 504 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 505 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 506 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 507 | :}
|
nkeynes@359 | 508 | ADDC Rm, Rn {:
|
nkeynes@359 | 509 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 510 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 511 | LDC_t();
|
nkeynes@359 | 512 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 513 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 514 | SETC_t();
|
nkeynes@359 | 515 | :}
|
nkeynes@359 | 516 | ADDV Rm, Rn {:
|
nkeynes@359 | 517 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 518 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 519 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 520 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 521 | SETO_t();
|
nkeynes@359 | 522 | :}
|
nkeynes@359 | 523 | AND Rm, Rn {:
|
nkeynes@359 | 524 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 525 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 526 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 527 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 528 | :}
|
nkeynes@359 | 529 | AND #imm, R0 {:
|
nkeynes@359 | 530 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 531 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 532 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 533 | :}
|
nkeynes@359 | 534 | AND.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 535 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 536 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 537 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 538 | PUSH_r32(R_ECX);
|
nkeynes@386 | 539 | call_func0(sh4_read_byte);
|
nkeynes@386 | 540 | POP_r32(R_ECX);
|
nkeynes@386 | 541 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 542 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 543 | :}
|
nkeynes@359 | 544 | CMP/EQ Rm, Rn {:
|
nkeynes@359 | 545 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 546 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 547 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 548 | SETE_t();
|
nkeynes@359 | 549 | :}
|
nkeynes@359 | 550 | CMP/EQ #imm, R0 {:
|
nkeynes@359 | 551 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 552 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 553 | SETE_t();
|
nkeynes@359 | 554 | :}
|
nkeynes@359 | 555 | CMP/GE Rm, Rn {:
|
nkeynes@359 | 556 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 557 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 558 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 559 | SETGE_t();
|
nkeynes@359 | 560 | :}
|
nkeynes@359 | 561 | CMP/GT Rm, Rn {:
|
nkeynes@359 | 562 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 563 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 564 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 565 | SETG_t();
|
nkeynes@359 | 566 | :}
|
nkeynes@359 | 567 | CMP/HI Rm, Rn {:
|
nkeynes@359 | 568 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 569 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 570 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 571 | SETA_t();
|
nkeynes@359 | 572 | :}
|
nkeynes@359 | 573 | CMP/HS Rm, Rn {:
|
nkeynes@359 | 574 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 575 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 576 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 577 | SETAE_t();
|
nkeynes@359 | 578 | :}
|
nkeynes@359 | 579 | CMP/PL Rn {:
|
nkeynes@359 | 580 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 581 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 582 | SETG_t();
|
nkeynes@359 | 583 | :}
|
nkeynes@359 | 584 | CMP/PZ Rn {:
|
nkeynes@359 | 585 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 586 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 587 | SETGE_t();
|
nkeynes@359 | 588 | :}
|
nkeynes@361 | 589 | CMP/STR Rm, Rn {:
|
nkeynes@368 | 590 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 591 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 592 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 593 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 594 | JE_rel8(13, target1);
|
nkeynes@368 | 595 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 596 | JE_rel8(9, target2);
|
nkeynes@368 | 597 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 598 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 599 | JE_rel8(2, target3);
|
nkeynes@368 | 600 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 601 | JMP_TARGET(target1);
|
nkeynes@380 | 602 | JMP_TARGET(target2);
|
nkeynes@380 | 603 | JMP_TARGET(target3);
|
nkeynes@368 | 604 | SETE_t();
|
nkeynes@361 | 605 | :}
|
nkeynes@361 | 606 | DIV0S Rm, Rn {:
|
nkeynes@361 | 607 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 608 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 609 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 610 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 611 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 612 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 613 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 614 | SETNE_t();
|
nkeynes@361 | 615 | :}
|
nkeynes@361 | 616 | DIV0U {:
|
nkeynes@361 | 617 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 618 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 619 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 620 | store_spreg( R_EAX, R_T );
|
nkeynes@361 | 621 | :}
|
nkeynes@386 | 622 | DIV1 Rm, Rn {:
|
nkeynes@386 | 623 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 624 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 625 | LDC_t();
|
nkeynes@386 | 626 | RCL1_r32( R_EAX );
|
nkeynes@386 | 627 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 628 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 629 | JE_rel8(5, mqequal);
|
nkeynes@386 | 630 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 631 | JMP_rel8(3, end);
|
nkeynes@380 | 632 | JMP_TARGET(mqequal);
|
nkeynes@386 | 633 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 634 | JMP_TARGET(end);
|
nkeynes@386 | 635 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 636 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 637 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 638 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 639 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 640 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 641 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 642 | store_spreg( R_EAX, R_T );
|
nkeynes@374 | 643 | :}
|
nkeynes@361 | 644 | DMULS.L Rm, Rn {:
|
nkeynes@361 | 645 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 646 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 647 | IMUL_r32(R_ECX);
|
nkeynes@361 | 648 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 649 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 650 | :}
|
nkeynes@361 | 651 | DMULU.L Rm, Rn {:
|
nkeynes@361 | 652 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 653 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 654 | MUL_r32(R_ECX);
|
nkeynes@361 | 655 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 656 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 657 | :}
|
nkeynes@359 | 658 | DT Rn {:
|
nkeynes@359 | 659 | load_reg( R_EAX, Rn );
|
nkeynes@382 | 660 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 661 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 662 | SETE_t();
|
nkeynes@359 | 663 | :}
|
nkeynes@359 | 664 | EXTS.B Rm, Rn {:
|
nkeynes@359 | 665 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 666 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 667 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 668 | :}
|
nkeynes@361 | 669 | EXTS.W Rm, Rn {:
|
nkeynes@361 | 670 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 671 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 672 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 673 | :}
|
nkeynes@361 | 674 | EXTU.B Rm, Rn {:
|
nkeynes@361 | 675 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 676 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 677 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 678 | :}
|
nkeynes@361 | 679 | EXTU.W Rm, Rn {:
|
nkeynes@361 | 680 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 681 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 682 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 683 | :}
|
nkeynes@386 | 684 | MAC.L @Rm+, @Rn+ {:
|
nkeynes@386 | 685 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 686 | check_ralign32( R_ECX );
|
nkeynes@386 | 687 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 688 | check_ralign32( R_ECX );
|
nkeynes@386 | 689 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 690 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 691 | PUSH_r32( R_EAX );
|
nkeynes@386 | 692 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 693 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 694 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 695 | POP_r32( R_ECX );
|
nkeynes@386 | 696 | IMUL_r32( R_ECX );
|
nkeynes@386 | 697 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 698 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 699 |
|
nkeynes@386 | 700 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 701 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@386 | 702 | JE_rel8( 7, nosat );
|
nkeynes@386 | 703 | call_func0( signsat48 );
|
nkeynes@386 | 704 | JMP_TARGET( nosat );
|
nkeynes@386 | 705 | :}
|
nkeynes@386 | 706 | MAC.W @Rm+, @Rn+ {:
|
nkeynes@386 | 707 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 708 | check_ralign16( R_ECX );
|
nkeynes@386 | 709 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 710 | check_ralign16( R_ECX );
|
nkeynes@386 | 711 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 712 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 713 | PUSH_r32( R_EAX );
|
nkeynes@386 | 714 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 715 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 716 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 717 | POP_r32( R_ECX );
|
nkeynes@386 | 718 | IMUL_r32( R_ECX );
|
nkeynes@386 | 719 |
|
nkeynes@386 | 720 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 721 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 722 | JE_rel8( 47, nosat );
|
nkeynes@386 | 723 |
|
nkeynes@386 | 724 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 725 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 726 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 727 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 728 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 729 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 730 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 731 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 732 |
|
nkeynes@386 | 733 | JMP_TARGET(positive);
|
nkeynes@386 | 734 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 735 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 736 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 737 |
|
nkeynes@386 | 738 | JMP_TARGET(nosat);
|
nkeynes@386 | 739 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 740 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 741 | JMP_TARGET(end);
|
nkeynes@386 | 742 | JMP_TARGET(end2);
|
nkeynes@386 | 743 | JMP_TARGET(end3);
|
nkeynes@386 | 744 | :}
|
nkeynes@359 | 745 | MOVT Rn {:
|
nkeynes@359 | 746 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 747 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 748 | :}
|
nkeynes@361 | 749 | MUL.L Rm, Rn {:
|
nkeynes@361 | 750 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 751 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 752 | MUL_r32( R_ECX );
|
nkeynes@361 | 753 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 754 | :}
|
nkeynes@374 | 755 | MULS.W Rm, Rn {:
|
nkeynes@374 | 756 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 757 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 758 | MUL_r32( R_ECX );
|
nkeynes@374 | 759 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 760 | :}
|
nkeynes@374 | 761 | MULU.W Rm, Rn {:
|
nkeynes@374 | 762 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 763 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 764 | MUL_r32( R_ECX );
|
nkeynes@374 | 765 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 766 | :}
|
nkeynes@359 | 767 | NEG Rm, Rn {:
|
nkeynes@359 | 768 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 769 | NEG_r32( R_EAX );
|
nkeynes@359 | 770 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 771 | :}
|
nkeynes@359 | 772 | NEGC Rm, Rn {:
|
nkeynes@359 | 773 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 774 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 775 | LDC_t();
|
nkeynes@359 | 776 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 777 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 778 | SETC_t();
|
nkeynes@359 | 779 | :}
|
nkeynes@359 | 780 | NOT Rm, Rn {:
|
nkeynes@359 | 781 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 782 | NOT_r32( R_EAX );
|
nkeynes@359 | 783 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 784 | :}
|
nkeynes@359 | 785 | OR Rm, Rn {:
|
nkeynes@359 | 786 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 787 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 788 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 789 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 790 | :}
|
nkeynes@359 | 791 | OR #imm, R0 {:
|
nkeynes@359 | 792 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 793 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 794 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 795 | :}
|
nkeynes@374 | 796 | OR.B #imm, @(R0, GBR) {:
|
nkeynes@374 | 797 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 798 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 799 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 800 | PUSH_r32(R_ECX);
|
nkeynes@386 | 801 | call_func0(sh4_read_byte);
|
nkeynes@386 | 802 | POP_r32(R_ECX);
|
nkeynes@386 | 803 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 804 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@374 | 805 | :}
|
nkeynes@359 | 806 | ROTCL Rn {:
|
nkeynes@359 | 807 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 808 | LDC_t();
|
nkeynes@359 | 809 | RCL1_r32( R_EAX );
|
nkeynes@359 | 810 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 811 | SETC_t();
|
nkeynes@359 | 812 | :}
|
nkeynes@359 | 813 | ROTCR Rn {:
|
nkeynes@359 | 814 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 815 | LDC_t();
|
nkeynes@359 | 816 | RCR1_r32( R_EAX );
|
nkeynes@359 | 817 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 818 | SETC_t();
|
nkeynes@359 | 819 | :}
|
nkeynes@359 | 820 | ROTL Rn {:
|
nkeynes@359 | 821 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 822 | ROL1_r32( R_EAX );
|
nkeynes@359 | 823 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 824 | SETC_t();
|
nkeynes@359 | 825 | :}
|
nkeynes@359 | 826 | ROTR Rn {:
|
nkeynes@359 | 827 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 828 | ROR1_r32( R_EAX );
|
nkeynes@359 | 829 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 830 | SETC_t();
|
nkeynes@359 | 831 | :}
|
nkeynes@359 | 832 | SHAD Rm, Rn {:
|
nkeynes@359 | 833 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 834 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 835 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 836 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 837 | JGE_rel8(16, doshl);
|
nkeynes@361 | 838 |
|
nkeynes@361 | 839 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 840 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 841 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 842 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 843 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 844 |
|
nkeynes@386 | 845 | JMP_TARGET(emptysar);
|
nkeynes@386 | 846 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 847 | JMP_rel8(5, end2);
|
nkeynes@382 | 848 |
|
nkeynes@380 | 849 | JMP_TARGET(doshl);
|
nkeynes@361 | 850 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 851 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 852 | JMP_TARGET(end);
|
nkeynes@386 | 853 | JMP_TARGET(end2);
|
nkeynes@361 | 854 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 855 | :}
|
nkeynes@359 | 856 | SHLD Rm, Rn {:
|
nkeynes@368 | 857 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 858 | load_reg( R_ECX, Rm );
|
nkeynes@382 | 859 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 860 | JGE_rel8(15, doshl);
|
nkeynes@368 | 861 |
|
nkeynes@382 | 862 | NEG_r32( R_ECX ); // 2
|
nkeynes@382 | 863 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 864 | JE_rel8( 4, emptyshr );
|
nkeynes@382 | 865 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 866 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 867 |
|
nkeynes@386 | 868 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 869 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 870 | JMP_rel8(5, end2);
|
nkeynes@382 | 871 |
|
nkeynes@382 | 872 | JMP_TARGET(doshl);
|
nkeynes@382 | 873 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@382 | 874 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@382 | 875 | JMP_TARGET(end);
|
nkeynes@386 | 876 | JMP_TARGET(end2);
|
nkeynes@368 | 877 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 878 | :}
|
nkeynes@359 | 879 | SHAL Rn {:
|
nkeynes@359 | 880 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 881 | SHL1_r32( R_EAX );
|
nkeynes@397 | 882 | SETC_t();
|
nkeynes@359 | 883 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 884 | :}
|
nkeynes@359 | 885 | SHAR Rn {:
|
nkeynes@359 | 886 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 887 | SAR1_r32( R_EAX );
|
nkeynes@397 | 888 | SETC_t();
|
nkeynes@359 | 889 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 890 | :}
|
nkeynes@359 | 891 | SHLL Rn {:
|
nkeynes@359 | 892 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 893 | SHL1_r32( R_EAX );
|
nkeynes@397 | 894 | SETC_t();
|
nkeynes@359 | 895 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 896 | :}
|
nkeynes@359 | 897 | SHLL2 Rn {:
|
nkeynes@359 | 898 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 899 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 900 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 901 | :}
|
nkeynes@359 | 902 | SHLL8 Rn {:
|
nkeynes@359 | 903 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 904 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 905 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 906 | :}
|
nkeynes@359 | 907 | SHLL16 Rn {:
|
nkeynes@359 | 908 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 909 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 910 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 911 | :}
|
nkeynes@359 | 912 | SHLR Rn {:
|
nkeynes@359 | 913 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 914 | SHR1_r32( R_EAX );
|
nkeynes@397 | 915 | SETC_t();
|
nkeynes@359 | 916 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 917 | :}
|
nkeynes@359 | 918 | SHLR2 Rn {:
|
nkeynes@359 | 919 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 920 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 921 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 922 | :}
|
nkeynes@359 | 923 | SHLR8 Rn {:
|
nkeynes@359 | 924 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 925 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 926 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 927 | :}
|
nkeynes@359 | 928 | SHLR16 Rn {:
|
nkeynes@359 | 929 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 930 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 931 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 932 | :}
|
nkeynes@359 | 933 | SUB Rm, Rn {:
|
nkeynes@359 | 934 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 935 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 936 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 937 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 938 | :}
|
nkeynes@359 | 939 | SUBC Rm, Rn {:
|
nkeynes@359 | 940 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 941 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 942 | LDC_t();
|
nkeynes@359 | 943 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 944 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 945 | SETC_t();
|
nkeynes@359 | 946 | :}
|
nkeynes@359 | 947 | SUBV Rm, Rn {:
|
nkeynes@359 | 948 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 949 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 950 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 951 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 952 | SETO_t();
|
nkeynes@359 | 953 | :}
|
nkeynes@359 | 954 | SWAP.B Rm, Rn {:
|
nkeynes@359 | 955 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 956 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 957 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 958 | :}
|
nkeynes@359 | 959 | SWAP.W Rm, Rn {:
|
nkeynes@359 | 960 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 961 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 962 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 963 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 964 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 965 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 966 | :}
|
nkeynes@361 | 967 | TAS.B @Rn {:
|
nkeynes@361 | 968 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 969 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 970 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 971 | SETE_t();
|
nkeynes@361 | 972 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 973 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 974 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 975 | :}
|
nkeynes@361 | 976 | TST Rm, Rn {:
|
nkeynes@361 | 977 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 978 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 979 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 980 | SETE_t();
|
nkeynes@361 | 981 | :}
|
nkeynes@368 | 982 | TST #imm, R0 {:
|
nkeynes@368 | 983 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 984 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 985 | SETE_t();
|
nkeynes@368 | 986 | :}
|
nkeynes@368 | 987 | TST.B #imm, @(R0, GBR) {:
|
nkeynes@368 | 988 | load_reg( R_EAX, 0);
|
nkeynes@368 | 989 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 990 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 991 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 992 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 993 | SETE_t();
|
nkeynes@368 | 994 | :}
|
nkeynes@359 | 995 | XOR Rm, Rn {:
|
nkeynes@359 | 996 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 997 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 998 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 999 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1000 | :}
|
nkeynes@359 | 1001 | XOR #imm, R0 {:
|
nkeynes@359 | 1002 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1003 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1004 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 1005 | :}
|
nkeynes@359 | 1006 | XOR.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 1007 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1008 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1009 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1010 | PUSH_r32(R_ECX);
|
nkeynes@386 | 1011 | call_func0(sh4_read_byte);
|
nkeynes@386 | 1012 | POP_r32(R_ECX);
|
nkeynes@359 | 1013 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1014 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1015 | :}
|
nkeynes@361 | 1016 | XTRCT Rm, Rn {:
|
nkeynes@361 | 1017 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1018 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1019 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1020 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1021 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1022 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1023 | :}
|
nkeynes@359 | 1024 |
|
nkeynes@359 | 1025 | /* Data move instructions */
|
nkeynes@359 | 1026 | MOV Rm, Rn {:
|
nkeynes@359 | 1027 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1028 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1029 | :}
|
nkeynes@359 | 1030 | MOV #imm, Rn {:
|
nkeynes@359 | 1031 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 1032 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1033 | :}
|
nkeynes@359 | 1034 | MOV.B Rm, @Rn {:
|
nkeynes@359 | 1035 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1036 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1037 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1038 | :}
|
nkeynes@359 | 1039 | MOV.B Rm, @-Rn {:
|
nkeynes@359 | 1040 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1041 | load_reg( R_ECX, Rn );
|
nkeynes@382 | 1042 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 1043 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1044 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1045 | :}
|
nkeynes@359 | 1046 | MOV.B Rm, @(R0, Rn) {:
|
nkeynes@359 | 1047 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1048 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1049 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1050 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1051 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1052 | :}
|
nkeynes@359 | 1053 | MOV.B R0, @(disp, GBR) {:
|
nkeynes@359 | 1054 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1055 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1056 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1057 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1058 | :}
|
nkeynes@359 | 1059 | MOV.B R0, @(disp, Rn) {:
|
nkeynes@359 | 1060 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1061 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1062 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1063 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1064 | :}
|
nkeynes@359 | 1065 | MOV.B @Rm, Rn {:
|
nkeynes@359 | 1066 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1067 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 1068 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1069 | :}
|
nkeynes@359 | 1070 | MOV.B @Rm+, Rn {:
|
nkeynes@359 | 1071 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1072 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 1073 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 1074 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1075 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1076 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1077 | :}
|
nkeynes@359 | 1078 | MOV.B @(R0, Rm), Rn {:
|
nkeynes@359 | 1079 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1080 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1081 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1082 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1083 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1084 | :}
|
nkeynes@359 | 1085 | MOV.B @(disp, GBR), R0 {:
|
nkeynes@359 | 1086 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1087 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1088 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1089 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 1090 | :}
|
nkeynes@359 | 1091 | MOV.B @(disp, Rm), R0 {:
|
nkeynes@359 | 1092 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1093 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1094 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1095 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 1096 | :}
|
nkeynes@374 | 1097 | MOV.L Rm, @Rn {:
|
nkeynes@361 | 1098 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1099 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1100 | check_walign32(R_ECX);
|
nkeynes@361 | 1101 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1102 | :}
|
nkeynes@361 | 1103 | MOV.L Rm, @-Rn {:
|
nkeynes@361 | 1104 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1105 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1106 | check_walign32( R_ECX );
|
nkeynes@361 | 1107 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 1108 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1109 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1110 | :}
|
nkeynes@361 | 1111 | MOV.L Rm, @(R0, Rn) {:
|
nkeynes@361 | 1112 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1113 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1114 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1115 | check_walign32( R_ECX );
|
nkeynes@361 | 1116 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1117 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1118 | :}
|
nkeynes@361 | 1119 | MOV.L R0, @(disp, GBR) {:
|
nkeynes@361 | 1120 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1121 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1122 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1123 | check_walign32( R_ECX );
|
nkeynes@361 | 1124 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1125 | :}
|
nkeynes@361 | 1126 | MOV.L Rm, @(disp, Rn) {:
|
nkeynes@361 | 1127 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1128 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1129 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1130 | check_walign32( R_ECX );
|
nkeynes@361 | 1131 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1132 | :}
|
nkeynes@361 | 1133 | MOV.L @Rm, Rn {:
|
nkeynes@361 | 1134 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 1135 | check_ralign32( R_ECX );
|
nkeynes@361 | 1136 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1137 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1138 | :}
|
nkeynes@361 | 1139 | MOV.L @Rm+, Rn {:
|
nkeynes@361 | 1140 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1141 | check_ralign32( R_EAX );
|
nkeynes@361 | 1142 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1143 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 1144 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1145 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1146 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1147 | :}
|
nkeynes@361 | 1148 | MOV.L @(R0, Rm), Rn {:
|
nkeynes@361 | 1149 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1150 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1151 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1152 | check_ralign32( R_ECX );
|
nkeynes@361 | 1153 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1154 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1155 | :}
|
nkeynes@361 | 1156 | MOV.L @(disp, GBR), R0 {:
|
nkeynes@361 | 1157 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1158 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1159 | check_ralign32( R_ECX );
|
nkeynes@361 | 1160 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1161 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1162 | :}
|
nkeynes@361 | 1163 | MOV.L @(disp, PC), Rn {:
|
nkeynes@374 | 1164 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1165 | SLOTILLEGAL();
|
nkeynes@374 | 1166 | } else {
|
nkeynes@388 | 1167 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@388 | 1168 | char *ptr = mem_get_region(target);
|
nkeynes@388 | 1169 | if( ptr != NULL ) {
|
nkeynes@388 | 1170 | MOV_moff32_EAX( (uint32_t)ptr );
|
nkeynes@388 | 1171 | } else {
|
nkeynes@388 | 1172 | load_imm32( R_ECX, target );
|
nkeynes@388 | 1173 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 1174 | }
|
nkeynes@382 | 1175 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1176 | }
|
nkeynes@361 | 1177 | :}
|
nkeynes@361 | 1178 | MOV.L @(disp, Rm), Rn {:
|
nkeynes@361 | 1179 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1180 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@374 | 1181 | check_ralign32( R_ECX );
|
nkeynes@361 | 1182 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1183 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1184 | :}
|
nkeynes@361 | 1185 | MOV.W Rm, @Rn {:
|
nkeynes@361 | 1186 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1187 | check_walign16( R_ECX );
|
nkeynes@382 | 1188 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1189 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1190 | :}
|
nkeynes@361 | 1191 | MOV.W Rm, @-Rn {:
|
nkeynes@361 | 1192 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1193 | check_walign16( R_ECX );
|
nkeynes@361 | 1194 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1195 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@382 | 1196 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1197 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1198 | :}
|
nkeynes@361 | 1199 | MOV.W Rm, @(R0, Rn) {:
|
nkeynes@361 | 1200 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1201 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1202 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1203 | check_walign16( R_ECX );
|
nkeynes@361 | 1204 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1205 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1206 | :}
|
nkeynes@361 | 1207 | MOV.W R0, @(disp, GBR) {:
|
nkeynes@361 | 1208 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1209 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1210 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1211 | check_walign16( R_ECX );
|
nkeynes@361 | 1212 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1213 | :}
|
nkeynes@361 | 1214 | MOV.W R0, @(disp, Rn) {:
|
nkeynes@361 | 1215 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1216 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1217 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1218 | check_walign16( R_ECX );
|
nkeynes@361 | 1219 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1220 | :}
|
nkeynes@361 | 1221 | MOV.W @Rm, Rn {:
|
nkeynes@361 | 1222 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 1223 | check_ralign16( R_ECX );
|
nkeynes@361 | 1224 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1225 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1226 | :}
|
nkeynes@361 | 1227 | MOV.W @Rm+, Rn {:
|
nkeynes@361 | 1228 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1229 | check_ralign16( R_EAX );
|
nkeynes@361 | 1230 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1231 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 1232 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1233 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1234 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1235 | :}
|
nkeynes@361 | 1236 | MOV.W @(R0, Rm), Rn {:
|
nkeynes@361 | 1237 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1238 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1239 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1240 | check_ralign16( R_ECX );
|
nkeynes@361 | 1241 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1242 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1243 | :}
|
nkeynes@361 | 1244 | MOV.W @(disp, GBR), R0 {:
|
nkeynes@361 | 1245 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1246 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1247 | check_ralign16( R_ECX );
|
nkeynes@361 | 1248 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1249 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1250 | :}
|
nkeynes@361 | 1251 | MOV.W @(disp, PC), Rn {:
|
nkeynes@374 | 1252 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1253 | SLOTILLEGAL();
|
nkeynes@374 | 1254 | } else {
|
nkeynes@374 | 1255 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 1256 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 1257 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1258 | }
|
nkeynes@361 | 1259 | :}
|
nkeynes@361 | 1260 | MOV.W @(disp, Rm), R0 {:
|
nkeynes@361 | 1261 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1262 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1263 | check_ralign16( R_ECX );
|
nkeynes@361 | 1264 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1265 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1266 | :}
|
nkeynes@361 | 1267 | MOVA @(disp, PC), R0 {:
|
nkeynes@374 | 1268 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1269 | SLOTILLEGAL();
|
nkeynes@374 | 1270 | } else {
|
nkeynes@374 | 1271 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 1272 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 1273 | }
|
nkeynes@361 | 1274 | :}
|
nkeynes@361 | 1275 | MOVCA.L R0, @Rn {:
|
nkeynes@361 | 1276 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1277 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1278 | check_walign32( R_ECX );
|
nkeynes@361 | 1279 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1280 | :}
|
nkeynes@359 | 1281 |
|
nkeynes@359 | 1282 | /* Control transfer instructions */
|
nkeynes@374 | 1283 | BF disp {:
|
nkeynes@374 | 1284 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1285 | SLOTILLEGAL();
|
nkeynes@374 | 1286 | } else {
|
nkeynes@374 | 1287 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 1288 | JNE_rel8( 30, nottaken );
|
nkeynes@408 | 1289 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 1290 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1291 | return 2;
|
nkeynes@374 | 1292 | }
|
nkeynes@374 | 1293 | :}
|
nkeynes@374 | 1294 | BF/S disp {:
|
nkeynes@374 | 1295 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1296 | SLOTILLEGAL();
|
nkeynes@374 | 1297 | } else {
|
nkeynes@408 | 1298 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1299 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 1300 | OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@408 | 1301 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1302 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 1303 | // not taken
|
nkeynes@408 | 1304 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@408 | 1305 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1306 | return 4;
|
nkeynes@374 | 1307 | }
|
nkeynes@374 | 1308 | :}
|
nkeynes@374 | 1309 | BRA disp {:
|
nkeynes@374 | 1310 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1311 | SLOTILLEGAL();
|
nkeynes@374 | 1312 | } else {
|
nkeynes@374 | 1313 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1314 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 1315 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 1316 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1317 | return 4;
|
nkeynes@374 | 1318 | }
|
nkeynes@374 | 1319 | :}
|
nkeynes@374 | 1320 | BRAF Rn {:
|
nkeynes@374 | 1321 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1322 | SLOTILLEGAL();
|
nkeynes@374 | 1323 | } else {
|
nkeynes@408 | 1324 | load_reg( R_EAX, Rn );
|
nkeynes@408 | 1325 | ADD_imm32_r32( pc + 4, R_EAX );
|
nkeynes@408 | 1326 | store_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@374 | 1327 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1328 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 1329 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1330 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1331 | return 4;
|
nkeynes@374 | 1332 | }
|
nkeynes@374 | 1333 | :}
|
nkeynes@374 | 1334 | BSR disp {:
|
nkeynes@374 | 1335 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1336 | SLOTILLEGAL();
|
nkeynes@374 | 1337 | } else {
|
nkeynes@374 | 1338 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1339 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1340 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1341 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 1342 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 1343 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1344 | return 4;
|
nkeynes@374 | 1345 | }
|
nkeynes@374 | 1346 | :}
|
nkeynes@374 | 1347 | BSRF Rn {:
|
nkeynes@374 | 1348 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1349 | SLOTILLEGAL();
|
nkeynes@374 | 1350 | } else {
|
nkeynes@408 | 1351 | load_imm32( R_ECX, pc + 4 );
|
nkeynes@408 | 1352 | store_spreg( R_ECX, R_PR );
|
nkeynes@408 | 1353 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
|
nkeynes@408 | 1354 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1355 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1356 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 1357 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1358 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1359 | return 4;
|
nkeynes@374 | 1360 | }
|
nkeynes@374 | 1361 | :}
|
nkeynes@374 | 1362 | BT disp {:
|
nkeynes@374 | 1363 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1364 | SLOTILLEGAL();
|
nkeynes@374 | 1365 | } else {
|
nkeynes@374 | 1366 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 1367 | JE_rel8( 30, nottaken );
|
nkeynes@408 | 1368 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 1369 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1370 | return 2;
|
nkeynes@374 | 1371 | }
|
nkeynes@374 | 1372 | :}
|
nkeynes@374 | 1373 | BT/S disp {:
|
nkeynes@374 | 1374 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1375 | SLOTILLEGAL();
|
nkeynes@374 | 1376 | } else {
|
nkeynes@408 | 1377 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1378 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 1379 | OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@408 | 1380 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1381 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 1382 | // not taken
|
nkeynes@408 | 1383 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@408 | 1384 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1385 | return 4;
|
nkeynes@374 | 1386 | }
|
nkeynes@374 | 1387 | :}
|
nkeynes@374 | 1388 | JMP @Rn {:
|
nkeynes@374 | 1389 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1390 | SLOTILLEGAL();
|
nkeynes@374 | 1391 | } else {
|
nkeynes@408 | 1392 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1393 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1394 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1395 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1396 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1397 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1398 | return 4;
|
nkeynes@374 | 1399 | }
|
nkeynes@374 | 1400 | :}
|
nkeynes@374 | 1401 | JSR @Rn {:
|
nkeynes@374 | 1402 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1403 | SLOTILLEGAL();
|
nkeynes@374 | 1404 | } else {
|
nkeynes@374 | 1405 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1406 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1407 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1408 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1409 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1410 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1411 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1412 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1413 | return 4;
|
nkeynes@374 | 1414 | }
|
nkeynes@374 | 1415 | :}
|
nkeynes@374 | 1416 | RTE {:
|
nkeynes@374 | 1417 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1418 | SLOTILLEGAL();
|
nkeynes@374 | 1419 | } else {
|
nkeynes@408 | 1420 | check_priv();
|
nkeynes@408 | 1421 | load_spreg( R_ECX, R_SPC );
|
nkeynes@408 | 1422 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1423 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 1424 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 1425 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 1426 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 1427 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@408 | 1428 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1429 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1430 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1431 | return 4;
|
nkeynes@374 | 1432 | }
|
nkeynes@374 | 1433 | :}
|
nkeynes@374 | 1434 | RTS {:
|
nkeynes@374 | 1435 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1436 | SLOTILLEGAL();
|
nkeynes@374 | 1437 | } else {
|
nkeynes@408 | 1438 | load_spreg( R_ECX, R_PR );
|
nkeynes@408 | 1439 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1440 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1441 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1442 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1443 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1444 | return 4;
|
nkeynes@374 | 1445 | }
|
nkeynes@374 | 1446 | :}
|
nkeynes@374 | 1447 | TRAPA #imm {:
|
nkeynes@374 | 1448 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1449 | SLOTILLEGAL();
|
nkeynes@374 | 1450 | } else {
|
nkeynes@388 | 1451 | PUSH_imm32( imm );
|
nkeynes@388 | 1452 | call_func0( sh4_raise_trap );
|
nkeynes@388 | 1453 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@408 | 1454 | exit_block_pcset(pc);
|
nkeynes@409 | 1455 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1456 | return 2;
|
nkeynes@374 | 1457 | }
|
nkeynes@374 | 1458 | :}
|
nkeynes@374 | 1459 | UNDEF {:
|
nkeynes@374 | 1460 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@382 | 1461 | SLOTILLEGAL();
|
nkeynes@374 | 1462 | } else {
|
nkeynes@386 | 1463 | JMP_exit(EXIT_ILLEGAL);
|
nkeynes@408 | 1464 | return 2;
|
nkeynes@374 | 1465 | }
|
nkeynes@368 | 1466 | :}
|
nkeynes@374 | 1467 |
|
nkeynes@374 | 1468 | CLRMAC {:
|
nkeynes@374 | 1469 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 1470 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 1471 | store_spreg( R_EAX, R_MACH );
|
nkeynes@368 | 1472 | :}
|
nkeynes@374 | 1473 | CLRS {:
|
nkeynes@374 | 1474 | CLC();
|
nkeynes@374 | 1475 | SETC_sh4r(R_S);
|
nkeynes@368 | 1476 | :}
|
nkeynes@374 | 1477 | CLRT {:
|
nkeynes@374 | 1478 | CLC();
|
nkeynes@374 | 1479 | SETC_t();
|
nkeynes@359 | 1480 | :}
|
nkeynes@374 | 1481 | SETS {:
|
nkeynes@374 | 1482 | STC();
|
nkeynes@374 | 1483 | SETC_sh4r(R_S);
|
nkeynes@359 | 1484 | :}
|
nkeynes@374 | 1485 | SETT {:
|
nkeynes@374 | 1486 | STC();
|
nkeynes@374 | 1487 | SETC_t();
|
nkeynes@374 | 1488 | :}
|
nkeynes@359 | 1489 |
|
nkeynes@375 | 1490 | /* Floating point moves */
|
nkeynes@375 | 1491 | FMOV FRm, FRn {:
|
nkeynes@375 | 1492 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 1493 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 1494 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 1495 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 1496 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 1497 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 1498 | */
|
nkeynes@377 | 1499 | check_fpuen();
|
nkeynes@375 | 1500 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1501 | load_fr_bank( R_EDX );
|
nkeynes@375 | 1502 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1503 | JNE_rel8(8, doublesize);
|
nkeynes@375 | 1504 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 1505 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1506 | if( FRm&1 ) {
|
nkeynes@386 | 1507 | JMP_rel8(24, end);
|
nkeynes@380 | 1508 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1509 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1510 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 1511 | if( FRn&1 ) {
|
nkeynes@375 | 1512 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 1513 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1514 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 1515 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 1516 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@388 | 1517 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@388 | 1518 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 1519 | }
|
nkeynes@380 | 1520 | JMP_TARGET(end);
|
nkeynes@375 | 1521 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 1522 | if( FRn&1 ) {
|
nkeynes@386 | 1523 | JMP_rel8(24, end);
|
nkeynes@375 | 1524 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1525 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1526 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 1527 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1528 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@380 | 1529 | JMP_TARGET(end);
|
nkeynes@375 | 1530 | } else /* FRn&1 == 0 */ {
|
nkeynes@380 | 1531 | JMP_rel8(12, end);
|
nkeynes@375 | 1532 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1533 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 1534 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1535 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@380 | 1536 | JMP_TARGET(end);
|
nkeynes@375 | 1537 | }
|
nkeynes@375 | 1538 | }
|
nkeynes@375 | 1539 | :}
|
nkeynes@375 | 1540 | FMOV FRm, @Rn {:
|
nkeynes@377 | 1541 | check_fpuen();
|
nkeynes@375 | 1542 | load_reg( R_EDX, Rn );
|
nkeynes@375 | 1543 | check_walign32( R_EDX );
|
nkeynes@375 | 1544 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1545 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1546 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 1547 | load_fr_bank( R_ECX );
|
nkeynes@375 | 1548 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@375 | 1549 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@375 | 1550 | if( FRm&1 ) {
|
nkeynes@386 | 1551 | JMP_rel8( 48, end );
|
nkeynes@380 | 1552 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1553 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1554 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1555 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1556 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1557 | JMP_TARGET(end);
|
nkeynes@375 | 1558 | } else {
|
nkeynes@380 | 1559 | JMP_rel8( 39, end );
|
nkeynes@380 | 1560 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1561 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1562 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1563 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1564 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1565 | JMP_TARGET(end);
|
nkeynes@375 | 1566 | }
|
nkeynes@375 | 1567 | :}
|
nkeynes@375 | 1568 | FMOV @Rm, FRn {:
|
nkeynes@377 | 1569 | check_fpuen();
|
nkeynes@375 | 1570 | load_reg( R_EDX, Rm );
|
nkeynes@375 | 1571 | check_ralign32( R_EDX );
|
nkeynes@375 | 1572 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1573 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1574 | JNE_rel8(19, doublesize);
|
nkeynes@375 | 1575 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1576 | load_fr_bank( R_ECX );
|
nkeynes@375 | 1577 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 1578 | if( FRn&1 ) {
|
nkeynes@386 | 1579 | JMP_rel8(48, end);
|
nkeynes@380 | 1580 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1581 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@375 | 1582 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@375 | 1583 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1584 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1585 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1586 | JMP_TARGET(end);
|
nkeynes@375 | 1587 | } else {
|
nkeynes@380 | 1588 | JMP_rel8(36, end);
|
nkeynes@380 | 1589 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1590 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1591 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1592 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1593 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1594 | JMP_TARGET(end);
|
nkeynes@375 | 1595 | }
|
nkeynes@375 | 1596 | :}
|
nkeynes@377 | 1597 | FMOV FRm, @-Rn {:
|
nkeynes@377 | 1598 | check_fpuen();
|
nkeynes@377 | 1599 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 1600 | check_walign32( R_EDX );
|
nkeynes@377 | 1601 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1602 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@382 | 1603 | JNE_rel8(26, doublesize);
|
nkeynes@377 | 1604 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1605 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1606 | ADD_imm8s_r32(-4,R_EDX);
|
nkeynes@377 | 1607 | store_reg( R_EDX, Rn );
|
nkeynes@377 | 1608 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 1609 | if( FRm&1 ) {
|
nkeynes@386 | 1610 | JMP_rel8( 54, end );
|
nkeynes@380 | 1611 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1612 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1613 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1614 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1615 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 1616 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 1617 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1618 | JMP_TARGET(end);
|
nkeynes@377 | 1619 | } else {
|
nkeynes@382 | 1620 | JMP_rel8( 45, end );
|
nkeynes@380 | 1621 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1622 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1623 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1624 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1625 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 1626 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 1627 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1628 | JMP_TARGET(end);
|
nkeynes@377 | 1629 | }
|
nkeynes@377 | 1630 | :}
|
nkeynes@377 | 1631 | FMOV @Rm+, FRn {:
|
nkeynes@377 | 1632 | check_fpuen();
|
nkeynes@377 | 1633 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 1634 | check_ralign32( R_EDX );
|
nkeynes@377 | 1635 | MOV_r32_r32( R_EDX, R_EAX );
|
nkeynes@377 | 1636 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1637 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1638 | JNE_rel8(25, doublesize);
|
nkeynes@377 | 1639 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@377 | 1640 | store_reg( R_EAX, Rm );
|
nkeynes@377 | 1641 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1642 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1643 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1644 | if( FRn&1 ) {
|
nkeynes@386 | 1645 | JMP_rel8(54, end);
|
nkeynes@380 | 1646 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1647 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 1648 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 1649 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1650 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 1651 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1652 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1653 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1654 | JMP_TARGET(end);
|
nkeynes@377 | 1655 | } else {
|
nkeynes@380 | 1656 | JMP_rel8(42, end);
|
nkeynes@377 | 1657 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 1658 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 1659 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1660 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1661 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1662 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1663 | JMP_TARGET(end);
|
nkeynes@377 | 1664 | }
|
nkeynes@377 | 1665 | :}
|
nkeynes@377 | 1666 | FMOV FRm, @(R0, Rn) {:
|
nkeynes@377 | 1667 | check_fpuen();
|
nkeynes@377 | 1668 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 1669 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@377 | 1670 | check_walign32( R_EDX );
|
nkeynes@377 | 1671 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1672 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1673 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 1674 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1675 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1676 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 1677 | if( FRm&1 ) {
|
nkeynes@386 | 1678 | JMP_rel8( 48, end );
|
nkeynes@380 | 1679 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1680 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1681 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1682 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1683 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1684 | JMP_TARGET(end);
|
nkeynes@377 | 1685 | } else {
|
nkeynes@380 | 1686 | JMP_rel8( 39, end );
|
nkeynes@380 | 1687 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1688 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1689 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1690 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1691 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1692 | JMP_TARGET(end);
|
nkeynes@377 | 1693 | }
|
nkeynes@377 | 1694 | :}
|
nkeynes@377 | 1695 | FMOV @(R0, Rm), FRn {:
|
nkeynes@377 | 1696 | check_fpuen();
|
nkeynes@377 | 1697 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 1698 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@377 | 1699 | check_ralign32( R_EDX );
|
nkeynes@377 | 1700 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1701 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1702 | JNE_rel8(19, doublesize);
|
nkeynes@377 | 1703 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1704 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1705 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1706 | if( FRn&1 ) {
|
nkeynes@386 | 1707 | JMP_rel8(48, end);
|
nkeynes@380 | 1708 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1709 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1710 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 1711 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1712 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1713 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1714 | JMP_TARGET(end);
|
nkeynes@377 | 1715 | } else {
|
nkeynes@380 | 1716 | JMP_rel8(36, end);
|
nkeynes@380 | 1717 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1718 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1719 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1720 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1721 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1722 | JMP_TARGET(end);
|
nkeynes@377 | 1723 | }
|
nkeynes@377 | 1724 | :}
|
nkeynes@377 | 1725 | FLDI0 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 1726 | check_fpuen();
|
nkeynes@377 | 1727 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1728 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1729 | JNE_rel8(8, end);
|
nkeynes@377 | 1730 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@377 | 1731 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 1732 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 1733 | JMP_TARGET(end);
|
nkeynes@377 | 1734 | :}
|
nkeynes@377 | 1735 | FLDI1 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 1736 | check_fpuen();
|
nkeynes@377 | 1737 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1738 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1739 | JNE_rel8(11, end);
|
nkeynes@377 | 1740 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@377 | 1741 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 1742 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 1743 | JMP_TARGET(end);
|
nkeynes@377 | 1744 | :}
|
nkeynes@377 | 1745 |
|
nkeynes@377 | 1746 | FLOAT FPUL, FRn {:
|
nkeynes@377 | 1747 | check_fpuen();
|
nkeynes@377 | 1748 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1749 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 1750 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 1751 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1752 | JNE_rel8(5, doubleprec);
|
nkeynes@377 | 1753 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 1754 | JMP_rel8(3, end);
|
nkeynes@380 | 1755 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1756 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 1757 | JMP_TARGET(end);
|
nkeynes@377 | 1758 | :}
|
nkeynes@377 | 1759 | FTRC FRm, FPUL {:
|
nkeynes@377 | 1760 | check_fpuen();
|
nkeynes@388 | 1761 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 1762 | load_fr_bank( R_EDX );
|
nkeynes@388 | 1763 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 1764 | JNE_rel8(5, doubleprec);
|
nkeynes@388 | 1765 | push_fr( R_EDX, FRm );
|
nkeynes@388 | 1766 | JMP_rel8(3, doop);
|
nkeynes@388 | 1767 | JMP_TARGET(doubleprec);
|
nkeynes@388 | 1768 | push_dr( R_EDX, FRm );
|
nkeynes@388 | 1769 | JMP_TARGET( doop );
|
nkeynes@388 | 1770 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 1771 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 1772 | FCOMIP_st(1);
|
nkeynes@394 | 1773 | JNA_rel8( 32, sat );
|
nkeynes@388 | 1774 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 1775 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 1776 | FCOMIP_st(1); // 2
|
nkeynes@394 | 1777 | JAE_rel8( 21, sat2 ); // 2
|
nkeynes@394 | 1778 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 1779 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 1780 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 1781 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 1782 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 1783 | FLDCW_r32ind( R_EAX );
|
nkeynes@388 | 1784 | JMP_rel8( 9, end ); // 2
|
nkeynes@388 | 1785 |
|
nkeynes@388 | 1786 | JMP_TARGET(sat);
|
nkeynes@388 | 1787 | JMP_TARGET(sat2);
|
nkeynes@388 | 1788 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 1789 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 1790 | FPOP_st();
|
nkeynes@388 | 1791 | JMP_TARGET(end);
|
nkeynes@377 | 1792 | :}
|
nkeynes@377 | 1793 | FLDS FRm, FPUL {:
|
nkeynes@377 | 1794 | check_fpuen();
|
nkeynes@377 | 1795 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1796 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1797 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 1798 | :}
|
nkeynes@377 | 1799 | FSTS FPUL, FRn {:
|
nkeynes@377 | 1800 | check_fpuen();
|
nkeynes@377 | 1801 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1802 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 1803 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1804 | :}
|
nkeynes@377 | 1805 | FCNVDS FRm, FPUL {:
|
nkeynes@377 | 1806 | check_fpuen();
|
nkeynes@377 | 1807 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1808 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1809 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 1810 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1811 | push_dr( R_ECX, FRm );
|
nkeynes@377 | 1812 | pop_fpul();
|
nkeynes@380 | 1813 | JMP_TARGET(end);
|
nkeynes@377 | 1814 | :}
|
nkeynes@377 | 1815 | FCNVSD FPUL, FRn {:
|
nkeynes@377 | 1816 | check_fpuen();
|
nkeynes@377 | 1817 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1818 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1819 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 1820 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1821 | push_fpul();
|
nkeynes@377 | 1822 | pop_dr( R_ECX, FRn );
|
nkeynes@380 | 1823 | JMP_TARGET(end);
|
nkeynes@377 | 1824 | :}
|
nkeynes@375 | 1825 |
|
nkeynes@359 | 1826 | /* Floating point instructions */
|
nkeynes@374 | 1827 | FABS FRn {:
|
nkeynes@377 | 1828 | check_fpuen();
|
nkeynes@374 | 1829 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1830 | load_fr_bank( R_EDX );
|
nkeynes@374 | 1831 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1832 | JNE_rel8(10, doubleprec);
|
nkeynes@374 | 1833 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 1834 | FABS_st0(); // 2
|
nkeynes@374 | 1835 | pop_fr( R_EDX, FRn); //3
|
nkeynes@380 | 1836 | JMP_rel8(8,end); // 2
|
nkeynes@380 | 1837 | JMP_TARGET(doubleprec);
|
nkeynes@374 | 1838 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 1839 | FABS_st0();
|
nkeynes@374 | 1840 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1841 | JMP_TARGET(end);
|
nkeynes@374 | 1842 | :}
|
nkeynes@377 | 1843 | FADD FRm, FRn {:
|
nkeynes@377 | 1844 | check_fpuen();
|
nkeynes@375 | 1845 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1846 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1847 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1848 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 1849 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1850 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1851 | FADDP_st(1);
|
nkeynes@377 | 1852 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1853 | JMP_rel8(11,end);
|
nkeynes@380 | 1854 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1855 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1856 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1857 | FADDP_st(1);
|
nkeynes@377 | 1858 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1859 | JMP_TARGET(end);
|
nkeynes@375 | 1860 | :}
|
nkeynes@377 | 1861 | FDIV FRm, FRn {:
|
nkeynes@377 | 1862 | check_fpuen();
|
nkeynes@375 | 1863 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1864 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1865 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1866 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1867 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1868 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1869 | FDIVP_st(1);
|
nkeynes@377 | 1870 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1871 | JMP_rel8(11, end);
|
nkeynes@380 | 1872 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1873 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1874 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1875 | FDIVP_st(1);
|
nkeynes@377 | 1876 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1877 | JMP_TARGET(end);
|
nkeynes@375 | 1878 | :}
|
nkeynes@375 | 1879 | FMAC FR0, FRm, FRn {:
|
nkeynes@377 | 1880 | check_fpuen();
|
nkeynes@375 | 1881 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1882 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@375 | 1883 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1884 | JNE_rel8(18, doubleprec);
|
nkeynes@375 | 1885 | push_fr( R_EDX, 0 );
|
nkeynes@375 | 1886 | push_fr( R_EDX, FRm );
|
nkeynes@375 | 1887 | FMULP_st(1);
|
nkeynes@375 | 1888 | push_fr( R_EDX, FRn );
|
nkeynes@375 | 1889 | FADDP_st(1);
|
nkeynes@375 | 1890 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 1891 | JMP_rel8(16, end);
|
nkeynes@380 | 1892 | JMP_TARGET(doubleprec);
|
nkeynes@375 | 1893 | push_dr( R_EDX, 0 );
|
nkeynes@375 | 1894 | push_dr( R_EDX, FRm );
|
nkeynes@375 | 1895 | FMULP_st(1);
|
nkeynes@375 | 1896 | push_dr( R_EDX, FRn );
|
nkeynes@375 | 1897 | FADDP_st(1);
|
nkeynes@375 | 1898 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 1899 | JMP_TARGET(end);
|
nkeynes@375 | 1900 | :}
|
nkeynes@375 | 1901 |
|
nkeynes@377 | 1902 | FMUL FRm, FRn {:
|
nkeynes@377 | 1903 | check_fpuen();
|
nkeynes@377 | 1904 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1905 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1906 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1907 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1908 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1909 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1910 | FMULP_st(1);
|
nkeynes@377 | 1911 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1912 | JMP_rel8(11, end);
|
nkeynes@380 | 1913 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1914 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1915 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1916 | FMULP_st(1);
|
nkeynes@377 | 1917 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1918 | JMP_TARGET(end);
|
nkeynes@377 | 1919 | :}
|
nkeynes@377 | 1920 | FNEG FRn {:
|
nkeynes@377 | 1921 | check_fpuen();
|
nkeynes@377 | 1922 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1923 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1924 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1925 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 1926 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1927 | FCHS_st0();
|
nkeynes@377 | 1928 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1929 | JMP_rel8(8, end);
|
nkeynes@380 | 1930 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1931 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1932 | FCHS_st0();
|
nkeynes@377 | 1933 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1934 | JMP_TARGET(end);
|
nkeynes@377 | 1935 | :}
|
nkeynes@377 | 1936 | FSRRA FRn {:
|
nkeynes@377 | 1937 | check_fpuen();
|
nkeynes@377 | 1938 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1939 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1940 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1941 | JNE_rel8(12, end); // PR=0 only
|
nkeynes@377 | 1942 | FLD1_st0();
|
nkeynes@377 | 1943 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1944 | FSQRT_st0();
|
nkeynes@377 | 1945 | FDIVP_st(1);
|
nkeynes@377 | 1946 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1947 | JMP_TARGET(end);
|
nkeynes@377 | 1948 | :}
|
nkeynes@377 | 1949 | FSQRT FRn {:
|
nkeynes@377 | 1950 | check_fpuen();
|
nkeynes@377 | 1951 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1952 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1953 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1954 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 1955 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1956 | FSQRT_st0();
|
nkeynes@377 | 1957 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1958 | JMP_rel8(8, end);
|
nkeynes@380 | 1959 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1960 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1961 | FSQRT_st0();
|
nkeynes@377 | 1962 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1963 | JMP_TARGET(end);
|
nkeynes@377 | 1964 | :}
|
nkeynes@377 | 1965 | FSUB FRm, FRn {:
|
nkeynes@377 | 1966 | check_fpuen();
|
nkeynes@377 | 1967 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1968 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1969 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1970 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1971 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1972 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 1973 | FSUBP_st(1);
|
nkeynes@377 | 1974 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1975 | JMP_rel8(11, end);
|
nkeynes@380 | 1976 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1977 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1978 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 1979 | FSUBP_st(1);
|
nkeynes@377 | 1980 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1981 | JMP_TARGET(end);
|
nkeynes@377 | 1982 | :}
|
nkeynes@377 | 1983 |
|
nkeynes@377 | 1984 | FCMP/EQ FRm, FRn {:
|
nkeynes@377 | 1985 | check_fpuen();
|
nkeynes@377 | 1986 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1987 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1988 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1989 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 1990 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1991 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 1992 | JMP_rel8(6, end);
|
nkeynes@380 | 1993 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1994 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1995 | push_dr(R_EDX, FRn);
|
nkeynes@382 | 1996 | JMP_TARGET(end);
|
nkeynes@377 | 1997 | FCOMIP_st(1);
|
nkeynes@377 | 1998 | SETE_t();
|
nkeynes@377 | 1999 | FPOP_st();
|
nkeynes@377 | 2000 | :}
|
nkeynes@377 | 2001 | FCMP/GT FRm, FRn {:
|
nkeynes@377 | 2002 | check_fpuen();
|
nkeynes@377 | 2003 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2004 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2005 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2006 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2007 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2008 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2009 | JMP_rel8(6, end);
|
nkeynes@380 | 2010 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2011 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2012 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 2013 | JMP_TARGET(end);
|
nkeynes@377 | 2014 | FCOMIP_st(1);
|
nkeynes@377 | 2015 | SETA_t();
|
nkeynes@377 | 2016 | FPOP_st();
|
nkeynes@377 | 2017 | :}
|
nkeynes@377 | 2018 |
|
nkeynes@377 | 2019 | FSCA FPUL, FRn {:
|
nkeynes@377 | 2020 | check_fpuen();
|
nkeynes@388 | 2021 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2022 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2023 | JNE_rel8( 21, doubleprec );
|
nkeynes@388 | 2024 | load_fr_bank( R_ECX );
|
nkeynes@388 | 2025 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
|
nkeynes@388 | 2026 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 2027 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 2028 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2029 | :}
|
nkeynes@377 | 2030 | FIPR FVm, FVn {:
|
nkeynes@377 | 2031 | check_fpuen();
|
nkeynes@388 | 2032 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2033 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2034 | JNE_rel8(44, doubleprec);
|
nkeynes@388 | 2035 |
|
nkeynes@388 | 2036 | load_fr_bank( R_ECX );
|
nkeynes@388 | 2037 | push_fr( R_ECX, FVm<<2 );
|
nkeynes@388 | 2038 | push_fr( R_ECX, FVn<<2 );
|
nkeynes@388 | 2039 | FMULP_st(1);
|
nkeynes@388 | 2040 | push_fr( R_ECX, (FVm<<2)+1);
|
nkeynes@388 | 2041 | push_fr( R_ECX, (FVn<<2)+1);
|
nkeynes@388 | 2042 | FMULP_st(1);
|
nkeynes@388 | 2043 | FADDP_st(1);
|
nkeynes@388 | 2044 | push_fr( R_ECX, (FVm<<2)+2);
|
nkeynes@388 | 2045 | push_fr( R_ECX, (FVn<<2)+2);
|
nkeynes@388 | 2046 | FMULP_st(1);
|
nkeynes@388 | 2047 | FADDP_st(1);
|
nkeynes@388 | 2048 | push_fr( R_ECX, (FVm<<2)+3);
|
nkeynes@388 | 2049 | push_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2050 | FMULP_st(1);
|
nkeynes@388 | 2051 | FADDP_st(1);
|
nkeynes@388 | 2052 | pop_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2053 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2054 | :}
|
nkeynes@377 | 2055 | FTRV XMTRX, FVn {:
|
nkeynes@377 | 2056 | check_fpuen();
|
nkeynes@388 | 2057 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2058 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2059 | JNE_rel8( 30, doubleprec );
|
nkeynes@388 | 2060 | load_fr_bank( R_EDX ); // 3
|
nkeynes@388 | 2061 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
|
nkeynes@388 | 2062 | load_xf_bank( R_ECX ); // 12
|
nkeynes@388 | 2063 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
|
nkeynes@388 | 2064 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2065 | :}
|
nkeynes@377 | 2066 |
|
nkeynes@377 | 2067 | FRCHG {:
|
nkeynes@377 | 2068 | check_fpuen();
|
nkeynes@377 | 2069 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2070 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 2071 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@386 | 2072 | update_fr_bank( R_ECX );
|
nkeynes@377 | 2073 | :}
|
nkeynes@377 | 2074 | FSCHG {:
|
nkeynes@377 | 2075 | check_fpuen();
|
nkeynes@377 | 2076 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2077 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 2078 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2079 | :}
|
nkeynes@359 | 2080 |
|
nkeynes@359 | 2081 | /* Processor control instructions */
|
nkeynes@368 | 2082 | LDC Rm, SR {:
|
nkeynes@386 | 2083 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2084 | SLOTILLEGAL();
|
nkeynes@386 | 2085 | } else {
|
nkeynes@386 | 2086 | check_priv();
|
nkeynes@386 | 2087 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2088 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2089 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2090 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 2091 | }
|
nkeynes@368 | 2092 | :}
|
nkeynes@359 | 2093 | LDC Rm, GBR {:
|
nkeynes@359 | 2094 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2095 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2096 | :}
|
nkeynes@359 | 2097 | LDC Rm, VBR {:
|
nkeynes@386 | 2098 | check_priv();
|
nkeynes@359 | 2099 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2100 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2101 | :}
|
nkeynes@359 | 2102 | LDC Rm, SSR {:
|
nkeynes@386 | 2103 | check_priv();
|
nkeynes@359 | 2104 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2105 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2106 | :}
|
nkeynes@359 | 2107 | LDC Rm, SGR {:
|
nkeynes@386 | 2108 | check_priv();
|
nkeynes@359 | 2109 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2110 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2111 | :}
|
nkeynes@359 | 2112 | LDC Rm, SPC {:
|
nkeynes@386 | 2113 | check_priv();
|
nkeynes@359 | 2114 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2115 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2116 | :}
|
nkeynes@359 | 2117 | LDC Rm, DBR {:
|
nkeynes@386 | 2118 | check_priv();
|
nkeynes@359 | 2119 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2120 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2121 | :}
|
nkeynes@374 | 2122 | LDC Rm, Rn_BANK {:
|
nkeynes@386 | 2123 | check_priv();
|
nkeynes@374 | 2124 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2125 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@374 | 2126 | :}
|
nkeynes@359 | 2127 | LDC.L @Rm+, GBR {:
|
nkeynes@359 | 2128 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2129 | check_ralign32( R_EAX );
|
nkeynes@359 | 2130 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2131 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2132 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2133 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2134 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2135 | :}
|
nkeynes@368 | 2136 | LDC.L @Rm+, SR {:
|
nkeynes@386 | 2137 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2138 | SLOTILLEGAL();
|
nkeynes@386 | 2139 | } else {
|
nkeynes@386 | 2140 | check_priv();
|
nkeynes@386 | 2141 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2142 | check_ralign32( R_EAX );
|
nkeynes@386 | 2143 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2144 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 2145 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 2146 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 2147 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2148 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2149 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 2150 | }
|
nkeynes@359 | 2151 | :}
|
nkeynes@359 | 2152 | LDC.L @Rm+, VBR {:
|
nkeynes@386 | 2153 | check_priv();
|
nkeynes@359 | 2154 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2155 | check_ralign32( R_EAX );
|
nkeynes@359 | 2156 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2157 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2158 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2159 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2160 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2161 | :}
|
nkeynes@359 | 2162 | LDC.L @Rm+, SSR {:
|
nkeynes@386 | 2163 | check_priv();
|
nkeynes@359 | 2164 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2165 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2166 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2167 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2168 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2169 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2170 | :}
|
nkeynes@359 | 2171 | LDC.L @Rm+, SGR {:
|
nkeynes@386 | 2172 | check_priv();
|
nkeynes@359 | 2173 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2174 | check_ralign32( R_EAX );
|
nkeynes@359 | 2175 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2176 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2177 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2178 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2179 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2180 | :}
|
nkeynes@359 | 2181 | LDC.L @Rm+, SPC {:
|
nkeynes@386 | 2182 | check_priv();
|
nkeynes@359 | 2183 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2184 | check_ralign32( R_EAX );
|
nkeynes@359 | 2185 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2186 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2187 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2188 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2189 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2190 | :}
|
nkeynes@359 | 2191 | LDC.L @Rm+, DBR {:
|
nkeynes@386 | 2192 | check_priv();
|
nkeynes@359 | 2193 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2194 | check_ralign32( R_EAX );
|
nkeynes@359 | 2195 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2196 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2197 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2198 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2199 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2200 | :}
|
nkeynes@359 | 2201 | LDC.L @Rm+, Rn_BANK {:
|
nkeynes@386 | 2202 | check_priv();
|
nkeynes@374 | 2203 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2204 | check_ralign32( R_EAX );
|
nkeynes@374 | 2205 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 2206 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 2207 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 2208 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 2209 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 2210 | :}
|
nkeynes@359 | 2211 | LDS Rm, FPSCR {:
|
nkeynes@359 | 2212 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2213 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2214 | update_fr_bank( R_EAX );
|
nkeynes@359 | 2215 | :}
|
nkeynes@359 | 2216 | LDS.L @Rm+, FPSCR {:
|
nkeynes@359 | 2217 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2218 | check_ralign32( R_EAX );
|
nkeynes@359 | 2219 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2220 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2221 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2222 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2223 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2224 | update_fr_bank( R_EAX );
|
nkeynes@359 | 2225 | :}
|
nkeynes@359 | 2226 | LDS Rm, FPUL {:
|
nkeynes@359 | 2227 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2228 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2229 | :}
|
nkeynes@359 | 2230 | LDS.L @Rm+, FPUL {:
|
nkeynes@359 | 2231 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2232 | check_ralign32( R_EAX );
|
nkeynes@359 | 2233 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2234 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2235 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2236 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2237 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2238 | :}
|
nkeynes@359 | 2239 | LDS Rm, MACH {:
|
nkeynes@359 | 2240 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2241 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2242 | :}
|
nkeynes@359 | 2243 | LDS.L @Rm+, MACH {:
|
nkeynes@359 | 2244 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2245 | check_ralign32( R_EAX );
|
nkeynes@359 | 2246 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2247 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2248 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2249 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2250 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2251 | :}
|
nkeynes@359 | 2252 | LDS Rm, MACL {:
|
nkeynes@359 | 2253 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2254 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2255 | :}
|
nkeynes@359 | 2256 | LDS.L @Rm+, MACL {:
|
nkeynes@359 | 2257 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2258 | check_ralign32( R_EAX );
|
nkeynes@359 | 2259 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2260 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2261 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2262 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2263 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2264 | :}
|
nkeynes@359 | 2265 | LDS Rm, PR {:
|
nkeynes@359 | 2266 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2267 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2268 | :}
|
nkeynes@359 | 2269 | LDS.L @Rm+, PR {:
|
nkeynes@359 | 2270 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2271 | check_ralign32( R_EAX );
|
nkeynes@359 | 2272 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2273 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2274 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2275 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2276 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2277 | :}
|
nkeynes@359 | 2278 | LDTLB {: :}
|
nkeynes@359 | 2279 | OCBI @Rn {: :}
|
nkeynes@359 | 2280 | OCBP @Rn {: :}
|
nkeynes@359 | 2281 | OCBWB @Rn {: :}
|
nkeynes@374 | 2282 | PREF @Rn {:
|
nkeynes@374 | 2283 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 2284 | PUSH_r32( R_EAX );
|
nkeynes@374 | 2285 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 2286 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@380 | 2287 | JNE_rel8(7, end);
|
nkeynes@374 | 2288 | call_func0( sh4_flush_store_queue );
|
nkeynes@380 | 2289 | JMP_TARGET(end);
|
nkeynes@377 | 2290 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@374 | 2291 | :}
|
nkeynes@388 | 2292 | SLEEP {:
|
nkeynes@388 | 2293 | check_priv();
|
nkeynes@388 | 2294 | call_func0( sh4_sleep );
|
nkeynes@388 | 2295 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@394 | 2296 | INC_r32(R_ESI);
|
nkeynes@408 | 2297 | return 2;
|
nkeynes@388 | 2298 | :}
|
nkeynes@386 | 2299 | STC SR, Rn {:
|
nkeynes@386 | 2300 | check_priv();
|
nkeynes@386 | 2301 | call_func0(sh4_read_sr);
|
nkeynes@386 | 2302 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2303 | :}
|
nkeynes@359 | 2304 | STC GBR, Rn {:
|
nkeynes@359 | 2305 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2306 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2307 | :}
|
nkeynes@359 | 2308 | STC VBR, Rn {:
|
nkeynes@386 | 2309 | check_priv();
|
nkeynes@359 | 2310 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2311 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2312 | :}
|
nkeynes@359 | 2313 | STC SSR, Rn {:
|
nkeynes@386 | 2314 | check_priv();
|
nkeynes@359 | 2315 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2316 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2317 | :}
|
nkeynes@359 | 2318 | STC SPC, Rn {:
|
nkeynes@386 | 2319 | check_priv();
|
nkeynes@359 | 2320 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2321 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2322 | :}
|
nkeynes@359 | 2323 | STC SGR, Rn {:
|
nkeynes@386 | 2324 | check_priv();
|
nkeynes@359 | 2325 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2326 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2327 | :}
|
nkeynes@359 | 2328 | STC DBR, Rn {:
|
nkeynes@386 | 2329 | check_priv();
|
nkeynes@359 | 2330 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2331 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2332 | :}
|
nkeynes@374 | 2333 | STC Rm_BANK, Rn {:
|
nkeynes@386 | 2334 | check_priv();
|
nkeynes@374 | 2335 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2336 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2337 | :}
|
nkeynes@374 | 2338 | STC.L SR, @-Rn {:
|
nkeynes@386 | 2339 | check_priv();
|
nkeynes@395 | 2340 | call_func0( sh4_read_sr );
|
nkeynes@368 | 2341 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2342 | check_walign32( R_ECX );
|
nkeynes@382 | 2343 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@368 | 2344 | store_reg( R_ECX, Rn );
|
nkeynes@368 | 2345 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2346 | :}
|
nkeynes@359 | 2347 | STC.L VBR, @-Rn {:
|
nkeynes@386 | 2348 | check_priv();
|
nkeynes@359 | 2349 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2350 | check_walign32( R_ECX );
|
nkeynes@382 | 2351 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2352 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2353 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2354 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2355 | :}
|
nkeynes@359 | 2356 | STC.L SSR, @-Rn {:
|
nkeynes@386 | 2357 | check_priv();
|
nkeynes@359 | 2358 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2359 | check_walign32( R_ECX );
|
nkeynes@382 | 2360 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2361 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2362 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2363 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2364 | :}
|
nkeynes@359 | 2365 | STC.L SPC, @-Rn {:
|
nkeynes@386 | 2366 | check_priv();
|
nkeynes@359 | 2367 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2368 | check_walign32( R_ECX );
|
nkeynes@382 | 2369 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2370 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2371 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2372 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2373 | :}
|
nkeynes@359 | 2374 | STC.L SGR, @-Rn {:
|
nkeynes@386 | 2375 | check_priv();
|
nkeynes@359 | 2376 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2377 | check_walign32( R_ECX );
|
nkeynes@382 | 2378 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2379 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2380 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2381 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2382 | :}
|
nkeynes@359 | 2383 | STC.L DBR, @-Rn {:
|
nkeynes@386 | 2384 | check_priv();
|
nkeynes@359 | 2385 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2386 | check_walign32( R_ECX );
|
nkeynes@382 | 2387 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2388 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2389 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2390 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2391 | :}
|
nkeynes@374 | 2392 | STC.L Rm_BANK, @-Rn {:
|
nkeynes@386 | 2393 | check_priv();
|
nkeynes@374 | 2394 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2395 | check_walign32( R_ECX );
|
nkeynes@382 | 2396 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 2397 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 2398 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2399 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 2400 | :}
|
nkeynes@359 | 2401 | STC.L GBR, @-Rn {:
|
nkeynes@359 | 2402 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2403 | check_walign32( R_ECX );
|
nkeynes@382 | 2404 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2405 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2406 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2407 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2408 | :}
|
nkeynes@359 | 2409 | STS FPSCR, Rn {:
|
nkeynes@359 | 2410 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 2411 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2412 | :}
|
nkeynes@359 | 2413 | STS.L FPSCR, @-Rn {:
|
nkeynes@359 | 2414 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2415 | check_walign32( R_ECX );
|
nkeynes@382 | 2416 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2417 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2418 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 2419 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2420 | :}
|
nkeynes@359 | 2421 | STS FPUL, Rn {:
|
nkeynes@359 | 2422 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2423 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2424 | :}
|
nkeynes@359 | 2425 | STS.L FPUL, @-Rn {:
|
nkeynes@359 | 2426 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2427 | check_walign32( R_ECX );
|
nkeynes@382 | 2428 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2429 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2430 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2431 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2432 | :}
|
nkeynes@359 | 2433 | STS MACH, Rn {:
|
nkeynes@359 | 2434 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2435 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2436 | :}
|
nkeynes@359 | 2437 | STS.L MACH, @-Rn {:
|
nkeynes@359 | 2438 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2439 | check_walign32( R_ECX );
|
nkeynes@382 | 2440 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2441 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2442 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2443 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2444 | :}
|
nkeynes@359 | 2445 | STS MACL, Rn {:
|
nkeynes@359 | 2446 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2447 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2448 | :}
|
nkeynes@359 | 2449 | STS.L MACL, @-Rn {:
|
nkeynes@359 | 2450 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2451 | check_walign32( R_ECX );
|
nkeynes@382 | 2452 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2453 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2454 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2455 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2456 | :}
|
nkeynes@359 | 2457 | STS PR, Rn {:
|
nkeynes@359 | 2458 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2459 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2460 | :}
|
nkeynes@359 | 2461 | STS.L PR, @-Rn {:
|
nkeynes@359 | 2462 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2463 | check_walign32( R_ECX );
|
nkeynes@382 | 2464 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2465 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2466 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2467 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2468 | :}
|
nkeynes@359 | 2469 |
|
nkeynes@359 | 2470 | NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
|
nkeynes@359 | 2471 | %%
|
nkeynes@374 | 2472 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2473 | ADD_imm8s_r32(2,R_ESI);
|
nkeynes@374 | 2474 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@386 | 2475 | } else {
|
nkeynes@386 | 2476 | INC_r32(R_ESI);
|
nkeynes@374 | 2477 | }
|
nkeynes@359 | 2478 | return 0;
|
nkeynes@359 | 2479 | }
|