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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 334:59073f812bd3
prev325:5717ae5d4746
next342:850502f0e8de
author nkeynes
date Sat Jan 27 12:02:54 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Add register masks on IDE DMA registers
file annotate diff log raw
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/**
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 * $Id: asic.c,v 1.27 2007-01-27 12:02:54 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static uint32_t asic_run_slice( uint32_t nanosecs );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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					NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 60
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#define G2_BIT4_TICKS 160
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#define G2_BIT0_ON_TICKS 120
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#define G2_BIT0_OFF_TICKS 420
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struct asic_g2_state {
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    int bit5_off_timer;
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    int bit4_on_timer;
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    int bit4_off_timer;
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    int bit0_on_timer;
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    int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static uint32_t asic_run_slice( uint32_t nanosecs )
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{
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    g2_update_fifo_status(nanosecs);
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    if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit5_off_timer = -1;
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    } else {
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	g2_state.bit5_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_off_timer = -1;
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    } else {
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	g2_state.bit4_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_on_timer = -1;
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    } else {
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	g2_state.bit4_on_timer -= nanosecs;
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    }
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    if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_off_timer = -1;
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    } else {
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	g2_state.bit0_off_timer -= nanosecs;
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    }
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    if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_on_timer = -1;
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    } else {
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	g2_state.bit0_on_timer -= nanosecs;
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    }
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    return nanosecs;
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}
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0xFF, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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	return 1;
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    else
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	return 0;
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}
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/**
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 * Setup the timers for the 3 FIFO status bits following a write through the G2
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 * bus from the SH4 side. The timing is roughly as follows: (times are
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 * approximate based on software readings - I wouldn't take this as gospel but
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 * it seems to be enough to fool most programs). 
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 *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
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 *   40ns: Bit 5 goes low and bit 4 goes high
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 *  120ns: Bit 4 goes low, bit 0 goes high
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 *  240ns: Bit 0 goes low.
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 *
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 * Additional writes while the FIFO is in operation extend the time that the
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 * bits remain high as one might expect, without altering the time at which
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 * they initially go high.
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 */
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void asic_g2_write_word()
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{
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    if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    } else {
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	g2_state.bit5_off_timer += G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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    } else {
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	g2_state.bit4_off_timer += G2_BIT4_TICKS;
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    }
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    if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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    }
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    if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_update_fifo_status( uint32_t nanos )
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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	val = val & (~0x20);
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	g2_state.bit5_off_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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	val = val | 0x10;
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	g2_state.bit4_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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	val = val & (~0x10);
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	g2_state.bit4_off_timer = -1;
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    } 
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    if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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	val = val | 0x01;
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	g2_state.bit0_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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	val = val & (~0x01);
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	g2_state.bit0_off_timer = -1;
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    } 
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    MMIO_WRITE( ASIC, G2STATUS, val );
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    return val;
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}   
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static int g2_read_status() {
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    return g2_update_fifo_status( sh4r.slice_cycle );
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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    if( event >= 64 ) { /* Third word */
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	asic_event( EVENT_CASCADE2 );
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    } else if( event >= 32 ) { /* Second word */
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	asic_event( EVENT_CASCADE1 );
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    }
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    if( result == 0 ) {
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	/* clear cascades if necessary */
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	if( event >= 64 ) {
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	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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	} else if( event >= 32 ) {
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	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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	}
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    }
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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{
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    uint32_t offset = channel << 5;
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    if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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	if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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	    uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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	    uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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	    uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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	    uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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	    uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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	    char buf[length];
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	    if( dir == 0 ) { /* SH4 to device */
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		mem_copy_from_sh4( buf, sh4addr, length );
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		mem_copy_to_sh4( extaddr, buf, length );
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	    } else { /* Device to SH4 */
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		mem_copy_from_sh4( buf, extaddr, length );
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		mem_copy_to_sh4( sh4addr, buf, length );
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	    }
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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	    asic_event( EVENT_G2_DMA0 + channel );
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	} else {
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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	}
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    }
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   287
}
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   288
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   289
void asic_ide_dma_transfer( )
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   290
{	
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   291
    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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   294
	    
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	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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   296
	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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   297
	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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   298
	    
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	    uint32_t xfer = ide_read_data_dma( addr, length );
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	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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	} else { /* 0 */
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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   304
	}
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    }
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   306
}
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   307
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   308
void pvr_dma_transfer( )
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   309
{
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   310
    sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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   311
    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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   312
    char *data = alloca( count );
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   313
    uint32_t rcount = DMAC_get_buffer( 2, data, count );
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   314
    if( rcount != count )
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   315
	WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@325
   316
    
nkeynes@325
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    pvr2_dma_write( destaddr, data, rcount );
nkeynes@325
   318
    
nkeynes@325
   319
    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@325
   320
    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@325
   321
    if( destaddr & 0x01000000 ) { /* Write to texture RAM */
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   322
	MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
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   323
    }
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   324
    asic_event( EVENT_PVR_DMA );
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   325
}
nkeynes@155
   326
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   327
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
nkeynes@1
   328
{
nkeynes@1
   329
    switch( reg ) {
nkeynes@125
   330
    case PIRQ1:
nkeynes@305
   331
	break; /* Treat this as read-only for the moment */
nkeynes@56
   332
    case PIRQ0:
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   333
	val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
nkeynes@305
   334
	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
nkeynes@305
   335
	asic_check_cleared_events();
nkeynes@305
   336
	break;
nkeynes@56
   337
    case PIRQ2:
nkeynes@305
   338
	/* Clear any events */
nkeynes@305
   339
	val = MMIO_READ(ASIC, reg)&(~val);
nkeynes@305
   340
	MMIO_WRITE( ASIC, reg, val );
nkeynes@305
   341
	if( val == 0 ) { /* all clear - clear the cascade bit */
nkeynes@305
   342
	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
nkeynes@305
   343
	}
nkeynes@56
   344
	asic_check_cleared_events();
nkeynes@56
   345
	break;
nkeynes@244
   346
    case SYSRESET:
nkeynes@244
   347
	if( val == 0x7611 ) {
nkeynes@244
   348
	    dreamcast_reset();
nkeynes@255
   349
	    sh4r.new_pc = sh4r.pc;
nkeynes@244
   350
	} else {
nkeynes@244
   351
	    WARN( "Unknown value %08X written to SYSRESET port", val );
nkeynes@244
   352
	}
nkeynes@244
   353
	break;
nkeynes@56
   354
    case MAPLE_STATE:
nkeynes@56
   355
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   356
	if( val & 1 ) {
nkeynes@56
   357
	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@56
   358
	    maple_handle_buffer( maple_addr );
nkeynes@56
   359
	    MMIO_WRITE( ASIC, reg, 0 );
nkeynes@56
   360
	}
nkeynes@56
   361
	break;
nkeynes@325
   362
    case PVRDMADEST:
nkeynes@325
   363
	MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
nkeynes@325
   364
	break;
nkeynes@325
   365
    case PVRDMACNT: 
nkeynes@325
   366
	MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
nkeynes@325
   367
	break;
nkeynes@56
   368
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@325
   369
	val = val & 0x01;
nkeynes@94
   370
	MMIO_WRITE( ASIC, reg, val );
nkeynes@325
   371
	if( val == 1 ) {
nkeynes@325
   372
	    pvr_dma_transfer();
nkeynes@56
   373
	}
nkeynes@56
   374
	break;
nkeynes@325
   375
    case MAPLE_DMA:
nkeynes@158
   376
	MMIO_WRITE( ASIC, reg, val );
nkeynes@158
   377
	break;
nkeynes@56
   378
    default:
nkeynes@56
   379
	MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   380
    }
nkeynes@1
   381
}
nkeynes@1
   382
nkeynes@1
   383
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   384
{
nkeynes@1
   385
    int32_t val;
nkeynes@1
   386
    switch( reg ) {
nkeynes@2
   387
        /*
nkeynes@2
   388
        case 0x89C:
nkeynes@2
   389
            sh4_stop();
nkeynes@2
   390
            return 0x000000B;
nkeynes@2
   391
        */     
nkeynes@94
   392
    case PIRQ0:
nkeynes@94
   393
    case PIRQ1:
nkeynes@94
   394
    case PIRQ2:
nkeynes@94
   395
    case IRQA0:
nkeynes@94
   396
    case IRQA1:
nkeynes@94
   397
    case IRQA2:
nkeynes@94
   398
    case IRQB0:
nkeynes@94
   399
    case IRQB1:
nkeynes@94
   400
    case IRQB2:
nkeynes@94
   401
    case IRQC0:
nkeynes@94
   402
    case IRQC1:
nkeynes@94
   403
    case IRQC2:
nkeynes@158
   404
    case MAPLE_STATE:
nkeynes@94
   405
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   406
	return val;            
nkeynes@94
   407
    case G2STATUS:
nkeynes@137
   408
	return g2_read_status();
nkeynes@94
   409
    default:
nkeynes@94
   410
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   411
	return val;
nkeynes@1
   412
    }
nkeynes@94
   413
    
nkeynes@1
   414
}
nkeynes@1
   415
nkeynes@1
   416
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   417
{
nkeynes@244
   418
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   419
	return; /* disabled */
nkeynes@244
   420
    }
nkeynes@244
   421
nkeynes@2
   422
    switch( reg ) {
nkeynes@125
   423
    case IDEALTSTATUS: /* Device control */
nkeynes@125
   424
	ide_write_control( val );
nkeynes@125
   425
	break;
nkeynes@125
   426
    case IDEDATA:
nkeynes@125
   427
	ide_write_data_pio( val );
nkeynes@125
   428
	break;
nkeynes@125
   429
    case IDEFEAT:
nkeynes@125
   430
	if( ide_can_write_regs() )
nkeynes@125
   431
	    idereg.feature = (uint8_t)val;
nkeynes@125
   432
	break;
nkeynes@125
   433
    case IDECOUNT:
nkeynes@125
   434
	if( ide_can_write_regs() )
nkeynes@125
   435
	    idereg.count = (uint8_t)val;
nkeynes@125
   436
	break;
nkeynes@125
   437
    case IDELBA0:
nkeynes@125
   438
	if( ide_can_write_regs() )
nkeynes@125
   439
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   440
	break;
nkeynes@125
   441
    case IDELBA1:
nkeynes@125
   442
	if( ide_can_write_regs() )
nkeynes@125
   443
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   444
	break;
nkeynes@125
   445
    case IDELBA2:
nkeynes@125
   446
	if( ide_can_write_regs() )
nkeynes@125
   447
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   448
	break;
nkeynes@125
   449
    case IDEDEV:
nkeynes@125
   450
	if( ide_can_write_regs() )
nkeynes@125
   451
	    idereg.device = (uint8_t)val;
nkeynes@125
   452
	break;
nkeynes@125
   453
    case IDECMD:
nkeynes@240
   454
	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@125
   455
	    ide_write_command( (uint8_t)val );
nkeynes@125
   456
	}
nkeynes@125
   457
	break;
nkeynes@334
   458
    case IDEDMASH4:
nkeynes@334
   459
	MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
nkeynes@334
   460
	break;
nkeynes@334
   461
    case IDEDMASIZ:
nkeynes@334
   462
	MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
nkeynes@334
   463
	break;
nkeynes@125
   464
    case IDEDMACTL1:
nkeynes@125
   465
    case IDEDMACTL2:
nkeynes@334
   466
	MMIO_WRITE( EXTDMA, reg, val & 0x01 );
nkeynes@155
   467
	asic_ide_dma_transfer( );
nkeynes@125
   468
	break;
nkeynes@244
   469
    case IDEACTIVATE:
nkeynes@244
   470
	if( val == 0x001FFFFF ) {
nkeynes@244
   471
	    idereg.interface_enabled = TRUE;
nkeynes@244
   472
	    /* Conventional wisdom says that this is necessary but not
nkeynes@244
   473
	     * sufficient to enable the IDE interface.
nkeynes@244
   474
	     */
nkeynes@244
   475
	} else if( val == 0x000042FE ) {
nkeynes@244
   476
	    idereg.interface_enabled = FALSE;
nkeynes@244
   477
	}
nkeynes@279
   478
	break;
nkeynes@302
   479
    case G2DMA0CTL1:
nkeynes@302
   480
    case G2DMA0CTL2:
nkeynes@279
   481
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   482
	g2_dma_transfer( 0 );
nkeynes@279
   483
	break;
nkeynes@302
   484
    case G2DMA0STOP:
nkeynes@279
   485
	break;
nkeynes@302
   486
    case G2DMA1CTL1:
nkeynes@302
   487
    case G2DMA1CTL2:
nkeynes@279
   488
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   489
	g2_dma_transfer( 1 );
nkeynes@279
   490
	break;
nkeynes@279
   491
nkeynes@302
   492
    case G2DMA1STOP:
nkeynes@279
   493
	break;
nkeynes@302
   494
    case G2DMA2CTL1:
nkeynes@302
   495
    case G2DMA2CTL2:
nkeynes@279
   496
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   497
	g2_dma_transfer( 2 );
nkeynes@279
   498
	break;
nkeynes@302
   499
    case G2DMA2STOP:
nkeynes@279
   500
	break;
nkeynes@302
   501
    case G2DMA3CTL1:
nkeynes@302
   502
    case G2DMA3CTL2:
nkeynes@279
   503
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   504
	g2_dma_transfer( 3 );
nkeynes@279
   505
	break;
nkeynes@302
   506
    case G2DMA3STOP:
nkeynes@279
   507
	break;
nkeynes@279
   508
    case PVRDMA2CTL1:
nkeynes@279
   509
    case PVRDMA2CTL2:
nkeynes@279
   510
	if( val != 0 ) {
nkeynes@279
   511
	    ERROR( "Write to unimplemented DMA control register %08X", reg );
nkeynes@279
   512
	    //dreamcast_stop();
nkeynes@279
   513
	    //sh4_stop();
nkeynes@279
   514
	}
nkeynes@279
   515
	break;
nkeynes@125
   516
    default:
nkeynes@2
   517
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   518
    }
nkeynes@1
   519
}
nkeynes@1
   520
nkeynes@1
   521
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   522
{
nkeynes@56
   523
    uint32_t val;
nkeynes@244
   524
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   525
	return 0xFFFFFFFF; /* disabled */
nkeynes@244
   526
    }
nkeynes@244
   527
nkeynes@1
   528
    switch( reg ) {
nkeynes@158
   529
    case IDEALTSTATUS: 
nkeynes@158
   530
	val = idereg.status;
nkeynes@158
   531
	return val;
nkeynes@158
   532
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   533
    case IDEFEAT: return idereg.error;
nkeynes@158
   534
    case IDECOUNT:return idereg.count;
nkeynes@158
   535
    case IDELBA0: return idereg.disc;
nkeynes@158
   536
    case IDELBA1: return idereg.lba1;
nkeynes@158
   537
    case IDELBA2: return idereg.lba2;
nkeynes@158
   538
    case IDEDEV: return idereg.device;
nkeynes@158
   539
    case IDECMD:
nkeynes@158
   540
	val = ide_read_status();
nkeynes@158
   541
	return val;
nkeynes@158
   542
    default:
nkeynes@158
   543
	val = MMIO_READ( EXTDMA, reg );
nkeynes@158
   544
	return val;
nkeynes@1
   545
    }
nkeynes@1
   546
}
nkeynes@1
   547
.