nkeynes@378 | 1 | /**
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nkeynes@561 | 2 | * $Id$
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nkeynes@378 | 3 | *
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nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral
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nkeynes@378 | 5 | * modules.
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nkeynes@378 | 6 | *
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nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@378 | 8 | *
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nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@378 | 12 | * (at your option) any later version.
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nkeynes@378 | 13 | *
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nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@378 | 17 | * GNU General Public License for more details.
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nkeynes@378 | 18 | */
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nkeynes@378 | 19 |
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nkeynes@378 | 20 | #define MODULE sh4_module
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nkeynes@378 | 21 | #include <math.h>
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nkeynes@378 | 22 | #include "dream.h"
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nkeynes@422 | 23 | #include "dreamcast.h"
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nkeynes@378 | 24 | #include "sh4/sh4core.h"
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nkeynes@378 | 25 | #include "sh4/sh4mmio.h"
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nkeynes@378 | 26 | #include "sh4/intc.h"
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nkeynes@422 | 27 | #include "sh4/xltcache.h"
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nkeynes@422 | 28 | #include "sh4/sh4stat.h"
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nkeynes@378 | 29 | #include "mem.h"
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nkeynes@378 | 30 | #include "clock.h"
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nkeynes@378 | 31 | #include "syscall.h"
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nkeynes@378 | 32 |
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nkeynes@378 | 33 | void sh4_init( void );
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nkeynes@526 | 34 | void sh4_xlat_init( void );
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nkeynes@378 | 35 | void sh4_reset( void );
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nkeynes@378 | 36 | void sh4_start( void );
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nkeynes@378 | 37 | void sh4_stop( void );
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nkeynes@378 | 38 | void sh4_save_state( FILE *f );
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nkeynes@378 | 39 | int sh4_load_state( FILE *f );
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nkeynes@378 | 40 |
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nkeynes@378 | 41 | uint32_t sh4_run_slice( uint32_t );
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nkeynes@378 | 42 | uint32_t sh4_xlat_run_slice( uint32_t );
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nkeynes@378 | 43 |
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nkeynes@378 | 44 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
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nkeynes@378 | 45 | NULL, sh4_run_slice, sh4_stop,
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nkeynes@378 | 46 | sh4_save_state, sh4_load_state };
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nkeynes@378 | 47 |
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nkeynes@378 | 48 | struct sh4_registers sh4r;
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nkeynes@378 | 49 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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nkeynes@378 | 50 | int sh4_breakpoint_count = 0;
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nkeynes@502 | 51 | extern sh4ptr_t sh4_main_ram;
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nkeynes@526 | 52 | static gboolean sh4_use_translator = FALSE;
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nkeynes@378 | 53 |
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nkeynes@566 | 54 | struct sh4_icache_info {
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nkeynes@566 | 55 | char *page;
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nkeynes@566 | 56 | uint32_t page_start;
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nkeynes@566 | 57 | uint32_t page_size;
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nkeynes@566 | 58 | };
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nkeynes@566 | 59 |
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nkeynes@566 | 60 | extern struct sh4_icache_info sh4_icache;
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nkeynes@566 | 61 |
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nkeynes@566 | 62 | // struct sh4_icache_info sh4_icache = { NULL, -1, -1 };
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nkeynes@566 | 63 |
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nkeynes@378 | 64 | void sh4_set_use_xlat( gboolean use )
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nkeynes@378 | 65 | {
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nkeynes@526 | 66 | // No-op if the translator was not built
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nkeynes@526 | 67 | #ifdef SH4_TRANSLATOR
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nkeynes@378 | 68 | if( use ) {
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nkeynes@378 | 69 | xlat_cache_init();
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nkeynes@378 | 70 | sh4_x86_init();
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nkeynes@378 | 71 | sh4_module.run_time_slice = sh4_xlat_run_slice;
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nkeynes@378 | 72 | } else {
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nkeynes@378 | 73 | sh4_module.run_time_slice = sh4_run_slice;
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nkeynes@378 | 74 | }
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nkeynes@526 | 75 | sh4_use_translator = use;
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nkeynes@526 | 76 | #endif
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nkeynes@378 | 77 | }
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nkeynes@378 | 78 |
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nkeynes@378 | 79 | void sh4_init(void)
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nkeynes@378 | 80 | {
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nkeynes@378 | 81 | register_io_regions( mmio_list_sh4mmio );
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nkeynes@418 | 82 | sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
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nkeynes@378 | 83 | MMU_init();
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nkeynes@378 | 84 | sh4_reset();
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nkeynes@378 | 85 | }
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nkeynes@378 | 86 |
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nkeynes@378 | 87 | void sh4_reset(void)
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nkeynes@378 | 88 | {
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nkeynes@526 | 89 | if( sh4_use_translator ) {
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nkeynes@472 | 90 | xlat_flush_cache();
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nkeynes@472 | 91 | }
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nkeynes@472 | 92 |
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nkeynes@378 | 93 | /* zero everything out, for the sake of having a consistent state. */
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nkeynes@378 | 94 | memset( &sh4r, 0, sizeof(sh4r) );
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nkeynes@378 | 95 |
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nkeynes@378 | 96 | /* Resume running if we were halted */
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nkeynes@378 | 97 | sh4r.sh4_state = SH4_STATE_RUNNING;
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nkeynes@378 | 98 |
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nkeynes@378 | 99 | sh4r.pc = 0xA0000000;
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nkeynes@378 | 100 | sh4r.new_pc= 0xA0000002;
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nkeynes@378 | 101 | sh4r.vbr = 0x00000000;
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nkeynes@378 | 102 | sh4r.fpscr = 0x00040001;
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nkeynes@378 | 103 | sh4r.sr = 0x700000F0;
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nkeynes@378 | 104 | sh4r.fr_bank = &sh4r.fr[0][0];
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nkeynes@378 | 105 |
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nkeynes@378 | 106 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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nkeynes@378 | 107 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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nkeynes@378 | 108 |
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nkeynes@378 | 109 | /* Peripheral modules */
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nkeynes@378 | 110 | CPG_reset();
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nkeynes@378 | 111 | INTC_reset();
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nkeynes@378 | 112 | MMU_reset();
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nkeynes@378 | 113 | TMU_reset();
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nkeynes@378 | 114 | SCIF_reset();
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nkeynes@401 | 115 | sh4_stats_reset();
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nkeynes@378 | 116 | }
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nkeynes@378 | 117 |
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nkeynes@378 | 118 | void sh4_stop(void)
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nkeynes@378 | 119 | {
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nkeynes@526 | 120 | if( sh4_use_translator ) {
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nkeynes@502 | 121 | /* If we were running with the translator, update new_pc and in_delay_slot */
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nkeynes@502 | 122 | sh4r.new_pc = sh4r.pc+2;
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nkeynes@502 | 123 | sh4r.in_delay_slot = FALSE;
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nkeynes@502 | 124 | }
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nkeynes@378 | 125 |
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nkeynes@378 | 126 | }
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nkeynes@378 | 127 |
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nkeynes@378 | 128 | void sh4_save_state( FILE *f )
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nkeynes@378 | 129 | {
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nkeynes@526 | 130 | if( sh4_use_translator ) {
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nkeynes@401 | 131 | /* If we were running with the translator, update new_pc and in_delay_slot */
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nkeynes@401 | 132 | sh4r.new_pc = sh4r.pc+2;
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nkeynes@401 | 133 | sh4r.in_delay_slot = FALSE;
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nkeynes@401 | 134 | }
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nkeynes@401 | 135 |
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nkeynes@378 | 136 | fwrite( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@378 | 137 | MMU_save_state( f );
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nkeynes@378 | 138 | INTC_save_state( f );
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nkeynes@378 | 139 | TMU_save_state( f );
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nkeynes@378 | 140 | SCIF_save_state( f );
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nkeynes@378 | 141 | }
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nkeynes@378 | 142 |
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nkeynes@378 | 143 | int sh4_load_state( FILE * f )
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nkeynes@378 | 144 | {
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nkeynes@526 | 145 | if( sh4_use_translator ) {
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nkeynes@472 | 146 | xlat_flush_cache();
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nkeynes@472 | 147 | }
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nkeynes@378 | 148 | fread( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@412 | 149 | sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
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nkeynes@378 | 150 | MMU_load_state( f );
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nkeynes@378 | 151 | INTC_load_state( f );
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nkeynes@378 | 152 | TMU_load_state( f );
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nkeynes@378 | 153 | return SCIF_load_state( f );
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nkeynes@378 | 154 | }
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nkeynes@378 | 155 |
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nkeynes@378 | 156 |
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nkeynes@566 | 157 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
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nkeynes@378 | 158 | {
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nkeynes@378 | 159 | sh4_breakpoints[sh4_breakpoint_count].address = pc;
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nkeynes@378 | 160 | sh4_breakpoints[sh4_breakpoint_count].type = type;
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nkeynes@378 | 161 | sh4_breakpoint_count++;
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nkeynes@378 | 162 | }
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nkeynes@378 | 163 |
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nkeynes@566 | 164 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
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nkeynes@378 | 165 | {
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nkeynes@378 | 166 | int i;
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nkeynes@378 | 167 |
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nkeynes@378 | 168 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@378 | 169 | if( sh4_breakpoints[i].address == pc &&
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nkeynes@378 | 170 | sh4_breakpoints[i].type == type ) {
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nkeynes@378 | 171 | while( ++i < sh4_breakpoint_count ) {
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nkeynes@378 | 172 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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nkeynes@378 | 173 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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nkeynes@378 | 174 | }
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nkeynes@378 | 175 | sh4_breakpoint_count--;
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nkeynes@378 | 176 | return TRUE;
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nkeynes@378 | 177 | }
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nkeynes@378 | 178 | }
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nkeynes@378 | 179 | return FALSE;
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nkeynes@378 | 180 | }
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nkeynes@378 | 181 |
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nkeynes@378 | 182 | int sh4_get_breakpoint( uint32_t pc )
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nkeynes@378 | 183 | {
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nkeynes@378 | 184 | int i;
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nkeynes@378 | 185 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@378 | 186 | if( sh4_breakpoints[i].address == pc )
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nkeynes@378 | 187 | return sh4_breakpoints[i].type;
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nkeynes@378 | 188 | }
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nkeynes@378 | 189 | return 0;
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nkeynes@378 | 190 | }
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nkeynes@378 | 191 |
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nkeynes@401 | 192 | void sh4_set_pc( int pc )
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nkeynes@401 | 193 | {
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nkeynes@401 | 194 | sh4r.pc = pc;
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nkeynes@401 | 195 | sh4r.new_pc = pc+2;
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nkeynes@401 | 196 | }
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nkeynes@401 | 197 |
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nkeynes@401 | 198 |
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nkeynes@401 | 199 | /******************************* Support methods ***************************/
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nkeynes@401 | 200 |
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nkeynes@401 | 201 | static void sh4_switch_banks( )
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nkeynes@401 | 202 | {
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nkeynes@401 | 203 | uint32_t tmp[8];
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nkeynes@401 | 204 |
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nkeynes@401 | 205 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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nkeynes@401 | 206 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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nkeynes@401 | 207 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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nkeynes@401 | 208 | }
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nkeynes@401 | 209 |
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nkeynes@401 | 210 | void sh4_write_sr( uint32_t newval )
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nkeynes@401 | 211 | {
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nkeynes@401 | 212 | if( (newval ^ sh4r.sr) & SR_RB )
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nkeynes@401 | 213 | sh4_switch_banks();
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nkeynes@401 | 214 | sh4r.sr = newval;
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nkeynes@401 | 215 | sh4r.t = (newval&SR_T) ? 1 : 0;
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nkeynes@401 | 216 | sh4r.s = (newval&SR_S) ? 1 : 0;
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nkeynes@401 | 217 | sh4r.m = (newval&SR_M) ? 1 : 0;
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nkeynes@401 | 218 | sh4r.q = (newval&SR_Q) ? 1 : 0;
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nkeynes@401 | 219 | intc_mask_changed();
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nkeynes@401 | 220 | }
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nkeynes@401 | 221 |
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nkeynes@401 | 222 | uint32_t sh4_read_sr( void )
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nkeynes@401 | 223 | {
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nkeynes@401 | 224 | /* synchronize sh4r.sr with the various bitflags */
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nkeynes@401 | 225 | sh4r.sr &= SR_MQSTMASK;
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nkeynes@401 | 226 | if( sh4r.t ) sh4r.sr |= SR_T;
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nkeynes@401 | 227 | if( sh4r.s ) sh4r.sr |= SR_S;
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nkeynes@401 | 228 | if( sh4r.m ) sh4r.sr |= SR_M;
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nkeynes@401 | 229 | if( sh4r.q ) sh4r.sr |= SR_Q;
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nkeynes@401 | 230 | return sh4r.sr;
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nkeynes@401 | 231 | }
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nkeynes@401 | 232 |
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nkeynes@401 | 233 |
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nkeynes@401 | 234 |
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nkeynes@401 | 235 | #define RAISE( x, v ) do{ \
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nkeynes@401 | 236 | if( sh4r.vbr == 0 ) { \
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nkeynes@401 | 237 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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nkeynes@401 | 238 | dreamcast_stop(); return FALSE; \
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nkeynes@401 | 239 | } else { \
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nkeynes@401 | 240 | sh4r.spc = sh4r.pc; \
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nkeynes@401 | 241 | sh4r.ssr = sh4_read_sr(); \
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nkeynes@401 | 242 | sh4r.sgr = sh4r.r[15]; \
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nkeynes@401 | 243 | MMIO_WRITE(MMU,EXPEVT,x); \
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nkeynes@401 | 244 | sh4r.pc = sh4r.vbr + v; \
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nkeynes@401 | 245 | sh4r.new_pc = sh4r.pc + 2; \
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nkeynes@401 | 246 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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nkeynes@401 | 247 | if( sh4r.in_delay_slot ) { \
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nkeynes@401 | 248 | sh4r.in_delay_slot = 0; \
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nkeynes@401 | 249 | sh4r.spc -= 2; \
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nkeynes@401 | 250 | } \
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nkeynes@401 | 251 | } \
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nkeynes@401 | 252 | return TRUE; } while(0)
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nkeynes@401 | 253 |
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nkeynes@401 | 254 | /**
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nkeynes@401 | 255 | * Raise a general CPU exception for the specified exception code.
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nkeynes@401 | 256 | * (NOT for TRAPA or TLB exceptions)
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nkeynes@401 | 257 | */
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nkeynes@401 | 258 | gboolean sh4_raise_exception( int code )
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nkeynes@401 | 259 | {
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nkeynes@401 | 260 | RAISE( code, EXV_EXCEPTION );
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nkeynes@401 | 261 | }
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nkeynes@401 | 262 |
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nkeynes@559 | 263 | /**
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nkeynes@559 | 264 | * Raise a CPU reset exception with the specified exception code.
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nkeynes@559 | 265 | */
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nkeynes@559 | 266 | gboolean sh4_raise_reset( int code )
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nkeynes@559 | 267 | {
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nkeynes@559 | 268 | // FIXME: reset modules as per "manual reset"
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nkeynes@559 | 269 | sh4_reset();
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nkeynes@559 | 270 | MMIO_WRITE(MMU,EXPEVT,code);
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nkeynes@559 | 271 | sh4r.vbr = 0;
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nkeynes@559 | 272 | sh4r.pc = 0xA0000000;
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nkeynes@559 | 273 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@559 | 274 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
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nkeynes@559 | 275 | &(~SR_FD) );
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nkeynes@559 | 276 | }
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nkeynes@559 | 277 |
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nkeynes@401 | 278 | gboolean sh4_raise_trap( int trap )
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nkeynes@401 | 279 | {
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nkeynes@401 | 280 | MMIO_WRITE( MMU, TRA, trap<<2 );
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nkeynes@401 | 281 | return sh4_raise_exception( EXC_TRAP );
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nkeynes@401 | 282 | }
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nkeynes@401 | 283 |
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nkeynes@401 | 284 | gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
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nkeynes@401 | 285 | if( sh4r.in_delay_slot ) {
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nkeynes@401 | 286 | return sh4_raise_exception(slot_code);
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nkeynes@401 | 287 | } else {
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nkeynes@401 | 288 | return sh4_raise_exception(normal_code);
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nkeynes@401 | 289 | }
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nkeynes@401 | 290 | }
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nkeynes@401 | 291 |
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nkeynes@401 | 292 | gboolean sh4_raise_tlb_exception( int code )
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nkeynes@401 | 293 | {
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nkeynes@401 | 294 | RAISE( code, EXV_TLBMISS );
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nkeynes@401 | 295 | }
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nkeynes@401 | 296 |
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nkeynes@401 | 297 | void sh4_accept_interrupt( void )
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nkeynes@401 | 298 | {
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nkeynes@401 | 299 | uint32_t code = intc_accept_interrupt();
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nkeynes@401 | 300 | sh4r.ssr = sh4_read_sr();
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nkeynes@401 | 301 | sh4r.spc = sh4r.pc;
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nkeynes@401 | 302 | sh4r.sgr = sh4r.r[15];
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nkeynes@401 | 303 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
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nkeynes@401 | 304 | MMIO_WRITE( MMU, INTEVT, code );
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nkeynes@401 | 305 | sh4r.pc = sh4r.vbr + 0x600;
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nkeynes@401 | 306 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@401 | 307 | // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
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nkeynes@401 | 308 | }
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nkeynes@401 | 309 |
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nkeynes@401 | 310 | void signsat48( void )
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nkeynes@401 | 311 | {
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nkeynes@401 | 312 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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nkeynes@401 | 313 | sh4r.mac = 0xFFFF800000000000LL;
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nkeynes@401 | 314 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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nkeynes@401 | 315 | sh4r.mac = 0x00007FFFFFFFFFFFLL;
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nkeynes@401 | 316 | }
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nkeynes@401 | 317 |
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nkeynes@401 | 318 | void sh4_fsca( uint32_t anglei, float *fr )
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nkeynes@401 | 319 | {
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nkeynes@401 | 320 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
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nkeynes@401 | 321 | *fr++ = cosf(angle);
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nkeynes@401 | 322 | *fr = sinf(angle);
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nkeynes@401 | 323 | }
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nkeynes@401 | 324 |
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nkeynes@401 | 325 | void sh4_sleep(void)
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nkeynes@401 | 326 | {
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nkeynes@401 | 327 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
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nkeynes@401 | 328 | sh4r.sh4_state = SH4_STATE_STANDBY;
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nkeynes@401 | 329 | } else {
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nkeynes@401 | 330 | sh4r.sh4_state = SH4_STATE_SLEEP;
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nkeynes@401 | 331 | }
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nkeynes@401 | 332 | }
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nkeynes@401 | 333 |
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nkeynes@401 | 334 | /**
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nkeynes@401 | 335 | * Compute the matrix tranform of fv given the matrix xf.
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nkeynes@401 | 336 | * Both fv and xf are word-swapped as per the sh4r.fr banks
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nkeynes@401 | 337 | */
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nkeynes@401 | 338 | void sh4_ftrv( float *target, float *xf )
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nkeynes@401 | 339 | {
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nkeynes@401 | 340 | float fv[4] = { target[1], target[0], target[3], target[2] };
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nkeynes@401 | 341 | target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
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nkeynes@401 | 342 | xf[9]*fv[2] + xf[13]*fv[3];
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nkeynes@401 | 343 | target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
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nkeynes@401 | 344 | xf[8]*fv[2] + xf[12]*fv[3];
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nkeynes@401 | 345 | target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
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nkeynes@401 | 346 | xf[11]*fv[2] + xf[15]*fv[3];
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nkeynes@401 | 347 | target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
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nkeynes@401 | 348 | xf[10]*fv[2] + xf[14]*fv[3];
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nkeynes@401 | 349 | }
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nkeynes@401 | 350 |
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