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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 904:5b92e51ac06b
prev903:1337c7a7dd6b
next905:4c17ebd9ef5e
author nkeynes
date Wed Oct 29 23:36:31 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Enable the FIPR SSE3 code for now, and add a comment on the sh4r.fr alignment
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    // Note: Include the push/pop ebx sequence in case of PIC builds. This 
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    // isn't exactly on a critical path anyway
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    __asm__ __volatile__(
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        "pushl %%ebx\n\t"
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t"
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        "popl %%ebx" : "=c" (features) : : "eax", "edx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   311
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   312
 */
nkeynes@586
   313
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   314
nkeynes@586
   315
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   316
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   317
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   318
nkeynes@590
   319
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   320
nkeynes@539
   321
/****** Import appropriate calling conventions ******/
nkeynes@675
   322
#if SIZEOF_VOID_P == 8
nkeynes@539
   323
#include "sh4/ia64abi.h"
nkeynes@675
   324
#else /* 32-bit system */
nkeynes@539
   325
#ifdef APPLE_BUILD
nkeynes@539
   326
#include "sh4/ia32mac.h"
nkeynes@539
   327
#else
nkeynes@539
   328
#include "sh4/ia32abi.h"
nkeynes@539
   329
#endif
nkeynes@539
   330
#endif
nkeynes@539
   331
nkeynes@901
   332
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   333
{
nkeynes@901
   334
	enter_block();
nkeynes@901
   335
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   336
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   337
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   338
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   339
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   340
    sh4_x86.block_start_pc = pc;
nkeynes@901
   341
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   343
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   344
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   345
}
nkeynes@901
   346
nkeynes@901
   347
nkeynes@593
   348
uint32_t sh4_translate_end_block_size()
nkeynes@593
   349
{
nkeynes@596
   350
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   351
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   352
    } else {
nkeynes@901
   353
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   354
    }
nkeynes@593
   355
}
nkeynes@593
   356
nkeynes@593
   357
nkeynes@590
   358
/**
nkeynes@590
   359
 * Embed a breakpoint into the generated code
nkeynes@590
   360
 */
nkeynes@586
   361
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   362
{
nkeynes@591
   363
    load_imm32( R_EAX, pc );
nkeynes@591
   364
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   365
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   366
}
nkeynes@590
   367
nkeynes@601
   368
nkeynes@601
   369
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   370
nkeynes@590
   371
/**
nkeynes@590
   372
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   373
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   374
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   375
 *
nkeynes@601
   376
 * Performs:
nkeynes@601
   377
 *   Set PC = endpc
nkeynes@601
   378
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   379
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   380
 *   Call sh4_execute_instruction
nkeynes@601
   381
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   382
 */
nkeynes@601
   383
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   384
{
nkeynes@590
   385
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   386
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   387
    
nkeynes@601
   388
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   389
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   390
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   391
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   392
nkeynes@590
   393
    call_func0( sh4_execute_instruction );    
nkeynes@601
   394
    load_spreg( R_EAX, R_PC );
nkeynes@590
   395
    if( sh4_x86.tlb_on ) {
nkeynes@590
   396
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   397
    } else {
nkeynes@590
   398
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   399
    }
nkeynes@601
   400
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   401
    POP_r32(R_EBP);
nkeynes@590
   402
    RET();
nkeynes@590
   403
} 
nkeynes@539
   404
nkeynes@359
   405
/**
nkeynes@359
   406
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   407
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   408
 * 
nkeynes@586
   409
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   410
 *
nkeynes@359
   411
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   412
 * (eg a branch or 
nkeynes@359
   413
 */
nkeynes@590
   414
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   415
{
nkeynes@388
   416
    uint32_t ir;
nkeynes@586
   417
    /* Read instruction from icache */
nkeynes@586
   418
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   419
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   420
    
nkeynes@586
   421
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   422
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   423
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   424
	 * almost certainly in a delay slot.
nkeynes@586
   425
	 *
nkeynes@586
   426
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   427
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   428
	 * small repairs to cope with the different environment).
nkeynes@586
   429
	 */
nkeynes@586
   430
nkeynes@586
   431
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   432
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   433
    }
nkeynes@359
   434
%%
nkeynes@359
   435
/* ALU operations */
nkeynes@359
   436
ADD Rm, Rn {:
nkeynes@671
   437
    COUNT_INST(I_ADD);
nkeynes@359
   438
    load_reg( R_EAX, Rm );
nkeynes@359
   439
    load_reg( R_ECX, Rn );
nkeynes@359
   440
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   441
    store_reg( R_ECX, Rn );
nkeynes@417
   442
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   443
:}
nkeynes@359
   444
ADD #imm, Rn {:  
nkeynes@671
   445
    COUNT_INST(I_ADDI);
nkeynes@359
   446
    load_reg( R_EAX, Rn );
nkeynes@359
   447
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   448
    store_reg( R_EAX, Rn );
nkeynes@417
   449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   450
:}
nkeynes@359
   451
ADDC Rm, Rn {:
nkeynes@671
   452
    COUNT_INST(I_ADDC);
nkeynes@417
   453
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   454
	LDC_t();
nkeynes@417
   455
    }
nkeynes@359
   456
    load_reg( R_EAX, Rm );
nkeynes@359
   457
    load_reg( R_ECX, Rn );
nkeynes@359
   458
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   459
    store_reg( R_ECX, Rn );
nkeynes@359
   460
    SETC_t();
nkeynes@417
   461
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   462
:}
nkeynes@359
   463
ADDV Rm, Rn {:
nkeynes@671
   464
    COUNT_INST(I_ADDV);
nkeynes@359
   465
    load_reg( R_EAX, Rm );
nkeynes@359
   466
    load_reg( R_ECX, Rn );
nkeynes@359
   467
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   468
    store_reg( R_ECX, Rn );
nkeynes@359
   469
    SETO_t();
nkeynes@417
   470
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   471
:}
nkeynes@359
   472
AND Rm, Rn {:
nkeynes@671
   473
    COUNT_INST(I_AND);
nkeynes@359
   474
    load_reg( R_EAX, Rm );
nkeynes@359
   475
    load_reg( R_ECX, Rn );
nkeynes@359
   476
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   477
    store_reg( R_ECX, Rn );
nkeynes@417
   478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   479
:}
nkeynes@359
   480
AND #imm, R0 {:  
nkeynes@671
   481
    COUNT_INST(I_ANDI);
nkeynes@359
   482
    load_reg( R_EAX, 0 );
nkeynes@359
   483
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   484
    store_reg( R_EAX, 0 );
nkeynes@417
   485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   486
:}
nkeynes@359
   487
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   488
    COUNT_INST(I_ANDB);
nkeynes@359
   489
    load_reg( R_EAX, 0 );
nkeynes@359
   490
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   491
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   492
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   493
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   494
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   495
    POP_realigned_r32(R_ECX);
nkeynes@386
   496
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   497
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/EQ Rm, Rn {:  
nkeynes@671
   501
    COUNT_INST(I_CMPEQ);
nkeynes@359
   502
    load_reg( R_EAX, Rm );
nkeynes@359
   503
    load_reg( R_ECX, Rn );
nkeynes@359
   504
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   505
    SETE_t();
nkeynes@417
   506
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   507
:}
nkeynes@359
   508
CMP/EQ #imm, R0 {:  
nkeynes@671
   509
    COUNT_INST(I_CMPEQI);
nkeynes@359
   510
    load_reg( R_EAX, 0 );
nkeynes@359
   511
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   512
    SETE_t();
nkeynes@417
   513
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   514
:}
nkeynes@359
   515
CMP/GE Rm, Rn {:  
nkeynes@671
   516
    COUNT_INST(I_CMPGE);
nkeynes@359
   517
    load_reg( R_EAX, Rm );
nkeynes@359
   518
    load_reg( R_ECX, Rn );
nkeynes@359
   519
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   520
    SETGE_t();
nkeynes@417
   521
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   522
:}
nkeynes@359
   523
CMP/GT Rm, Rn {: 
nkeynes@671
   524
    COUNT_INST(I_CMPGT);
nkeynes@359
   525
    load_reg( R_EAX, Rm );
nkeynes@359
   526
    load_reg( R_ECX, Rn );
nkeynes@359
   527
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   528
    SETG_t();
nkeynes@417
   529
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   530
:}
nkeynes@359
   531
CMP/HI Rm, Rn {:  
nkeynes@671
   532
    COUNT_INST(I_CMPHI);
nkeynes@359
   533
    load_reg( R_EAX, Rm );
nkeynes@359
   534
    load_reg( R_ECX, Rn );
nkeynes@359
   535
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   536
    SETA_t();
nkeynes@417
   537
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   538
:}
nkeynes@359
   539
CMP/HS Rm, Rn {: 
nkeynes@671
   540
    COUNT_INST(I_CMPHS);
nkeynes@359
   541
    load_reg( R_EAX, Rm );
nkeynes@359
   542
    load_reg( R_ECX, Rn );
nkeynes@359
   543
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   544
    SETAE_t();
nkeynes@417
   545
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   546
 :}
nkeynes@359
   547
CMP/PL Rn {: 
nkeynes@671
   548
    COUNT_INST(I_CMPPL);
nkeynes@359
   549
    load_reg( R_EAX, Rn );
nkeynes@359
   550
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   551
    SETG_t();
nkeynes@417
   552
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   553
:}
nkeynes@359
   554
CMP/PZ Rn {:  
nkeynes@671
   555
    COUNT_INST(I_CMPPZ);
nkeynes@359
   556
    load_reg( R_EAX, Rn );
nkeynes@359
   557
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   558
    SETGE_t();
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   560
:}
nkeynes@361
   561
CMP/STR Rm, Rn {:  
nkeynes@671
   562
    COUNT_INST(I_CMPSTR);
nkeynes@368
   563
    load_reg( R_EAX, Rm );
nkeynes@368
   564
    load_reg( R_ECX, Rn );
nkeynes@368
   565
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   566
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   567
    JE_rel8(target1);
nkeynes@669
   568
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   569
    JE_rel8(target2);
nkeynes@669
   570
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   571
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   572
    JE_rel8(target3);
nkeynes@669
   573
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   574
    JMP_TARGET(target1);
nkeynes@380
   575
    JMP_TARGET(target2);
nkeynes@380
   576
    JMP_TARGET(target3);
nkeynes@368
   577
    SETE_t();
nkeynes@417
   578
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   579
:}
nkeynes@361
   580
DIV0S Rm, Rn {:
nkeynes@671
   581
    COUNT_INST(I_DIV0S);
nkeynes@361
   582
    load_reg( R_EAX, Rm );
nkeynes@386
   583
    load_reg( R_ECX, Rn );
nkeynes@361
   584
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   585
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   586
    store_spreg( R_EAX, R_M );
nkeynes@361
   587
    store_spreg( R_ECX, R_Q );
nkeynes@361
   588
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   589
    SETNE_t();
nkeynes@417
   590
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   591
:}
nkeynes@361
   592
DIV0U {:  
nkeynes@671
   593
    COUNT_INST(I_DIV0U);
nkeynes@361
   594
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   595
    store_spreg( R_EAX, R_Q );
nkeynes@361
   596
    store_spreg( R_EAX, R_M );
nkeynes@361
   597
    store_spreg( R_EAX, R_T );
nkeynes@417
   598
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   599
:}
nkeynes@386
   600
DIV1 Rm, Rn {:
nkeynes@671
   601
    COUNT_INST(I_DIV1);
nkeynes@386
   602
    load_spreg( R_ECX, R_M );
nkeynes@386
   603
    load_reg( R_EAX, Rn );
nkeynes@417
   604
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   605
	LDC_t();
nkeynes@417
   606
    }
nkeynes@386
   607
    RCL1_r32( R_EAX );
nkeynes@386
   608
    SETC_r8( R_DL ); // Q'
nkeynes@386
   609
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   610
    JE_rel8(mqequal);
nkeynes@386
   611
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   612
    JMP_rel8(end);
nkeynes@380
   613
    JMP_TARGET(mqequal);
nkeynes@386
   614
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   615
    JMP_TARGET(end);
nkeynes@386
   616
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   617
    SETC_r8(R_AL); // tmp1
nkeynes@386
   618
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   619
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   620
    store_spreg( R_ECX, R_Q );
nkeynes@386
   621
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   622
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   623
    store_spreg( R_EAX, R_T );
nkeynes@417
   624
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   625
:}
nkeynes@361
   626
DMULS.L Rm, Rn {:  
nkeynes@671
   627
    COUNT_INST(I_DMULS);
nkeynes@361
   628
    load_reg( R_EAX, Rm );
nkeynes@361
   629
    load_reg( R_ECX, Rn );
nkeynes@361
   630
    IMUL_r32(R_ECX);
nkeynes@361
   631
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   632
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   633
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   634
:}
nkeynes@361
   635
DMULU.L Rm, Rn {:  
nkeynes@671
   636
    COUNT_INST(I_DMULU);
nkeynes@361
   637
    load_reg( R_EAX, Rm );
nkeynes@361
   638
    load_reg( R_ECX, Rn );
nkeynes@361
   639
    MUL_r32(R_ECX);
nkeynes@361
   640
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   641
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   642
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   643
:}
nkeynes@359
   644
DT Rn {:  
nkeynes@671
   645
    COUNT_INST(I_DT);
nkeynes@359
   646
    load_reg( R_EAX, Rn );
nkeynes@382
   647
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   648
    store_reg( R_EAX, Rn );
nkeynes@359
   649
    SETE_t();
nkeynes@417
   650
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   651
:}
nkeynes@359
   652
EXTS.B Rm, Rn {:  
nkeynes@671
   653
    COUNT_INST(I_EXTSB);
nkeynes@359
   654
    load_reg( R_EAX, Rm );
nkeynes@359
   655
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   656
    store_reg( R_EAX, Rn );
nkeynes@359
   657
:}
nkeynes@361
   658
EXTS.W Rm, Rn {:  
nkeynes@671
   659
    COUNT_INST(I_EXTSW);
nkeynes@361
   660
    load_reg( R_EAX, Rm );
nkeynes@361
   661
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   662
    store_reg( R_EAX, Rn );
nkeynes@361
   663
:}
nkeynes@361
   664
EXTU.B Rm, Rn {:  
nkeynes@671
   665
    COUNT_INST(I_EXTUB);
nkeynes@361
   666
    load_reg( R_EAX, Rm );
nkeynes@361
   667
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   668
    store_reg( R_EAX, Rn );
nkeynes@361
   669
:}
nkeynes@361
   670
EXTU.W Rm, Rn {:  
nkeynes@671
   671
    COUNT_INST(I_EXTUW);
nkeynes@361
   672
    load_reg( R_EAX, Rm );
nkeynes@361
   673
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   674
    store_reg( R_EAX, Rn );
nkeynes@361
   675
:}
nkeynes@586
   676
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   677
    COUNT_INST(I_MACL);
nkeynes@586
   678
    if( Rm == Rn ) {
nkeynes@586
   679
	load_reg( R_EAX, Rm );
nkeynes@586
   680
	check_ralign32( R_EAX );
nkeynes@586
   681
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   682
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   683
	load_reg( R_EAX, Rn );
nkeynes@586
   684
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   685
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   686
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   687
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   688
	// adding a page-boundary check to skip the second translation
nkeynes@586
   689
    } else {
nkeynes@586
   690
	load_reg( R_EAX, Rm );
nkeynes@586
   691
	check_ralign32( R_EAX );
nkeynes@586
   692
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   693
	load_reg( R_ECX, Rn );
nkeynes@596
   694
	check_ralign32( R_ECX );
nkeynes@586
   695
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   696
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   697
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   698
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   699
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   700
    }
nkeynes@586
   701
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   702
    POP_r32( R_ECX );
nkeynes@586
   703
    PUSH_r32( R_EAX );
nkeynes@386
   704
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   705
    POP_realigned_r32( R_ECX );
nkeynes@586
   706
nkeynes@386
   707
    IMUL_r32( R_ECX );
nkeynes@386
   708
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   709
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   710
nkeynes@386
   711
    load_spreg( R_ECX, R_S );
nkeynes@386
   712
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   713
    JE_rel8( nosat );
nkeynes@386
   714
    call_func0( signsat48 );
nkeynes@386
   715
    JMP_TARGET( nosat );
nkeynes@417
   716
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   717
:}
nkeynes@386
   718
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   719
    COUNT_INST(I_MACW);
nkeynes@586
   720
    if( Rm == Rn ) {
nkeynes@586
   721
	load_reg( R_EAX, Rm );
nkeynes@586
   722
	check_ralign16( R_EAX );
nkeynes@586
   723
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   724
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   725
	load_reg( R_EAX, Rn );
nkeynes@586
   726
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   727
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   728
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   729
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   730
	// adding a page-boundary check to skip the second translation
nkeynes@586
   731
    } else {
nkeynes@586
   732
	load_reg( R_EAX, Rm );
nkeynes@586
   733
	check_ralign16( R_EAX );
nkeynes@586
   734
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   735
	load_reg( R_ECX, Rn );
nkeynes@596
   736
	check_ralign16( R_ECX );
nkeynes@586
   737
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   738
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   739
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   740
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   741
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   742
    }
nkeynes@586
   743
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   744
    POP_r32( R_ECX );
nkeynes@586
   745
    PUSH_r32( R_EAX );
nkeynes@386
   746
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   747
    POP_realigned_r32( R_ECX );
nkeynes@386
   748
    IMUL_r32( R_ECX );
nkeynes@386
   749
nkeynes@386
   750
    load_spreg( R_ECX, R_S );
nkeynes@386
   751
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   752
    JE_rel8( nosat );
nkeynes@386
   753
nkeynes@386
   754
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   755
    JNO_rel8( end );            // 2
nkeynes@386
   756
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   757
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   758
    JS_rel8( positive );        // 2
nkeynes@386
   759
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   760
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   761
    JMP_rel8(end2);           // 2
nkeynes@386
   762
nkeynes@386
   763
    JMP_TARGET(positive);
nkeynes@386
   764
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   765
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   766
    JMP_rel8(end3);            // 2
nkeynes@386
   767
nkeynes@386
   768
    JMP_TARGET(nosat);
nkeynes@386
   769
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   770
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   771
    JMP_TARGET(end);
nkeynes@386
   772
    JMP_TARGET(end2);
nkeynes@386
   773
    JMP_TARGET(end3);
nkeynes@417
   774
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   775
:}
nkeynes@359
   776
MOVT Rn {:  
nkeynes@671
   777
    COUNT_INST(I_MOVT);
nkeynes@359
   778
    load_spreg( R_EAX, R_T );
nkeynes@359
   779
    store_reg( R_EAX, Rn );
nkeynes@359
   780
:}
nkeynes@361
   781
MUL.L Rm, Rn {:  
nkeynes@671
   782
    COUNT_INST(I_MULL);
nkeynes@361
   783
    load_reg( R_EAX, Rm );
nkeynes@361
   784
    load_reg( R_ECX, Rn );
nkeynes@361
   785
    MUL_r32( R_ECX );
nkeynes@361
   786
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   788
:}
nkeynes@374
   789
MULS.W Rm, Rn {:
nkeynes@671
   790
    COUNT_INST(I_MULSW);
nkeynes@374
   791
    load_reg16s( R_EAX, Rm );
nkeynes@374
   792
    load_reg16s( R_ECX, Rn );
nkeynes@374
   793
    MUL_r32( R_ECX );
nkeynes@374
   794
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   796
:}
nkeynes@374
   797
MULU.W Rm, Rn {:  
nkeynes@671
   798
    COUNT_INST(I_MULUW);
nkeynes@374
   799
    load_reg16u( R_EAX, Rm );
nkeynes@374
   800
    load_reg16u( R_ECX, Rn );
nkeynes@374
   801
    MUL_r32( R_ECX );
nkeynes@374
   802
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   803
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   804
:}
nkeynes@359
   805
NEG Rm, Rn {:
nkeynes@671
   806
    COUNT_INST(I_NEG);
nkeynes@359
   807
    load_reg( R_EAX, Rm );
nkeynes@359
   808
    NEG_r32( R_EAX );
nkeynes@359
   809
    store_reg( R_EAX, Rn );
nkeynes@417
   810
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   811
:}
nkeynes@359
   812
NEGC Rm, Rn {:  
nkeynes@671
   813
    COUNT_INST(I_NEGC);
nkeynes@359
   814
    load_reg( R_EAX, Rm );
nkeynes@359
   815
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   816
    LDC_t();
nkeynes@359
   817
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   818
    store_reg( R_ECX, Rn );
nkeynes@359
   819
    SETC_t();
nkeynes@417
   820
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   821
:}
nkeynes@359
   822
NOT Rm, Rn {:  
nkeynes@671
   823
    COUNT_INST(I_NOT);
nkeynes@359
   824
    load_reg( R_EAX, Rm );
nkeynes@359
   825
    NOT_r32( R_EAX );
nkeynes@359
   826
    store_reg( R_EAX, Rn );
nkeynes@417
   827
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   828
:}
nkeynes@359
   829
OR Rm, Rn {:  
nkeynes@671
   830
    COUNT_INST(I_OR);
nkeynes@359
   831
    load_reg( R_EAX, Rm );
nkeynes@359
   832
    load_reg( R_ECX, Rn );
nkeynes@359
   833
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   834
    store_reg( R_ECX, Rn );
nkeynes@417
   835
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   836
:}
nkeynes@359
   837
OR #imm, R0 {:
nkeynes@671
   838
    COUNT_INST(I_ORI);
nkeynes@359
   839
    load_reg( R_EAX, 0 );
nkeynes@359
   840
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   841
    store_reg( R_EAX, 0 );
nkeynes@417
   842
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   843
:}
nkeynes@374
   844
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   845
    COUNT_INST(I_ORB);
nkeynes@374
   846
    load_reg( R_EAX, 0 );
nkeynes@374
   847
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   848
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   849
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   850
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   851
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   852
    POP_realigned_r32(R_ECX);
nkeynes@386
   853
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   854
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   855
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   856
:}
nkeynes@359
   857
ROTCL Rn {:
nkeynes@671
   858
    COUNT_INST(I_ROTCL);
nkeynes@359
   859
    load_reg( R_EAX, Rn );
nkeynes@417
   860
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   861
	LDC_t();
nkeynes@417
   862
    }
nkeynes@359
   863
    RCL1_r32( R_EAX );
nkeynes@359
   864
    store_reg( R_EAX, Rn );
nkeynes@359
   865
    SETC_t();
nkeynes@417
   866
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   867
:}
nkeynes@359
   868
ROTCR Rn {:  
nkeynes@671
   869
    COUNT_INST(I_ROTCR);
nkeynes@359
   870
    load_reg( R_EAX, Rn );
nkeynes@417
   871
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   872
	LDC_t();
nkeynes@417
   873
    }
nkeynes@359
   874
    RCR1_r32( R_EAX );
nkeynes@359
   875
    store_reg( R_EAX, Rn );
nkeynes@359
   876
    SETC_t();
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   878
:}
nkeynes@359
   879
ROTL Rn {:  
nkeynes@671
   880
    COUNT_INST(I_ROTL);
nkeynes@359
   881
    load_reg( R_EAX, Rn );
nkeynes@359
   882
    ROL1_r32( R_EAX );
nkeynes@359
   883
    store_reg( R_EAX, Rn );
nkeynes@359
   884
    SETC_t();
nkeynes@417
   885
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   886
:}
nkeynes@359
   887
ROTR Rn {:  
nkeynes@671
   888
    COUNT_INST(I_ROTR);
nkeynes@359
   889
    load_reg( R_EAX, Rn );
nkeynes@359
   890
    ROR1_r32( R_EAX );
nkeynes@359
   891
    store_reg( R_EAX, Rn );
nkeynes@359
   892
    SETC_t();
nkeynes@417
   893
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   894
:}
nkeynes@359
   895
SHAD Rm, Rn {:
nkeynes@671
   896
    COUNT_INST(I_SHAD);
nkeynes@359
   897
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   898
    load_reg( R_EAX, Rn );
nkeynes@361
   899
    load_reg( R_ECX, Rm );
nkeynes@361
   900
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   901
    JGE_rel8(doshl);
nkeynes@361
   902
                    
nkeynes@361
   903
    NEG_r32( R_ECX );      // 2
nkeynes@361
   904
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   905
    JE_rel8(emptysar);     // 2
nkeynes@361
   906
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   907
    JMP_rel8(end);          // 2
nkeynes@386
   908
nkeynes@386
   909
    JMP_TARGET(emptysar);
nkeynes@386
   910
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   911
    JMP_rel8(end2);
nkeynes@382
   912
nkeynes@380
   913
    JMP_TARGET(doshl);
nkeynes@361
   914
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   915
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   916
    JMP_TARGET(end);
nkeynes@386
   917
    JMP_TARGET(end2);
nkeynes@361
   918
    store_reg( R_EAX, Rn );
nkeynes@417
   919
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   920
:}
nkeynes@359
   921
SHLD Rm, Rn {:  
nkeynes@671
   922
    COUNT_INST(I_SHLD);
nkeynes@368
   923
    load_reg( R_EAX, Rn );
nkeynes@368
   924
    load_reg( R_ECX, Rm );
nkeynes@382
   925
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   926
    JGE_rel8(doshl);
nkeynes@368
   927
nkeynes@382
   928
    NEG_r32( R_ECX );      // 2
nkeynes@382
   929
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   930
    JE_rel8(emptyshr );
nkeynes@382
   931
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   932
    JMP_rel8(end);          // 2
nkeynes@386
   933
nkeynes@386
   934
    JMP_TARGET(emptyshr);
nkeynes@386
   935
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   936
    JMP_rel8(end2);
nkeynes@382
   937
nkeynes@382
   938
    JMP_TARGET(doshl);
nkeynes@382
   939
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   940
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   941
    JMP_TARGET(end);
nkeynes@386
   942
    JMP_TARGET(end2);
nkeynes@368
   943
    store_reg( R_EAX, Rn );
nkeynes@417
   944
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   945
:}
nkeynes@359
   946
SHAL Rn {: 
nkeynes@671
   947
    COUNT_INST(I_SHAL);
nkeynes@359
   948
    load_reg( R_EAX, Rn );
nkeynes@359
   949
    SHL1_r32( R_EAX );
nkeynes@397
   950
    SETC_t();
nkeynes@359
   951
    store_reg( R_EAX, Rn );
nkeynes@417
   952
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   953
:}
nkeynes@359
   954
SHAR Rn {:  
nkeynes@671
   955
    COUNT_INST(I_SHAR);
nkeynes@359
   956
    load_reg( R_EAX, Rn );
nkeynes@359
   957
    SAR1_r32( R_EAX );
nkeynes@397
   958
    SETC_t();
nkeynes@359
   959
    store_reg( R_EAX, Rn );
nkeynes@417
   960
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   961
:}
nkeynes@359
   962
SHLL Rn {:  
nkeynes@671
   963
    COUNT_INST(I_SHLL);
nkeynes@359
   964
    load_reg( R_EAX, Rn );
nkeynes@359
   965
    SHL1_r32( R_EAX );
nkeynes@397
   966
    SETC_t();
nkeynes@359
   967
    store_reg( R_EAX, Rn );
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   969
:}
nkeynes@359
   970
SHLL2 Rn {:
nkeynes@671
   971
    COUNT_INST(I_SHLL);
nkeynes@359
   972
    load_reg( R_EAX, Rn );
nkeynes@359
   973
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   974
    store_reg( R_EAX, Rn );
nkeynes@417
   975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   976
:}
nkeynes@359
   977
SHLL8 Rn {:  
nkeynes@671
   978
    COUNT_INST(I_SHLL);
nkeynes@359
   979
    load_reg( R_EAX, Rn );
nkeynes@359
   980
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   981
    store_reg( R_EAX, Rn );
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   983
:}
nkeynes@359
   984
SHLL16 Rn {:  
nkeynes@671
   985
    COUNT_INST(I_SHLL);
nkeynes@359
   986
    load_reg( R_EAX, Rn );
nkeynes@359
   987
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   988
    store_reg( R_EAX, Rn );
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   990
:}
nkeynes@359
   991
SHLR Rn {:  
nkeynes@671
   992
    COUNT_INST(I_SHLR);
nkeynes@359
   993
    load_reg( R_EAX, Rn );
nkeynes@359
   994
    SHR1_r32( R_EAX );
nkeynes@397
   995
    SETC_t();
nkeynes@359
   996
    store_reg( R_EAX, Rn );
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   998
:}
nkeynes@359
   999
SHLR2 Rn {:  
nkeynes@671
  1000
    COUNT_INST(I_SHLR);
nkeynes@359
  1001
    load_reg( R_EAX, Rn );
nkeynes@359
  1002
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1003
    store_reg( R_EAX, Rn );
nkeynes@417
  1004
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1005
:}
nkeynes@359
  1006
SHLR8 Rn {:  
nkeynes@671
  1007
    COUNT_INST(I_SHLR);
nkeynes@359
  1008
    load_reg( R_EAX, Rn );
nkeynes@359
  1009
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1010
    store_reg( R_EAX, Rn );
nkeynes@417
  1011
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1012
:}
nkeynes@359
  1013
SHLR16 Rn {:  
nkeynes@671
  1014
    COUNT_INST(I_SHLR);
nkeynes@359
  1015
    load_reg( R_EAX, Rn );
nkeynes@359
  1016
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1017
    store_reg( R_EAX, Rn );
nkeynes@417
  1018
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1019
:}
nkeynes@359
  1020
SUB Rm, Rn {:  
nkeynes@671
  1021
    COUNT_INST(I_SUB);
nkeynes@359
  1022
    load_reg( R_EAX, Rm );
nkeynes@359
  1023
    load_reg( R_ECX, Rn );
nkeynes@359
  1024
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1025
    store_reg( R_ECX, Rn );
nkeynes@417
  1026
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1027
:}
nkeynes@359
  1028
SUBC Rm, Rn {:  
nkeynes@671
  1029
    COUNT_INST(I_SUBC);
nkeynes@359
  1030
    load_reg( R_EAX, Rm );
nkeynes@359
  1031
    load_reg( R_ECX, Rn );
nkeynes@417
  1032
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1033
	LDC_t();
nkeynes@417
  1034
    }
nkeynes@359
  1035
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1036
    store_reg( R_ECX, Rn );
nkeynes@394
  1037
    SETC_t();
nkeynes@417
  1038
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1039
:}
nkeynes@359
  1040
SUBV Rm, Rn {:  
nkeynes@671
  1041
    COUNT_INST(I_SUBV);
nkeynes@359
  1042
    load_reg( R_EAX, Rm );
nkeynes@359
  1043
    load_reg( R_ECX, Rn );
nkeynes@359
  1044
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1045
    store_reg( R_ECX, Rn );
nkeynes@359
  1046
    SETO_t();
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1048
:}
nkeynes@359
  1049
SWAP.B Rm, Rn {:  
nkeynes@671
  1050
    COUNT_INST(I_SWAPB);
nkeynes@359
  1051
    load_reg( R_EAX, Rm );
nkeynes@601
  1052
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1053
    store_reg( R_EAX, Rn );
nkeynes@359
  1054
:}
nkeynes@359
  1055
SWAP.W Rm, Rn {:  
nkeynes@671
  1056
    COUNT_INST(I_SWAPB);
nkeynes@359
  1057
    load_reg( R_EAX, Rm );
nkeynes@359
  1058
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1059
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1060
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1061
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1062
    store_reg( R_ECX, Rn );
nkeynes@417
  1063
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1064
:}
nkeynes@361
  1065
TAS.B @Rn {:  
nkeynes@671
  1066
    COUNT_INST(I_TASB);
nkeynes@586
  1067
    load_reg( R_EAX, Rn );
nkeynes@586
  1068
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1069
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1070
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1071
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1072
    SETE_t();
nkeynes@361
  1073
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1074
    POP_realigned_r32( R_ECX );
nkeynes@361
  1075
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1076
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1077
:}
nkeynes@361
  1078
TST Rm, Rn {:  
nkeynes@671
  1079
    COUNT_INST(I_TST);
nkeynes@361
  1080
    load_reg( R_EAX, Rm );
nkeynes@361
  1081
    load_reg( R_ECX, Rn );
nkeynes@361
  1082
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1083
    SETE_t();
nkeynes@417
  1084
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1085
:}
nkeynes@368
  1086
TST #imm, R0 {:  
nkeynes@671
  1087
    COUNT_INST(I_TSTI);
nkeynes@368
  1088
    load_reg( R_EAX, 0 );
nkeynes@368
  1089
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1090
    SETE_t();
nkeynes@417
  1091
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1092
:}
nkeynes@368
  1093
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1094
    COUNT_INST(I_TSTB);
nkeynes@368
  1095
    load_reg( R_EAX, 0);
nkeynes@368
  1096
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1097
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1098
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1099
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1100
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1101
    SETE_t();
nkeynes@417
  1102
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1103
:}
nkeynes@359
  1104
XOR Rm, Rn {:  
nkeynes@671
  1105
    COUNT_INST(I_XOR);
nkeynes@359
  1106
    load_reg( R_EAX, Rm );
nkeynes@359
  1107
    load_reg( R_ECX, Rn );
nkeynes@359
  1108
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1109
    store_reg( R_ECX, Rn );
nkeynes@417
  1110
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1111
:}
nkeynes@359
  1112
XOR #imm, R0 {:  
nkeynes@671
  1113
    COUNT_INST(I_XORI);
nkeynes@359
  1114
    load_reg( R_EAX, 0 );
nkeynes@359
  1115
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1116
    store_reg( R_EAX, 0 );
nkeynes@417
  1117
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1118
:}
nkeynes@359
  1119
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1120
    COUNT_INST(I_XORB);
nkeynes@359
  1121
    load_reg( R_EAX, 0 );
nkeynes@359
  1122
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1123
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1124
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1125
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1126
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1127
    POP_realigned_r32(R_ECX);
nkeynes@359
  1128
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1129
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
:}
nkeynes@361
  1132
XTRCT Rm, Rn {:
nkeynes@671
  1133
    COUNT_INST(I_XTRCT);
nkeynes@361
  1134
    load_reg( R_EAX, Rm );
nkeynes@394
  1135
    load_reg( R_ECX, Rn );
nkeynes@394
  1136
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1137
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1138
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1139
    store_reg( R_ECX, Rn );
nkeynes@417
  1140
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1141
:}
nkeynes@359
  1142
nkeynes@359
  1143
/* Data move instructions */
nkeynes@359
  1144
MOV Rm, Rn {:  
nkeynes@671
  1145
    COUNT_INST(I_MOV);
nkeynes@359
  1146
    load_reg( R_EAX, Rm );
nkeynes@359
  1147
    store_reg( R_EAX, Rn );
nkeynes@359
  1148
:}
nkeynes@359
  1149
MOV #imm, Rn {:  
nkeynes@671
  1150
    COUNT_INST(I_MOVI);
nkeynes@359
  1151
    load_imm32( R_EAX, imm );
nkeynes@359
  1152
    store_reg( R_EAX, Rn );
nkeynes@359
  1153
:}
nkeynes@359
  1154
MOV.B Rm, @Rn {:  
nkeynes@671
  1155
    COUNT_INST(I_MOVB);
nkeynes@586
  1156
    load_reg( R_EAX, Rn );
nkeynes@586
  1157
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1158
    load_reg( R_EDX, Rm );
nkeynes@586
  1159
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1160
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1161
:}
nkeynes@359
  1162
MOV.B Rm, @-Rn {:  
nkeynes@671
  1163
    COUNT_INST(I_MOVB);
nkeynes@586
  1164
    load_reg( R_EAX, Rn );
nkeynes@586
  1165
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1166
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1167
    load_reg( R_EDX, Rm );
nkeynes@586
  1168
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1169
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1171
:}
nkeynes@359
  1172
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1173
    COUNT_INST(I_MOVB);
nkeynes@359
  1174
    load_reg( R_EAX, 0 );
nkeynes@359
  1175
    load_reg( R_ECX, Rn );
nkeynes@586
  1176
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1177
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1178
    load_reg( R_EDX, Rm );
nkeynes@586
  1179
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1181
:}
nkeynes@359
  1182
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1183
    COUNT_INST(I_MOVB);
nkeynes@586
  1184
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1185
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1186
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1187
    load_reg( R_EDX, 0 );
nkeynes@586
  1188
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1189
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1190
:}
nkeynes@359
  1191
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1192
    COUNT_INST(I_MOVB);
nkeynes@586
  1193
    load_reg( R_EAX, Rn );
nkeynes@586
  1194
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1195
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1196
    load_reg( R_EDX, 0 );
nkeynes@586
  1197
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1199
:}
nkeynes@359
  1200
MOV.B @Rm, Rn {:  
nkeynes@671
  1201
    COUNT_INST(I_MOVB);
nkeynes@586
  1202
    load_reg( R_EAX, Rm );
nkeynes@586
  1203
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1204
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1205
    store_reg( R_EAX, Rn );
nkeynes@417
  1206
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1207
:}
nkeynes@359
  1208
MOV.B @Rm+, Rn {:  
nkeynes@671
  1209
    COUNT_INST(I_MOVB);
nkeynes@586
  1210
    load_reg( R_EAX, Rm );
nkeynes@586
  1211
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1212
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1213
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1214
    store_reg( R_EAX, Rn );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1216
:}
nkeynes@359
  1217
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1218
    COUNT_INST(I_MOVB);
nkeynes@359
  1219
    load_reg( R_EAX, 0 );
nkeynes@359
  1220
    load_reg( R_ECX, Rm );
nkeynes@586
  1221
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1222
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1223
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1224
    store_reg( R_EAX, Rn );
nkeynes@417
  1225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1226
:}
nkeynes@359
  1227
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1228
    COUNT_INST(I_MOVB);
nkeynes@586
  1229
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1230
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1231
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1232
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1233
    store_reg( R_EAX, 0 );
nkeynes@417
  1234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1235
:}
nkeynes@359
  1236
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1237
    COUNT_INST(I_MOVB);
nkeynes@586
  1238
    load_reg( R_EAX, Rm );
nkeynes@586
  1239
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1240
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1241
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1242
    store_reg( R_EAX, 0 );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1244
:}
nkeynes@374
  1245
MOV.L Rm, @Rn {:
nkeynes@671
  1246
    COUNT_INST(I_MOVL);
nkeynes@586
  1247
    load_reg( R_EAX, Rn );
nkeynes@586
  1248
    check_walign32(R_EAX);
nkeynes@586
  1249
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1250
    load_reg( R_EDX, Rm );
nkeynes@586
  1251
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1253
:}
nkeynes@361
  1254
MOV.L Rm, @-Rn {:  
nkeynes@671
  1255
    COUNT_INST(I_MOVL);
nkeynes@586
  1256
    load_reg( R_EAX, Rn );
nkeynes@586
  1257
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1258
    check_walign32( R_EAX );
nkeynes@586
  1259
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1260
    load_reg( R_EDX, Rm );
nkeynes@586
  1261
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1262
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1263
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1264
:}
nkeynes@361
  1265
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1266
    COUNT_INST(I_MOVL);
nkeynes@361
  1267
    load_reg( R_EAX, 0 );
nkeynes@361
  1268
    load_reg( R_ECX, Rn );
nkeynes@586
  1269
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1270
    check_walign32( R_EAX );
nkeynes@586
  1271
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1272
    load_reg( R_EDX, Rm );
nkeynes@586
  1273
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1274
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1275
:}
nkeynes@361
  1276
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1277
    COUNT_INST(I_MOVL);
nkeynes@586
  1278
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1279
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1280
    check_walign32( R_EAX );
nkeynes@586
  1281
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1282
    load_reg( R_EDX, 0 );
nkeynes@586
  1283
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1284
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1285
:}
nkeynes@361
  1286
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1287
    COUNT_INST(I_MOVL);
nkeynes@586
  1288
    load_reg( R_EAX, Rn );
nkeynes@586
  1289
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1290
    check_walign32( R_EAX );
nkeynes@586
  1291
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1292
    load_reg( R_EDX, Rm );
nkeynes@586
  1293
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1295
:}
nkeynes@361
  1296
MOV.L @Rm, Rn {:  
nkeynes@671
  1297
    COUNT_INST(I_MOVL);
nkeynes@586
  1298
    load_reg( R_EAX, Rm );
nkeynes@586
  1299
    check_ralign32( R_EAX );
nkeynes@586
  1300
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1301
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1302
    store_reg( R_EAX, Rn );
nkeynes@417
  1303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1304
:}
nkeynes@361
  1305
MOV.L @Rm+, Rn {:  
nkeynes@671
  1306
    COUNT_INST(I_MOVL);
nkeynes@361
  1307
    load_reg( R_EAX, Rm );
nkeynes@382
  1308
    check_ralign32( R_EAX );
nkeynes@586
  1309
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1310
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1311
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1312
    store_reg( R_EAX, Rn );
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1314
:}
nkeynes@361
  1315
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1316
    COUNT_INST(I_MOVL);
nkeynes@361
  1317
    load_reg( R_EAX, 0 );
nkeynes@361
  1318
    load_reg( R_ECX, Rm );
nkeynes@586
  1319
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1320
    check_ralign32( R_EAX );
nkeynes@586
  1321
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1322
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1323
    store_reg( R_EAX, Rn );
nkeynes@417
  1324
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1325
:}
nkeynes@361
  1326
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1327
    COUNT_INST(I_MOVL);
nkeynes@586
  1328
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1329
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1330
    check_ralign32( R_EAX );
nkeynes@586
  1331
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1332
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1333
    store_reg( R_EAX, 0 );
nkeynes@417
  1334
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1335
:}
nkeynes@361
  1336
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1337
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1338
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1339
	SLOTILLEGAL();
nkeynes@374
  1340
    } else {
nkeynes@388
  1341
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1342
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1343
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1344
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1345
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1346
nkeynes@586
  1347
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1348
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1349
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1350
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1351
	    // behaviour though.
nkeynes@586
  1352
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1353
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1354
	} else {
nkeynes@586
  1355
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1356
	    // different virtual address than the translation was done with,
nkeynes@586
  1357
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1358
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1359
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1360
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1361
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1362
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1363
	}
nkeynes@382
  1364
	store_reg( R_EAX, Rn );
nkeynes@374
  1365
    }
nkeynes@361
  1366
:}
nkeynes@361
  1367
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1368
    COUNT_INST(I_MOVL);
nkeynes@586
  1369
    load_reg( R_EAX, Rm );
nkeynes@586
  1370
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1371
    check_ralign32( R_EAX );
nkeynes@586
  1372
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1373
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1374
    store_reg( R_EAX, Rn );
nkeynes@417
  1375
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1376
:}
nkeynes@361
  1377
MOV.W Rm, @Rn {:  
nkeynes@671
  1378
    COUNT_INST(I_MOVW);
nkeynes@586
  1379
    load_reg( R_EAX, Rn );
nkeynes@586
  1380
    check_walign16( R_EAX );
nkeynes@586
  1381
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1382
    load_reg( R_EDX, Rm );
nkeynes@586
  1383
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1385
:}
nkeynes@361
  1386
MOV.W Rm, @-Rn {:  
nkeynes@671
  1387
    COUNT_INST(I_MOVW);
nkeynes@586
  1388
    load_reg( R_EAX, Rn );
nkeynes@586
  1389
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1390
    check_walign16( R_EAX );
nkeynes@586
  1391
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1392
    load_reg( R_EDX, Rm );
nkeynes@586
  1393
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1394
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1395
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1396
:}
nkeynes@361
  1397
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1398
    COUNT_INST(I_MOVW);
nkeynes@361
  1399
    load_reg( R_EAX, 0 );
nkeynes@361
  1400
    load_reg( R_ECX, Rn );
nkeynes@586
  1401
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1402
    check_walign16( R_EAX );
nkeynes@586
  1403
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1404
    load_reg( R_EDX, Rm );
nkeynes@586
  1405
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1406
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1407
:}
nkeynes@361
  1408
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1409
    COUNT_INST(I_MOVW);
nkeynes@586
  1410
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1411
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1412
    check_walign16( R_EAX );
nkeynes@586
  1413
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1414
    load_reg( R_EDX, 0 );
nkeynes@586
  1415
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1416
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1417
:}
nkeynes@361
  1418
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1419
    COUNT_INST(I_MOVW);
nkeynes@586
  1420
    load_reg( R_EAX, Rn );
nkeynes@586
  1421
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1422
    check_walign16( R_EAX );
nkeynes@586
  1423
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1424
    load_reg( R_EDX, 0 );
nkeynes@586
  1425
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1427
:}
nkeynes@361
  1428
MOV.W @Rm, Rn {:  
nkeynes@671
  1429
    COUNT_INST(I_MOVW);
nkeynes@586
  1430
    load_reg( R_EAX, Rm );
nkeynes@586
  1431
    check_ralign16( R_EAX );
nkeynes@586
  1432
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1433
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1434
    store_reg( R_EAX, Rn );
nkeynes@417
  1435
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1436
:}
nkeynes@361
  1437
MOV.W @Rm+, Rn {:  
nkeynes@671
  1438
    COUNT_INST(I_MOVW);
nkeynes@361
  1439
    load_reg( R_EAX, Rm );
nkeynes@374
  1440
    check_ralign16( R_EAX );
nkeynes@586
  1441
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1442
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1443
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1444
    store_reg( R_EAX, Rn );
nkeynes@417
  1445
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1446
:}
nkeynes@361
  1447
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1448
    COUNT_INST(I_MOVW);
nkeynes@361
  1449
    load_reg( R_EAX, 0 );
nkeynes@361
  1450
    load_reg( R_ECX, Rm );
nkeynes@586
  1451
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1452
    check_ralign16( R_EAX );
nkeynes@586
  1453
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1454
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1455
    store_reg( R_EAX, Rn );
nkeynes@417
  1456
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1457
:}
nkeynes@361
  1458
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1459
    COUNT_INST(I_MOVW);
nkeynes@586
  1460
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1461
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1462
    check_ralign16( R_EAX );
nkeynes@586
  1463
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1464
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1465
    store_reg( R_EAX, 0 );
nkeynes@417
  1466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1467
:}
nkeynes@361
  1468
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1469
    COUNT_INST(I_MOVW);
nkeynes@374
  1470
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1471
	SLOTILLEGAL();
nkeynes@374
  1472
    } else {
nkeynes@586
  1473
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1474
	uint32_t target = pc + disp + 4;
nkeynes@586
  1475
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1476
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1477
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1478
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1479
	} else {
nkeynes@586
  1480
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1481
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1482
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1483
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1484
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1485
	}
nkeynes@374
  1486
	store_reg( R_EAX, Rn );
nkeynes@374
  1487
    }
nkeynes@361
  1488
:}
nkeynes@361
  1489
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1490
    COUNT_INST(I_MOVW);
nkeynes@586
  1491
    load_reg( R_EAX, Rm );
nkeynes@586
  1492
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1493
    check_ralign16( R_EAX );
nkeynes@586
  1494
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1495
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1496
    store_reg( R_EAX, 0 );
nkeynes@417
  1497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1498
:}
nkeynes@361
  1499
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1500
    COUNT_INST(I_MOVA);
nkeynes@374
  1501
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1502
	SLOTILLEGAL();
nkeynes@374
  1503
    } else {
nkeynes@586
  1504
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1505
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1506
	store_reg( R_ECX, 0 );
nkeynes@586
  1507
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1508
    }
nkeynes@361
  1509
:}
nkeynes@361
  1510
MOVCA.L R0, @Rn {:  
nkeynes@671
  1511
    COUNT_INST(I_MOVCA);
nkeynes@586
  1512
    load_reg( R_EAX, Rn );
nkeynes@586
  1513
    check_walign32( R_EAX );
nkeynes@586
  1514
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1515
    load_reg( R_EDX, 0 );
nkeynes@586
  1516
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1518
:}
nkeynes@359
  1519
nkeynes@359
  1520
/* Control transfer instructions */
nkeynes@374
  1521
BF disp {:
nkeynes@671
  1522
    COUNT_INST(I_BF);
nkeynes@374
  1523
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1524
	SLOTILLEGAL();
nkeynes@374
  1525
    } else {
nkeynes@586
  1526
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1527
	JT_rel8( nottaken );
nkeynes@586
  1528
	exit_block_rel(target, pc+2 );
nkeynes@380
  1529
	JMP_TARGET(nottaken);
nkeynes@408
  1530
	return 2;
nkeynes@374
  1531
    }
nkeynes@374
  1532
:}
nkeynes@374
  1533
BF/S disp {:
nkeynes@671
  1534
    COUNT_INST(I_BFS);
nkeynes@374
  1535
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1536
	SLOTILLEGAL();
nkeynes@374
  1537
    } else {
nkeynes@590
  1538
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1539
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1540
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1541
	    JT_rel8(nottaken);
nkeynes@601
  1542
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1543
	    JMP_TARGET(nottaken);
nkeynes@601
  1544
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1545
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1546
	    exit_block_emu(pc+2);
nkeynes@601
  1547
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1548
	    return 2;
nkeynes@601
  1549
	} else {
nkeynes@601
  1550
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1551
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1552
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1553
	    }
nkeynes@601
  1554
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1555
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1556
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1557
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1558
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1559
	    
nkeynes@601
  1560
	    // not taken
nkeynes@601
  1561
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1562
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1563
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1564
	    return 4;
nkeynes@417
  1565
	}
nkeynes@374
  1566
    }
nkeynes@374
  1567
:}
nkeynes@374
  1568
BRA disp {:  
nkeynes@671
  1569
    COUNT_INST(I_BRA);
nkeynes@374
  1570
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1571
	SLOTILLEGAL();
nkeynes@374
  1572
    } else {
nkeynes@590
  1573
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1574
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1575
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1576
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1577
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1578
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1579
	    exit_block_emu(pc+2);
nkeynes@601
  1580
	    return 2;
nkeynes@601
  1581
	} else {
nkeynes@601
  1582
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1583
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1584
	    return 4;
nkeynes@601
  1585
	}
nkeynes@374
  1586
    }
nkeynes@374
  1587
:}
nkeynes@374
  1588
BRAF Rn {:  
nkeynes@671
  1589
    COUNT_INST(I_BRAF);
nkeynes@374
  1590
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1591
	SLOTILLEGAL();
nkeynes@374
  1592
    } else {
nkeynes@590
  1593
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1594
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1595
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1596
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1597
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1598
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1599
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1600
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1601
	    exit_block_emu(pc+2);
nkeynes@601
  1602
	    return 2;
nkeynes@601
  1603
	} else {
nkeynes@601
  1604
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1605
	    exit_block_newpcset(pc+2);
nkeynes@601
  1606
	    return 4;
nkeynes@601
  1607
	}
nkeynes@374
  1608
    }
nkeynes@374
  1609
:}
nkeynes@374
  1610
BSR disp {:  
nkeynes@671
  1611
    COUNT_INST(I_BSR);
nkeynes@374
  1612
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1613
	SLOTILLEGAL();
nkeynes@374
  1614
    } else {
nkeynes@590
  1615
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1616
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1617
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1618
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1619
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1620
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1621
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1622
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1623
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1624
	    exit_block_emu(pc+2);
nkeynes@601
  1625
	    return 2;
nkeynes@601
  1626
	} else {
nkeynes@601
  1627
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1628
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1629
	    return 4;
nkeynes@601
  1630
	}
nkeynes@374
  1631
    }
nkeynes@374
  1632
:}
nkeynes@374
  1633
BSRF Rn {:  
nkeynes@671
  1634
    COUNT_INST(I_BSRF);
nkeynes@374
  1635
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1636
	SLOTILLEGAL();
nkeynes@374
  1637
    } else {
nkeynes@590
  1638
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1639
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1640
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1641
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1642
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1643
nkeynes@601
  1644
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1645
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1646
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1647
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1648
	    exit_block_emu(pc+2);
nkeynes@601
  1649
	    return 2;
nkeynes@601
  1650
	} else {
nkeynes@601
  1651
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1652
	    exit_block_newpcset(pc+2);
nkeynes@601
  1653
	    return 4;
nkeynes@601
  1654
	}
nkeynes@374
  1655
    }
nkeynes@374
  1656
:}
nkeynes@374
  1657
BT disp {:
nkeynes@671
  1658
    COUNT_INST(I_BT);
nkeynes@374
  1659
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1660
	SLOTILLEGAL();
nkeynes@374
  1661
    } else {
nkeynes@586
  1662
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1663
	JF_rel8( nottaken );
nkeynes@586
  1664
	exit_block_rel(target, pc+2 );
nkeynes@380
  1665
	JMP_TARGET(nottaken);
nkeynes@408
  1666
	return 2;
nkeynes@374
  1667
    }
nkeynes@374
  1668
:}
nkeynes@374
  1669
BT/S disp {:
nkeynes@671
  1670
    COUNT_INST(I_BTS);
nkeynes@374
  1671
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1672
	SLOTILLEGAL();
nkeynes@374
  1673
    } else {
nkeynes@590
  1674
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1675
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1676
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1677
	    JF_rel8(nottaken);
nkeynes@601
  1678
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1679
	    JMP_TARGET(nottaken);
nkeynes@601
  1680
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1681
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1682
	    exit_block_emu(pc+2);
nkeynes@601
  1683
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1684
	    return 2;
nkeynes@601
  1685
	} else {
nkeynes@601
  1686
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1687
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1688
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1689
	    }
nkeynes@601
  1690
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1691
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1692
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1693
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1694
	    // not taken
nkeynes@601
  1695
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1696
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1697
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1698
	    return 4;
nkeynes@417
  1699
	}
nkeynes@374
  1700
    }
nkeynes@374
  1701
:}
nkeynes@374
  1702
JMP @Rn {:  
nkeynes@671
  1703
    COUNT_INST(I_JMP);
nkeynes@374
  1704
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1705
	SLOTILLEGAL();
nkeynes@374
  1706
    } else {
nkeynes@408
  1707
	load_reg( R_ECX, Rn );
nkeynes@590
  1708
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1709
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1710
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1711
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1712
	    exit_block_emu(pc+2);
nkeynes@601
  1713
	    return 2;
nkeynes@601
  1714
	} else {
nkeynes@601
  1715
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1716
	    exit_block_newpcset(pc+2);
nkeynes@601
  1717
	    return 4;
nkeynes@601
  1718
	}
nkeynes@374
  1719
    }
nkeynes@374
  1720
:}
nkeynes@374
  1721
JSR @Rn {:  
nkeynes@671
  1722
    COUNT_INST(I_JSR);
nkeynes@374
  1723
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1724
	SLOTILLEGAL();
nkeynes@374
  1725
    } else {
nkeynes@590
  1726
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1727
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1728
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1729
	load_reg( R_ECX, Rn );
nkeynes@590
  1730
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1731
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1732
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1733
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1734
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1735
	    exit_block_emu(pc+2);
nkeynes@601
  1736
	    return 2;
nkeynes@601
  1737
	} else {
nkeynes@601
  1738
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1739
	    exit_block_newpcset(pc+2);
nkeynes@601
  1740
	    return 4;
nkeynes@601
  1741
	}
nkeynes@374
  1742
    }
nkeynes@374
  1743
:}
nkeynes@374
  1744
RTE {:  
nkeynes@671
  1745
    COUNT_INST(I_RTE);
nkeynes@374
  1746
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1747
	SLOTILLEGAL();
nkeynes@374
  1748
    } else {
nkeynes@408
  1749
	check_priv();
nkeynes@408
  1750
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1751
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1752
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1753
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1754
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1755
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1756
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1757
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1758
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1759
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1760
	    exit_block_emu(pc+2);
nkeynes@601
  1761
	    return 2;
nkeynes@601
  1762
	} else {
nkeynes@601
  1763
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1764
	    exit_block_newpcset(pc+2);
nkeynes@601
  1765
	    return 4;
nkeynes@601
  1766
	}
nkeynes@374
  1767
    }
nkeynes@374
  1768
:}
nkeynes@374
  1769
RTS {:  
nkeynes@671
  1770
    COUNT_INST(I_RTS);
nkeynes@374
  1771
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1772
	SLOTILLEGAL();
nkeynes@374
  1773
    } else {
nkeynes@408
  1774
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1775
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1776
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1777
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1778
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1779
	    exit_block_emu(pc+2);
nkeynes@601
  1780
	    return 2;
nkeynes@601
  1781
	} else {
nkeynes@601
  1782
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1783
	    exit_block_newpcset(pc+2);
nkeynes@601
  1784
	    return 4;
nkeynes@601
  1785
	}
nkeynes@374
  1786
    }
nkeynes@374
  1787
:}
nkeynes@374
  1788
TRAPA #imm {:  
nkeynes@671
  1789
    COUNT_INST(I_TRAPA);
nkeynes@374
  1790
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1791
	SLOTILLEGAL();
nkeynes@374
  1792
    } else {
nkeynes@590
  1793
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1794
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1795
	load_imm32( R_EAX, imm );
nkeynes@527
  1796
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1797
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1798
	exit_block_pcset(pc);
nkeynes@409
  1799
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1800
	return 2;
nkeynes@374
  1801
    }
nkeynes@374
  1802
:}
nkeynes@374
  1803
UNDEF {:  
nkeynes@671
  1804
    COUNT_INST(I_UNDEF);
nkeynes@374
  1805
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1806
	SLOTILLEGAL();
nkeynes@374
  1807
    } else {
nkeynes@586
  1808
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1809
	return 2;
nkeynes@374
  1810
    }
nkeynes@368
  1811
:}
nkeynes@374
  1812
nkeynes@374
  1813
CLRMAC {:  
nkeynes@671
  1814
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1815
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1816
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1817
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1818
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1819
:}
nkeynes@374
  1820
CLRS {:
nkeynes@671
  1821
    COUNT_INST(I_CLRS);
nkeynes@374
  1822
    CLC();
nkeynes@374
  1823
    SETC_sh4r(R_S);
nkeynes@872
  1824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1825
:}
nkeynes@374
  1826
CLRT {:  
nkeynes@671
  1827
    COUNT_INST(I_CLRT);
nkeynes@374
  1828
    CLC();
nkeynes@374
  1829
    SETC_t();
nkeynes@417
  1830
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1831
:}
nkeynes@374
  1832
SETS {:  
nkeynes@671
  1833
    COUNT_INST(I_SETS);
nkeynes@374
  1834
    STC();
nkeynes@374
  1835
    SETC_sh4r(R_S);
nkeynes@872
  1836
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1837
:}
nkeynes@374
  1838
SETT {:  
nkeynes@671
  1839
    COUNT_INST(I_SETT);
nkeynes@374
  1840
    STC();
nkeynes@374
  1841
    SETC_t();
nkeynes@417
  1842
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1843
:}
nkeynes@359
  1844
nkeynes@375
  1845
/* Floating point moves */
nkeynes@375
  1846
FMOV FRm, FRn {:  
nkeynes@671
  1847
    COUNT_INST(I_FMOV1);
nkeynes@377
  1848
    check_fpuen();
nkeynes@901
  1849
    if( sh4_x86.double_size ) {
nkeynes@901
  1850
        load_dr0( R_EAX, FRm );
nkeynes@901
  1851
        load_dr1( R_ECX, FRm );
nkeynes@901
  1852
        store_dr0( R_EAX, FRn );
nkeynes@901
  1853
        store_dr1( R_ECX, FRn );
nkeynes@901
  1854
    } else {
nkeynes@901
  1855
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1856
        store_fr( R_EAX, FRn );
nkeynes@901
  1857
    }
nkeynes@375
  1858
:}
nkeynes@416
  1859
FMOV FRm, @Rn {: 
nkeynes@671
  1860
    COUNT_INST(I_FMOV2);
nkeynes@586
  1861
    check_fpuen();
nkeynes@586
  1862
    load_reg( R_EAX, Rn );
nkeynes@901
  1863
    if( sh4_x86.double_size ) {
nkeynes@901
  1864
        check_walign64( R_EAX );
nkeynes@901
  1865
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1866
        load_dr0( R_ECX, FRm );
nkeynes@901
  1867
        load_dr1( R_EDX, FRm );
nkeynes@901
  1868
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1869
    } else {
nkeynes@901
  1870
        check_walign32( R_EAX );
nkeynes@901
  1871
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1872
        load_fr( R_ECX, FRm );
nkeynes@901
  1873
        MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@901
  1874
    }
nkeynes@417
  1875
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1876
:}
nkeynes@375
  1877
FMOV @Rm, FRn {:  
nkeynes@671
  1878
    COUNT_INST(I_FMOV5);
nkeynes@586
  1879
    check_fpuen();
nkeynes@586
  1880
    load_reg( R_EAX, Rm );
nkeynes@901
  1881
    if( sh4_x86.double_size ) {
nkeynes@901
  1882
        check_ralign64( R_EAX );
nkeynes@901
  1883
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1884
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1885
        store_dr0( R_ECX, FRn );
nkeynes@901
  1886
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1887
    } else {
nkeynes@901
  1888
        check_ralign32( R_EAX );
nkeynes@901
  1889
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1890
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1891
        store_fr( R_EAX, FRn );
nkeynes@901
  1892
    }
nkeynes@417
  1893
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1894
:}
nkeynes@377
  1895
FMOV FRm, @-Rn {:  
nkeynes@671
  1896
    COUNT_INST(I_FMOV3);
nkeynes@586
  1897
    check_fpuen();
nkeynes@586
  1898
    load_reg( R_EAX, Rn );
nkeynes@901
  1899
    if( sh4_x86.double_size ) {
nkeynes@901
  1900
        check_walign64( R_EAX );
nkeynes@901
  1901
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1902
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1903
        load_dr0( R_ECX, FRm );
nkeynes@901
  1904
        load_dr1( R_EDX, FRm );
nkeynes@901
  1905
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1906
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1907
    } else {
nkeynes@901
  1908
        check_walign32( R_EAX );
nkeynes@901
  1909
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1910
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1911
        load_fr( R_ECX, FRm );
nkeynes@901
  1912
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1913
        MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@901
  1914
    }
nkeynes@417
  1915
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1916
:}
nkeynes@416
  1917
FMOV @Rm+, FRn {:
nkeynes@671
  1918
    COUNT_INST(I_FMOV6);
nkeynes@586
  1919
    check_fpuen();
nkeynes@586
  1920
    load_reg( R_EAX, Rm );
nkeynes@901
  1921
    if( sh4_x86.double_size ) {
nkeynes@901
  1922
        check_ralign64( R_EAX );
nkeynes@901
  1923
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1924
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1925
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1926
        store_dr0( R_ECX, FRn );
nkeynes@901
  1927
        store_dr1( R_EAX, FRn );
nkeynes@901
  1928
    } else {
nkeynes@901
  1929
        check_ralign32( R_EAX );
nkeynes@901
  1930
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1931
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1932
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1933
        store_fr( R_EAX, FRn );
nkeynes@901
  1934
    }
nkeynes@417
  1935
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1936
:}
nkeynes@377
  1937
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1938
    COUNT_INST(I_FMOV4);
nkeynes@586
  1939
    check_fpuen();
nkeynes@586
  1940
    load_reg( R_EAX, Rn );
nkeynes@586
  1941
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1942
    if( sh4_x86.double_size ) {
nkeynes@901
  1943
        check_walign64( R_EAX );
nkeynes@901
  1944
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1945
        load_dr0( R_ECX, FRm );
nkeynes@901
  1946
        load_dr1( R_EDX, FRm );
nkeynes@901
  1947
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1948
    } else {
nkeynes@901
  1949
        check_walign32( R_EAX );
nkeynes@901
  1950
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1951
        load_fr( R_ECX, FRm );
nkeynes@901
  1952
        MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@901
  1953
    }
nkeynes@417
  1954
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1955
:}
nkeynes@377
  1956
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1957
    COUNT_INST(I_FMOV7);
nkeynes@586
  1958
    check_fpuen();
nkeynes@586
  1959
    load_reg( R_EAX, Rm );
nkeynes@586
  1960
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1961
    if( sh4_x86.double_size ) {
nkeynes@901
  1962
        check_ralign64( R_EAX );
nkeynes@901
  1963
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1964
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1965
        store_dr0( R_ECX, FRn );
nkeynes@901
  1966
        store_dr1( R_EAX, FRn );
nkeynes@901
  1967
    } else {
nkeynes@901
  1968
        check_ralign32( R_EAX );
nkeynes@901
  1969
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1970
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1971
        store_fr( R_EAX, FRn );
nkeynes@901
  1972
    }
nkeynes@417
  1973
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1974
:}
nkeynes@377
  1975
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1976
    COUNT_INST(I_FLDI0);
nkeynes@377
  1977
    check_fpuen();
nkeynes@901
  1978
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1979
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1980
        store_fr( R_EAX, FRn );
nkeynes@901
  1981
    }
nkeynes@417
  1982
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1983
:}
nkeynes@377
  1984
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1985
    COUNT_INST(I_FLDI1);
nkeynes@377
  1986
    check_fpuen();
nkeynes@901
  1987
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1988
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1989
        store_fr( R_EAX, FRn );
nkeynes@901
  1990
    }
nkeynes@377
  1991
:}
nkeynes@377
  1992
nkeynes@377
  1993
FLOAT FPUL, FRn {:  
nkeynes@671
  1994
    COUNT_INST(I_FLOAT);
nkeynes@377
  1995
    check_fpuen();
nkeynes@377
  1996
    FILD_sh4r(R_FPUL);
nkeynes@901
  1997
    if( sh4_x86.double_prec ) {
nkeynes@901
  1998
        pop_dr( FRn );
nkeynes@901
  1999
    } else {
nkeynes@901
  2000
        pop_fr( FRn );
nkeynes@901
  2001
    }
nkeynes@377
  2002
:}
nkeynes@377
  2003
FTRC FRm, FPUL {:  
nkeynes@671
  2004
    COUNT_INST(I_FTRC);
nkeynes@377
  2005
    check_fpuen();
nkeynes@901
  2006
    if( sh4_x86.double_prec ) {
nkeynes@901
  2007
        push_dr( FRm );
nkeynes@901
  2008
    } else {
nkeynes@901
  2009
        push_fr( FRm );
nkeynes@901
  2010
    }
nkeynes@789
  2011
    load_ptr( R_ECX, &max_int );
nkeynes@388
  2012
    FILD_r32ind( R_ECX );
nkeynes@388
  2013
    FCOMIP_st(1);
nkeynes@669
  2014
    JNA_rel8( sat );
nkeynes@789
  2015
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2016
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2017
    FCOMIP_st(1);                   // 2
nkeynes@669
  2018
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2019
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2020
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2021
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2022
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2023
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2024
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2025
    JMP_rel8(end);             // 2
nkeynes@388
  2026
nkeynes@388
  2027
    JMP_TARGET(sat);
nkeynes@388
  2028
    JMP_TARGET(sat2);
nkeynes@388
  2029
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2030
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2031
    FPOP_st();
nkeynes@388
  2032
    JMP_TARGET(end);
nkeynes@417
  2033
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2034
:}
nkeynes@377
  2035
FLDS FRm, FPUL {:  
nkeynes@671
  2036
    COUNT_INST(I_FLDS);
nkeynes@377
  2037
    check_fpuen();
nkeynes@669
  2038
    load_fr( R_EAX, FRm );
nkeynes@377
  2039
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2040
:}
nkeynes@377
  2041
FSTS FPUL, FRn {:  
nkeynes@671
  2042
    COUNT_INST(I_FSTS);
nkeynes@377
  2043
    check_fpuen();
nkeynes@377
  2044
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2045
    store_fr( R_EAX, FRn );
nkeynes@377
  2046
:}
nkeynes@377
  2047
FCNVDS FRm, FPUL {:  
nkeynes@671
  2048
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2049
    check_fpuen();
nkeynes@901
  2050
    if( sh4_x86.double_prec ) {
nkeynes@901
  2051
        push_dr( FRm );
nkeynes@901
  2052
        pop_fpul();
nkeynes@901
  2053
    }
nkeynes@377
  2054
:}
nkeynes@377
  2055
FCNVSD FPUL, FRn {:  
nkeynes@671
  2056
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2057
    check_fpuen();
nkeynes@901
  2058
    if( sh4_x86.double_prec ) {
nkeynes@901
  2059
        push_fpul();
nkeynes@901
  2060
        pop_dr( FRn );
nkeynes@901
  2061
    }
nkeynes@377
  2062
:}
nkeynes@375
  2063
nkeynes@359
  2064
/* Floating point instructions */
nkeynes@374
  2065
FABS FRn {:  
nkeynes@671
  2066
    COUNT_INST(I_FABS);
nkeynes@377
  2067
    check_fpuen();
nkeynes@901
  2068
    if( sh4_x86.double_prec ) {
nkeynes@901
  2069
        push_dr(FRn);
nkeynes@901
  2070
        FABS_st0();
nkeynes@901
  2071
        pop_dr(FRn);
nkeynes@901
  2072
    } else {
nkeynes@901
  2073
        push_fr(FRn);
nkeynes@901
  2074
        FABS_st0();
nkeynes@901
  2075
        pop_fr(FRn);
nkeynes@901
  2076
    }
nkeynes@374
  2077
:}
nkeynes@377
  2078
FADD FRm, FRn {:  
nkeynes@671
  2079
    COUNT_INST(I_FADD);
nkeynes@377
  2080
    check_fpuen();
nkeynes@901
  2081
    if( sh4_x86.double_prec ) {
nkeynes@901
  2082
        push_dr(FRm);
nkeynes@901
  2083
        push_dr(FRn);
nkeynes@901
  2084
        FADDP_st(1);
nkeynes@901
  2085
        pop_dr(FRn);
nkeynes@901
  2086
    } else {
nkeynes@901
  2087
        push_fr(FRm);
nkeynes@901
  2088
        push_fr(FRn);
nkeynes@901
  2089
        FADDP_st(1);
nkeynes@901
  2090
        pop_fr(FRn);
nkeynes@901
  2091
    }
nkeynes@375
  2092
:}
nkeynes@377
  2093
FDIV FRm, FRn {:  
nkeynes@671
  2094
    COUNT_INST(I_FDIV);
nkeynes@377
  2095
    check_fpuen();
nkeynes@901
  2096
    if( sh4_x86.double_prec ) {
nkeynes@901
  2097
        push_dr(FRn);
nkeynes@901
  2098
        push_dr(FRm);
nkeynes@901
  2099
        FDIVP_st(1);
nkeynes@901
  2100
        pop_dr(FRn);
nkeynes@901
  2101
    } else {
nkeynes@901
  2102
        push_fr(FRn);
nkeynes@901
  2103
        push_fr(FRm);
nkeynes@901
  2104
        FDIVP_st(1);
nkeynes@901
  2105
        pop_fr(FRn);
nkeynes@901
  2106
    }
nkeynes@375
  2107
:}
nkeynes@375
  2108
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2109
    COUNT_INST(I_FMAC);
nkeynes@377
  2110
    check_fpuen();
nkeynes@901
  2111
    if( sh4_x86.double_prec ) {
nkeynes@901
  2112
        push_dr( 0 );
nkeynes@901
  2113
        push_dr( FRm );
nkeynes@901
  2114
        FMULP_st(1);
nkeynes@901
  2115
        push_dr( FRn );
nkeynes@901
  2116
        FADDP_st(1);
nkeynes@901
  2117
        pop_dr( FRn );
nkeynes@901
  2118
    } else {
nkeynes@901
  2119
        push_fr( 0 );
nkeynes@901
  2120
        push_fr( FRm );
nkeynes@901
  2121
        FMULP_st(1);
nkeynes@901
  2122
        push_fr( FRn );
nkeynes@901
  2123
        FADDP_st(1);
nkeynes@901
  2124
        pop_fr( FRn );
nkeynes@901
  2125
    }
nkeynes@375
  2126
:}
nkeynes@375
  2127
nkeynes@377
  2128
FMUL FRm, FRn {:  
nkeynes@671
  2129
    COUNT_INST(I_FMUL);
nkeynes@377
  2130
    check_fpuen();
nkeynes@901
  2131
    if( sh4_x86.double_prec ) {
nkeynes@901
  2132
        push_dr(FRm);
nkeynes@901
  2133
        push_dr(FRn);
nkeynes@901
  2134
        FMULP_st(1);
nkeynes@901
  2135
        pop_dr(FRn);
nkeynes@901
  2136
    } else {
nkeynes@901
  2137
        push_fr(FRm);
nkeynes@901
  2138
        push_fr(FRn);
nkeynes@901
  2139
        FMULP_st(1);
nkeynes@901
  2140
        pop_fr(FRn);
nkeynes@901
  2141
    }
nkeynes@377
  2142
:}
nkeynes@377
  2143
FNEG FRn {:  
nkeynes@671
  2144
    COUNT_INST(I_FNEG);
nkeynes@377
  2145
    check_fpuen();
nkeynes@901
  2146
    if( sh4_x86.double_prec ) {
nkeynes@901
  2147
        push_dr(FRn);
nkeynes@901
  2148
        FCHS_st0();
nkeynes@901
  2149
        pop_dr(FRn);
nkeynes@901
  2150
    } else {
nkeynes@901
  2151
        push_fr(FRn);
nkeynes@901
  2152
        FCHS_st0();
nkeynes@901
  2153
        pop_fr(FRn);
nkeynes@901
  2154
    }
nkeynes@377
  2155
:}
nkeynes@377
  2156
FSRRA FRn {:  
nkeynes@671
  2157
    COUNT_INST(I_FSRRA);
nkeynes@377
  2158
    check_fpuen();
nkeynes@901
  2159
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2160
        FLD1_st0();
nkeynes@901
  2161
        push_fr(FRn);
nkeynes@901
  2162
        FSQRT_st0();
nkeynes@901
  2163
        FDIVP_st(1);
nkeynes@901
  2164
        pop_fr(FRn);
nkeynes@901
  2165
    }
nkeynes@377
  2166
:}
nkeynes@377
  2167
FSQRT FRn {:  
nkeynes@671
  2168
    COUNT_INST(I_FSQRT);
nkeynes@377
  2169
    check_fpuen();
nkeynes@901
  2170
    if( sh4_x86.double_prec ) {
nkeynes@901
  2171
        push_dr(FRn);
nkeynes@901
  2172
        FSQRT_st0();
nkeynes@901
  2173
        pop_dr(FRn);
nkeynes@901
  2174
    } else {
nkeynes@901
  2175
        push_fr(FRn);
nkeynes@901
  2176
        FSQRT_st0();
nkeynes@901
  2177
        pop_fr(FRn);
nkeynes@901
  2178
    }
nkeynes@377
  2179
:}
nkeynes@377
  2180
FSUB FRm, FRn {:  
nkeynes@671
  2181
    COUNT_INST(I_FSUB);
nkeynes@377
  2182
    check_fpuen();
nkeynes@901
  2183
    if( sh4_x86.double_prec ) {
nkeynes@901
  2184
        push_dr(FRn);
nkeynes@901
  2185
        push_dr(FRm);
nkeynes@901
  2186
        FSUBP_st(1);
nkeynes@901
  2187
        pop_dr(FRn);
nkeynes@901
  2188
    } else {
nkeynes@901
  2189
        push_fr(FRn);
nkeynes@901
  2190
        push_fr(FRm);
nkeynes@901
  2191
        FSUBP_st(1);
nkeynes@901
  2192
        pop_fr(FRn);
nkeynes@901
  2193
    }
nkeynes@377
  2194
:}
nkeynes@377
  2195
nkeynes@377
  2196
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2197
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2198
    check_fpuen();
nkeynes@901
  2199
    if( sh4_x86.double_prec ) {
nkeynes@901
  2200
        push_dr(FRm);
nkeynes@901
  2201
        push_dr(FRn);
nkeynes@901
  2202
    } else {
nkeynes@901
  2203
        push_fr(FRm);
nkeynes@901
  2204
        push_fr(FRn);
nkeynes@901
  2205
    }
nkeynes@377
  2206
    FCOMIP_st(1);
nkeynes@377
  2207
    SETE_t();
nkeynes@377
  2208
    FPOP_st();
nkeynes@901
  2209
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2210
:}
nkeynes@377
  2211
FCMP/GT FRm, FRn {:  
nkeynes@671
  2212
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2213
    check_fpuen();
nkeynes@901
  2214
    if( sh4_x86.double_prec ) {
nkeynes@901
  2215
        push_dr(FRm);
nkeynes@901
  2216
        push_dr(FRn);
nkeynes@901
  2217
    } else {
nkeynes@901
  2218
        push_fr(FRm);
nkeynes@901
  2219
        push_fr(FRn);
nkeynes@901
  2220
    }
nkeynes@377
  2221
    FCOMIP_st(1);
nkeynes@377
  2222
    SETA_t();
nkeynes@377
  2223
    FPOP_st();
nkeynes@901
  2224
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2225
:}
nkeynes@377
  2226
nkeynes@377
  2227
FSCA FPUL, FRn {:  
nkeynes@671
  2228
    COUNT_INST(I_FSCA);
nkeynes@377
  2229
    check_fpuen();
nkeynes@901
  2230
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2231
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@901
  2232
        load_spreg( R_EDX, R_FPUL );
nkeynes@901
  2233
        call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@901
  2234
    }
nkeynes@417
  2235
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2236
:}
nkeynes@377
  2237
FIPR FVm, FVn {:  
nkeynes@671
  2238
    COUNT_INST(I_FIPR);
nkeynes@377
  2239
    check_fpuen();
nkeynes@901
  2240
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2241
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2242
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2243
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2244
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2245
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2246
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2247
        } else {
nkeynes@904
  2248
            push_fr( FVm<<2 );
nkeynes@903
  2249
            push_fr( FVn<<2 );
nkeynes@903
  2250
            FMULP_st(1);
nkeynes@903
  2251
            push_fr( (FVm<<2)+1);
nkeynes@903
  2252
            push_fr( (FVn<<2)+1);
nkeynes@903
  2253
            FMULP_st(1);
nkeynes@903
  2254
            FADDP_st(1);
nkeynes@903
  2255
            push_fr( (FVm<<2)+2);
nkeynes@903
  2256
            push_fr( (FVn<<2)+2);
nkeynes@903
  2257
            FMULP_st(1);
nkeynes@903
  2258
            FADDP_st(1);
nkeynes@903
  2259
            push_fr( (FVm<<2)+3);
nkeynes@903
  2260
            push_fr( (FVn<<2)+3);
nkeynes@903
  2261
            FMULP_st(1);
nkeynes@903
  2262
            FADDP_st(1);
nkeynes@903
  2263
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2264
        }
nkeynes@901
  2265
    }
nkeynes@377
  2266
:}
nkeynes@377
  2267
FTRV XMTRX, FVn {:  
nkeynes@671
  2268
    COUNT_INST(I_FTRV);
nkeynes@377
  2269
    check_fpuen();
nkeynes@901
  2270
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2271
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2272
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2273
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2274
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2275
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2276
nkeynes@903
  2277
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2278
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2279
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2280
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2281
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2282
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2283
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2284
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2285
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2286
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2287
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2288
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2289
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2290
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2291
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2292
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2293
        } else {
nkeynes@903
  2294
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2295
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2296
        }
nkeynes@901
  2297
    }
nkeynes@417
  2298
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2299
:}
nkeynes@377
  2300
nkeynes@377
  2301
FRCHG {:  
nkeynes@671
  2302
    COUNT_INST(I_FRCHG);
nkeynes@377
  2303
    check_fpuen();
nkeynes@377
  2304
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2305
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2306
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2307
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2308
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2309
:}
nkeynes@377
  2310
FSCHG {:  
nkeynes@671
  2311
    COUNT_INST(I_FSCHG);
nkeynes@377
  2312
    check_fpuen();
nkeynes@377
  2313
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2314
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2315
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2316
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2317
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2318
:}
nkeynes@359
  2319
nkeynes@359
  2320
/* Processor control instructions */
nkeynes@368
  2321
LDC Rm, SR {:
nkeynes@671
  2322
    COUNT_INST(I_LDCSR);
nkeynes@386
  2323
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2324
	SLOTILLEGAL();
nkeynes@386
  2325
    } else {
nkeynes@386
  2326
	check_priv();
nkeynes@386
  2327
	load_reg( R_EAX, Rm );
nkeynes@386
  2328
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2329
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2330
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2331
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2332
    }
nkeynes@368
  2333
:}
nkeynes@359
  2334
LDC Rm, GBR {: 
nkeynes@671
  2335
    COUNT_INST(I_LDC);
nkeynes@359
  2336
    load_reg( R_EAX, Rm );
nkeynes@359
  2337
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDC Rm, VBR {:  
nkeynes@671
  2340
    COUNT_INST(I_LDC);
nkeynes@386
  2341
    check_priv();
nkeynes@359
  2342
    load_reg( R_EAX, Rm );
nkeynes@359
  2343
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2344
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2345
:}
nkeynes@359
  2346
LDC Rm, SSR {:  
nkeynes@671
  2347
    COUNT_INST(I_LDC);
nkeynes@386
  2348
    check_priv();
nkeynes@359
  2349
    load_reg( R_EAX, Rm );
nkeynes@359
  2350
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2351
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2352
:}
nkeynes@359
  2353
LDC Rm, SGR {:  
nkeynes@671
  2354
    COUNT_INST(I_LDC);
nkeynes@386
  2355
    check_priv();
nkeynes@359
  2356
    load_reg( R_EAX, Rm );
nkeynes@359
  2357
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2359
:}
nkeynes@359
  2360
LDC Rm, SPC {:  
nkeynes@671
  2361
    COUNT_INST(I_LDC);
nkeynes@386
  2362
    check_priv();
nkeynes@359
  2363
    load_reg( R_EAX, Rm );
nkeynes@359
  2364
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2365
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2366
:}
nkeynes@359
  2367
LDC Rm, DBR {:  
nkeynes@671
  2368
    COUNT_INST(I_LDC);
nkeynes@386
  2369
    check_priv();
nkeynes@359
  2370
    load_reg( R_EAX, Rm );
nkeynes@359
  2371
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2373
:}
nkeynes@374
  2374
LDC Rm, Rn_BANK {:  
nkeynes@671
  2375
    COUNT_INST(I_LDC);
nkeynes@386
  2376
    check_priv();
nkeynes@374
  2377
    load_reg( R_EAX, Rm );
nkeynes@374
  2378
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2380
:}
nkeynes@359
  2381
LDC.L @Rm+, GBR {:  
nkeynes@671
  2382
    COUNT_INST(I_LDCM);
nkeynes@359
  2383
    load_reg( R_EAX, Rm );
nkeynes@395
  2384
    check_ralign32( R_EAX );
nkeynes@586
  2385
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2386
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2387
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2388
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2390
:}
nkeynes@368
  2391
LDC.L @Rm+, SR {:
nkeynes@671
  2392
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2393
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2394
	SLOTILLEGAL();
nkeynes@386
  2395
    } else {
nkeynes@586
  2396
	check_priv();
nkeynes@386
  2397
	load_reg( R_EAX, Rm );
nkeynes@395
  2398
	check_ralign32( R_EAX );
nkeynes@586
  2399
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2400
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2401
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2402
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2403
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2404
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2405
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2406
    }
nkeynes@359
  2407
:}
nkeynes@359
  2408
LDC.L @Rm+, VBR {:  
nkeynes@671
  2409
    COUNT_INST(I_LDCM);
nkeynes@586
  2410
    check_priv();
nkeynes@359
  2411
    load_reg( R_EAX, Rm );
nkeynes@395
  2412
    check_ralign32( R_EAX );
nkeynes@586
  2413
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2414
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2415
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2416
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2418
:}
nkeynes@359
  2419
LDC.L @Rm+, SSR {:
nkeynes@671
  2420
    COUNT_INST(I_LDCM);
nkeynes@586
  2421
    check_priv();
nkeynes@359
  2422
    load_reg( R_EAX, Rm );
nkeynes@416
  2423
    check_ralign32( R_EAX );
nkeynes@586
  2424
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2425
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2426
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2427
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2428
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2429
:}
nkeynes@359
  2430
LDC.L @Rm+, SGR {:  
nkeynes@671
  2431
    COUNT_INST(I_LDCM);
nkeynes@586
  2432
    check_priv();
nkeynes@359
  2433
    load_reg( R_EAX, Rm );
nkeynes@395
  2434
    check_ralign32( R_EAX );
nkeynes@586
  2435
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2436
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2437
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2438
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2439
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2440
:}
nkeynes@359
  2441
LDC.L @Rm+, SPC {:  
nkeynes@671
  2442
    COUNT_INST(I_LDCM);
nkeynes@586
  2443
    check_priv();
nkeynes@359
  2444
    load_reg( R_EAX, Rm );
nkeynes@395
  2445
    check_ralign32( R_EAX );
nkeynes@586
  2446
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2447
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2448
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2449
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2451
:}
nkeynes@359
  2452
LDC.L @Rm+, DBR {:  
nkeynes@671
  2453
    COUNT_INST(I_LDCM);
nkeynes@586
  2454
    check_priv();
nkeynes@359
  2455
    load_reg( R_EAX, Rm );
nkeynes@395
  2456
    check_ralign32( R_EAX );
nkeynes@586
  2457
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2458
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2459
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2460
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2462
:}
nkeynes@359
  2463
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2464
    COUNT_INST(I_LDCM);
nkeynes@586
  2465
    check_priv();
nkeynes@374
  2466
    load_reg( R_EAX, Rm );
nkeynes@395
  2467
    check_ralign32( R_EAX );
nkeynes@586
  2468
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2469
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2470
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2471
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2473
:}
nkeynes@626
  2474
LDS Rm, FPSCR {:
nkeynes@673
  2475
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2476
    check_fpuen();
nkeynes@359
  2477
    load_reg( R_EAX, Rm );
nkeynes@669
  2478
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2480
    return 2;
nkeynes@359
  2481
:}
nkeynes@359
  2482
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2483
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2484
    check_fpuen();
nkeynes@359
  2485
    load_reg( R_EAX, Rm );
nkeynes@395
  2486
    check_ralign32( R_EAX );
nkeynes@586
  2487
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2488
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2489
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2490
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2491
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2492
    return 2;
nkeynes@359
  2493
:}
nkeynes@359
  2494
LDS Rm, FPUL {:  
nkeynes@671
  2495
    COUNT_INST(I_LDS);
nkeynes@626
  2496
    check_fpuen();
nkeynes@359
  2497
    load_reg( R_EAX, Rm );
nkeynes@359
  2498
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2499
:}
nkeynes@359
  2500
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2501
    COUNT_INST(I_LDSM);
nkeynes@626
  2502
    check_fpuen();
nkeynes@359
  2503
    load_reg( R_EAX, Rm );
nkeynes@395
  2504
    check_ralign32( R_EAX );
nkeynes@586
  2505
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2506
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2507
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2508
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2509
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2510
:}
nkeynes@359
  2511
LDS Rm, MACH {: 
nkeynes@671
  2512
    COUNT_INST(I_LDS);
nkeynes@359
  2513
    load_reg( R_EAX, Rm );
nkeynes@359
  2514
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2515
:}
nkeynes@359
  2516
LDS.L @Rm+, MACH {:  
nkeynes@671
  2517
    COUNT_INST(I_LDSM);
nkeynes@359
  2518
    load_reg( R_EAX, Rm );
nkeynes@395
  2519
    check_ralign32( R_EAX );
nkeynes@586
  2520
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2521
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2522
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2523
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2524
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2525
:}
nkeynes@359
  2526
LDS Rm, MACL {:  
nkeynes@671
  2527
    COUNT_INST(I_LDS);
nkeynes@359
  2528
    load_reg( R_EAX, Rm );
nkeynes@359
  2529
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2530
:}
nkeynes@359
  2531
LDS.L @Rm+, MACL {:  
nkeynes@671
  2532
    COUNT_INST(I_LDSM);
nkeynes@359
  2533
    load_reg( R_EAX, Rm );
nkeynes@395
  2534
    check_ralign32( R_EAX );
nkeynes@586
  2535
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2536
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2537
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2538
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2539
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2540
:}
nkeynes@359
  2541
LDS Rm, PR {:  
nkeynes@671
  2542
    COUNT_INST(I_LDS);
nkeynes@359
  2543
    load_reg( R_EAX, Rm );
nkeynes@359
  2544
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2545
:}
nkeynes@359
  2546
LDS.L @Rm+, PR {:  
nkeynes@671
  2547
    COUNT_INST(I_LDSM);
nkeynes@359
  2548
    load_reg( R_EAX, Rm );
nkeynes@395
  2549
    check_ralign32( R_EAX );
nkeynes@586
  2550
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2551
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2552
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2553
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2554
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2555
:}
nkeynes@550
  2556
LDTLB {:  
nkeynes@671
  2557
    COUNT_INST(I_LDTLB);
nkeynes@553
  2558
    call_func0( MMU_ldtlb );
nkeynes@875
  2559
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2560
:}
nkeynes@671
  2561
OCBI @Rn {:
nkeynes@671
  2562
    COUNT_INST(I_OCBI);
nkeynes@671
  2563
:}
nkeynes@671
  2564
OCBP @Rn {:
nkeynes@671
  2565
    COUNT_INST(I_OCBP);
nkeynes@671
  2566
:}
nkeynes@671
  2567
OCBWB @Rn {:
nkeynes@671
  2568
    COUNT_INST(I_OCBWB);
nkeynes@671
  2569
:}
nkeynes@374
  2570
PREF @Rn {:
nkeynes@671
  2571
    COUNT_INST(I_PREF);
nkeynes@374
  2572
    load_reg( R_EAX, Rn );
nkeynes@532
  2573
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2574
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2575
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2576
    JNE_rel8(end);
nkeynes@532
  2577
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2578
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2579
    JE_exc(-1);
nkeynes@380
  2580
    JMP_TARGET(end);
nkeynes@417
  2581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2582
:}
nkeynes@388
  2583
SLEEP {: 
nkeynes@671
  2584
    COUNT_INST(I_SLEEP);
nkeynes@388
  2585
    check_priv();
nkeynes@388
  2586
    call_func0( sh4_sleep );
nkeynes@417
  2587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2588
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2589
    return 2;
nkeynes@388
  2590
:}
nkeynes@386
  2591
STC SR, Rn {:
nkeynes@671
  2592
    COUNT_INST(I_STCSR);
nkeynes@386
  2593
    check_priv();
nkeynes@386
  2594
    call_func0(sh4_read_sr);
nkeynes@386
  2595
    store_reg( R_EAX, Rn );
nkeynes@417
  2596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2597
:}
nkeynes@359
  2598
STC GBR, Rn {:  
nkeynes@671
  2599
    COUNT_INST(I_STC);
nkeynes@359
  2600
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2601
    store_reg( R_EAX, Rn );
nkeynes@359
  2602
:}
nkeynes@359
  2603
STC VBR, Rn {:  
nkeynes@671
  2604
    COUNT_INST(I_STC);
nkeynes@386
  2605
    check_priv();
nkeynes@359
  2606
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2607
    store_reg( R_EAX, Rn );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2609
:}
nkeynes@359
  2610
STC SSR, Rn {:  
nkeynes@671
  2611
    COUNT_INST(I_STC);
nkeynes@386
  2612
    check_priv();
nkeynes@359
  2613
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2614
    store_reg( R_EAX, Rn );
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
:}
nkeynes@359
  2617
STC SPC, Rn {:  
nkeynes@671
  2618
    COUNT_INST(I_STC);
nkeynes@386
  2619
    check_priv();
nkeynes@359
  2620
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2621
    store_reg( R_EAX, Rn );
nkeynes@417
  2622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2623
:}
nkeynes@359
  2624
STC SGR, Rn {:  
nkeynes@671
  2625
    COUNT_INST(I_STC);
nkeynes@386
  2626
    check_priv();
nkeynes@359
  2627
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2628
    store_reg( R_EAX, Rn );
nkeynes@417
  2629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2630
:}
nkeynes@359
  2631
STC DBR, Rn {:  
nkeynes@671
  2632
    COUNT_INST(I_STC);
nkeynes@386
  2633
    check_priv();
nkeynes@359
  2634
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2635
    store_reg( R_EAX, Rn );
nkeynes@417
  2636
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2637
:}
nkeynes@374
  2638
STC Rm_BANK, Rn {:
nkeynes@671
  2639
    COUNT_INST(I_STC);
nkeynes@386
  2640
    check_priv();
nkeynes@374
  2641
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2642
    store_reg( R_EAX, Rn );
nkeynes@417
  2643
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2644
:}
nkeynes@374
  2645
STC.L SR, @-Rn {:
nkeynes@671
  2646
    COUNT_INST(I_STCSRM);
nkeynes@586
  2647
    check_priv();
nkeynes@586
  2648
    load_reg( R_EAX, Rn );
nkeynes@586
  2649
    check_walign32( R_EAX );
nkeynes@586
  2650
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2651
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2652
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2653
    call_func0( sh4_read_sr );
nkeynes@586
  2654
    POP_realigned_r32( R_ECX );
nkeynes@586
  2655
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2656
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2657
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2658
:}
nkeynes@359
  2659
STC.L VBR, @-Rn {:  
nkeynes@671
  2660
    COUNT_INST(I_STCM);
nkeynes@586
  2661
    check_priv();
nkeynes@586
  2662
    load_reg( R_EAX, Rn );
nkeynes@586
  2663
    check_walign32( R_EAX );
nkeynes@586
  2664
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2665
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2666
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2667
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2668
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2669
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2670
:}
nkeynes@359
  2671
STC.L SSR, @-Rn {:  
nkeynes@671
  2672
    COUNT_INST(I_STCM);
nkeynes@586
  2673
    check_priv();
nkeynes@586
  2674
    load_reg( R_EAX, Rn );
nkeynes@586
  2675
    check_walign32( R_EAX );
nkeynes@586
  2676
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2677
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2678
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2679
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2680
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2681
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2682
:}
nkeynes@416
  2683
STC.L SPC, @-Rn {:
nkeynes@671
  2684
    COUNT_INST(I_STCM);
nkeynes@586
  2685
    check_priv();
nkeynes@586
  2686
    load_reg( R_EAX, Rn );
nkeynes@586
  2687
    check_walign32( R_EAX );
nkeynes@586
  2688
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2689
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2690
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2691
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2692
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2693
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2694
:}
nkeynes@359
  2695
STC.L SGR, @-Rn {:  
nkeynes@671
  2696
    COUNT_INST(I_STCM);
nkeynes@586
  2697
    check_priv();
nkeynes@586
  2698
    load_reg( R_EAX, Rn );
nkeynes@586
  2699
    check_walign32( R_EAX );
nkeynes@586
  2700
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2701
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2702
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2703
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2704
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2705
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2706
:}
nkeynes@359
  2707
STC.L DBR, @-Rn {:  
nkeynes@671
  2708
    COUNT_INST(I_STCM);
nkeynes@586
  2709
    check_priv();
nkeynes@586
  2710
    load_reg( R_EAX, Rn );
nkeynes@586
  2711
    check_walign32( R_EAX );
nkeynes@586
  2712
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2713
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2714
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2715
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2716
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2717
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2718
:}
nkeynes@374
  2719
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2720
    COUNT_INST(I_STCM);
nkeynes@586
  2721
    check_priv();
nkeynes@586
  2722
    load_reg( R_EAX, Rn );
nkeynes@586
  2723
    check_walign32( R_EAX );
nkeynes@586
  2724
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2725
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2726
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2727
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2728
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2729
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2730
:}
nkeynes@359
  2731
STC.L GBR, @-Rn {:  
nkeynes@671
  2732
    COUNT_INST(I_STCM);
nkeynes@586
  2733
    load_reg( R_EAX, Rn );
nkeynes@586
  2734
    check_walign32( R_EAX );
nkeynes@586
  2735
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2736
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2737
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2738
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2739
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2740
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2741
:}