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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 584:5c29dd7297df
prev577:a181aeacd6e8
next1065:bc1cc0c54917
author nkeynes
date Tue Jan 15 11:06:24 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Remove sh4_read_word accidentally left in
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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    uint32_t recovery_posn;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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void sh4_x86_add_recovery( uint32_t pc )
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{
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    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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    xlat_recovery_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@571
   335
/**
nkeynes@571
   336
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@571
   337
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@571
   338
 */
nkeynes@571
   339
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@570
   340
nkeynes@571
   341
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@571
   342
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@571
   343
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@559
   344
nkeynes@559
   345
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   346
nkeynes@539
   347
/****** Import appropriate calling conventions ******/
nkeynes@539
   348
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   349
#include "sh4/ia64abi.h"
nkeynes@539
   350
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   351
#ifdef APPLE_BUILD
nkeynes@539
   352
#include "sh4/ia32mac.h"
nkeynes@539
   353
#else
nkeynes@539
   354
#include "sh4/ia32abi.h"
nkeynes@539
   355
#endif
nkeynes@539
   356
#endif
nkeynes@539
   357
nkeynes@577
   358
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@577
   359
{
nkeynes@577
   360
    load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );
nkeynes@577
   361
    call_func1( sh4_translate_exit, R_EAX );
nkeynes@577
   362
}
nkeynes@577
   363
    
nkeynes@539
   364
nkeynes@359
   365
/**
nkeynes@359
   366
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   367
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   368
 * 
nkeynes@577
   369
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   370
 *
nkeynes@359
   371
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   372
 * (eg a branch or 
nkeynes@359
   373
 */
nkeynes@526
   374
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   375
{
nkeynes@388
   376
    uint32_t ir;
nkeynes@577
   377
    /* Read instruction from icache */
nkeynes@577
   378
    assert( IS_IN_ICACHE(pc) );
nkeynes@577
   379
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@577
   380
    
nkeynes@577
   381
	/* PC is not in the current icache - this usually means we're running
nkeynes@577
   382
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@577
   383
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@577
   384
	 * almost certainly in a delay slot.
nkeynes@577
   385
	 *
nkeynes@577
   386
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@577
   387
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@577
   388
	 * small repairs to cope with the different environment).
nkeynes@577
   389
	 */
nkeynes@577
   390
nkeynes@571
   391
    if( !sh4_x86.in_delay_slot ) {
nkeynes@571
   392
	sh4_x86_add_recovery(pc);
nkeynes@571
   393
    }
nkeynes@359
   394
%%
nkeynes@359
   395
/* ALU operations */
nkeynes@359
   396
ADD Rm, Rn {:
nkeynes@359
   397
    load_reg( R_EAX, Rm );
nkeynes@359
   398
    load_reg( R_ECX, Rn );
nkeynes@359
   399
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   400
    store_reg( R_ECX, Rn );
nkeynes@417
   401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   402
:}
nkeynes@359
   403
ADD #imm, Rn {:  
nkeynes@359
   404
    load_reg( R_EAX, Rn );
nkeynes@359
   405
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   406
    store_reg( R_EAX, Rn );
nkeynes@417
   407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   408
:}
nkeynes@359
   409
ADDC Rm, Rn {:
nkeynes@417
   410
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   411
	LDC_t();
nkeynes@417
   412
    }
nkeynes@359
   413
    load_reg( R_EAX, Rm );
nkeynes@359
   414
    load_reg( R_ECX, Rn );
nkeynes@359
   415
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   416
    store_reg( R_ECX, Rn );
nkeynes@359
   417
    SETC_t();
nkeynes@417
   418
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   419
:}
nkeynes@359
   420
ADDV Rm, Rn {:
nkeynes@359
   421
    load_reg( R_EAX, Rm );
nkeynes@359
   422
    load_reg( R_ECX, Rn );
nkeynes@359
   423
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   424
    store_reg( R_ECX, Rn );
nkeynes@359
   425
    SETO_t();
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   427
:}
nkeynes@359
   428
AND Rm, Rn {:
nkeynes@359
   429
    load_reg( R_EAX, Rm );
nkeynes@359
   430
    load_reg( R_ECX, Rn );
nkeynes@359
   431
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   432
    store_reg( R_ECX, Rn );
nkeynes@417
   433
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   434
:}
nkeynes@359
   435
AND #imm, R0 {:  
nkeynes@359
   436
    load_reg( R_EAX, 0 );
nkeynes@359
   437
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   438
    store_reg( R_EAX, 0 );
nkeynes@417
   439
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   440
:}
nkeynes@359
   441
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   442
    load_reg( R_EAX, 0 );
nkeynes@359
   443
    load_spreg( R_ECX, R_GBR );
nkeynes@571
   444
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   445
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   446
    PUSH_realigned_r32(R_EAX);
nkeynes@571
   447
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   448
    POP_realigned_r32(R_ECX);
nkeynes@386
   449
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   450
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   452
:}
nkeynes@359
   453
CMP/EQ Rm, Rn {:  
nkeynes@359
   454
    load_reg( R_EAX, Rm );
nkeynes@359
   455
    load_reg( R_ECX, Rn );
nkeynes@359
   456
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   457
    SETE_t();
nkeynes@417
   458
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   459
:}
nkeynes@359
   460
CMP/EQ #imm, R0 {:  
nkeynes@359
   461
    load_reg( R_EAX, 0 );
nkeynes@359
   462
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   463
    SETE_t();
nkeynes@417
   464
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   465
:}
nkeynes@359
   466
CMP/GE Rm, Rn {:  
nkeynes@359
   467
    load_reg( R_EAX, Rm );
nkeynes@359
   468
    load_reg( R_ECX, Rn );
nkeynes@359
   469
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   470
    SETGE_t();
nkeynes@417
   471
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   472
:}
nkeynes@359
   473
CMP/GT Rm, Rn {: 
nkeynes@359
   474
    load_reg( R_EAX, Rm );
nkeynes@359
   475
    load_reg( R_ECX, Rn );
nkeynes@359
   476
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   477
    SETG_t();
nkeynes@417
   478
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   479
:}
nkeynes@359
   480
CMP/HI Rm, Rn {:  
nkeynes@359
   481
    load_reg( R_EAX, Rm );
nkeynes@359
   482
    load_reg( R_ECX, Rn );
nkeynes@359
   483
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   484
    SETA_t();
nkeynes@417
   485
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   486
:}
nkeynes@359
   487
CMP/HS Rm, Rn {: 
nkeynes@359
   488
    load_reg( R_EAX, Rm );
nkeynes@359
   489
    load_reg( R_ECX, Rn );
nkeynes@359
   490
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   491
    SETAE_t();
nkeynes@417
   492
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   493
 :}
nkeynes@359
   494
CMP/PL Rn {: 
nkeynes@359
   495
    load_reg( R_EAX, Rn );
nkeynes@359
   496
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   497
    SETG_t();
nkeynes@417
   498
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/PZ Rn {:  
nkeynes@359
   501
    load_reg( R_EAX, Rn );
nkeynes@359
   502
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   503
    SETGE_t();
nkeynes@417
   504
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   505
:}
nkeynes@361
   506
CMP/STR Rm, Rn {:  
nkeynes@368
   507
    load_reg( R_EAX, Rm );
nkeynes@368
   508
    load_reg( R_ECX, Rn );
nkeynes@368
   509
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   510
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   511
    JE_rel8(13, target1);
nkeynes@368
   512
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   513
    JE_rel8(9, target2);
nkeynes@368
   514
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   515
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   516
    JE_rel8(2, target3);
nkeynes@368
   517
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   518
    JMP_TARGET(target1);
nkeynes@380
   519
    JMP_TARGET(target2);
nkeynes@380
   520
    JMP_TARGET(target3);
nkeynes@368
   521
    SETE_t();
nkeynes@417
   522
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   523
:}
nkeynes@361
   524
DIV0S Rm, Rn {:
nkeynes@361
   525
    load_reg( R_EAX, Rm );
nkeynes@386
   526
    load_reg( R_ECX, Rn );
nkeynes@361
   527
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   528
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   529
    store_spreg( R_EAX, R_M );
nkeynes@361
   530
    store_spreg( R_ECX, R_Q );
nkeynes@361
   531
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   532
    SETNE_t();
nkeynes@417
   533
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   534
:}
nkeynes@361
   535
DIV0U {:  
nkeynes@361
   536
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   537
    store_spreg( R_EAX, R_Q );
nkeynes@361
   538
    store_spreg( R_EAX, R_M );
nkeynes@361
   539
    store_spreg( R_EAX, R_T );
nkeynes@417
   540
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   541
:}
nkeynes@386
   542
DIV1 Rm, Rn {:
nkeynes@386
   543
    load_spreg( R_ECX, R_M );
nkeynes@386
   544
    load_reg( R_EAX, Rn );
nkeynes@417
   545
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   546
	LDC_t();
nkeynes@417
   547
    }
nkeynes@386
   548
    RCL1_r32( R_EAX );
nkeynes@386
   549
    SETC_r8( R_DL ); // Q'
nkeynes@386
   550
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   551
    JE_rel8(5, mqequal);
nkeynes@386
   552
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   553
    JMP_rel8(3, end);
nkeynes@380
   554
    JMP_TARGET(mqequal);
nkeynes@386
   555
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   556
    JMP_TARGET(end);
nkeynes@386
   557
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   558
    SETC_r8(R_AL); // tmp1
nkeynes@386
   559
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   560
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   561
    store_spreg( R_ECX, R_Q );
nkeynes@386
   562
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   563
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   564
    store_spreg( R_EAX, R_T );
nkeynes@417
   565
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   566
:}
nkeynes@361
   567
DMULS.L Rm, Rn {:  
nkeynes@361
   568
    load_reg( R_EAX, Rm );
nkeynes@361
   569
    load_reg( R_ECX, Rn );
nkeynes@361
   570
    IMUL_r32(R_ECX);
nkeynes@361
   571
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   572
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   573
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   574
:}
nkeynes@361
   575
DMULU.L Rm, Rn {:  
nkeynes@361
   576
    load_reg( R_EAX, Rm );
nkeynes@361
   577
    load_reg( R_ECX, Rn );
nkeynes@361
   578
    MUL_r32(R_ECX);
nkeynes@361
   579
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   580
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   582
:}
nkeynes@359
   583
DT Rn {:  
nkeynes@359
   584
    load_reg( R_EAX, Rn );
nkeynes@382
   585
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   586
    store_reg( R_EAX, Rn );
nkeynes@359
   587
    SETE_t();
nkeynes@417
   588
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   589
:}
nkeynes@359
   590
EXTS.B Rm, Rn {:  
nkeynes@359
   591
    load_reg( R_EAX, Rm );
nkeynes@359
   592
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   593
    store_reg( R_EAX, Rn );
nkeynes@359
   594
:}
nkeynes@361
   595
EXTS.W Rm, Rn {:  
nkeynes@361
   596
    load_reg( R_EAX, Rm );
nkeynes@361
   597
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   598
    store_reg( R_EAX, Rn );
nkeynes@361
   599
:}
nkeynes@361
   600
EXTU.B Rm, Rn {:  
nkeynes@361
   601
    load_reg( R_EAX, Rm );
nkeynes@361
   602
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   603
    store_reg( R_EAX, Rn );
nkeynes@361
   604
:}
nkeynes@361
   605
EXTU.W Rm, Rn {:  
nkeynes@361
   606
    load_reg( R_EAX, Rm );
nkeynes@361
   607
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   608
    store_reg( R_EAX, Rn );
nkeynes@361
   609
:}
nkeynes@571
   610
MAC.L @Rm+, @Rn+ {:
nkeynes@571
   611
    if( Rm == Rn ) {
nkeynes@571
   612
	load_reg( R_EAX, Rm );
nkeynes@571
   613
	check_ralign32( R_EAX );
nkeynes@571
   614
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   615
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   616
	load_reg( R_EAX, Rn );
nkeynes@571
   617
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@571
   618
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   619
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@571
   620
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   621
	// adding a page-boundary check to skip the second translation
nkeynes@571
   622
    } else {
nkeynes@571
   623
	load_reg( R_EAX, Rm );
nkeynes@571
   624
	check_ralign32( R_EAX );
nkeynes@571
   625
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   626
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   627
	load_reg( R_EAX, Rn );
nkeynes@571
   628
	check_ralign32( R_EAX );
nkeynes@571
   629
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   630
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   631
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
   632
    }
nkeynes@571
   633
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@571
   634
    POP_r32( R_ECX );
nkeynes@571
   635
    PUSH_r32( R_EAX );
nkeynes@386
   636
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   637
    POP_realigned_r32( R_ECX );
nkeynes@571
   638
nkeynes@386
   639
    IMUL_r32( R_ECX );
nkeynes@386
   640
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   641
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   642
nkeynes@386
   643
    load_spreg( R_ECX, R_S );
nkeynes@386
   644
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   645
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   646
    call_func0( signsat48 );
nkeynes@386
   647
    JMP_TARGET( nosat );
nkeynes@417
   648
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   649
:}
nkeynes@386
   650
MAC.W @Rm+, @Rn+ {:  
nkeynes@571
   651
    if( Rm == Rn ) {
nkeynes@571
   652
	load_reg( R_EAX, Rm );
nkeynes@571
   653
	check_ralign16( R_EAX );
nkeynes@571
   654
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   655
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   656
	load_reg( R_EAX, Rn );
nkeynes@571
   657
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@571
   658
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   659
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   660
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   661
	// adding a page-boundary check to skip the second translation
nkeynes@571
   662
    } else {
nkeynes@571
   663
	load_reg( R_EAX, Rm );
nkeynes@571
   664
	check_ralign16( R_EAX );
nkeynes@571
   665
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   666
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   667
	load_reg( R_EAX, Rn );
nkeynes@571
   668
	check_ralign16( R_EAX );
nkeynes@571
   669
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   670
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@571
   671
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
   672
    }
nkeynes@571
   673
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@571
   674
    POP_r32( R_ECX );
nkeynes@571
   675
    PUSH_r32( R_EAX );
nkeynes@386
   676
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   677
    POP_realigned_r32( R_ECX );
nkeynes@386
   678
    IMUL_r32( R_ECX );
nkeynes@386
   679
nkeynes@386
   680
    load_spreg( R_ECX, R_S );
nkeynes@386
   681
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   682
    JE_rel8( 47, nosat );
nkeynes@386
   683
nkeynes@386
   684
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   685
    JNO_rel8( 51, end );            // 2
nkeynes@386
   686
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   687
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   688
    JS_rel8( 13, positive );        // 2
nkeynes@386
   689
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   690
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   691
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   692
nkeynes@386
   693
    JMP_TARGET(positive);
nkeynes@386
   694
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   695
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   696
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   697
nkeynes@386
   698
    JMP_TARGET(nosat);
nkeynes@386
   699
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   700
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   701
    JMP_TARGET(end);
nkeynes@386
   702
    JMP_TARGET(end2);
nkeynes@386
   703
    JMP_TARGET(end3);
nkeynes@417
   704
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   705
:}
nkeynes@359
   706
MOVT Rn {:  
nkeynes@359
   707
    load_spreg( R_EAX, R_T );
nkeynes@359
   708
    store_reg( R_EAX, Rn );
nkeynes@359
   709
:}
nkeynes@361
   710
MUL.L Rm, Rn {:  
nkeynes@361
   711
    load_reg( R_EAX, Rm );
nkeynes@361
   712
    load_reg( R_ECX, Rn );
nkeynes@361
   713
    MUL_r32( R_ECX );
nkeynes@361
   714
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   715
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   716
:}
nkeynes@374
   717
MULS.W Rm, Rn {:
nkeynes@374
   718
    load_reg16s( R_EAX, Rm );
nkeynes@374
   719
    load_reg16s( R_ECX, Rn );
nkeynes@374
   720
    MUL_r32( R_ECX );
nkeynes@374
   721
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   722
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   723
:}
nkeynes@374
   724
MULU.W Rm, Rn {:  
nkeynes@374
   725
    load_reg16u( R_EAX, Rm );
nkeynes@374
   726
    load_reg16u( R_ECX, Rn );
nkeynes@374
   727
    MUL_r32( R_ECX );
nkeynes@374
   728
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   729
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   730
:}
nkeynes@359
   731
NEG Rm, Rn {:
nkeynes@359
   732
    load_reg( R_EAX, Rm );
nkeynes@359
   733
    NEG_r32( R_EAX );
nkeynes@359
   734
    store_reg( R_EAX, Rn );
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   736
:}
nkeynes@359
   737
NEGC Rm, Rn {:  
nkeynes@359
   738
    load_reg( R_EAX, Rm );
nkeynes@359
   739
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   740
    LDC_t();
nkeynes@359
   741
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   742
    store_reg( R_ECX, Rn );
nkeynes@359
   743
    SETC_t();
nkeynes@417
   744
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   745
:}
nkeynes@359
   746
NOT Rm, Rn {:  
nkeynes@359
   747
    load_reg( R_EAX, Rm );
nkeynes@359
   748
    NOT_r32( R_EAX );
nkeynes@359
   749
    store_reg( R_EAX, Rn );
nkeynes@417
   750
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   751
:}
nkeynes@359
   752
OR Rm, Rn {:  
nkeynes@359
   753
    load_reg( R_EAX, Rm );
nkeynes@359
   754
    load_reg( R_ECX, Rn );
nkeynes@359
   755
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   756
    store_reg( R_ECX, Rn );
nkeynes@417
   757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   758
:}
nkeynes@359
   759
OR #imm, R0 {:
nkeynes@359
   760
    load_reg( R_EAX, 0 );
nkeynes@359
   761
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   762
    store_reg( R_EAX, 0 );
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   764
:}
nkeynes@374
   765
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   766
    load_reg( R_EAX, 0 );
nkeynes@374
   767
    load_spreg( R_ECX, R_GBR );
nkeynes@571
   768
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   769
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   770
    PUSH_realigned_r32(R_EAX);
nkeynes@571
   771
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   772
    POP_realigned_r32(R_ECX);
nkeynes@386
   773
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   774
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   775
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   776
:}
nkeynes@359
   777
ROTCL Rn {:
nkeynes@359
   778
    load_reg( R_EAX, Rn );
nkeynes@417
   779
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   780
	LDC_t();
nkeynes@417
   781
    }
nkeynes@359
   782
    RCL1_r32( R_EAX );
nkeynes@359
   783
    store_reg( R_EAX, Rn );
nkeynes@359
   784
    SETC_t();
nkeynes@417
   785
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   786
:}
nkeynes@359
   787
ROTCR Rn {:  
nkeynes@359
   788
    load_reg( R_EAX, Rn );
nkeynes@417
   789
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   790
	LDC_t();
nkeynes@417
   791
    }
nkeynes@359
   792
    RCR1_r32( R_EAX );
nkeynes@359
   793
    store_reg( R_EAX, Rn );
nkeynes@359
   794
    SETC_t();
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   796
:}
nkeynes@359
   797
ROTL Rn {:  
nkeynes@359
   798
    load_reg( R_EAX, Rn );
nkeynes@359
   799
    ROL1_r32( R_EAX );
nkeynes@359
   800
    store_reg( R_EAX, Rn );
nkeynes@359
   801
    SETC_t();
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   803
:}
nkeynes@359
   804
ROTR Rn {:  
nkeynes@359
   805
    load_reg( R_EAX, Rn );
nkeynes@359
   806
    ROR1_r32( R_EAX );
nkeynes@359
   807
    store_reg( R_EAX, Rn );
nkeynes@359
   808
    SETC_t();
nkeynes@417
   809
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   810
:}
nkeynes@359
   811
SHAD Rm, Rn {:
nkeynes@359
   812
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   813
    load_reg( R_EAX, Rn );
nkeynes@361
   814
    load_reg( R_ECX, Rm );
nkeynes@361
   815
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   816
    JGE_rel8(16, doshl);
nkeynes@361
   817
                    
nkeynes@361
   818
    NEG_r32( R_ECX );      // 2
nkeynes@361
   819
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   820
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   821
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   822
    JMP_rel8(10, end);          // 2
nkeynes@386
   823
nkeynes@386
   824
    JMP_TARGET(emptysar);
nkeynes@386
   825
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   826
    JMP_rel8(5, end2);
nkeynes@382
   827
nkeynes@380
   828
    JMP_TARGET(doshl);
nkeynes@361
   829
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   830
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   831
    JMP_TARGET(end);
nkeynes@386
   832
    JMP_TARGET(end2);
nkeynes@361
   833
    store_reg( R_EAX, Rn );
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   835
:}
nkeynes@359
   836
SHLD Rm, Rn {:  
nkeynes@368
   837
    load_reg( R_EAX, Rn );
nkeynes@368
   838
    load_reg( R_ECX, Rm );
nkeynes@382
   839
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   840
    JGE_rel8(15, doshl);
nkeynes@368
   841
nkeynes@382
   842
    NEG_r32( R_ECX );      // 2
nkeynes@382
   843
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   844
    JE_rel8( 4, emptyshr );
nkeynes@382
   845
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   846
    JMP_rel8(9, end);          // 2
nkeynes@386
   847
nkeynes@386
   848
    JMP_TARGET(emptyshr);
nkeynes@386
   849
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   850
    JMP_rel8(5, end2);
nkeynes@382
   851
nkeynes@382
   852
    JMP_TARGET(doshl);
nkeynes@382
   853
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   854
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   855
    JMP_TARGET(end);
nkeynes@386
   856
    JMP_TARGET(end2);
nkeynes@368
   857
    store_reg( R_EAX, Rn );
nkeynes@417
   858
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   859
:}
nkeynes@359
   860
SHAL Rn {: 
nkeynes@359
   861
    load_reg( R_EAX, Rn );
nkeynes@359
   862
    SHL1_r32( R_EAX );
nkeynes@397
   863
    SETC_t();
nkeynes@359
   864
    store_reg( R_EAX, Rn );
nkeynes@417
   865
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   866
:}
nkeynes@359
   867
SHAR Rn {:  
nkeynes@359
   868
    load_reg( R_EAX, Rn );
nkeynes@359
   869
    SAR1_r32( R_EAX );
nkeynes@397
   870
    SETC_t();
nkeynes@359
   871
    store_reg( R_EAX, Rn );
nkeynes@417
   872
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   873
:}
nkeynes@359
   874
SHLL Rn {:  
nkeynes@359
   875
    load_reg( R_EAX, Rn );
nkeynes@359
   876
    SHL1_r32( R_EAX );
nkeynes@397
   877
    SETC_t();
nkeynes@359
   878
    store_reg( R_EAX, Rn );
nkeynes@417
   879
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   880
:}
nkeynes@359
   881
SHLL2 Rn {:
nkeynes@359
   882
    load_reg( R_EAX, Rn );
nkeynes@359
   883
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   884
    store_reg( R_EAX, Rn );
nkeynes@417
   885
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   886
:}
nkeynes@359
   887
SHLL8 Rn {:  
nkeynes@359
   888
    load_reg( R_EAX, Rn );
nkeynes@359
   889
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   890
    store_reg( R_EAX, Rn );
nkeynes@417
   891
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   892
:}
nkeynes@359
   893
SHLL16 Rn {:  
nkeynes@359
   894
    load_reg( R_EAX, Rn );
nkeynes@359
   895
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   896
    store_reg( R_EAX, Rn );
nkeynes@417
   897
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   898
:}
nkeynes@359
   899
SHLR Rn {:  
nkeynes@359
   900
    load_reg( R_EAX, Rn );
nkeynes@359
   901
    SHR1_r32( R_EAX );
nkeynes@397
   902
    SETC_t();
nkeynes@359
   903
    store_reg( R_EAX, Rn );
nkeynes@417
   904
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   905
:}
nkeynes@359
   906
SHLR2 Rn {:  
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@359
   908
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   909
    store_reg( R_EAX, Rn );
nkeynes@417
   910
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   911
:}
nkeynes@359
   912
SHLR8 Rn {:  
nkeynes@359
   913
    load_reg( R_EAX, Rn );
nkeynes@359
   914
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   915
    store_reg( R_EAX, Rn );
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   917
:}
nkeynes@359
   918
SHLR16 Rn {:  
nkeynes@359
   919
    load_reg( R_EAX, Rn );
nkeynes@359
   920
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   921
    store_reg( R_EAX, Rn );
nkeynes@417
   922
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   923
:}
nkeynes@359
   924
SUB Rm, Rn {:  
nkeynes@359
   925
    load_reg( R_EAX, Rm );
nkeynes@359
   926
    load_reg( R_ECX, Rn );
nkeynes@359
   927
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   928
    store_reg( R_ECX, Rn );
nkeynes@417
   929
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   930
:}
nkeynes@359
   931
SUBC Rm, Rn {:  
nkeynes@359
   932
    load_reg( R_EAX, Rm );
nkeynes@359
   933
    load_reg( R_ECX, Rn );
nkeynes@417
   934
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   935
	LDC_t();
nkeynes@417
   936
    }
nkeynes@359
   937
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   938
    store_reg( R_ECX, Rn );
nkeynes@394
   939
    SETC_t();
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   941
:}
nkeynes@359
   942
SUBV Rm, Rn {:  
nkeynes@359
   943
    load_reg( R_EAX, Rm );
nkeynes@359
   944
    load_reg( R_ECX, Rn );
nkeynes@359
   945
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   946
    store_reg( R_ECX, Rn );
nkeynes@359
   947
    SETO_t();
nkeynes@417
   948
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   949
:}
nkeynes@359
   950
SWAP.B Rm, Rn {:  
nkeynes@359
   951
    load_reg( R_EAX, Rm );
nkeynes@359
   952
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   953
    store_reg( R_EAX, Rn );
nkeynes@359
   954
:}
nkeynes@359
   955
SWAP.W Rm, Rn {:  
nkeynes@359
   956
    load_reg( R_EAX, Rm );
nkeynes@359
   957
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   958
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   959
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   960
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   961
    store_reg( R_ECX, Rn );
nkeynes@417
   962
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   963
:}
nkeynes@361
   964
TAS.B @Rn {:  
nkeynes@571
   965
    load_reg( R_EAX, Rn );
nkeynes@571
   966
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   967
    PUSH_realigned_r32( R_EAX );
nkeynes@571
   968
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
   969
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   970
    SETE_t();
nkeynes@361
   971
    OR_imm8_r8( 0x80, R_AL );
nkeynes@571
   972
    POP_realigned_r32( R_ECX );
nkeynes@361
   973
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   974
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   975
:}
nkeynes@361
   976
TST Rm, Rn {:  
nkeynes@361
   977
    load_reg( R_EAX, Rm );
nkeynes@361
   978
    load_reg( R_ECX, Rn );
nkeynes@361
   979
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   980
    SETE_t();
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   982
:}
nkeynes@368
   983
TST #imm, R0 {:  
nkeynes@368
   984
    load_reg( R_EAX, 0 );
nkeynes@368
   985
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   986
    SETE_t();
nkeynes@417
   987
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   988
:}
nkeynes@368
   989
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   990
    load_reg( R_EAX, 0);
nkeynes@368
   991
    load_reg( R_ECX, R_GBR);
nkeynes@571
   992
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   993
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   994
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
   995
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   996
    SETE_t();
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   998
:}
nkeynes@359
   999
XOR Rm, Rn {:  
nkeynes@359
  1000
    load_reg( R_EAX, Rm );
nkeynes@359
  1001
    load_reg( R_ECX, Rn );
nkeynes@359
  1002
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1003
    store_reg( R_ECX, Rn );
nkeynes@417
  1004
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1005
:}
nkeynes@359
  1006
XOR #imm, R0 {:  
nkeynes@359
  1007
    load_reg( R_EAX, 0 );
nkeynes@359
  1008
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1009
    store_reg( R_EAX, 0 );
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1011
:}
nkeynes@359
  1012
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1013
    load_reg( R_EAX, 0 );
nkeynes@359
  1014
    load_spreg( R_ECX, R_GBR );
nkeynes@571
  1015
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1016
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1017
    PUSH_realigned_r32(R_EAX);
nkeynes@571
  1018
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1019
    POP_realigned_r32(R_ECX);
nkeynes@359
  1020
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1021
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1023
:}
nkeynes@361
  1024
XTRCT Rm, Rn {:
nkeynes@361
  1025
    load_reg( R_EAX, Rm );
nkeynes@394
  1026
    load_reg( R_ECX, Rn );
nkeynes@394
  1027
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1028
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1029
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1030
    store_reg( R_ECX, Rn );
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1032
:}
nkeynes@359
  1033
nkeynes@359
  1034
/* Data move instructions */
nkeynes@359
  1035
MOV Rm, Rn {:  
nkeynes@359
  1036
    load_reg( R_EAX, Rm );
nkeynes@359
  1037
    store_reg( R_EAX, Rn );
nkeynes@359
  1038
:}
nkeynes@359
  1039
MOV #imm, Rn {:  
nkeynes@359
  1040
    load_imm32( R_EAX, imm );
nkeynes@359
  1041
    store_reg( R_EAX, Rn );
nkeynes@359
  1042
:}
nkeynes@359
  1043
MOV.B Rm, @Rn {:  
nkeynes@571
  1044
    load_reg( R_EAX, Rn );
nkeynes@571
  1045
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1046
    load_reg( R_EDX, Rm );
nkeynes@571
  1047
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1048
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1049
:}
nkeynes@359
  1050
MOV.B Rm, @-Rn {:  
nkeynes@571
  1051
    load_reg( R_EAX, Rn );
nkeynes@571
  1052
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@571
  1053
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1054
    load_reg( R_EDX, Rm );
nkeynes@571
  1055
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@571
  1056
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1057
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1058
:}
nkeynes@359
  1059
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1060
    load_reg( R_EAX, 0 );
nkeynes@359
  1061
    load_reg( R_ECX, Rn );
nkeynes@571
  1062
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1063
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1064
    load_reg( R_EDX, Rm );
nkeynes@571
  1065
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1067
:}
nkeynes@359
  1068
MOV.B R0, @(disp, GBR) {:  
nkeynes@571
  1069
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1070
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1071
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1072
    load_reg( R_EDX, 0 );
nkeynes@571
  1073
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1075
:}
nkeynes@359
  1076
MOV.B R0, @(disp, Rn) {:  
nkeynes@571
  1077
    load_reg( R_EAX, Rn );
nkeynes@571
  1078
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1079
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1080
    load_reg( R_EDX, 0 );
nkeynes@571
  1081
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1083
:}
nkeynes@359
  1084
MOV.B @Rm, Rn {:  
nkeynes@571
  1085
    load_reg( R_EAX, Rm );
nkeynes@571
  1086
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1087
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1088
    store_reg( R_EAX, Rn );
nkeynes@417
  1089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1090
:}
nkeynes@359
  1091
MOV.B @Rm+, Rn {:  
nkeynes@571
  1092
    load_reg( R_EAX, Rm );
nkeynes@571
  1093
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1094
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@571
  1095
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1096
    store_reg( R_EAX, Rn );
nkeynes@417
  1097
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1098
:}
nkeynes@359
  1099
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1100
    load_reg( R_EAX, 0 );
nkeynes@359
  1101
    load_reg( R_ECX, Rm );
nkeynes@571
  1102
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1103
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@571
  1104
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1105
    store_reg( R_EAX, Rn );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV.B @(disp, GBR), R0 {:  
nkeynes@571
  1109
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1110
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1111
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1112
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1113
    store_reg( R_EAX, 0 );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
:}
nkeynes@359
  1116
MOV.B @(disp, Rm), R0 {:  
nkeynes@571
  1117
    load_reg( R_EAX, Rm );
nkeynes@571
  1118
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1119
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1120
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1121
    store_reg( R_EAX, 0 );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1123
:}
nkeynes@374
  1124
MOV.L Rm, @Rn {:
nkeynes@571
  1125
    load_reg( R_EAX, Rn );
nkeynes@571
  1126
    check_walign32(R_EAX);
nkeynes@571
  1127
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1128
    load_reg( R_EDX, Rm );
nkeynes@571
  1129
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1131
:}
nkeynes@361
  1132
MOV.L Rm, @-Rn {:  
nkeynes@571
  1133
    load_reg( R_EAX, Rn );
nkeynes@571
  1134
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1135
    check_walign32( R_EAX );
nkeynes@571
  1136
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1137
    load_reg( R_EDX, Rm );
nkeynes@571
  1138
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1139
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1140
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1141
:}
nkeynes@361
  1142
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1143
    load_reg( R_EAX, 0 );
nkeynes@361
  1144
    load_reg( R_ECX, Rn );
nkeynes@571
  1145
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1146
    check_walign32( R_EAX );
nkeynes@571
  1147
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1148
    load_reg( R_EDX, Rm );
nkeynes@571
  1149
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1150
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1151
:}
nkeynes@361
  1152
MOV.L R0, @(disp, GBR) {:  
nkeynes@571
  1153
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1154
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1155
    check_walign32( R_EAX );
nkeynes@571
  1156
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1157
    load_reg( R_EDX, 0 );
nkeynes@571
  1158
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1159
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1160
:}
nkeynes@361
  1161
MOV.L Rm, @(disp, Rn) {:  
nkeynes@571
  1162
    load_reg( R_EAX, Rn );
nkeynes@571
  1163
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1164
    check_walign32( R_EAX );
nkeynes@571
  1165
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1166
    load_reg( R_EDX, Rm );
nkeynes@571
  1167
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1168
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1169
:}
nkeynes@361
  1170
MOV.L @Rm, Rn {:  
nkeynes@571
  1171
    load_reg( R_EAX, Rm );
nkeynes@571
  1172
    check_ralign32( R_EAX );
nkeynes@571
  1173
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1174
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1175
    store_reg( R_EAX, Rn );
nkeynes@417
  1176
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1177
:}
nkeynes@361
  1178
MOV.L @Rm+, Rn {:  
nkeynes@361
  1179
    load_reg( R_EAX, Rm );
nkeynes@382
  1180
    check_ralign32( R_EAX );
nkeynes@571
  1181
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1182
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1183
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1184
    store_reg( R_EAX, Rn );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1186
:}
nkeynes@361
  1187
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1188
    load_reg( R_EAX, 0 );
nkeynes@361
  1189
    load_reg( R_ECX, Rm );
nkeynes@571
  1190
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1191
    check_ralign32( R_EAX );
nkeynes@571
  1192
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1193
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1194
    store_reg( R_EAX, Rn );
nkeynes@417
  1195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1196
:}
nkeynes@361
  1197
MOV.L @(disp, GBR), R0 {:
nkeynes@571
  1198
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1199
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1200
    check_ralign32( R_EAX );
nkeynes@571
  1201
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1202
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1203
    store_reg( R_EAX, 0 );
nkeynes@417
  1204
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1205
:}
nkeynes@361
  1206
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1207
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1208
	SLOTILLEGAL();
nkeynes@374
  1209
    } else {
nkeynes@388
  1210
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  1211
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1212
	    // If the target address is in the same page as the code, it's
nkeynes@569
  1213
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  1214
	    // memory subsystem. (this is a big performance win)
nkeynes@569
  1215
nkeynes@569
  1216
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  1217
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  1218
	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  1219
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  1220
	    // behaviour though.
nkeynes@569
  1221
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1222
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1223
	} else {
nkeynes@569
  1224
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  1225
	    // different virtual address than the translation was done with,
nkeynes@569
  1226
	    // but we can safely assume that the low bits are the same.
nkeynes@571
  1227
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@571
  1228
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@571
  1229
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1230
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@569
  1231
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1232
	}
nkeynes@382
  1233
	store_reg( R_EAX, Rn );
nkeynes@374
  1234
    }
nkeynes@361
  1235
:}
nkeynes@361
  1236
MOV.L @(disp, Rm), Rn {:  
nkeynes@571
  1237
    load_reg( R_EAX, Rm );
nkeynes@571
  1238
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@571
  1239
    check_ralign32( R_EAX );
nkeynes@571
  1240
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1241
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1242
    store_reg( R_EAX, Rn );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.W Rm, @Rn {:  
nkeynes@571
  1246
    load_reg( R_EAX, Rn );
nkeynes@571
  1247
    check_walign16( R_EAX );
nkeynes@571
  1248
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@571
  1249
    load_reg( R_EDX, Rm );
nkeynes@571
  1250
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1251
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1252
:}
nkeynes@361
  1253
MOV.W Rm, @-Rn {:  
nkeynes@571
  1254
    load_reg( R_EAX, Rn );
nkeynes@571
  1255
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@571
  1256
    check_walign16( R_EAX );
nkeynes@571
  1257
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1258
    load_reg( R_EDX, Rm );
nkeynes@571
  1259
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@571
  1260
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1261
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1262
:}
nkeynes@361
  1263
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1264
    load_reg( R_EAX, 0 );
nkeynes@361
  1265
    load_reg( R_ECX, Rn );
nkeynes@571
  1266
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1267
    check_walign16( R_EAX );
nkeynes@571
  1268
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1269
    load_reg( R_EDX, Rm );
nkeynes@571
  1270
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1271
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1272
:}
nkeynes@361
  1273
MOV.W R0, @(disp, GBR) {:  
nkeynes@571
  1274
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1275
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1276
    check_walign16( R_EAX );
nkeynes@571
  1277
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1278
    load_reg( R_EDX, 0 );
nkeynes@571
  1279
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1280
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1281
:}
nkeynes@361
  1282
MOV.W R0, @(disp, Rn) {:  
nkeynes@571
  1283
    load_reg( R_EAX, Rn );
nkeynes@571
  1284
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1285
    check_walign16( R_EAX );
nkeynes@571
  1286
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1287
    load_reg( R_EDX, 0 );
nkeynes@571
  1288
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1290
:}
nkeynes@361
  1291
MOV.W @Rm, Rn {:  
nkeynes@571
  1292
    load_reg( R_EAX, Rm );
nkeynes@571
  1293
    check_ralign16( R_EAX );
nkeynes@571
  1294
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1295
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1296
    store_reg( R_EAX, Rn );
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1298
:}
nkeynes@361
  1299
MOV.W @Rm+, Rn {:  
nkeynes@361
  1300
    load_reg( R_EAX, Rm );
nkeynes@374
  1301
    check_ralign16( R_EAX );
nkeynes@571
  1302
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1303
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
  1304
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1305
    store_reg( R_EAX, Rn );
nkeynes@417
  1306
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1307
:}
nkeynes@361
  1308
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1309
    load_reg( R_EAX, 0 );
nkeynes@361
  1310
    load_reg( R_ECX, Rm );
nkeynes@571
  1311
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1312
    check_ralign16( R_EAX );
nkeynes@571
  1313
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1314
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1315
    store_reg( R_EAX, Rn );
nkeynes@417
  1316
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1317
:}
nkeynes@361
  1318
MOV.W @(disp, GBR), R0 {:  
nkeynes@571
  1319
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1320
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1321
    check_ralign16( R_EAX );
nkeynes@571
  1322
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1323
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1324
    store_reg( R_EAX, 0 );
nkeynes@417
  1325
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1326
:}
nkeynes@361
  1327
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1328
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1329
	SLOTILLEGAL();
nkeynes@374
  1330
    } else {
nkeynes@569
  1331
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  1332
	uint32_t target = pc + disp + 4;
nkeynes@569
  1333
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1334
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  1335
	    MOV_moff32_EAX( ptr );
nkeynes@569
  1336
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  1337
	} else {
nkeynes@571
  1338
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@571
  1339
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@571
  1340
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1341
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@569
  1342
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  1343
	}
nkeynes@374
  1344
	store_reg( R_EAX, Rn );
nkeynes@374
  1345
    }
nkeynes@361
  1346
:}
nkeynes@361
  1347
MOV.W @(disp, Rm), R0 {:  
nkeynes@571
  1348
    load_reg( R_EAX, Rm );
nkeynes@571
  1349
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1350
    check_ralign16( R_EAX );
nkeynes@571
  1351
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1352
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1353
    store_reg( R_EAX, 0 );
nkeynes@417
  1354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1355
:}
nkeynes@361
  1356
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1357
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1358
	SLOTILLEGAL();
nkeynes@374
  1359
    } else {
nkeynes@569
  1360
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1361
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1362
	store_reg( R_ECX, 0 );
nkeynes@571
  1363
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1364
    }
nkeynes@361
  1365
:}
nkeynes@361
  1366
MOVCA.L R0, @Rn {:  
nkeynes@571
  1367
    load_reg( R_EAX, Rn );
nkeynes@571
  1368
    check_walign32( R_EAX );
nkeynes@571
  1369
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1370
    load_reg( R_EDX, 0 );
nkeynes@571
  1371
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1373
:}
nkeynes@359
  1374
nkeynes@359
  1375
/* Control transfer instructions */
nkeynes@374
  1376
BF disp {:
nkeynes@374
  1377
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1378
	SLOTILLEGAL();
nkeynes@374
  1379
    } else {
nkeynes@571
  1380
	sh4vma_t target = disp + pc + 4;
nkeynes@571
  1381
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  1382
	exit_block_rel(target, pc+2 );
nkeynes@380
  1383
	JMP_TARGET(nottaken);
nkeynes@408
  1384
	return 2;
nkeynes@374
  1385
    }
nkeynes@374
  1386
:}
nkeynes@374
  1387
BF/S disp {:
nkeynes@374
  1388
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1389
	SLOTILLEGAL();
nkeynes@374
  1390
    } else {
nkeynes@571
  1391
	sh4vma_t target = disp + pc + 4;
nkeynes@408
  1392
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1393
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1394
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1395
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1396
	}
nkeynes@417
  1397
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1398
	sh4_translate_instruction(pc+2);
nkeynes@571
  1399
	exit_block_rel( target, pc+4 );
nkeynes@408
  1400
	// not taken
nkeynes@408
  1401
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1402
	sh4_translate_instruction(pc+2);
nkeynes@408
  1403
	return 4;
nkeynes@374
  1404
    }
nkeynes@374
  1405
:}
nkeynes@374
  1406
BRA disp {:  
nkeynes@374
  1407
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1408
	SLOTILLEGAL();
nkeynes@374
  1409
    } else {
nkeynes@374
  1410
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1411
	sh4_translate_instruction( pc + 2 );
nkeynes@571
  1412
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1413
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1414
	return 4;
nkeynes@374
  1415
    }
nkeynes@374
  1416
:}
nkeynes@374
  1417
BRAF Rn {:  
nkeynes@374
  1418
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1419
	SLOTILLEGAL();
nkeynes@374
  1420
    } else {
nkeynes@408
  1421
	load_reg( R_EAX, Rn );
nkeynes@408
  1422
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1423
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1424
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1425
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1426
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1427
	exit_block_pcset(pc+2);
nkeynes@409
  1428
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1429
	return 4;
nkeynes@374
  1430
    }
nkeynes@374
  1431
:}
nkeynes@374
  1432
BSR disp {:  
nkeynes@374
  1433
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1434
	SLOTILLEGAL();
nkeynes@374
  1435
    } else {
nkeynes@374
  1436
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1437
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1438
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1439
	sh4_translate_instruction( pc + 2 );
nkeynes@571
  1440
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1441
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1442
	return 4;
nkeynes@374
  1443
    }
nkeynes@374
  1444
:}
nkeynes@374
  1445
BSRF Rn {:  
nkeynes@374
  1446
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1447
	SLOTILLEGAL();
nkeynes@374
  1448
    } else {
nkeynes@408
  1449
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1450
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1451
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1452
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1453
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1454
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1455
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1456
	exit_block_pcset(pc+2);
nkeynes@409
  1457
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1458
	return 4;
nkeynes@374
  1459
    }
nkeynes@374
  1460
:}
nkeynes@374
  1461
BT disp {:
nkeynes@374
  1462
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1463
	SLOTILLEGAL();
nkeynes@374
  1464
    } else {
nkeynes@571
  1465
	sh4vma_t target = disp + pc + 4;
nkeynes@571
  1466
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  1467
	exit_block_rel(target, pc+2 );
nkeynes@380
  1468
	JMP_TARGET(nottaken);
nkeynes@408
  1469
	return 2;
nkeynes@374
  1470
    }
nkeynes@374
  1471
:}
nkeynes@374
  1472
BT/S disp {:
nkeynes@374
  1473
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1474
	SLOTILLEGAL();
nkeynes@374
  1475
    } else {
nkeynes@408
  1476
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1477
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1478
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1479
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1480
	}
nkeynes@417
  1481
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1482
	sh4_translate_instruction(pc+2);
nkeynes@571
  1483
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  1484
	// not taken
nkeynes@408
  1485
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1486
	sh4_translate_instruction(pc+2);
nkeynes@408
  1487
	return 4;
nkeynes@374
  1488
    }
nkeynes@374
  1489
:}
nkeynes@374
  1490
JMP @Rn {:  
nkeynes@374
  1491
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1492
	SLOTILLEGAL();
nkeynes@374
  1493
    } else {
nkeynes@408
  1494
	load_reg( R_ECX, Rn );
nkeynes@408
  1495
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1496
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1497
	sh4_translate_instruction(pc+2);
nkeynes@408
  1498
	exit_block_pcset(pc+2);
nkeynes@409
  1499
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1500
	return 4;
nkeynes@374
  1501
    }
nkeynes@374
  1502
:}
nkeynes@374
  1503
JSR @Rn {:  
nkeynes@374
  1504
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1505
	SLOTILLEGAL();
nkeynes@374
  1506
    } else {
nkeynes@374
  1507
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1508
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1509
	load_reg( R_ECX, Rn );
nkeynes@408
  1510
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1511
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1512
	sh4_translate_instruction(pc+2);
nkeynes@408
  1513
	exit_block_pcset(pc+2);
nkeynes@409
  1514
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1515
	return 4;
nkeynes@374
  1516
    }
nkeynes@374
  1517
:}
nkeynes@374
  1518
RTE {:  
nkeynes@374
  1519
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1520
	SLOTILLEGAL();
nkeynes@374
  1521
    } else {
nkeynes@408
  1522
	check_priv();
nkeynes@408
  1523
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1524
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1525
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1526
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1527
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1528
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1529
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1530
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1531
	sh4_translate_instruction(pc+2);
nkeynes@408
  1532
	exit_block_pcset(pc+2);
nkeynes@409
  1533
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1534
	return 4;
nkeynes@374
  1535
    }
nkeynes@374
  1536
:}
nkeynes@374
  1537
RTS {:  
nkeynes@374
  1538
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1539
	SLOTILLEGAL();
nkeynes@374
  1540
    } else {
nkeynes@408
  1541
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1542
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1543
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1544
	sh4_translate_instruction(pc+2);
nkeynes@408
  1545
	exit_block_pcset(pc+2);
nkeynes@409
  1546
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1547
	return 4;
nkeynes@374
  1548
    }
nkeynes@374
  1549
:}
nkeynes@374
  1550
TRAPA #imm {:  
nkeynes@374
  1551
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1552
	SLOTILLEGAL();
nkeynes@374
  1553
    } else {
nkeynes@533
  1554
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1555
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1556
	load_imm32( R_EAX, imm );
nkeynes@527
  1557
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1558
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1559
	exit_block_pcset(pc);
nkeynes@409
  1560
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1561
	return 2;
nkeynes@374
  1562
    }
nkeynes@374
  1563
:}
nkeynes@374
  1564
UNDEF {:  
nkeynes@374
  1565
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1566
	SLOTILLEGAL();
nkeynes@374
  1567
    } else {
nkeynes@559
  1568
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1569
	return 2;
nkeynes@374
  1570
    }
nkeynes@368
  1571
:}
nkeynes@374
  1572
nkeynes@374
  1573
CLRMAC {:  
nkeynes@374
  1574
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1575
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1576
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1577
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1578
:}
nkeynes@374
  1579
CLRS {:
nkeynes@374
  1580
    CLC();
nkeynes@374
  1581
    SETC_sh4r(R_S);
nkeynes@417
  1582
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1583
:}
nkeynes@374
  1584
CLRT {:  
nkeynes@374
  1585
    CLC();
nkeynes@374
  1586
    SETC_t();
nkeynes@417
  1587
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1588
:}
nkeynes@374
  1589
SETS {:  
nkeynes@374
  1590
    STC();
nkeynes@374
  1591
    SETC_sh4r(R_S);
nkeynes@417
  1592
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1593
:}
nkeynes@374
  1594
SETT {:  
nkeynes@374
  1595
    STC();
nkeynes@374
  1596
    SETC_t();
nkeynes@417
  1597
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1598
:}
nkeynes@359
  1599
nkeynes@375
  1600
/* Floating point moves */
nkeynes@375
  1601
FMOV FRm, FRn {:  
nkeynes@375
  1602
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1603
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1604
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1605
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1606
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1607
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1608
     */
nkeynes@377
  1609
    check_fpuen();
nkeynes@375
  1610
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1611
    load_fr_bank( R_EDX );
nkeynes@375
  1612
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1613
    JNE_rel8(8, doublesize);
nkeynes@375
  1614
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1615
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1616
    if( FRm&1 ) {
nkeynes@386
  1617
	JMP_rel8(24, end);
nkeynes@380
  1618
	JMP_TARGET(doublesize);
nkeynes@375
  1619
	load_xf_bank( R_ECX ); 
nkeynes@375
  1620
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1621
	if( FRn&1 ) {
nkeynes@375
  1622
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1623
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1624
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1625
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1626
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1627
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1628
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1629
	}
nkeynes@380
  1630
	JMP_TARGET(end);
nkeynes@375
  1631
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1632
	if( FRn&1 ) {
nkeynes@386
  1633
	    JMP_rel8(24, end);
nkeynes@375
  1634
	    load_xf_bank( R_ECX );
nkeynes@375
  1635
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1636
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1637
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1638
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1639
	    JMP_TARGET(end);
nkeynes@375
  1640
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1641
	    JMP_rel8(12, end);
nkeynes@375
  1642
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1643
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1644
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1645
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1646
	    JMP_TARGET(end);
nkeynes@375
  1647
	}
nkeynes@375
  1648
    }
nkeynes@417
  1649
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1650
:}
nkeynes@416
  1651
FMOV FRm, @Rn {: 
nkeynes@559
  1652
    check_fpuen();
nkeynes@571
  1653
    load_reg( R_EAX, Rn );
nkeynes@571
  1654
    check_walign32( R_EAX );
nkeynes@571
  1655
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1656
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1657
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1658
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1659
    load_fr_bank( R_EDX );
nkeynes@571
  1660
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1661
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1662
    if( FRm&1 ) {
nkeynes@527
  1663
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1664
	JMP_TARGET(doublesize);
nkeynes@416
  1665
	load_xf_bank( R_EDX );
nkeynes@571
  1666
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1667
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1668
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1669
	JMP_TARGET(end);
nkeynes@375
  1670
    } else {
nkeynes@527
  1671
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1672
	JMP_TARGET(doublesize);
nkeynes@416
  1673
	load_fr_bank( R_EDX );
nkeynes@571
  1674
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1675
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1676
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1677
	JMP_TARGET(end);
nkeynes@375
  1678
    }
nkeynes@417
  1679
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1680
:}
nkeynes@375
  1681
FMOV @Rm, FRn {:  
nkeynes@559
  1682
    check_fpuen();
nkeynes@571
  1683
    load_reg( R_EAX, Rm );
nkeynes@571
  1684
    check_ralign32( R_EAX );
nkeynes@571
  1685
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1686
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1687
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1688
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1689
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1690
    load_fr_bank( R_EDX );
nkeynes@416
  1691
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1692
    if( FRn&1 ) {
nkeynes@527
  1693
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1694
	JMP_TARGET(doublesize);
nkeynes@571
  1695
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1696
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1697
	load_xf_bank( R_EDX );
nkeynes@571
  1698
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1699
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1700
	JMP_TARGET(end);
nkeynes@375
  1701
    } else {
nkeynes@527
  1702
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1703
	JMP_TARGET(doublesize);
nkeynes@571
  1704
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1705
	load_fr_bank( R_EDX );
nkeynes@571
  1706
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1707
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1708
	JMP_TARGET(end);
nkeynes@375
  1709
    }
nkeynes@417
  1710
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1711
:}
nkeynes@377
  1712
FMOV FRm, @-Rn {:  
nkeynes@559
  1713
    check_fpuen();
nkeynes@571
  1714
    load_reg( R_EAX, Rn );
nkeynes@571
  1715
    check_walign32( R_EAX );
nkeynes@416
  1716
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1717
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@571
  1718
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@571
  1719
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1720
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1721
    load_fr_bank( R_EDX );
nkeynes@571
  1722
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1723
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@571
  1724
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1725
    if( FRm&1 ) {
nkeynes@571
  1726
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1727
	JMP_TARGET(doublesize);
nkeynes@571
  1728
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@571
  1729
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1730
	load_xf_bank( R_EDX );
nkeynes@571
  1731
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1732
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1733
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@571
  1734
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1735
	JMP_TARGET(end);
nkeynes@377
  1736
    } else {
nkeynes@571
  1737
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1738
	JMP_TARGET(doublesize);
nkeynes@571
  1739
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@571
  1740
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1741
	load_fr_bank( R_EDX );
nkeynes@571
  1742
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1743
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1744
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@571
  1745
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1746
	JMP_TARGET(end);
nkeynes@377
  1747
    }
nkeynes@417
  1748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1749
:}
nkeynes@416
  1750
FMOV @Rm+, FRn {:
nkeynes@559
  1751
    check_fpuen();
nkeynes@571
  1752
    load_reg( R_EAX, Rm );
nkeynes@571
  1753
    check_ralign32( R_EAX );
nkeynes@571
  1754
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1755
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1756
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@571
  1757
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1758
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1759
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1760
    load_fr_bank( R_EDX );
nkeynes@416
  1761
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1762
    if( FRn&1 ) {
nkeynes@571
  1763
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1764
	JMP_TARGET(doublesize);
nkeynes@571
  1765
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@571
  1766
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1767
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1768
	load_xf_bank( R_EDX );
nkeynes@571
  1769
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1770
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1771
	JMP_TARGET(end);
nkeynes@377
  1772
    } else {
nkeynes@571
  1773
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@571
  1774
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@571
  1775
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1776
	load_fr_bank( R_EDX );
nkeynes@571
  1777
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1778
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1779
	JMP_TARGET(end);
nkeynes@377
  1780
    }
nkeynes@417
  1781
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1782
:}
nkeynes@377
  1783
FMOV FRm, @(R0, Rn) {:  
nkeynes@559
  1784
    check_fpuen();
nkeynes@571
  1785
    load_reg( R_EAX, Rn );
nkeynes@571
  1786
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@571
  1787
    check_walign32( R_EAX );
nkeynes@571
  1788
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1789
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1790
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1791
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1792
    load_fr_bank( R_EDX );
nkeynes@571
  1793
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1794
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1795
    if( FRm&1 ) {
nkeynes@527
  1796
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1797
	JMP_TARGET(doublesize);
nkeynes@416
  1798
	load_xf_bank( R_EDX );
nkeynes@571
  1799
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1800
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1801
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1802
	JMP_TARGET(end);
nkeynes@377
  1803
    } else {
nkeynes@527
  1804
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1805
	JMP_TARGET(doublesize);
nkeynes@416
  1806
	load_fr_bank( R_EDX );
nkeynes@571
  1807
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1808
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1809
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1810
	JMP_TARGET(end);
nkeynes@377
  1811
    }
nkeynes@417
  1812
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1813
:}
nkeynes@377
  1814
FMOV @(R0, Rm), FRn {:  
nkeynes@559
  1815
    check_fpuen();
nkeynes@571
  1816
    load_reg( R_EAX, Rm );
nkeynes@571
  1817
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@571
  1818
    check_ralign32( R_EAX );
nkeynes@571
  1819
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1820
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1821
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1822
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1823
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1824
    load_fr_bank( R_EDX );
nkeynes@416
  1825
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1826
    if( FRn&1 ) {
nkeynes@527
  1827
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1828
	JMP_TARGET(doublesize);
nkeynes@571
  1829
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1830
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1831
	load_xf_bank( R_EDX );
nkeynes@571
  1832
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1833
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1834
	JMP_TARGET(end);
nkeynes@377
  1835
    } else {
nkeynes@527
  1836
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1837
	JMP_TARGET(doublesize);
nkeynes@571
  1838
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1839
	load_fr_bank( R_EDX );
nkeynes@571
  1840
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1841
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1842
	JMP_TARGET(end);
nkeynes@377
  1843
    }
nkeynes@417
  1844
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1845
:}
nkeynes@377
  1846
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1847
    check_fpuen();
nkeynes@377
  1848
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1849
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1850
    JNE_rel8(8, end);
nkeynes@377
  1851
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1852
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1853
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1854
    JMP_TARGET(end);
nkeynes@417
  1855
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1856
:}
nkeynes@377
  1857
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1858
    check_fpuen();
nkeynes@377
  1859
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1860
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1861
    JNE_rel8(11, end);
nkeynes@377
  1862
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1863
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1864
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1865
    JMP_TARGET(end);
nkeynes@417
  1866
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1867
:}
nkeynes@377
  1868
nkeynes@377
  1869
FLOAT FPUL, FRn {:  
nkeynes@377
  1870
    check_fpuen();
nkeynes@377
  1871
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1872
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1873
    FILD_sh4r(R_FPUL);
nkeynes@377
  1874
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1875
    JNE_rel8(5, doubleprec);
nkeynes@377
  1876
    pop_fr( R_EDX, FRn );
nkeynes@380
  1877
    JMP_rel8(3, end);
nkeynes@380
  1878
    JMP_TARGET(doubleprec);
nkeynes@377
  1879
    pop_dr( R_EDX, FRn );
nkeynes@380
  1880
    JMP_TARGET(end);
nkeynes@417
  1881
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1882
:}
nkeynes@377
  1883
FTRC FRm, FPUL {:  
nkeynes@377
  1884
    check_fpuen();
nkeynes@388
  1885
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1886
    load_fr_bank( R_EDX );
nkeynes@388
  1887
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1888
    JNE_rel8(5, doubleprec);
nkeynes@388
  1889
    push_fr( R_EDX, FRm );
nkeynes@388
  1890
    JMP_rel8(3, doop);
nkeynes@388
  1891
    JMP_TARGET(doubleprec);
nkeynes@388
  1892
    push_dr( R_EDX, FRm );
nkeynes@388
  1893
    JMP_TARGET( doop );
nkeynes@388
  1894
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1895
    FILD_r32ind( R_ECX );
nkeynes@388
  1896
    FCOMIP_st(1);
nkeynes@394
  1897
    JNA_rel8( 32, sat );
nkeynes@388
  1898
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1899
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1900
    FCOMIP_st(1);                   // 2
nkeynes@394
  1901
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1902
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1903
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1904
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1905
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1906
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1907
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1908
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1909
nkeynes@388
  1910
    JMP_TARGET(sat);
nkeynes@388
  1911
    JMP_TARGET(sat2);
nkeynes@388
  1912
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1913
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1914
    FPOP_st();
nkeynes@388
  1915
    JMP_TARGET(end);
nkeynes@417
  1916
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1917
:}
nkeynes@377
  1918
FLDS FRm, FPUL {:  
nkeynes@377
  1919
    check_fpuen();
nkeynes@377
  1920
    load_fr_bank( R_ECX );
nkeynes@377
  1921
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1922
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1923
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1924
:}
nkeynes@377
  1925
FSTS FPUL, FRn {:  
nkeynes@377
  1926
    check_fpuen();
nkeynes@377
  1927
    load_fr_bank( R_ECX );
nkeynes@377
  1928
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1929
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1930
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1931
:}
nkeynes@377
  1932
FCNVDS FRm, FPUL {:  
nkeynes@377
  1933
    check_fpuen();
nkeynes@377
  1934
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1935
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1936
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1937
    load_fr_bank( R_ECX );
nkeynes@377
  1938
    push_dr( R_ECX, FRm );
nkeynes@377
  1939
    pop_fpul();
nkeynes@380
  1940
    JMP_TARGET(end);
nkeynes@417
  1941
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1942
:}
nkeynes@377
  1943
FCNVSD FPUL, FRn {:  
nkeynes@377
  1944
    check_fpuen();
nkeynes@377
  1945
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1946
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1947
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1948
    load_fr_bank( R_ECX );
nkeynes@377
  1949
    push_fpul();
nkeynes@377
  1950
    pop_dr( R_ECX, FRn );
nkeynes@380
  1951
    JMP_TARGET(end);
nkeynes@417
  1952
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1953
:}
nkeynes@375
  1954
nkeynes@359
  1955
/* Floating point instructions */
nkeynes@374
  1956
FABS FRn {:  
nkeynes@377
  1957
    check_fpuen();
nkeynes@374
  1958
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1959
    load_fr_bank( R_EDX );
nkeynes@374
  1960
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1961
    JNE_rel8(10, doubleprec);
nkeynes@374
  1962
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1963
    FABS_st0(); // 2
nkeynes@374
  1964
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1965
    JMP_rel8(8,end); // 2
nkeynes@380
  1966
    JMP_TARGET(doubleprec);
nkeynes@374
  1967
    push_dr(R_EDX, FRn);
nkeynes@374
  1968
    FABS_st0();
nkeynes@374
  1969
    pop_dr(R_EDX, FRn);
nkeynes@380
  1970
    JMP_TARGET(end);
nkeynes@417
  1971
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1972
:}
nkeynes@377
  1973
FADD FRm, FRn {:  
nkeynes@377
  1974
    check_fpuen();
nkeynes@375
  1975
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1976
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1977
    load_fr_bank( R_EDX );
nkeynes@380
  1978
    JNE_rel8(13,doubleprec);
nkeynes@377
  1979
    push_fr(R_EDX, FRm);
nkeynes@377
  1980
    push_fr(R_EDX, FRn);
nkeynes@377
  1981
    FADDP_st(1);
nkeynes@377
  1982
    pop_fr(R_EDX, FRn);
nkeynes@380
  1983
    JMP_rel8(11,end);
nkeynes@380
  1984
    JMP_TARGET(doubleprec);
nkeynes@377
  1985
    push_dr(R_EDX, FRm);
nkeynes@377
  1986
    push_dr(R_EDX, FRn);
nkeynes@377
  1987
    FADDP_st(1);
nkeynes@377
  1988
    pop_dr(R_EDX, FRn);
nkeynes@380
  1989
    JMP_TARGET(end);
nkeynes@417
  1990
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1991
:}
nkeynes@377
  1992
FDIV FRm, FRn {:  
nkeynes@377
  1993
    check_fpuen();
nkeynes@375
  1994
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1995
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1996
    load_fr_bank( R_EDX );
nkeynes@380
  1997
    JNE_rel8(13, doubleprec);
nkeynes@377
  1998
    push_fr(R_EDX, FRn);
nkeynes@377
  1999
    push_fr(R_EDX, FRm);
nkeynes@377
  2000
    FDIVP_st(1);
nkeynes@377
  2001
    pop_fr(R_EDX, FRn);
nkeynes@380
  2002
    JMP_rel8(11, end);
nkeynes@380
  2003
    JMP_TARGET(doubleprec);
nkeynes@377
  2004
    push_dr(R_EDX, FRn);
nkeynes@377
  2005
    push_dr(R_EDX, FRm);
nkeynes@377
  2006
    FDIVP_st(1);
nkeynes@377
  2007
    pop_dr(R_EDX, FRn);
nkeynes@380
  2008
    JMP_TARGET(end);
nkeynes@417
  2009
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2010
:}
nkeynes@375
  2011
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2012
    check_fpuen();
nkeynes@375
  2013
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2014
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2015
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2016
    JNE_rel8(18, doubleprec);
nkeynes@375
  2017
    push_fr( R_EDX, 0 );
nkeynes@375
  2018
    push_fr( R_EDX, FRm );
nkeynes@375
  2019
    FMULP_st(1);
nkeynes@375
  2020
    push_fr( R_EDX, FRn );
nkeynes@375
  2021
    FADDP_st(1);
nkeynes@375
  2022
    pop_fr( R_EDX, FRn );
nkeynes@380
  2023
    JMP_rel8(16, end);
nkeynes@380
  2024
    JMP_TARGET(doubleprec);
nkeynes@375
  2025
    push_dr( R_EDX, 0 );
nkeynes@375
  2026
    push_dr( R_EDX, FRm );
nkeynes@375
  2027
    FMULP_st(1);
nkeynes@375
  2028
    push_dr( R_EDX, FRn );
nkeynes@375
  2029
    FADDP_st(1);
nkeynes@375
  2030
    pop_dr( R_EDX, FRn );
nkeynes@380
  2031
    JMP_TARGET(end);
nkeynes@417
  2032
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2033
:}
nkeynes@375
  2034
nkeynes@377
  2035
FMUL FRm, FRn {:  
nkeynes@377
  2036
    check_fpuen();
nkeynes@377
  2037
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2038
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2039
    load_fr_bank( R_EDX );
nkeynes@380
  2040
    JNE_rel8(13, doubleprec);
nkeynes@377
  2041
    push_fr(R_EDX, FRm);
nkeynes@377
  2042
    push_fr(R_EDX, FRn);
nkeynes@377
  2043
    FMULP_st(1);
nkeynes@377
  2044
    pop_fr(R_EDX, FRn);
nkeynes@380
  2045
    JMP_rel8(11, end);
nkeynes@380
  2046
    JMP_TARGET(doubleprec);
nkeynes@377
  2047
    push_dr(R_EDX, FRm);
nkeynes@377
  2048
    push_dr(R_EDX, FRn);
nkeynes@377
  2049
    FMULP_st(1);
nkeynes@377
  2050
    pop_dr(R_EDX, FRn);
nkeynes@380
  2051
    JMP_TARGET(end);
nkeynes@417
  2052
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2053
:}
nkeynes@377
  2054
FNEG FRn {:  
nkeynes@377
  2055
    check_fpuen();
nkeynes@377
  2056
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2057
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2058
    load_fr_bank( R_EDX );
nkeynes@380
  2059
    JNE_rel8(10, doubleprec);
nkeynes@377
  2060
    push_fr(R_EDX, FRn);
nkeynes@377
  2061
    FCHS_st0();
nkeynes@377
  2062
    pop_fr(R_EDX, FRn);
nkeynes@380
  2063
    JMP_rel8(8, end);
nkeynes@380
  2064
    JMP_TARGET(doubleprec);
nkeynes@377
  2065
    push_dr(R_EDX, FRn);
nkeynes@377
  2066
    FCHS_st0();
nkeynes@377
  2067
    pop_dr(R_EDX, FRn);
nkeynes@380
  2068
    JMP_TARGET(end);
nkeynes@417
  2069
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2070
:}
nkeynes@377
  2071
FSRRA FRn {:  
nkeynes@377
  2072
    check_fpuen();
nkeynes@377
  2073
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2074
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2075
    load_fr_bank( R_EDX );
nkeynes@380
  2076
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2077
    FLD1_st0();
nkeynes@377
  2078
    push_fr(R_EDX, FRn);
nkeynes@377
  2079
    FSQRT_st0();
nkeynes@377
  2080
    FDIVP_st(1);
nkeynes@377
  2081
    pop_fr(R_EDX, FRn);
nkeynes@380
  2082
    JMP_TARGET(end);
nkeynes@417
  2083
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2084
:}
nkeynes@377
  2085
FSQRT FRn {:  
nkeynes@377
  2086
    check_fpuen();
nkeynes@377
  2087
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2088
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2089
    load_fr_bank( R_EDX );
nkeynes@380
  2090
    JNE_rel8(10, doubleprec);
nkeynes@377
  2091
    push_fr(R_EDX, FRn);
nkeynes@377
  2092
    FSQRT_st0();
nkeynes@377
  2093
    pop_fr(R_EDX, FRn);
nkeynes@380
  2094
    JMP_rel8(8, end);
nkeynes@380
  2095
    JMP_TARGET(doubleprec);
nkeynes@377
  2096
    push_dr(R_EDX, FRn);
nkeynes@377
  2097
    FSQRT_st0();
nkeynes@377
  2098
    pop_dr(R_EDX, FRn);
nkeynes@380
  2099
    JMP_TARGET(end);
nkeynes@417
  2100
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2101
:}
nkeynes@377
  2102
FSUB FRm, FRn {:  
nkeynes@377
  2103
    check_fpuen();
nkeynes@377
  2104
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2105
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2106
    load_fr_bank( R_EDX );
nkeynes@380
  2107
    JNE_rel8(13, doubleprec);
nkeynes@377
  2108
    push_fr(R_EDX, FRn);
nkeynes@377
  2109
    push_fr(R_EDX, FRm);
nkeynes@388
  2110
    FSUBP_st(1);
nkeynes@377
  2111
    pop_fr(R_EDX, FRn);
nkeynes@380
  2112
    JMP_rel8(11, end);
nkeynes@380
  2113
    JMP_TARGET(doubleprec);
nkeynes@377
  2114
    push_dr(R_EDX, FRn);
nkeynes@377
  2115
    push_dr(R_EDX, FRm);
nkeynes@388
  2116
    FSUBP_st(1);
nkeynes@377
  2117
    pop_dr(R_EDX, FRn);
nkeynes@380
  2118
    JMP_TARGET(end);
nkeynes@417
  2119
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2120
:}
nkeynes@377
  2121
nkeynes@377
  2122
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2123
    check_fpuen();
nkeynes@377
  2124
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2125
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2126
    load_fr_bank( R_EDX );
nkeynes@380
  2127
    JNE_rel8(8, doubleprec);
nkeynes@377
  2128
    push_fr(R_EDX, FRm);
nkeynes@377
  2129
    push_fr(R_EDX, FRn);
nkeynes@380
  2130
    JMP_rel8(6, end);
nkeynes@380
  2131
    JMP_TARGET(doubleprec);
nkeynes@377
  2132
    push_dr(R_EDX, FRm);
nkeynes@377
  2133
    push_dr(R_EDX, FRn);
nkeynes@382
  2134
    JMP_TARGET(end);
nkeynes@377
  2135
    FCOMIP_st(1);
nkeynes@377
  2136
    SETE_t();
nkeynes@377
  2137
    FPOP_st();
nkeynes@417
  2138
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2139
:}
nkeynes@377
  2140
FCMP/GT FRm, FRn {:  
nkeynes@377
  2141
    check_fpuen();
nkeynes@377
  2142
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2143
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2144
    load_fr_bank( R_EDX );
nkeynes@380
  2145
    JNE_rel8(8, doubleprec);
nkeynes@377
  2146
    push_fr(R_EDX, FRm);
nkeynes@377
  2147
    push_fr(R_EDX, FRn);
nkeynes@380
  2148
    JMP_rel8(6, end);
nkeynes@380
  2149
    JMP_TARGET(doubleprec);
nkeynes@377
  2150
    push_dr(R_EDX, FRm);
nkeynes@377
  2151
    push_dr(R_EDX, FRn);
nkeynes@380
  2152
    JMP_TARGET(end);
nkeynes@377
  2153
    FCOMIP_st(1);
nkeynes@377
  2154
    SETA_t();
nkeynes@377
  2155
    FPOP_st();
nkeynes@417
  2156
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2157
:}
nkeynes@377
  2158
nkeynes@377
  2159
FSCA FPUL, FRn {:  
nkeynes@377
  2160
    check_fpuen();
nkeynes@388
  2161
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2162
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2163
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2164
    load_fr_bank( R_ECX );
nkeynes@388
  2165
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2166
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2167
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2168
    JMP_TARGET(doubleprec);
nkeynes@417
  2169
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2170
:}
nkeynes@377
  2171
FIPR FVm, FVn {:  
nkeynes@377
  2172
    check_fpuen();
nkeynes@388
  2173
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2174
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2175
    JNE_rel8(44, doubleprec);
nkeynes@388
  2176
    
nkeynes@388
  2177
    load_fr_bank( R_ECX );
nkeynes@388
  2178
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2179
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2180
    FMULP_st(1);
nkeynes@388
  2181
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2182
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2183
    FMULP_st(1);
nkeynes@388
  2184
    FADDP_st(1);
nkeynes@388
  2185
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2186
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2187
    FMULP_st(1);
nkeynes@388
  2188
    FADDP_st(1);
nkeynes@388
  2189
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2190
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2191
    FMULP_st(1);
nkeynes@388
  2192
    FADDP_st(1);
nkeynes@388
  2193
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2194
    JMP_TARGET(doubleprec);
nkeynes@417
  2195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2196
:}
nkeynes@377
  2197
FTRV XMTRX, FVn {:  
nkeynes@377
  2198
    check_fpuen();
nkeynes@388
  2199
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2200
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2201
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2202
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2203
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2204
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2205
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2206
    JMP_TARGET(doubleprec);
nkeynes@417
  2207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2208
:}
nkeynes@377
  2209
nkeynes@377
  2210
FRCHG {:  
nkeynes@377
  2211
    check_fpuen();
nkeynes@377
  2212
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2213
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2214
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2215
    update_fr_bank( R_ECX );
nkeynes@417
  2216
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2217
:}
nkeynes@377
  2218
FSCHG {:  
nkeynes@377
  2219
    check_fpuen();
nkeynes@377
  2220
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2221
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2222
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2223
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2224
:}
nkeynes@359
  2225
nkeynes@359
  2226
/* Processor control instructions */
nkeynes@368
  2227
LDC Rm, SR {:
nkeynes@386
  2228
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2229
	SLOTILLEGAL();
nkeynes@386
  2230
    } else {
nkeynes@386
  2231
	check_priv();
nkeynes@386
  2232
	load_reg( R_EAX, Rm );
nkeynes@386
  2233
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2234
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2235
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2236
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2237
    }
nkeynes@368
  2238
:}
nkeynes@359
  2239
LDC Rm, GBR {: 
nkeynes@359
  2240
    load_reg( R_EAX, Rm );
nkeynes@359
  2241
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2242
:}
nkeynes@359
  2243
LDC Rm, VBR {:  
nkeynes@386
  2244
    check_priv();
nkeynes@359
  2245
    load_reg( R_EAX, Rm );
nkeynes@359
  2246
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2248
:}
nkeynes@359
  2249
LDC Rm, SSR {:  
nkeynes@386
  2250
    check_priv();
nkeynes@359
  2251
    load_reg( R_EAX, Rm );
nkeynes@359
  2252
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2254
:}
nkeynes@359
  2255
LDC Rm, SGR {:  
nkeynes@386
  2256
    check_priv();
nkeynes@359
  2257
    load_reg( R_EAX, Rm );
nkeynes@359
  2258
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2260
:}
nkeynes@359
  2261
LDC Rm, SPC {:  
nkeynes@386
  2262
    check_priv();
nkeynes@359
  2263
    load_reg( R_EAX, Rm );
nkeynes@359
  2264
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2265
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2266
:}
nkeynes@359
  2267
LDC Rm, DBR {:  
nkeynes@386
  2268
    check_priv();
nkeynes@359
  2269
    load_reg( R_EAX, Rm );
nkeynes@359
  2270
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2271
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2272
:}
nkeynes@374
  2273
LDC Rm, Rn_BANK {:  
nkeynes@386
  2274
    check_priv();
nkeynes@374
  2275
    load_reg( R_EAX, Rm );
nkeynes@374
  2276
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2277
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2278
:}
nkeynes@359
  2279
LDC.L @Rm+, GBR {:  
nkeynes@359
  2280
    load_reg( R_EAX, Rm );
nkeynes@395
  2281
    check_ralign32( R_EAX );
nkeynes@571
  2282
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2283
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2284
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2285
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2286
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2287
:}
nkeynes@368
  2288
LDC.L @Rm+, SR {:
nkeynes@386
  2289
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2290
	SLOTILLEGAL();
nkeynes@386
  2291
    } else {
nkeynes@559
  2292
	check_priv();
nkeynes@386
  2293
	load_reg( R_EAX, Rm );
nkeynes@395
  2294
	check_ralign32( R_EAX );
nkeynes@571
  2295
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2296
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2297
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2298
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2299
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2300
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2301
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2302
    }
nkeynes@359
  2303
:}
nkeynes@359
  2304
LDC.L @Rm+, VBR {:  
nkeynes@559
  2305
    check_priv();
nkeynes@359
  2306
    load_reg( R_EAX, Rm );
nkeynes@395
  2307
    check_ralign32( R_EAX );
nkeynes@571
  2308
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2309
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2310
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2311
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2312
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2313
:}
nkeynes@359
  2314
LDC.L @Rm+, SSR {:
nkeynes@559
  2315
    check_priv();
nkeynes@359
  2316
    load_reg( R_EAX, Rm );
nkeynes@416
  2317
    check_ralign32( R_EAX );
nkeynes@571
  2318
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2319
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2320
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2321
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2323
:}
nkeynes@359
  2324
LDC.L @Rm+, SGR {:  
nkeynes@559
  2325
    check_priv();
nkeynes@359
  2326
    load_reg( R_EAX, Rm );
nkeynes@395
  2327
    check_ralign32( R_EAX );
nkeynes@571
  2328
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2329
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2330
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2331
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2332
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2333
:}
nkeynes@359
  2334
LDC.L @Rm+, SPC {:  
nkeynes@559
  2335
    check_priv();
nkeynes@359
  2336
    load_reg( R_EAX, Rm );
nkeynes@395
  2337
    check_ralign32( R_EAX );
nkeynes@571
  2338
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2339
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2340
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2341
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2343
:}
nkeynes@359
  2344
LDC.L @Rm+, DBR {:  
nkeynes@559
  2345
    check_priv();
nkeynes@359
  2346
    load_reg( R_EAX, Rm );
nkeynes@395
  2347
    check_ralign32( R_EAX );
nkeynes@571
  2348
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2349
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2350
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2351
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2352
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2353
:}
nkeynes@359
  2354
LDC.L @Rm+, Rn_BANK {:  
nkeynes@559
  2355
    check_priv();
nkeynes@374
  2356
    load_reg( R_EAX, Rm );
nkeynes@395
  2357
    check_ralign32( R_EAX );
nkeynes@571
  2358
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2359
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2360
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2361
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2363
:}
nkeynes@359
  2364
LDS Rm, FPSCR {:  
nkeynes@359
  2365
    load_reg( R_EAX, Rm );
nkeynes@359
  2366
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2367
    update_fr_bank( R_EAX );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2369
:}
nkeynes@359
  2370
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2371
    load_reg( R_EAX, Rm );
nkeynes@395
  2372
    check_ralign32( R_EAX );
nkeynes@571
  2373
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2374
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2375
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2376
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2377
    update_fr_bank( R_EAX );
nkeynes@417
  2378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2379
:}
nkeynes@359
  2380
LDS Rm, FPUL {:  
nkeynes@359
  2381
    load_reg( R_EAX, Rm );
nkeynes@359
  2382
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2383
:}
nkeynes@359
  2384
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2385
    load_reg( R_EAX, Rm );
nkeynes@395
  2386
    check_ralign32( R_EAX );
nkeynes@571
  2387
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2388
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2389
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2390
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2392
:}
nkeynes@359
  2393
LDS Rm, MACH {: 
nkeynes@359
  2394
    load_reg( R_EAX, Rm );
nkeynes@359
  2395
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2396
:}
nkeynes@359
  2397
LDS.L @Rm+, MACH {:  
nkeynes@359
  2398
    load_reg( R_EAX, Rm );
nkeynes@395
  2399
    check_ralign32( R_EAX );
nkeynes@571
  2400
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2401
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2402
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2403
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2405
:}
nkeynes@359
  2406
LDS Rm, MACL {:  
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@359
  2408
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2409
:}
nkeynes@359
  2410
LDS.L @Rm+, MACL {:  
nkeynes@359
  2411
    load_reg( R_EAX, Rm );
nkeynes@395
  2412
    check_ralign32( R_EAX );
nkeynes@571
  2413
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2414
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2415
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2416
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2418
:}
nkeynes@359
  2419
LDS Rm, PR {:  
nkeynes@359
  2420
    load_reg( R_EAX, Rm );
nkeynes@359
  2421
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2422
:}
nkeynes@359
  2423
LDS.L @Rm+, PR {:  
nkeynes@359
  2424
    load_reg( R_EAX, Rm );
nkeynes@395
  2425
    check_ralign32( R_EAX );
nkeynes@571
  2426
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2427
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2428
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2429
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2430
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2431
:}
nkeynes@550
  2432
LDTLB {:  
nkeynes@553
  2433
    call_func0( MMU_ldtlb );
nkeynes@550
  2434
:}
nkeynes@359
  2435
OCBI @Rn {:  :}
nkeynes@359
  2436
OCBP @Rn {:  :}
nkeynes@359
  2437
OCBWB @Rn {:  :}
nkeynes@374
  2438
PREF @Rn {:
nkeynes@374
  2439
    load_reg( R_EAX, Rn );
nkeynes@532
  2440
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2441
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2442
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@577
  2443
    JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
  2444
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@577
  2445
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@577
  2446
    JE_exc(-1);
nkeynes@380
  2447
    JMP_TARGET(end);
nkeynes@417
  2448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2449
:}
nkeynes@388
  2450
SLEEP {: 
nkeynes@388
  2451
    check_priv();
nkeynes@388
  2452
    call_func0( sh4_sleep );
nkeynes@417
  2453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2454
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2455
    return 2;
nkeynes@388
  2456
:}
nkeynes@386
  2457
STC SR, Rn {:
nkeynes@386
  2458
    check_priv();
nkeynes@386
  2459
    call_func0(sh4_read_sr);
nkeynes@386
  2460
    store_reg( R_EAX, Rn );
nkeynes@417
  2461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2462
:}
nkeynes@359
  2463
STC GBR, Rn {:  
nkeynes@359
  2464
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2465
    store_reg( R_EAX, Rn );
nkeynes@359
  2466
:}
nkeynes@359
  2467
STC VBR, Rn {:  
nkeynes@386
  2468
    check_priv();
nkeynes@359
  2469
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2470
    store_reg( R_EAX, Rn );
nkeynes@417
  2471
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2472
:}
nkeynes@359
  2473
STC SSR, Rn {:  
nkeynes@386
  2474
    check_priv();
nkeynes@359
  2475
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2476
    store_reg( R_EAX, Rn );
nkeynes@417
  2477
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2478
:}
nkeynes@359
  2479
STC SPC, Rn {:  
nkeynes@386
  2480
    check_priv();
nkeynes@359
  2481
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2482
    store_reg( R_EAX, Rn );
nkeynes@417
  2483
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2484
:}
nkeynes@359
  2485
STC SGR, Rn {:  
nkeynes@386
  2486
    check_priv();
nkeynes@359
  2487
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2488
    store_reg( R_EAX, Rn );
nkeynes@417
  2489
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2490
:}
nkeynes@359
  2491
STC DBR, Rn {:  
nkeynes@386
  2492
    check_priv();
nkeynes@359
  2493
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2494
    store_reg( R_EAX, Rn );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2496
:}
nkeynes@374
  2497
STC Rm_BANK, Rn {:
nkeynes@386
  2498
    check_priv();
nkeynes@374
  2499
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2500
    store_reg( R_EAX, Rn );
nkeynes@417
  2501
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2502
:}
nkeynes@374
  2503
STC.L SR, @-Rn {:
nkeynes@559
  2504
    check_priv();
nkeynes@571
  2505
    load_reg( R_EAX, Rn );
nkeynes@571
  2506
    check_walign32( R_EAX );
nkeynes@571
  2507
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2508
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2509
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2510
    call_func0( sh4_read_sr );
nkeynes@571
  2511
    POP_realigned_r32( R_ECX );
nkeynes@571
  2512
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2513
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2514
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2515
:}
nkeynes@359
  2516
STC.L VBR, @-Rn {:  
nkeynes@559
  2517
    check_priv();
nkeynes@571
  2518
    load_reg( R_EAX, Rn );
nkeynes@571
  2519
    check_walign32( R_EAX );
nkeynes@571
  2520
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2521
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2522
    load_spreg( R_EDX, R_VBR );
nkeynes@571
  2523
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2524
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
STC.L SSR, @-Rn {:  
nkeynes@559
  2528
    check_priv();
nkeynes@571
  2529
    load_reg( R_EAX, Rn );
nkeynes@571
  2530
    check_walign32( R_EAX );
nkeynes@571
  2531
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2532
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2533
    load_spreg( R_EDX, R_SSR );
nkeynes@571
  2534
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2535
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2537
:}
nkeynes@416
  2538
STC.L SPC, @-Rn {:
nkeynes@559
  2539
    check_priv();
nkeynes@571
  2540
    load_reg( R_EAX, Rn );
nkeynes@571
  2541
    check_walign32( R_EAX );
nkeynes@571
  2542
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2543
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2544
    load_spreg( R_EDX, R_SPC );
nkeynes@571
  2545
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2546
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2547
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2548
:}
nkeynes@359
  2549
STC.L SGR, @-Rn {:  
nkeynes@559
  2550
    check_priv();
nkeynes@571
  2551
    load_reg( R_EAX, Rn );
nkeynes@571
  2552
    check_walign32( R_EAX );
nkeynes@571
  2553
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2554
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2555
    load_spreg( R_EDX, R_SGR );
nkeynes@571
  2556
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2557
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2558
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2559
:}
nkeynes@359
  2560
STC.L DBR, @-Rn {:  
nkeynes@559
  2561
    check_priv();
nkeynes@571
  2562
    load_reg( R_EAX, Rn );
nkeynes@571
  2563
    check_walign32( R_EAX );
nkeynes@571
  2564
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2565
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2566
    load_spreg( R_EDX, R_DBR );
nkeynes@571
  2567
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2568
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2569
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2570
:}
nkeynes@374
  2571
STC.L Rm_BANK, @-Rn {:  
nkeynes@559
  2572
    check_priv();
nkeynes@571
  2573
    load_reg( R_EAX, Rn );
nkeynes@571
  2574
    check_walign32( R_EAX );
nkeynes@571
  2575
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2576
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2577
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@571
  2578
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2579
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2580
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2581
:}
nkeynes@359
  2582
STC.L GBR, @-Rn {:  
nkeynes@571
  2583
    load_reg( R_EAX, Rn );
nkeynes@571
  2584
    check_walign32( R_EAX );
nkeynes@571
  2585
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2586
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2587
    load_spreg( R_EDX, R_GBR );
nkeynes@571
  2588
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2589
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2591
:}
nkeynes@359
  2592
STS FPSCR, Rn {:  
nkeynes@359
  2593
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2594
    store_reg( R_EAX, Rn );
nkeynes@359
  2595
:}
nkeynes@359
  2596
STS.L FPSCR, @-Rn {:  
nkeynes@571
  2597
    load_reg( R_EAX, Rn );
nkeynes@571
  2598
    check_walign32( R_EAX );
nkeynes@571
  2599
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2600
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2601
    load_spreg( R_EDX, R_FPSCR );
nkeynes@571
  2602
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2603
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2604
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2605
:}
nkeynes@359
  2606
STS FPUL, Rn {:  
nkeynes@359
  2607
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2608
    store_reg( R_EAX, Rn );
nkeynes@359
  2609
:}
nkeynes@359
  2610
STS.L FPUL, @-Rn {:  
nkeynes@571
  2611
    load_reg( R_EAX, Rn );
nkeynes@571
  2612
    check_walign32( R_EAX );
nkeynes@571
  2613
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2614
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2615
    load_spreg( R_EDX, R_FPUL );
nkeynes@571
  2616
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2617
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2618
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2619
:}
nkeynes@359
  2620
STS MACH, Rn {:  
nkeynes@359
  2621
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2622
    store_reg( R_EAX, Rn );
nkeynes@359
  2623
:}
nkeynes@359
  2624
STS.L MACH, @-Rn {:  
nkeynes@571
  2625
    load_reg( R_EAX, Rn );
nkeynes@571
  2626
    check_walign32( R_EAX );
nkeynes@571
  2627
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2628
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2629
    load_spreg( R_EDX, R_MACH );
nkeynes@571
  2630
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2631
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2632
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2633
:}
nkeynes@359
  2634
STS MACL, Rn {:  
nkeynes@359
  2635
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2636
    store_reg( R_EAX, Rn );
nkeynes@359
  2637
:}
nkeynes@359
  2638
STS.L MACL, @-Rn {:  
nkeynes@571
  2639
    load_reg( R_EAX, Rn );
nkeynes@571
  2640
    check_walign32( R_EAX );
nkeynes@571
  2641
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2642
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2643
    load_spreg( R_EDX, R_MACL );
nkeynes@571
  2644
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2645
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2646
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2647
:}
nkeynes@359
  2648
STS PR, Rn {:  
nkeynes@359
  2649
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2650
    store_reg( R_EAX, Rn );
nkeynes@359
  2651
:}
nkeynes@359
  2652
STS.L PR, @-Rn {:  
nkeynes@571
  2653
    load_reg( R_EAX, Rn );
nkeynes@571
  2654
    check_walign32( R_EAX );
nkeynes@571
  2655
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2656
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2657
    load_spreg( R_EDX, R_PR );
nkeynes@571
  2658
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2659
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2660
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2661
:}
nkeynes@359
  2662
nkeynes@359
  2663
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2664
%%
nkeynes@416
  2665
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2666
    return 0;
nkeynes@359
  2667
}
.