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lxdream.org :: lxdream/src/sh4/intc.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/intc.c
changeset 265:5daf59b7f31b
prev157:fbe03268ad8a
next421:e51bf0aedd90
author nkeynes
date Sat Jan 06 04:06:36 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Implement event queue.
Fix pvr2 timing (yes, again).
file annotate diff log raw
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/**
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 * $Id: intc.c,v 1.7 2007-01-06 04:06:36 nkeynes Exp $
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 *
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 * SH4 onboard interrupt controller (INTC) implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4mmio.h"
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#include "sh4core.h"
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#include "intc.h"
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#include "eventq.h"
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struct intc_sources_t {
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    char *name;
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    uint32_t code;
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} intc_sources[INT_NUM_SOURCES] = {
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    { "IRQ0", 0x200 },  { "IRQ1", 0x220 },  { "IRQ2", 0x240 },
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    { "IRQ3", 0x260 },  { "IRQ4", 0x280 },  { "IRQ5", 0x2A0 },
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    { "IRQ6", 0x2C0 },  { "IRQ7", 0x2E0 },  { "IRQ8", 0x300 },
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    { "IRQ9", 0x320 },  { "IRQ10",0x340 },  { "IRQ11",0x360 },
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    { "IRQ12",0x380 },  { "IRQ13",0x3A0 },  { "IRQ14",0x3C0 },
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    { "NMI", 0x1C0 },   { "H-UDI",0x600 },  { "GPIOI",0x620 },
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    { "DMTE0",0x640 },  { "DMTE1",0x660 },  { "DMTE2",0x680 },
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    { "DMTE3",0x6A0 },  { "DMTAE",0x6C0 },  { "TUNI0",0x400 },
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    { "TUNI1",0x420 },  { "TUNI2",0x440 },  { "TICPI2",0x460 },
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    { "RTC_ATI",0x480 },{ "RTC_PRI",0x4A0 },{ "RTC_CUI",0x4C0 },
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    { "SCI_ERI",0x4E0 },{ "SCI_RXI",0x500 },{ "SCI_TXI",0x520 },
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    { "SCI_TEI",0x540 },
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    { "SCIF_ERI",0x700 },{ "SCIF_RXI",0x720, 0 },{ "SCIF_BRI",0x740 },
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    { "SCIF_TXI",0x760 },
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    { "WDT_ITI",0x560 },{ "RCMI",0x580 },   { "ROVI",0x5A0 } };
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static int intc_default_priority[INT_NUM_SOURCES] = { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 16 };
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#define PRIORITY(which) intc_state.priority[which]
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#define INTCODE(which) intc_sources[which].code
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static struct intc_state {
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    int num_pending;
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    int pending[INT_NUM_SOURCES];
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    int priority[INT_NUM_SOURCES];
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} intc_state;
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void mmio_region_INTC_write( uint32_t reg, uint32_t val )
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{
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    /* Well it saves having to use an intermediate table... */
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    switch( reg ) {
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        case ICR: /* care about this later */
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            break;
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        case IPRA:
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            PRIORITY(INT_TMU_TUNI0) = (val>>12)&0x000F;
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            PRIORITY(INT_TMU_TUNI1) = (val>>8)&0x000F;
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            PRIORITY(INT_TMU_TUNI2) =
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                PRIORITY(INT_TMU_TICPI2) = (val>>4)&0x000F;
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            PRIORITY(INT_RTC_ATI) =
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                PRIORITY(INT_RTC_PRI) =
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                PRIORITY(INT_RTC_CUI) = val&0x000F;
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            break;
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        case IPRB:
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            PRIORITY(INT_WDT_ITI) = (val>>12)&0x000F;
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            PRIORITY(INT_REF_RCMI) =
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                PRIORITY(INT_REF_ROVI) = (val>>8)&0x000F;
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            PRIORITY(INT_SCI_ERI) =
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                PRIORITY(INT_SCI_RXI) =
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                PRIORITY(INT_SCI_TXI) =
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                PRIORITY(INT_SCI_TEI) = (val>>4)&0x000F;
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            /* Bits 0-3 reserved */
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            break;
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        case IPRC:
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            PRIORITY(INT_GPIO) = (val>>12)&0x000F;
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            PRIORITY(INT_DMA_DMTE0) =
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                PRIORITY(INT_DMA_DMTE1) =
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                PRIORITY(INT_DMA_DMTE2) =
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                PRIORITY(INT_DMA_DMTE3) =
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                PRIORITY(INT_DMA_DMAE) = (val>>8)&0x000F;
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            PRIORITY(INT_SCIF_ERI) =
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                PRIORITY(INT_SCIF_RXI) =
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                PRIORITY(INT_SCIF_BRI) =
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                PRIORITY(INT_SCIF_TXI) = (val>>4)&0x000F;
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            PRIORITY(INT_HUDI) = val&0x000F;
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            break;
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    }
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    MMIO_WRITE( INTC, reg, val );
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}
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int32_t mmio_region_INTC_read( uint32_t reg )
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{
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    return MMIO_READ( INTC, reg );
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}
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void INTC_reset()
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{
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    int i;
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    intc_state.num_pending = 0;
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    for( i=0; i<INT_NUM_SOURCES; i++ )
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	intc_state.priority[i] = intc_default_priority[i];
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    sh4r.event_pending = event_get_next_time();
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    sh4r.event_types &= (~PENDING_IRQ);
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}
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void INTC_save_state( FILE *f )
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{
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    fwrite( &intc_state, sizeof(intc_state), 1, f );
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}
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int INTC_load_state( FILE *f )
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{
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    if( fread(&intc_state, sizeof(intc_state), 1, f) != 1 )
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	return -1;
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    return 0;
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}
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/* We basically maintain a priority queue here, raise_interrupt adds an entry,
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 * accept_interrupt takes it off. At the moment this is done as a simple
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 * ordered array, on the basis that in practice there's unlikely to be more
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 * than one at a time. There are lots of ways to optimize this if it turns out
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 * to be necessary, but I'd doubt it will be...
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 */
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void intc_raise_interrupt( int which )
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{
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    int i, j, pri;
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    pri = PRIORITY(which);
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    if( pri == 0 ) return; /* masked off */
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    for( i=0; i<intc_state.num_pending; i++ ) {
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        if( intc_state.pending[i] == which ) return; /* Don't queue more than once */
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        if( PRIORITY(intc_state.pending[i]) > pri ||
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            (PRIORITY(intc_state.pending[i]) == pri &&
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             intc_state.pending[i] < which))
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            break;
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    }
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    /* i == insertion point */
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    for( j=intc_state.num_pending; j > i; j-- )
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        intc_state.pending[j] = intc_state.pending[j-1];
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    intc_state.pending[i] = which;
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    if( i == intc_state.num_pending && (sh4r.sr&SR_BL)==0 && SH4_INTMASK() < pri ) {
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        sh4r.event_pending = 0;
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	sh4r.event_types |= PENDING_IRQ;
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    }
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    intc_state.num_pending++;
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}
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void intc_clear_interrupt( int which )
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{
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    int i;
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    for( i=intc_state.num_pending-1; i>=0; i-- ) {
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	if( intc_state.pending[i] == which ) {
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	    /* Shift array contents down */
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	    while( i < intc_state.num_pending-1 ) {
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		intc_state.pending[i] = intc_state.pending[++i];
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	    }
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	    intc_state.num_pending--;
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	    intc_mask_changed();
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	    break;
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	}
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    }
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}
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uint32_t intc_accept_interrupt( void )
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{
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    assert(intc_state.num_pending > 0);
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    return INTCODE(intc_state.pending[intc_state.num_pending-1]);
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}
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void intc_mask_changed( void )
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{   
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    if( intc_state.num_pending > 0 && (sh4r.sr&SR_BL)==0 &&
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        SH4_INTMASK() < PRIORITY(intc_state.pending[intc_state.num_pending-1]) ) {
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        sh4r.event_pending = 0;
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	sh4r.event_types |= PENDING_IRQ ;
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    }
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    else {
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	sh4r.event_pending = event_get_next_time();
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	sh4r.event_types &= (~PENDING_IRQ);
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    }
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}
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char *intc_get_interrupt_name( int code )
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{
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    return intc_sources[code].name;
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}
.