Search
lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.c
changeset 265:5daf59b7f31b
prev260:c82e26ec0cac
next273:48eb3304a41e
author nkeynes
date Sat Jan 06 04:06:36 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Implement event queue.
Fix pvr2 timing (yes, again).
file annotate diff log raw
nkeynes@23
     1
/**
nkeynes@265
     2
 * $Id: sh4core.c,v 1.37 2007-01-06 04:06:36 nkeynes Exp $
nkeynes@23
     3
 * 
nkeynes@23
     4
 * SH4 emulation core, and parent module for all the SH4 peripheral
nkeynes@23
     5
 * modules.
nkeynes@23
     6
 *
nkeynes@23
     7
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@23
     8
 *
nkeynes@23
     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@23
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@23
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@23
    12
 * (at your option) any later version.
nkeynes@23
    13
 *
nkeynes@23
    14
 * This program is distributed in the hope that it will be useful,
nkeynes@23
    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@23
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@23
    17
 * GNU General Public License for more details.
nkeynes@23
    18
 */
nkeynes@23
    19
nkeynes@35
    20
#define MODULE sh4_module
nkeynes@1
    21
#include <math.h>
nkeynes@1
    22
#include "dream.h"
nkeynes@84
    23
#include "sh4/sh4core.h"
nkeynes@84
    24
#include "sh4/sh4mmio.h"
nkeynes@84
    25
#include "sh4/intc.h"
nkeynes@1
    26
#include "mem.h"
nkeynes@23
    27
#include "clock.h"
nkeynes@102
    28
#include "syscall.h"
nkeynes@1
    29
nkeynes@157
    30
#define SH4_CALLTRACE 1
nkeynes@157
    31
nkeynes@123
    32
#define MAX_INT 0x7FFFFFFF
nkeynes@123
    33
#define MIN_INT 0x80000000
nkeynes@123
    34
#define MAX_INTF 2147483647.0
nkeynes@123
    35
#define MIN_INTF -2147483648.0
nkeynes@123
    36
nkeynes@27
    37
/* CPU-generated exception code/vector pairs */
nkeynes@27
    38
#define EXC_POWER_RESET  0x000 /* vector special */
nkeynes@27
    39
#define EXC_MANUAL_RESET 0x020
nkeynes@208
    40
#define EXC_READ_ADDR_ERR 0x0E0
nkeynes@208
    41
#define EXC_WRITE_ADDR_ERR 0x100
nkeynes@27
    42
#define EXC_SLOT_ILLEGAL 0x1A0
nkeynes@27
    43
#define EXC_ILLEGAL      0x180
nkeynes@27
    44
#define EXC_TRAP         0x160
nkeynes@27
    45
#define EXC_FPDISABLE    0x800
nkeynes@246
    46
#define EXC_SLOT_FPDISABLE 0x820
nkeynes@246
    47
nkeynes@246
    48
#define EXV_EXCEPTION    0x100  /* General exception vector */
nkeynes@246
    49
#define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
nkeynes@246
    50
#define EXV_INTERRUPT    0x600  /* External interrupt vector */
nkeynes@27
    51
nkeynes@23
    52
/********************** SH4 Module Definition ****************************/
nkeynes@23
    53
nkeynes@23
    54
void sh4_init( void );
nkeynes@23
    55
void sh4_reset( void );
nkeynes@30
    56
uint32_t sh4_run_slice( uint32_t );
nkeynes@23
    57
void sh4_start( void );
nkeynes@23
    58
void sh4_stop( void );
nkeynes@23
    59
void sh4_save_state( FILE *f );
nkeynes@23
    60
int sh4_load_state( FILE *f );
nkeynes@265
    61
static void sh4_accept_interrupt( void );
nkeynes@16
    62
nkeynes@15
    63
struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
nkeynes@23
    64
				       NULL, sh4_run_slice, sh4_stop,
nkeynes@23
    65
				       sh4_save_state, sh4_load_state };
nkeynes@15
    66
nkeynes@1
    67
struct sh4_registers sh4r;
nkeynes@1
    68
nkeynes@1
    69
void sh4_init(void)
nkeynes@1
    70
{
nkeynes@1
    71
    register_io_regions( mmio_list_sh4mmio );
nkeynes@10
    72
    mmu_init();
nkeynes@27
    73
    sh4_reset();
nkeynes@1
    74
}
nkeynes@1
    75
nkeynes@1
    76
void sh4_reset(void)
nkeynes@1
    77
{
nkeynes@19
    78
    /* zero everything out, for the sake of having a consistent state. */
nkeynes@19
    79
    memset( &sh4r, 0, sizeof(sh4r) );
nkeynes@27
    80
nkeynes@27
    81
    /* Resume running if we were halted */
nkeynes@27
    82
    sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@27
    83
nkeynes@1
    84
    sh4r.pc    = 0xA0000000;
nkeynes@1
    85
    sh4r.new_pc= 0xA0000002;
nkeynes@1
    86
    sh4r.vbr   = 0x00000000;
nkeynes@1
    87
    sh4r.fpscr = 0x00040001;
nkeynes@1
    88
    sh4r.sr    = 0x700000F0;
nkeynes@27
    89
nkeynes@27
    90
    /* Mem reset will do this, but if we want to reset _just_ the SH4... */
nkeynes@27
    91
    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
nkeynes@27
    92
nkeynes@27
    93
    /* Peripheral modules */
nkeynes@260
    94
    CPG_reset();
nkeynes@157
    95
    INTC_reset();
nkeynes@157
    96
    TMU_reset();
nkeynes@32
    97
    SCIF_reset();
nkeynes@1
    98
}
nkeynes@1
    99
nkeynes@43
   100
static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
nkeynes@43
   101
static int sh4_breakpoint_count = 0;
nkeynes@235
   102
static uint16_t *sh4_icache = NULL;
nkeynes@235
   103
static uint32_t sh4_icache_addr = 0;
nkeynes@43
   104
nkeynes@43
   105
void sh4_set_breakpoint( uint32_t pc, int type )
nkeynes@43
   106
{
nkeynes@43
   107
    sh4_breakpoints[sh4_breakpoint_count].address = pc;
nkeynes@43
   108
    sh4_breakpoints[sh4_breakpoint_count].type = type;
nkeynes@43
   109
    sh4_breakpoint_count++;
nkeynes@43
   110
}
nkeynes@43
   111
nkeynes@43
   112
gboolean sh4_clear_breakpoint( uint32_t pc, int type )
nkeynes@43
   113
{
nkeynes@43
   114
    int i;
nkeynes@43
   115
nkeynes@43
   116
    for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@43
   117
	if( sh4_breakpoints[i].address == pc && 
nkeynes@43
   118
	    sh4_breakpoints[i].type == type ) {
nkeynes@43
   119
	    while( ++i < sh4_breakpoint_count ) {
nkeynes@43
   120
		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
nkeynes@43
   121
		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
nkeynes@43
   122
	    }
nkeynes@43
   123
	    sh4_breakpoint_count--;
nkeynes@43
   124
	    return TRUE;
nkeynes@43
   125
	}
nkeynes@43
   126
    }
nkeynes@43
   127
    return FALSE;
nkeynes@43
   128
}
nkeynes@43
   129
nkeynes@43
   130
int sh4_get_breakpoint( uint32_t pc )
nkeynes@43
   131
{
nkeynes@43
   132
    int i;
nkeynes@43
   133
    for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@43
   134
	if( sh4_breakpoints[i].address == pc )
nkeynes@43
   135
	    return sh4_breakpoints[i].type;
nkeynes@43
   136
    }
nkeynes@43
   137
    return 0;
nkeynes@43
   138
}
nkeynes@43
   139
nkeynes@30
   140
uint32_t sh4_run_slice( uint32_t nanosecs ) 
nkeynes@1
   141
{
nkeynes@23
   142
    int i;
nkeynes@265
   143
    sh4r.slice_cycle = 0;
nkeynes@23
   144
nkeynes@27
   145
    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
nkeynes@265
   146
	if( sh4r.event_pending < nanosecs ) {
nkeynes@265
   147
	    sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@265
   148
	    sh4r.slice_cycle = sh4r.event_pending;
nkeynes@265
   149
	}
nkeynes@23
   150
    }
nkeynes@27
   151
nkeynes@235
   152
    if( sh4_breakpoint_count == 0 ) {
nkeynes@265
   153
	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
nkeynes@265
   154
	    if( SH4_EVENT_PENDING() ) {
nkeynes@265
   155
		if( sh4r.event_types & PENDING_EVENT ) {
nkeynes@265
   156
		    event_execute();
nkeynes@265
   157
		}
nkeynes@265
   158
		/* Eventq execute may (quite likely) deliver an immediate IRQ */
nkeynes@265
   159
		if( sh4r.event_types & PENDING_IRQ ) {
nkeynes@265
   160
		    sh4_accept_interrupt();
nkeynes@265
   161
		}
nkeynes@265
   162
	    }
nkeynes@235
   163
	    if( !sh4_execute_instruction() ) {
nkeynes@43
   164
		break;
nkeynes@43
   165
	    }
nkeynes@43
   166
	}
nkeynes@235
   167
    } else {
nkeynes@265
   168
	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
nkeynes@265
   169
	    if( SH4_EVENT_PENDING() ) {
nkeynes@265
   170
		if( sh4r.event_types & PENDING_EVENT ) {
nkeynes@265
   171
		    event_execute();
nkeynes@265
   172
		}
nkeynes@265
   173
		/* Eventq execute may (quite likely) deliver an immediate IRQ */
nkeynes@265
   174
		if( sh4r.event_types & PENDING_IRQ ) {
nkeynes@265
   175
		    sh4_accept_interrupt();
nkeynes@265
   176
		}
nkeynes@265
   177
	    }
nkeynes@265
   178
                 
nkeynes@235
   179
	    if( !sh4_execute_instruction() )
nkeynes@235
   180
		break;
nkeynes@235
   181
#ifdef ENABLE_DEBUG_MODE
nkeynes@235
   182
	    for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@235
   183
		if( sh4_breakpoints[i].address == sh4r.pc ) {
nkeynes@235
   184
		    break;
nkeynes@235
   185
		}
nkeynes@235
   186
	    }
nkeynes@235
   187
	    if( i != sh4_breakpoint_count ) {
nkeynes@235
   188
		dreamcast_stop();
nkeynes@235
   189
		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
nkeynes@235
   190
		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
nkeynes@235
   191
		break;
nkeynes@235
   192
	    }
nkeynes@235
   193
#endif	
nkeynes@43
   194
	}
nkeynes@27
   195
    }
nkeynes@30
   196
nkeynes@30
   197
    /* If we aborted early, but the cpu is still technically running,
nkeynes@30
   198
     * we're doing a hard abort - cut the timeslice back to what we
nkeynes@30
   199
     * actually executed
nkeynes@30
   200
     */
nkeynes@53
   201
    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
nkeynes@53
   202
	nanosecs = sh4r.slice_cycle;
nkeynes@27
   203
    }
nkeynes@27
   204
    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
nkeynes@30
   205
	TMU_run_slice( nanosecs );
nkeynes@30
   206
	SCIF_run_slice( nanosecs );
nkeynes@27
   207
    }
nkeynes@53
   208
    sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
nkeynes@30
   209
    return nanosecs;
nkeynes@1
   210
}
nkeynes@1
   211
nkeynes@1
   212
void sh4_stop(void)
nkeynes@1
   213
{
nkeynes@27
   214
nkeynes@1
   215
}
nkeynes@1
   216
nkeynes@23
   217
void sh4_save_state( FILE *f )
nkeynes@16
   218
{
nkeynes@16
   219
    fwrite( &sh4r, sizeof(sh4r), 1, f );
nkeynes@157
   220
    INTC_save_state( f );
nkeynes@53
   221
    TMU_save_state( f );
nkeynes@23
   222
    SCIF_save_state( f );
nkeynes@16
   223
}
nkeynes@16
   224
nkeynes@23
   225
int sh4_load_state( FILE * f )
nkeynes@16
   226
{
nkeynes@18
   227
    fread( &sh4r, sizeof(sh4r), 1, f );
nkeynes@157
   228
    INTC_load_state( f );
nkeynes@53
   229
    TMU_load_state( f );
nkeynes@23
   230
    return SCIF_load_state( f );
nkeynes@16
   231
}
nkeynes@16
   232
nkeynes@23
   233
/********************** SH4 emulation core  ****************************/
nkeynes@23
   234
nkeynes@23
   235
void sh4_set_pc( int pc )
nkeynes@23
   236
{
nkeynes@23
   237
    sh4r.pc = pc;
nkeynes@23
   238
    sh4r.new_pc = pc+2;
nkeynes@23
   239
}
nkeynes@23
   240
nkeynes@246
   241
#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
nkeynes@27
   242
#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
nkeynes@1
   243
nkeynes@157
   244
#if(SH4_CALLTRACE == 1)
nkeynes@157
   245
#define MAX_CALLSTACK 32
nkeynes@157
   246
static struct call_stack {
nkeynes@157
   247
    sh4addr_t call_addr;
nkeynes@157
   248
    sh4addr_t target_addr;
nkeynes@157
   249
    sh4addr_t stack_pointer;
nkeynes@157
   250
} call_stack[MAX_CALLSTACK];
nkeynes@157
   251
nkeynes@157
   252
static int call_stack_depth = 0;
nkeynes@157
   253
int sh4_call_trace_on = 0;
nkeynes@157
   254
nkeynes@157
   255
static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
nkeynes@157
   256
{
nkeynes@157
   257
    if( call_stack_depth < MAX_CALLSTACK ) {
nkeynes@157
   258
	call_stack[call_stack_depth].call_addr = source;
nkeynes@157
   259
	call_stack[call_stack_depth].target_addr = dest;
nkeynes@157
   260
	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
nkeynes@157
   261
    }
nkeynes@157
   262
    call_stack_depth++;
nkeynes@157
   263
}
nkeynes@157
   264
nkeynes@157
   265
static inline trace_return( sh4addr_t source, sh4addr_t dest )
nkeynes@157
   266
{
nkeynes@157
   267
    if( call_stack_depth > 0 ) {
nkeynes@157
   268
	call_stack_depth--;
nkeynes@157
   269
    }
nkeynes@157
   270
}
nkeynes@157
   271
nkeynes@157
   272
void fprint_stack_trace( FILE *f )
nkeynes@157
   273
{
nkeynes@157
   274
    int i = call_stack_depth -1;
nkeynes@157
   275
    if( i >= MAX_CALLSTACK )
nkeynes@157
   276
	i = MAX_CALLSTACK - 1;
nkeynes@157
   277
    for( ; i >= 0; i-- ) {
nkeynes@157
   278
	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
nkeynes@157
   279
		 (call_stack_depth - i), call_stack[i].call_addr,
nkeynes@157
   280
		 call_stack[i].target_addr, call_stack[i].stack_pointer );
nkeynes@157
   281
    }
nkeynes@157
   282
}
nkeynes@157
   283
nkeynes@157
   284
#define TRACE_CALL( source, dest ) trace_call(source, dest)
nkeynes@157
   285
#define TRACE_RETURN( source, dest ) trace_return(source, dest)
nkeynes@157
   286
#else
nkeynes@157
   287
#define TRACE_CALL( dest, rts ) 
nkeynes@157
   288
#define TRACE_RETURN( source, dest )
nkeynes@157
   289
#endif
nkeynes@157
   290
nkeynes@246
   291
#define RAISE( x, v ) do{			\
nkeynes@1
   292
    if( sh4r.vbr == 0 ) { \
nkeynes@1
   293
        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
nkeynes@104
   294
        dreamcast_stop(); return FALSE;	\
nkeynes@1
   295
    } else { \
nkeynes@246
   296
        sh4r.spc = sh4r.pc;	\
nkeynes@1
   297
        sh4r.ssr = sh4_read_sr(); \
nkeynes@1
   298
        sh4r.sgr = sh4r.r[15]; \
nkeynes@1
   299
        MMIO_WRITE(MMU,EXPEVT,x); \
nkeynes@1
   300
        sh4r.pc = sh4r.vbr + v; \
nkeynes@1
   301
        sh4r.new_pc = sh4r.pc + 2; \
nkeynes@1
   302
        sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
nkeynes@246
   303
	if( sh4r.in_delay_slot ) { \
nkeynes@246
   304
	    sh4r.in_delay_slot = 0; \
nkeynes@246
   305
	    sh4r.spc -= 2; \
nkeynes@246
   306
	} \
nkeynes@1
   307
    } \
nkeynes@27
   308
    return TRUE; } while(0)
nkeynes@229
   309
nkeynes@10
   310
#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
nkeynes@10
   311
#define MEM_READ_WORD( addr ) sh4_read_word(addr)
nkeynes@10
   312
#define MEM_READ_LONG( addr ) sh4_read_long(addr)
nkeynes@10
   313
#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
nkeynes@10
   314
#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
nkeynes@10
   315
#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
nkeynes@1
   316
nkeynes@1
   317
#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
nkeynes@1
   318
nkeynes@124
   319
#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
nkeynes@124
   320
#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
nkeynes@84
   321
nkeynes@246
   322
#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
nkeynes@246
   323
#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
nkeynes@246
   324
#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
nkeynes@246
   325
#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
nkeynes@246
   326
#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
nkeynes@208
   327
nkeynes@246
   328
#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE )
nkeynes@84
   329
#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
nkeynes@246
   330
#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
nkeynes@1
   331
nkeynes@1
   332
static void sh4_switch_banks( )
nkeynes@1
   333
{
nkeynes@1
   334
    uint32_t tmp[8];
nkeynes@1
   335
nkeynes@1
   336
    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
nkeynes@1
   337
    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
nkeynes@1
   338
    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
nkeynes@1
   339
}
nkeynes@1
   340
nkeynes@1
   341
static void sh4_load_sr( uint32_t newval )
nkeynes@1
   342
{
nkeynes@1
   343
    if( (newval ^ sh4r.sr) & SR_RB )
nkeynes@1
   344
        sh4_switch_banks();
nkeynes@1
   345
    sh4r.sr = newval;
nkeynes@1
   346
    sh4r.t = (newval&SR_T) ? 1 : 0;
nkeynes@1
   347
    sh4r.s = (newval&SR_S) ? 1 : 0;
nkeynes@1
   348
    sh4r.m = (newval&SR_M) ? 1 : 0;
nkeynes@1
   349
    sh4r.q = (newval&SR_Q) ? 1 : 0;
nkeynes@1
   350
    intc_mask_changed();
nkeynes@1
   351
}
nkeynes@1
   352
nkeynes@124
   353
static void sh4_write_float( uint32_t addr, int reg )
nkeynes@124
   354
{
nkeynes@124
   355
    if( IS_FPU_DOUBLESIZE() ) {
nkeynes@124
   356
	if( reg & 1 ) {
nkeynes@124
   357
	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
nkeynes@124
   358
	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
nkeynes@124
   359
	} else {
nkeynes@124
   360
	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
nkeynes@124
   361
	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
nkeynes@124
   362
	}
nkeynes@124
   363
    } else {
nkeynes@124
   364
	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
nkeynes@124
   365
    }
nkeynes@124
   366
}
nkeynes@124
   367
nkeynes@124
   368
static void sh4_read_float( uint32_t addr, int reg )
nkeynes@124
   369
{
nkeynes@124
   370
    if( IS_FPU_DOUBLESIZE() ) {
nkeynes@124
   371
	if( reg & 1 ) {
nkeynes@124
   372
	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
nkeynes@124
   373
	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
nkeynes@124
   374
	} else {
nkeynes@124
   375
	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@124
   376
	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
nkeynes@124
   377
	}
nkeynes@124
   378
    } else {
nkeynes@124
   379
	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@124
   380
    }
nkeynes@124
   381
}
nkeynes@124
   382
nkeynes@1
   383
static uint32_t sh4_read_sr( void )
nkeynes@1
   384
{
nkeynes@1
   385
    /* synchronize sh4r.sr with the various bitflags */
nkeynes@1
   386
    sh4r.sr &= SR_MQSTMASK;
nkeynes@1
   387
    if( sh4r.t ) sh4r.sr |= SR_T;
nkeynes@1
   388
    if( sh4r.s ) sh4r.sr |= SR_S;
nkeynes@1
   389
    if( sh4r.m ) sh4r.sr |= SR_M;
nkeynes@1
   390
    if( sh4r.q ) sh4r.sr |= SR_Q;
nkeynes@1
   391
    return sh4r.sr;
nkeynes@1
   392
}
nkeynes@246
   393
nkeynes@246
   394
/**
nkeynes@246
   395
 * Raise a general CPU exception for the specified exception code.
nkeynes@246
   396
 * (NOT for TRAPA or TLB exceptions)
nkeynes@246
   397
 */
nkeynes@246
   398
gboolean sh4_raise_exception( int code )
nkeynes@1
   399
{
nkeynes@246
   400
    RAISE( code, EXV_EXCEPTION );
nkeynes@246
   401
}
nkeynes@246
   402
nkeynes@246
   403
gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
nkeynes@246
   404
    if( sh4r.in_delay_slot ) {
nkeynes@246
   405
	return sh4_raise_exception(slot_code);
nkeynes@246
   406
    } else {
nkeynes@246
   407
	return sh4_raise_exception(normal_code);
nkeynes@246
   408
    }
nkeynes@246
   409
}
nkeynes@246
   410
nkeynes@246
   411
gboolean sh4_raise_tlb_exception( int code )
nkeynes@246
   412
{
nkeynes@246
   413
    RAISE( code, EXV_TLBMISS );
nkeynes@1
   414
}
nkeynes@1
   415
nkeynes@1
   416
static void sh4_accept_interrupt( void )
nkeynes@1
   417
{
nkeynes@1
   418
    uint32_t code = intc_accept_interrupt();
nkeynes@1
   419
    sh4r.ssr = sh4_read_sr();
nkeynes@1
   420
    sh4r.spc = sh4r.pc;
nkeynes@1
   421
    sh4r.sgr = sh4r.r[15];
nkeynes@1
   422
    sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
nkeynes@1
   423
    MMIO_WRITE( MMU, INTEVT, code );
nkeynes@1
   424
    sh4r.pc = sh4r.vbr + 0x600;
nkeynes@1
   425
    sh4r.new_pc = sh4r.pc + 2;
nkeynes@92
   426
    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
nkeynes@1
   427
}
nkeynes@1
   428
nkeynes@27
   429
gboolean sh4_execute_instruction( void )
nkeynes@1
   430
{
nkeynes@84
   431
    uint32_t pc;
nkeynes@2
   432
    unsigned short ir;
nkeynes@1
   433
    uint32_t tmp;
nkeynes@1
   434
    uint64_t tmpl;
nkeynes@123
   435
    float ftmp;
nkeynes@123
   436
    double dtmp;
nkeynes@1
   437
    
nkeynes@1
   438
#define R0 sh4r.r[0]
nkeynes@84
   439
#define FR0 FR(0)
nkeynes@84
   440
#define DR0 DR(0)
nkeynes@1
   441
#define RN(ir) sh4r.r[(ir&0x0F00)>>8]
nkeynes@1
   442
#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
nkeynes@1
   443
#define RM(ir) sh4r.r[(ir&0x00F0)>>4]
nkeynes@1
   444
#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
nkeynes@1
   445
#define DISP8(ir) (ir&0x00FF)
nkeynes@1
   446
#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1
   447
#define IMM8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1
   448
#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
nkeynes@1
   449
#define DISP12(ir) SIGNEXT12(ir&0x0FFF)
nkeynes@84
   450
#define FRNn(ir) ((ir&0x0F00)>>8)
nkeynes@84
   451
#define FRMn(ir) ((ir&0x00F0)>>4)
nkeynes@84
   452
#define DRNn(ir) ((ir&0x0E00)>>9)
nkeynes@84
   453
#define DRMn(ir) ((ir&0x00E0)>>5)
nkeynes@2
   454
#define FVN(ir) ((ir&0x0C00)>>8)
nkeynes@2
   455
#define FVM(ir) ((ir&0x0300)>>6)
nkeynes@84
   456
#define FRN(ir) FR(FRNn(ir))
nkeynes@84
   457
#define FRM(ir) FR(FRMn(ir))
nkeynes@84
   458
#define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
nkeynes@84
   459
#define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
nkeynes@95
   460
#define DRN(ir) DRb(DRNn(ir), ir&0x0100)
nkeynes@95
   461
#define DRM(ir) DRb(DRMn(ir),ir&0x0010)
nkeynes@84
   462
#define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
nkeynes@84
   463
#define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
nkeynes@1
   464
#define FPULf   *((float *)&sh4r.fpul)
nkeynes@1
   465
#define FPULi    (sh4r.fpul)
nkeynes@1
   466
nkeynes@2
   467
    pc = sh4r.pc;
nkeynes@84
   468
    if( pc > 0xFFFFFF00 ) {
nkeynes@84
   469
	/* SYSCALL Magic */
nkeynes@102
   470
	syscall_invoke( pc );
nkeynes@104
   471
	sh4r.in_delay_slot = 0;
nkeynes@84
   472
	pc = sh4r.pc = sh4r.pr;
nkeynes@84
   473
	sh4r.new_pc = sh4r.pc + 2;
nkeynes@84
   474
    }
nkeynes@208
   475
    CHECKRALIGN16(pc);
nkeynes@235
   476
nkeynes@235
   477
    /* Read instruction */
nkeynes@235
   478
    uint32_t pageaddr = pc >> 12;
nkeynes@235
   479
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@235
   480
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@235
   481
    } else {
nkeynes@235
   482
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@235
   483
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@235
   484
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@235
   485
	     * region, fallback on the full-blown memory read
nkeynes@235
   486
	     */
nkeynes@235
   487
	    sh4_icache = NULL;
nkeynes@235
   488
	    ir = MEM_READ_WORD(pc);
nkeynes@235
   489
	} else {
nkeynes@235
   490
	    sh4_icache_addr = pageaddr;
nkeynes@235
   491
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@235
   492
	}
nkeynes@235
   493
    }
nkeynes@1
   494
    sh4r.icount++;
nkeynes@1
   495
    
nkeynes@1
   496
    switch( (ir&0xF000)>>12 ) {
nkeynes@1
   497
        case 0: /* 0000nnnnmmmmxxxx */
nkeynes@1
   498
            switch( ir&0x000F ) {
nkeynes@1
   499
                case 2:
nkeynes@1
   500
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   501
                        case 0: /* STC     SR, Rn */
nkeynes@1
   502
                            CHECKPRIV();
nkeynes@1
   503
                            RN(ir) = sh4_read_sr();
nkeynes@1
   504
                            break;
nkeynes@1
   505
                        case 1: /* STC     GBR, Rn */
nkeynes@1
   506
                            RN(ir) = sh4r.gbr;
nkeynes@1
   507
                            break;
nkeynes@1
   508
                        case 2: /* STC     VBR, Rn */
nkeynes@1
   509
                            CHECKPRIV();
nkeynes@1
   510
                            RN(ir) = sh4r.vbr;
nkeynes@1
   511
                            break;
nkeynes@1
   512
                        case 3: /* STC     SSR, Rn */
nkeynes@1
   513
                            CHECKPRIV();
nkeynes@1
   514
                            RN(ir) = sh4r.ssr;
nkeynes@1
   515
                            break;
nkeynes@1
   516
                        case 4: /* STC     SPC, Rn */
nkeynes@1
   517
                            CHECKPRIV();
nkeynes@1
   518
                            RN(ir) = sh4r.spc;
nkeynes@1
   519
                            break;
nkeynes@1
   520
                        case 8: case 9: case 10: case 11: case 12: case 13:
nkeynes@1
   521
                        case 14: case 15:/* STC     Rm_bank, Rn */
nkeynes@1
   522
                            CHECKPRIV();
nkeynes@1
   523
                            RN(ir) = RN_BANK(ir);
nkeynes@1
   524
                            break;
nkeynes@1
   525
                        default: UNDEF(ir);
nkeynes@1
   526
                    }
nkeynes@1
   527
                    break;
nkeynes@1
   528
                case 3:
nkeynes@1
   529
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   530
                        case 0: /* BSRF    Rn */
nkeynes@232
   531
                            CHECKSLOTILLEGAL();
nkeynes@1
   532
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   533
                            sh4r.in_delay_slot = 1;
nkeynes@1
   534
                            sh4r.pr = sh4r.pc + 4;
nkeynes@1
   535
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   536
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@157
   537
			    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
   538
                            return TRUE;
nkeynes@1
   539
                        case 2: /* BRAF    Rn */
nkeynes@232
   540
                            CHECKSLOTILLEGAL();
nkeynes@1
   541
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   542
                            sh4r.in_delay_slot = 1;
nkeynes@1
   543
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   544
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27
   545
                            return TRUE;
nkeynes@1
   546
                        case 8: /* PREF    [Rn] */
nkeynes@2
   547
                            tmp = RN(ir);
nkeynes@2
   548
                            if( (tmp & 0xFC000000) == 0xE0000000 ) {
nkeynes@2
   549
                                /* Store queue operation */
nkeynes@2
   550
                                int queue = (tmp&0x20)>>2;
nkeynes@2
   551
                                int32_t *src = &sh4r.store_queue[queue];
nkeynes@2
   552
                                uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@2
   553
                                uint32_t target = tmp&0x03FFFFE0 | hi;
nkeynes@2
   554
                                mem_copy_to_sh4( target, src, 32 );
nkeynes@2
   555
                            }
nkeynes@2
   556
                            break;
nkeynes@1
   557
                        case 9: /* OCBI    [Rn] */
nkeynes@1
   558
                        case 10:/* OCBP    [Rn] */
nkeynes@1
   559
                        case 11:/* OCBWB   [Rn] */
nkeynes@1
   560
                            /* anything? */
nkeynes@1
   561
                            break;
nkeynes@1
   562
                        case 12:/* MOVCA.L R0, [Rn] */
nkeynes@164
   563
			    tmp = RN(ir);
nkeynes@208
   564
			    CHECKWALIGN32(tmp);
nkeynes@164
   565
			    MEM_WRITE_LONG( tmp, R0 );
nkeynes@164
   566
			    break;
nkeynes@1
   567
                        default: UNDEF(ir);
nkeynes@1
   568
                    }
nkeynes@1
   569
                    break;
nkeynes@1
   570
                case 4: /* MOV.B   Rm, [R0 + Rn] */
nkeynes@1
   571
                    MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
nkeynes@1
   572
                    break;
nkeynes@1
   573
                case 5: /* MOV.W   Rm, [R0 + Rn] */
nkeynes@208
   574
		    CHECKWALIGN16( R0 + RN(ir) );
nkeynes@1
   575
                    MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
nkeynes@1
   576
                    break;
nkeynes@1
   577
                case 6: /* MOV.L   Rm, [R0 + Rn] */
nkeynes@208
   578
		    CHECKWALIGN32( R0 + RN(ir) );
nkeynes@1
   579
                    MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
nkeynes@1
   580
                    break;
nkeynes@1
   581
                case 7: /* MUL.L   Rm, Rn */
nkeynes@2
   582
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   583
                        (RM(ir) * RN(ir));
nkeynes@1
   584
                    break;
nkeynes@1
   585
                case 8: 
nkeynes@1
   586
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   587
                        case 0: /* CLRT    */
nkeynes@1
   588
                            sh4r.t = 0;
nkeynes@1
   589
                            break;
nkeynes@1
   590
                        case 1: /* SETT    */
nkeynes@1
   591
                            sh4r.t = 1;
nkeynes@1
   592
                            break;
nkeynes@1
   593
                        case 2: /* CLRMAC  */
nkeynes@1
   594
                            sh4r.mac = 0;
nkeynes@1
   595
                            break;
nkeynes@1
   596
                        case 3: /* LDTLB   */
nkeynes@1
   597
                            break;
nkeynes@1
   598
                        case 4: /* CLRS    */
nkeynes@1
   599
                            sh4r.s = 0;
nkeynes@1
   600
                            break;
nkeynes@1
   601
                        case 5: /* SETS    */
nkeynes@1
   602
                            sh4r.s = 1;
nkeynes@1
   603
                            break;
nkeynes@1
   604
                        default: UNDEF(ir);
nkeynes@1
   605
                    }
nkeynes@1
   606
                    break;
nkeynes@1
   607
                case 9: 
nkeynes@1
   608
                    if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
nkeynes@1
   609
                        RN(ir) = sh4r.t;
nkeynes@1
   610
                    else if( ir == 0x0019 ) /* DIV0U   */
nkeynes@1
   611
                        sh4r.m = sh4r.q = sh4r.t = 0;
nkeynes@1
   612
                    else if( ir == 0x0009 )
nkeynes@1
   613
                        /* NOP     */;
nkeynes@1
   614
                    else UNDEF(ir);
nkeynes@1
   615
                    break;
nkeynes@1
   616
                case 10:
nkeynes@1
   617
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@1
   618
                        case 0: /* STS     MACH, Rn */
nkeynes@1
   619
                            RN(ir) = sh4r.mac >> 32;
nkeynes@1
   620
                            break;
nkeynes@1
   621
                        case 1: /* STS     MACL, Rn */
nkeynes@1
   622
                            RN(ir) = (uint32_t)sh4r.mac;
nkeynes@1
   623
                            break;
nkeynes@1
   624
                        case 2: /* STS     PR, Rn */
nkeynes@1
   625
                            RN(ir) = sh4r.pr;
nkeynes@1
   626
                            break;
nkeynes@1
   627
                        case 3: /* STC     SGR, Rn */
nkeynes@1
   628
                            CHECKPRIV();
nkeynes@1
   629
                            RN(ir) = sh4r.sgr;
nkeynes@1
   630
                            break;
nkeynes@1
   631
                        case 5:/* STS      FPUL, Rn */
nkeynes@1
   632
                            RN(ir) = sh4r.fpul;
nkeynes@1
   633
                            break;
nkeynes@1
   634
                        case 6: /* STS     FPSCR, Rn */
nkeynes@1
   635
                            RN(ir) = sh4r.fpscr;
nkeynes@1
   636
                            break;
nkeynes@1
   637
                        case 15:/* STC     DBR, Rn */
nkeynes@1
   638
                            CHECKPRIV();
nkeynes@1
   639
                            RN(ir) = sh4r.dbr;
nkeynes@1
   640
                            break;
nkeynes@1
   641
                        default: UNDEF(ir);
nkeynes@1
   642
                    }
nkeynes@1
   643
                    break;
nkeynes@1
   644
                case 11:
nkeynes@1
   645
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   646
                        case 0: /* RTS     */
nkeynes@232
   647
                            CHECKSLOTILLEGAL();
nkeynes@1
   648
                            CHECKDEST( sh4r.pr );
nkeynes@2
   649
                            sh4r.in_delay_slot = 1;
nkeynes@1
   650
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   651
                            sh4r.new_pc = sh4r.pr;
nkeynes@157
   652
                            TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@27
   653
                            return TRUE;
nkeynes@1
   654
                        case 1: /* SLEEP   */
nkeynes@27
   655
			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@27
   656
				sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@27
   657
			    } else {
nkeynes@27
   658
				sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@27
   659
			    }
nkeynes@27
   660
			    return FALSE; /* Halt CPU */
nkeynes@1
   661
                        case 2: /* RTE     */
nkeynes@1
   662
                            CHECKPRIV();
nkeynes@1
   663
                            CHECKDEST( sh4r.spc );
nkeynes@2
   664
                            CHECKSLOTILLEGAL();
nkeynes@2
   665
                            sh4r.in_delay_slot = 1;
nkeynes@1
   666
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   667
                            sh4r.new_pc = sh4r.spc;
nkeynes@1
   668
                            sh4_load_sr( sh4r.ssr );
nkeynes@27
   669
                            return TRUE;
nkeynes@1
   670
                        default:UNDEF(ir);
nkeynes@1
   671
                    }
nkeynes@1
   672
                    break;
nkeynes@1
   673
                case 12:/* MOV.B   [R0+R%d], R%d */
nkeynes@1
   674
                    RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
nkeynes@1
   675
                    break;
nkeynes@1
   676
                case 13:/* MOV.W   [R0+R%d], R%d */
nkeynes@208
   677
		    CHECKRALIGN16( R0 + RM(ir) );
nkeynes@1
   678
                    RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
nkeynes@1
   679
                    break;
nkeynes@1
   680
                case 14:/* MOV.L   [R0+R%d], R%d */
nkeynes@208
   681
		    CHECKRALIGN32( R0 + RM(ir) );
nkeynes@1
   682
                    RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
nkeynes@1
   683
                    break;
nkeynes@1
   684
                case 15:/* MAC.L   [Rm++], [Rn++] */
nkeynes@208
   685
		    CHECKRALIGN32( RM(ir) );
nkeynes@208
   686
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   687
                    tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
nkeynes@1
   688
                                  SIGNEXT32(MEM_READ_LONG(RN(ir))) );
nkeynes@1
   689
                    if( sh4r.s ) {
nkeynes@1
   690
                        /* 48-bit Saturation. Yuch */
nkeynes@1
   691
                        tmpl += SIGNEXT48(sh4r.mac);
nkeynes@2
   692
                        if( tmpl < 0xFFFF800000000000LL )
nkeynes@2
   693
                            tmpl = 0xFFFF800000000000LL;
nkeynes@2
   694
                        else if( tmpl > 0x00007FFFFFFFFFFFLL )
nkeynes@2
   695
                            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@2
   696
                        sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
nkeynes@2
   697
                            (tmpl&0x0000FFFFFFFFFFFFLL);
nkeynes@1
   698
                    } else sh4r.mac = tmpl;
nkeynes@1
   699
                    
nkeynes@1
   700
                    RM(ir) += 4;
nkeynes@1
   701
                    RN(ir) += 4;
nkeynes@1
   702
                    
nkeynes@1
   703
                    break;
nkeynes@1
   704
                default: UNDEF(ir);
nkeynes@1
   705
            }
nkeynes@1
   706
            break;
nkeynes@1
   707
        case 1: /* 0001nnnnmmmmdddd */
nkeynes@1
   708
            /* MOV.L   Rm, [Rn + disp4*4] */
nkeynes@208
   709
	    tmp = RN(ir) + (DISP4(ir)<<2);
nkeynes@208
   710
	    CHECKWALIGN32( tmp );
nkeynes@208
   711
            MEM_WRITE_LONG( tmp, RM(ir) );
nkeynes@1
   712
            break;
nkeynes@1
   713
        case 2: /* 0010nnnnmmmmxxxx */
nkeynes@1
   714
            switch( ir&0x000F ) {
nkeynes@1
   715
                case 0: /* MOV.B   Rm, [Rn] */
nkeynes@1
   716
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   717
                    break;
nkeynes@1
   718
                case 1: /* MOV.W   Rm, [Rn] */
nkeynes@208
   719
               	    CHECKWALIGN16( RN(ir) );
nkeynes@208
   720
		    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   721
                    break;
nkeynes@1
   722
                case 2: /* MOV.L   Rm, [Rn] */
nkeynes@208
   723
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   724
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   725
                    break;
nkeynes@1
   726
                case 3: UNDEF(ir);
nkeynes@1
   727
                    break;
nkeynes@1
   728
                case 4: /* MOV.B   Rm, [--Rn] */
nkeynes@1
   729
                    RN(ir) --;
nkeynes@1
   730
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   731
                    break;
nkeynes@1
   732
                case 5: /* MOV.W   Rm, [--Rn] */
nkeynes@1
   733
                    RN(ir) -= 2;
nkeynes@208
   734
		    CHECKWALIGN16( RN(ir) );
nkeynes@1
   735
                    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   736
                    break;
nkeynes@1
   737
                case 6: /* MOV.L   Rm, [--Rn] */
nkeynes@1
   738
                    RN(ir) -= 4;
nkeynes@208
   739
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   740
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   741
                    break;
nkeynes@1
   742
                case 7: /* DIV0S   Rm, Rn */
nkeynes@1
   743
                    sh4r.q = RN(ir)>>31;
nkeynes@1
   744
                    sh4r.m = RM(ir)>>31;
nkeynes@1
   745
                    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@1
   746
                    break;
nkeynes@1
   747
                case 8: /* TST     Rm, Rn */
nkeynes@1
   748
                    sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
nkeynes@1
   749
                    break;
nkeynes@1
   750
                case 9: /* AND     Rm, Rn */
nkeynes@1
   751
                    RN(ir) &= RM(ir);
nkeynes@1
   752
                    break;
nkeynes@1
   753
                case 10:/* XOR     Rm, Rn */
nkeynes@1
   754
                    RN(ir) ^= RM(ir);
nkeynes@1
   755
                    break;
nkeynes@1
   756
                case 11:/* OR      Rm, Rn */
nkeynes@1
   757
                    RN(ir) |= RM(ir);
nkeynes@1
   758
                    break;
nkeynes@1
   759
                case 12:/* CMP/STR Rm, Rn */
nkeynes@1
   760
                    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@1
   761
                    tmp = RM(ir) ^ RN(ir);
nkeynes@1
   762
                    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@1
   763
                              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@1
   764
                    break;
nkeynes@1
   765
                case 13:/* XTRCT   Rm, Rn */
nkeynes@1
   766
                    RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
nkeynes@1
   767
                    break;
nkeynes@1
   768
                case 14:/* MULU.W  Rm, Rn */
nkeynes@2
   769
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   770
                        (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
nkeynes@1
   771
                    break;
nkeynes@1
   772
                case 15:/* MULS.W  Rm, Rn */
nkeynes@2
   773
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   774
                        (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
nkeynes@1
   775
                    break;
nkeynes@1
   776
            }
nkeynes@1
   777
            break;
nkeynes@1
   778
        case 3: /* 0011nnnnmmmmxxxx */
nkeynes@1
   779
            switch( ir&0x000F ) {
nkeynes@1
   780
                case 0: /* CMP/EQ  Rm, Rn */
nkeynes@1
   781
                    sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
nkeynes@1
   782
                    break;
nkeynes@1
   783
                case 2: /* CMP/HS  Rm, Rn */
nkeynes@1
   784
                    sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
nkeynes@1
   785
                    break;
nkeynes@1
   786
                case 3: /* CMP/GE  Rm, Rn */
nkeynes@1
   787
                    sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   788
                    break;
nkeynes@1
   789
                case 4: { /* DIV1    Rm, Rn */
nkeynes@1
   790
                    /* This is just from the sh4p manual with some
nkeynes@1
   791
                     * simplifications (someone want to check it's correct? :)
nkeynes@1
   792
                     * Why they couldn't just provide a real DIV instruction...
nkeynes@1
   793
                     * Please oh please let the translator batch these things
nkeynes@1
   794
                     * up into a single DIV... */
nkeynes@1
   795
                    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@1
   796
nkeynes@1
   797
                    dir = sh4r.q ^ sh4r.m;
nkeynes@1
   798
                    sh4r.q = (RN(ir) >> 31);
nkeynes@1
   799
                    tmp2 = RM(ir);
nkeynes@1
   800
                    RN(ir) = (RN(ir) << 1) | sh4r.t;
nkeynes@1
   801
                    tmp0 = RN(ir);
nkeynes@1
   802
                    if( dir ) {
nkeynes@1
   803
                        RN(ir) += tmp2;
nkeynes@1
   804
                        tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
nkeynes@1
   805
                    } else {
nkeynes@1
   806
                        RN(ir) -= tmp2;
nkeynes@1
   807
                        tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
nkeynes@1
   808
                    }
nkeynes@1
   809
                    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@1
   810
                    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@1
   811
                    break; }
nkeynes@1
   812
                case 5: /* DMULU.L Rm, Rn */
nkeynes@1
   813
                    sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
nkeynes@1
   814
                    break;
nkeynes@1
   815
                case 6: /* CMP/HI  Rm, Rn */
nkeynes@1
   816
                    sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
nkeynes@1
   817
                    break;
nkeynes@1
   818
                case 7: /* CMP/GT  Rm, Rn */
nkeynes@1
   819
                    sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   820
                    break;
nkeynes@1
   821
                case 8: /* SUB     Rm, Rn */
nkeynes@1
   822
                    RN(ir) -= RM(ir);
nkeynes@1
   823
                    break;
nkeynes@1
   824
                case 10:/* SUBC    Rm, Rn */
nkeynes@1
   825
                    tmp = RN(ir);
nkeynes@1
   826
                    RN(ir) = RN(ir) - RM(ir) - sh4r.t;
nkeynes@1
   827
                    sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
nkeynes@1
   828
                    break;
nkeynes@1
   829
                case 11:/* SUBV    Rm, Rn */
nkeynes@1
   830
                    UNIMP(ir);
nkeynes@1
   831
                    break;
nkeynes@1
   832
                case 12:/* ADD     Rm, Rn */
nkeynes@1
   833
                    RN(ir) += RM(ir);
nkeynes@1
   834
                    break;
nkeynes@1
   835
                case 13:/* DMULS.L Rm, Rn */
nkeynes@1
   836
                    sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
nkeynes@1
   837
                    break;
nkeynes@1
   838
                case 14:/* ADDC    Rm, Rn */
nkeynes@1
   839
                    tmp = RN(ir);
nkeynes@1
   840
                    RN(ir) += RM(ir) + sh4r.t;
nkeynes@1
   841
                    sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@1
   842
                    break;
nkeynes@1
   843
                case 15:/* ADDV    Rm, Rn */
nkeynes@227
   844
		    tmp = RN(ir) + RM(ir);
nkeynes@227
   845
		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
nkeynes@227
   846
		    RN(ir) = tmp;
nkeynes@1
   847
                    break;
nkeynes@1
   848
                default: UNDEF(ir);
nkeynes@1
   849
            }
nkeynes@1
   850
            break;
nkeynes@1
   851
        case 4: /* 0100nnnnxxxxxxxx */
nkeynes@1
   852
            switch( ir&0x00FF ) {
nkeynes@1
   853
                case 0x00: /* SHLL    Rn */
nkeynes@1
   854
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   855
                    RN(ir) <<= 1;
nkeynes@1
   856
                    break;
nkeynes@1
   857
                case 0x01: /* SHLR    Rn */
nkeynes@1
   858
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   859
                    RN(ir) >>= 1;
nkeynes@1
   860
                    break;
nkeynes@1
   861
                case 0x02: /* STS.L   MACH, [--Rn] */
nkeynes@1
   862
                    RN(ir) -= 4;
nkeynes@208
   863
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   864
                    MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
nkeynes@1
   865
                    break;
nkeynes@1
   866
                case 0x03: /* STC.L   SR, [--Rn] */
nkeynes@1
   867
                    CHECKPRIV();
nkeynes@1
   868
                    RN(ir) -= 4;
nkeynes@208
   869
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   870
                    MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
nkeynes@1
   871
                    break;
nkeynes@1
   872
                case 0x04: /* ROTL    Rn */
nkeynes@1
   873
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   874
                    RN(ir) <<= 1;
nkeynes@1
   875
                    RN(ir) |= sh4r.t;
nkeynes@1
   876
                    break;
nkeynes@1
   877
                case 0x05: /* ROTR    Rn */
nkeynes@1
   878
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   879
                    RN(ir) >>= 1;
nkeynes@1
   880
                    RN(ir) |= (sh4r.t << 31);
nkeynes@1
   881
                    break;
nkeynes@1
   882
                case 0x06: /* LDS.L   [Rn++], MACH */
nkeynes@208
   883
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   884
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   885
                        (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
nkeynes@1
   886
                    RN(ir) += 4;
nkeynes@1
   887
                    break;
nkeynes@1
   888
                case 0x07: /* LDC.L   [Rn++], SR */
nkeynes@232
   889
		    CHECKSLOTILLEGAL();
nkeynes@1
   890
                    CHECKPRIV();
nkeynes@208
   891
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   892
                    sh4_load_sr( MEM_READ_LONG(RN(ir)) );
nkeynes@1
   893
                    RN(ir) +=4;
nkeynes@1
   894
                    break;
nkeynes@1
   895
                case 0x08: /* SHLL2   Rn */
nkeynes@1
   896
                    RN(ir) <<= 2;
nkeynes@1
   897
                    break;
nkeynes@1
   898
                case 0x09: /* SHLR2   Rn */
nkeynes@1
   899
                    RN(ir) >>= 2;
nkeynes@1
   900
                    break;
nkeynes@1
   901
                case 0x0A: /* LDS     Rn, MACH */
nkeynes@1
   902
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   903
                        (((uint64_t)RN(ir))<<32);
nkeynes@1
   904
                    break;
nkeynes@1
   905
                case 0x0B: /* JSR     [Rn] */
nkeynes@1
   906
                    CHECKDEST( RN(ir) );
nkeynes@2
   907
                    CHECKSLOTILLEGAL();
nkeynes@2
   908
                    sh4r.in_delay_slot = 1;
nkeynes@1
   909
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
   910
                    sh4r.new_pc = RN(ir);
nkeynes@1
   911
                    sh4r.pr = pc + 4;
nkeynes@157
   912
		    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
   913
                    return TRUE;
nkeynes@1
   914
                case 0x0E: /* LDC     Rn, SR */
nkeynes@232
   915
		    CHECKSLOTILLEGAL();
nkeynes@1
   916
                    CHECKPRIV();
nkeynes@1
   917
                    sh4_load_sr( RN(ir) );
nkeynes@1
   918
                    break;
nkeynes@1
   919
                case 0x10: /* DT      Rn */
nkeynes@1
   920
                    RN(ir) --;
nkeynes@1
   921
                    sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
nkeynes@1
   922
                    break;
nkeynes@1
   923
                case 0x11: /* CMP/PZ  Rn */
nkeynes@1
   924
                    sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
nkeynes@1
   925
                    break;
nkeynes@1
   926
                case 0x12: /* STS.L   MACL, [--Rn] */
nkeynes@1
   927
                    RN(ir) -= 4;
nkeynes@208
   928
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   929
                    MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
nkeynes@1
   930
                    break;
nkeynes@1
   931
                case 0x13: /* STC.L   GBR, [--Rn] */
nkeynes@1
   932
                    RN(ir) -= 4;
nkeynes@208
   933
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   934
                    MEM_WRITE_LONG( RN(ir), sh4r.gbr );
nkeynes@1
   935
                    break;
nkeynes@1
   936
                case 0x15: /* CMP/PL  Rn */
nkeynes@1
   937
                    sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
nkeynes@1
   938
                    break;
nkeynes@1
   939
                case 0x16: /* LDS.L   [Rn++], MACL */
nkeynes@208
   940
		    CHECKRALIGN32( RN(ir) );
nkeynes@2
   941
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   942
                        (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
nkeynes@1
   943
                    RN(ir) += 4;
nkeynes@1
   944
                    break;
nkeynes@1
   945
                case 0x17: /* LDC.L   [Rn++], GBR */
nkeynes@208
   946
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   947
                    sh4r.gbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   948
                    RN(ir) +=4;
nkeynes@1
   949
                    break;
nkeynes@1
   950
                case 0x18: /* SHLL8   Rn */
nkeynes@1
   951
                    RN(ir) <<= 8;
nkeynes@1
   952
                    break;
nkeynes@1
   953
                case 0x19: /* SHLR8   Rn */
nkeynes@1
   954
                    RN(ir) >>= 8;
nkeynes@1
   955
                    break;
nkeynes@1
   956
                case 0x1A: /* LDS     Rn, MACL */
nkeynes@2
   957
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   958
                        (uint64_t)((uint32_t)(RN(ir)));
nkeynes@1
   959
                    break;
nkeynes@1
   960
                case 0x1B: /* TAS.B   [Rn] */
nkeynes@1
   961
                    tmp = MEM_READ_BYTE( RN(ir) );
nkeynes@1
   962
                    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@1
   963
                    MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
nkeynes@1
   964
                    break;
nkeynes@1
   965
                case 0x1E: /* LDC     Rn, GBR */
nkeynes@1
   966
                    sh4r.gbr = RN(ir);
nkeynes@1
   967
                    break;
nkeynes@1
   968
                case 0x20: /* SHAL    Rn */
nkeynes@1
   969
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   970
                    RN(ir) <<= 1;
nkeynes@1
   971
                    break;
nkeynes@1
   972
                case 0x21: /* SHAR    Rn */
nkeynes@1
   973
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   974
                    RN(ir) = ((int32_t)RN(ir)) >> 1;
nkeynes@1
   975
                    break;
nkeynes@1
   976
                case 0x22: /* STS.L   PR, [--Rn] */
nkeynes@1
   977
                    RN(ir) -= 4;
nkeynes@208
   978
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   979
                    MEM_WRITE_LONG( RN(ir), sh4r.pr );
nkeynes@1
   980
                    break;
nkeynes@1
   981
                case 0x23: /* STC.L   VBR, [--Rn] */
nkeynes@1
   982
                    CHECKPRIV();
nkeynes@1
   983
                    RN(ir) -= 4;
nkeynes@208
   984
		    CHECKWALIGN32( RN(ir) );
nkeynes@2
   985
                    MEM_WRITE_LONG( RN(ir), sh4r.vbr );
nkeynes@1
   986
                    break;
nkeynes@1
   987
                case 0x24: /* ROTCL   Rn */
nkeynes@1
   988
                    tmp = RN(ir) >> 31;
nkeynes@1
   989
                    RN(ir) <<= 1;
nkeynes@1
   990
                    RN(ir) |= sh4r.t;
nkeynes@1
   991
                    sh4r.t = tmp;
nkeynes@1
   992
                    break;
nkeynes@1
   993
                case 0x25: /* ROTCR   Rn */
nkeynes@1
   994
                    tmp = RN(ir) & 0x00000001;
nkeynes@1
   995
                    RN(ir) >>= 1;
nkeynes@1
   996
                    RN(ir) |= (sh4r.t << 31 );
nkeynes@1
   997
                    sh4r.t = tmp;
nkeynes@1
   998
                    break;
nkeynes@1
   999
                case 0x26: /* LDS.L   [Rn++], PR */
nkeynes@208
  1000
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1001
                    sh4r.pr = MEM_READ_LONG( RN(ir) );
nkeynes@1
  1002
                    RN(ir) += 4;
nkeynes@1
  1003
                    break;
nkeynes@1
  1004
                case 0x27: /* LDC.L   [Rn++], VBR */
nkeynes@1
  1005
                    CHECKPRIV();
nkeynes@208
  1006
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1007
                    sh4r.vbr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1008
                    RN(ir) +=4;
nkeynes@1
  1009
                    break;
nkeynes@1
  1010
                case 0x28: /* SHLL16  Rn */
nkeynes@1
  1011
                    RN(ir) <<= 16;
nkeynes@1
  1012
                    break;
nkeynes@1
  1013
                case 0x29: /* SHLR16  Rn */
nkeynes@1
  1014
                    RN(ir) >>= 16;
nkeynes@1
  1015
                    break;
nkeynes@1
  1016
                case 0x2A: /* LDS     Rn, PR */
nkeynes@1
  1017
                    sh4r.pr = RN(ir);
nkeynes@1
  1018
                    break;
nkeynes@1
  1019
                case 0x2B: /* JMP     [Rn] */
nkeynes@1
  1020
                    CHECKDEST( RN(ir) );
nkeynes@2
  1021
                    CHECKSLOTILLEGAL();
nkeynes@2
  1022
                    sh4r.in_delay_slot = 1;
nkeynes@1
  1023
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
  1024
                    sh4r.new_pc = RN(ir);
nkeynes@27
  1025
                    return TRUE;
nkeynes@1
  1026
                case 0x2E: /* LDC     Rn, VBR */
nkeynes@1
  1027
                    CHECKPRIV();
nkeynes@1
  1028
                    sh4r.vbr = RN(ir);
nkeynes@1
  1029
                    break;
nkeynes@1
  1030
                case 0x32: /* STC.L   SGR, [--Rn] */
nkeynes@1
  1031
                    CHECKPRIV();
nkeynes@1
  1032
                    RN(ir) -= 4;
nkeynes@208
  1033
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1034
                    MEM_WRITE_LONG( RN(ir), sh4r.sgr );
nkeynes@1
  1035
                    break;
nkeynes@1
  1036
                case 0x33: /* STC.L   SSR, [--Rn] */
nkeynes@1
  1037
                    CHECKPRIV();
nkeynes@1
  1038
                    RN(ir) -= 4;
nkeynes@208
  1039
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1040
                    MEM_WRITE_LONG( RN(ir), sh4r.ssr );
nkeynes@1
  1041
                    break;
nkeynes@1
  1042
                case 0x37: /* LDC.L   [Rn++], SSR */
nkeynes@1
  1043
                    CHECKPRIV();
nkeynes@208
  1044
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1045
                    sh4r.ssr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1046
                    RN(ir) +=4;
nkeynes@1
  1047
                    break;
nkeynes@1
  1048
                case 0x3E: /* LDC     Rn, SSR */
nkeynes@1
  1049
                    CHECKPRIV();
nkeynes@1
  1050
                    sh4r.ssr = RN(ir);
nkeynes@1
  1051
                    break;
nkeynes@1
  1052
                case 0x43: /* STC.L   SPC, [--Rn] */
nkeynes@1
  1053
                    CHECKPRIV();
nkeynes@1
  1054
                    RN(ir) -= 4;
nkeynes@208
  1055
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1056
                    MEM_WRITE_LONG( RN(ir), sh4r.spc );
nkeynes@1
  1057
                    break;
nkeynes@1
  1058
                case 0x47: /* LDC.L   [Rn++], SPC */
nkeynes@1
  1059
                    CHECKPRIV();
nkeynes@208
  1060
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1061
                    sh4r.spc = MEM_READ_LONG(RN(ir));
nkeynes@1
  1062
                    RN(ir) +=4;
nkeynes@1
  1063
                    break;
nkeynes@1
  1064
                case 0x4E: /* LDC     Rn, SPC */
nkeynes@1
  1065
                    CHECKPRIV();
nkeynes@1
  1066
                    sh4r.spc = RN(ir);
nkeynes@1
  1067
                    break;
nkeynes@1
  1068
                case 0x52: /* STS.L   FPUL, [--Rn] */
nkeynes@1
  1069
                    RN(ir) -= 4;
nkeynes@208
  1070
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1071
                    MEM_WRITE_LONG( RN(ir), sh4r.fpul );
nkeynes@1
  1072
                    break;
nkeynes@1
  1073
                case 0x56: /* LDS.L   [Rn++], FPUL */
nkeynes@208
  1074
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1075
                    sh4r.fpul = MEM_READ_LONG(RN(ir));
nkeynes@1
  1076
                    RN(ir) +=4;
nkeynes@1
  1077
                    break;
nkeynes@1
  1078
                case 0x5A: /* LDS     Rn, FPUL */
nkeynes@1
  1079
                    sh4r.fpul = RN(ir);
nkeynes@1
  1080
                    break;
nkeynes@1
  1081
                case 0x62: /* STS.L   FPSCR, [--Rn] */
nkeynes@1
  1082
                    RN(ir) -= 4;
nkeynes@208
  1083
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1084
                    MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
nkeynes@1
  1085
                    break;
nkeynes@1
  1086
                case 0x66: /* LDS.L   [Rn++], FPSCR */
nkeynes@208
  1087
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1088
                    sh4r.fpscr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1089
                    RN(ir) +=4;
nkeynes@1
  1090
                    break;
nkeynes@1
  1091
                case 0x6A: /* LDS     Rn, FPSCR */
nkeynes@1
  1092
                    sh4r.fpscr = RN(ir);
nkeynes@1
  1093
                    break;
nkeynes@1
  1094
                case 0xF2: /* STC.L   DBR, [--Rn] */
nkeynes@1
  1095
                    CHECKPRIV();
nkeynes@1
  1096
                    RN(ir) -= 4;
nkeynes@208
  1097
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1098
                    MEM_WRITE_LONG( RN(ir), sh4r.dbr );
nkeynes@1
  1099
                    break;
nkeynes@1
  1100
                case 0xF6: /* LDC.L   [Rn++], DBR */
nkeynes@1
  1101
                    CHECKPRIV();
nkeynes@208
  1102
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1103
                    sh4r.dbr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1104
                    RN(ir) +=4;
nkeynes@1
  1105
                    break;
nkeynes@1
  1106
                case 0xFA: /* LDC     Rn, DBR */
nkeynes@1
  1107
                    CHECKPRIV();
nkeynes@1
  1108
                    sh4r.dbr = RN(ir);
nkeynes@1
  1109
                    break;
nkeynes@1
  1110
                case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
nkeynes@1
  1111
                case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
nkeynes@1
  1112
                    CHECKPRIV();
nkeynes@1
  1113
                    RN(ir) -= 4;
nkeynes@208
  1114
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1115
                    MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
nkeynes@1
  1116
                    break;
nkeynes@1
  1117
                case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
nkeynes@1
  1118
                case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
nkeynes@1
  1119
                    CHECKPRIV();
nkeynes@208
  1120
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1121
                    RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
nkeynes@1
  1122
                    RN(ir) += 4;
nkeynes@1
  1123
                    break;
nkeynes@1
  1124
                case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
nkeynes@1
  1125
                case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
nkeynes@1
  1126
                    CHECKPRIV();
nkeynes@1
  1127
                    RN_BANK(ir) = RM(ir);
nkeynes@1
  1128
                    break;
nkeynes@1
  1129
                default:
nkeynes@1
  1130
                    if( (ir&0x000F) == 0x0F ) {
nkeynes@1
  1131
                        /* MAC.W   [Rm++], [Rn++] */
nkeynes@208
  1132
			CHECKRALIGN16( RN(ir) );
nkeynes@208
  1133
			CHECKRALIGN16( RM(ir) );
nkeynes@1
  1134
                        tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
nkeynes@1
  1135
                            SIGNEXT16(MEM_READ_WORD(RN(ir)));
nkeynes@1
  1136
                        if( sh4r.s ) {
nkeynes@1
  1137
                            /* FIXME */
nkeynes@1
  1138
                            UNIMP(ir);
nkeynes@1
  1139
                        } else sh4r.mac += SIGNEXT32(tmp);
nkeynes@1
  1140
                        RM(ir) += 2;
nkeynes@1
  1141
                        RN(ir) += 2;
nkeynes@1
  1142
                    } else if( (ir&0x000F) == 0x0C ) {
nkeynes@1
  1143
                        /* SHAD    Rm, Rn */
nkeynes@1
  1144
                        tmp = RM(ir);
nkeynes@1
  1145
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@9
  1146
                        else if( (tmp & 0x1F) == 0 )  
nkeynes@9
  1147
			  RN(ir) = ((int32_t)RN(ir)) >> 31;
nkeynes@9
  1148
                        else 
nkeynes@9
  1149
			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
nkeynes@1
  1150
                    } else if( (ir&0x000F) == 0x0D ) {
nkeynes@1
  1151
                        /* SHLD    Rm, Rn */
nkeynes@1
  1152
                        tmp = RM(ir);
nkeynes@1
  1153
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@1
  1154
                        else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
nkeynes@1
  1155
                        else RN(ir) >>= (((~tmp) & 0x1F)+1);
nkeynes@1
  1156
                    } else UNDEF(ir);
nkeynes@1
  1157
            }
nkeynes@1
  1158
            break;
nkeynes@1
  1159
        case 5: /* 0101nnnnmmmmdddd */
nkeynes@1
  1160
            /* MOV.L   [Rm + disp4*4], Rn */
nkeynes@208
  1161
	    tmp = RM(ir) + (DISP4(ir)<<2);
nkeynes@208
  1162
	    CHECKRALIGN32( tmp );
nkeynes@208
  1163
            RN(ir) = MEM_READ_LONG( tmp );
nkeynes@1
  1164
            break;
nkeynes@1
  1165
        case 6: /* 0110xxxxxxxxxxxx */
nkeynes@1
  1166
            switch( ir&0x000f ) {
nkeynes@1
  1167
                case 0: /* MOV.B   [Rm], Rn */
nkeynes@1
  1168
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
  1169
                    break;
nkeynes@1
  1170
                case 1: /* MOV.W   [Rm], Rn */
nkeynes@208
  1171
		    CHECKRALIGN16( RM(ir) );
nkeynes@1
  1172
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
  1173
                    break;
nkeynes@1
  1174
                case 2: /* MOV.L   [Rm], Rn */
nkeynes@208
  1175
		    CHECKRALIGN32( RM(ir) );
nkeynes@1
  1176
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
  1177
                    break;
nkeynes@1
  1178
                case 3: /* MOV     Rm, Rn */
nkeynes@1
  1179
                    RN(ir) = RM(ir);
nkeynes@1
  1180
                    break;
nkeynes@1
  1181
                case 4: /* MOV.B   [Rm++], Rn */
nkeynes@1
  1182
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
  1183
                    RM(ir) ++;
nkeynes@1
  1184
                    break;
nkeynes@1
  1185
                case 5: /* MOV.W   [Rm++], Rn */
nkeynes@208
  1186
		    CHECKRALIGN16( RM(ir) );
nkeynes@1
  1187
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
  1188
                    RM(ir) += 2;
nkeynes@1
  1189
                    break;
nkeynes@1
  1190
                case 6: /* MOV.L   [Rm++], Rn */
nkeynes@208
  1191
		    CHECKRALIGN32( RM(ir) );
nkeynes@1
  1192
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
  1193
                    RM(ir) += 4;
nkeynes@1
  1194
                    break;
nkeynes@1
  1195
                case 7: /* NOT     Rm, Rn */
nkeynes@1
  1196
                    RN(ir) = ~RM(ir);
nkeynes@1
  1197
                    break;
nkeynes@1
  1198
                case 8: /* SWAP.B  Rm, Rn */
nkeynes@1
  1199
                    RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
nkeynes@1
  1200
                        ((RM(ir)&0x000000FF)<<8);
nkeynes@1
  1201
                    break;
nkeynes@1
  1202
                case 9: /* SWAP.W  Rm, Rn */
nkeynes@1
  1203
                    RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
nkeynes@1
  1204
                    break;
nkeynes@1
  1205
                case 10:/* NEGC    Rm, Rn */
nkeynes@1
  1206
                    tmp = 0 - RM(ir);
nkeynes@1
  1207
                    RN(ir) = tmp - sh4r.t;
nkeynes@1
  1208
                    sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
nkeynes@1
  1209
                    break;
nkeynes@1
  1210
                case 11:/* NEG     Rm, Rn */
nkeynes@1
  1211
                    RN(ir) = 0 - RM(ir);
nkeynes@1
  1212
                    break;
nkeynes@1
  1213
                case 12:/* EXTU.B  Rm, Rn */
nkeynes@1
  1214
                    RN(ir) = RM(ir)&0x000000FF;
nkeynes@1
  1215
                    break;
nkeynes@1
  1216
                case 13:/* EXTU.W  Rm, Rn */
nkeynes@1
  1217
                    RN(ir) = RM(ir)&0x0000FFFF;
nkeynes@1
  1218
                    break;
nkeynes@1
  1219
                case 14:/* EXTS.B  Rm, Rn */
nkeynes@1
  1220
                    RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
nkeynes@1
  1221
                    break;
nkeynes@1
  1222
                case 15:/* EXTS.W  Rm, Rn */
nkeynes@1
  1223
                    RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
nkeynes@1
  1224
                    break;
nkeynes@1
  1225
            }
nkeynes@1
  1226
            break;
nkeynes@1
  1227
        case 7: /* 0111nnnniiiiiiii */
nkeynes@1
  1228
            /* ADD    imm8, Rn */
nkeynes@1
  1229
            RN(ir) += IMM8(ir);
nkeynes@1
  1230
            break;
nkeynes@1
  1231
        case 8: /* 1000xxxxxxxxxxxx */
nkeynes@1
  1232
            switch( (ir&0x0F00) >> 8 ) {
nkeynes@1
  1233
                case 0: /* MOV.B   R0, [Rm + disp4] */
nkeynes@1
  1234
                    MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
nkeynes@1
  1235
                    break;
nkeynes@1
  1236
                case 1: /* MOV.W   R0, [Rm + disp4*2] */
nkeynes@208
  1237
		    tmp = RM(ir) + (DISP4(ir)<<1);
nkeynes@208
  1238
		    CHECKWALIGN16( tmp );
nkeynes@208
  1239
                    MEM_WRITE_WORD( tmp, R0 );
nkeynes@1
  1240
                    break;
nkeynes@1
  1241
                case 4: /* MOV.B   [Rm + disp4], R0 */
nkeynes@1
  1242
                    R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
nkeynes@1
  1243
                    break;
nkeynes@1
  1244
                case 5: /* MOV.W   [Rm + disp4*2], R0 */
nkeynes@208
  1245
		    tmp = RM(ir) + (DISP4(ir)<<1);
nkeynes@208
  1246
		    CHECKRALIGN16( tmp );
nkeynes@208
  1247
                    R0 = MEM_READ_WORD( tmp );
nkeynes@1
  1248
                    break;
nkeynes@1
  1249
                case 8: /* CMP/EQ  imm, R0 */
nkeynes@1
  1250
                    sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
nkeynes@1
  1251
                    break;
nkeynes@1
  1252
                case 9: /* BT      disp8 */
nkeynes@246
  1253
                    CHECKSLOTILLEGAL();
nkeynes@1
  1254
                    if( sh4r.t ) {
nkeynes@1
  1255
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1256
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1257
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1258
                        return TRUE;
nkeynes@1
  1259
                    }
nkeynes@1
  1260
                    break;
nkeynes@1
  1261
                case 11:/* BF      disp8 */
nkeynes@246
  1262
                    CHECKSLOTILLEGAL();
nkeynes@1
  1263
                    if( !sh4r.t ) {
nkeynes@1
  1264
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1265
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1266
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1267
                        return TRUE;
nkeynes@1
  1268
                    }
nkeynes@1
  1269
                    break;
nkeynes@1
  1270
                case 13:/* BT/S    disp8 */
nkeynes@246
  1271
                    CHECKSLOTILLEGAL();
nkeynes@1
  1272
                    if( sh4r.t ) {
nkeynes@1
  1273
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1274
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1275
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1276
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@2
  1277
                        sh4r.in_delay_slot = 1;
nkeynes@27
  1278
                        return TRUE;
nkeynes@1
  1279
                    }
nkeynes@1
  1280
                    break;
nkeynes@1
  1281
                case 15:/* BF/S    disp8 */
nkeynes@246
  1282
                    CHECKSLOTILLEGAL();
nkeynes@1
  1283
                    if( !sh4r.t ) {
nkeynes@1
  1284
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1285
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1286
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1287
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@27
  1288
                        return TRUE;
nkeynes@1
  1289
                    }
nkeynes@1
  1290
                    break;
nkeynes@1
  1291
                default: UNDEF(ir);
nkeynes@1
  1292
            }
nkeynes@1
  1293
            break;
nkeynes@1
  1294
        case 9: /* 1001xxxxxxxxxxxx */
nkeynes@1
  1295
            /* MOV.W   [disp8*2 + pc + 4], Rn */
nkeynes@232
  1296
	    CHECKSLOTILLEGAL();
nkeynes@208
  1297
	    tmp = pc + 4 + (DISP8(ir)<<1);
nkeynes@208
  1298
            RN(ir) = MEM_READ_WORD( tmp );
nkeynes@1
  1299
            break;
nkeynes@1
  1300
        case 10:/* 1010dddddddddddd */
nkeynes@1
  1301
            /* BRA     disp12 */
nkeynes@246
  1302
            CHECKSLOTILLEGAL();
nkeynes@246
  1303
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
nkeynes@2
  1304
            sh4r.in_delay_slot = 1;
nkeynes@1
  1305
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1306
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27
  1307
            return TRUE;
nkeynes@1
  1308
        case 11:/* 1011dddddddddddd */
nkeynes@1
  1309
            /* BSR     disp12 */
nkeynes@246
  1310
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
nkeynes@246
  1311
	    CHECKSLOTILLEGAL();
nkeynes@2
  1312
            sh4r.in_delay_slot = 1;
nkeynes@1
  1313
            sh4r.pr = pc + 4;
nkeynes@1
  1314
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1315
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@157
  1316
	    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
  1317
            return TRUE;
nkeynes@1
  1318
        case 12:/* 1100xxxxdddddddd */
nkeynes@1
  1319
        switch( (ir&0x0F00)>>8 ) {
nkeynes@1
  1320
                case 0: /* MOV.B  R0, [GBR + disp8] */
nkeynes@1
  1321
                    MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
nkeynes@1
  1322
                    break;
nkeynes@1
  1323
                case 1: /* MOV.W  R0, [GBR + disp8*2] */
nkeynes@208
  1324
		    tmp = sh4r.gbr + (DISP8(ir)<<1);
nkeynes@208
  1325
		    CHECKWALIGN16( tmp );
nkeynes@208
  1326
                    MEM_WRITE_WORD( tmp, R0 );
nkeynes@1
  1327
                    break;
nkeynes@1
  1328
                case  2: /*MOV.L   R0, [GBR + disp8*4] */
nkeynes@208
  1329
		    tmp = sh4r.gbr + (DISP8(ir)<<2);
nkeynes@208
  1330
		    CHECKWALIGN32( tmp );
nkeynes@208
  1331
                    MEM_WRITE_LONG( tmp, R0 );
nkeynes@1
  1332
                    break;
nkeynes@1
  1333
                case 3: /* TRAPA   imm8 */
nkeynes@246
  1334
                    CHECKSLOTILLEGAL();
nkeynes@116
  1335
                    MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
nkeynes@246
  1336
		    sh4r.pc += 2;
nkeynes@246
  1337
                    sh4_raise_exception( EXC_TRAP );
nkeynes@1
  1338
                    break;
nkeynes@1
  1339
                case 4: /* MOV.B   [GBR + disp8], R0 */
nkeynes@1
  1340
                    R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
nkeynes@1
  1341
                    break;
nkeynes@1
  1342
                case 5: /* MOV.W   [GBR + disp8*2], R0 */
nkeynes@208
  1343
		    tmp = sh4r.gbr + (DISP8(ir)<<1);
nkeynes@208
  1344
		    CHECKRALIGN16( tmp );
nkeynes@208
  1345
                    R0 = MEM_READ_WORD( tmp );
nkeynes@1
  1346
                    break;
nkeynes@1
  1347
                case 6: /* MOV.L   [GBR + disp8*4], R0 */
nkeynes@208
  1348
		    tmp = sh4r.gbr + (DISP8(ir)<<2);
nkeynes@208
  1349
		    CHECKRALIGN32( tmp );
nkeynes@208
  1350
                    R0 = MEM_READ_LONG( tmp );
nkeynes@1
  1351
                    break;
nkeynes@1
  1352
                case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
nkeynes@232
  1353
		    CHECKSLOTILLEGAL();
nkeynes@1
  1354
                    R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@1
  1355
                    break;
nkeynes@1
  1356
                case 8: /* TST     imm8, R0 */
nkeynes@1
  1357
                    sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
nkeynes@1
  1358
                    break;
nkeynes@1
  1359
                case 9: /* AND     imm8, R0 */
nkeynes@1
  1360
                    R0 &= UIMM8(ir);
nkeynes@1
  1361
                    break;
nkeynes@1
  1362
                case 10:/* XOR     imm8, R0 */
nkeynes@1
  1363
                    R0 ^= UIMM8(ir);
nkeynes@1
  1364
                    break;
nkeynes@1
  1365
                case 11:/* OR      imm8, R0 */
nkeynes@1
  1366
                    R0 |= UIMM8(ir);
nkeynes@1
  1367
                    break;
nkeynes@208
  1368
                case 12:/* TST.B   imm8, [R0+GBR] */		    
nkeynes@1
  1369
                    sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
nkeynes@1
  1370
                    break;
nkeynes@1
  1371
                case 13:/* AND.B   imm8, [R0+GBR] */
nkeynes@1
  1372
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1373
                                    UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1374
                    break;
nkeynes@1
  1375
                case 14:/* XOR.B   imm8, [R0+GBR] */
nkeynes@1
  1376
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1377
                                    UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1378
                    break;
nkeynes@1
  1379
                case 15:/* OR.B    imm8, [R0+GBR] */
nkeynes@1
  1380
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1381
                                    UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1382
                    break;
nkeynes@1
  1383
            }
nkeynes@1
  1384
            break;
nkeynes@1
  1385
        case 13:/* 1101nnnndddddddd */
nkeynes@1
  1386
            /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
nkeynes@232
  1387
	    CHECKSLOTILLEGAL();
nkeynes@208
  1388
	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@208
  1389
            RN(ir) = MEM_READ_LONG( tmp );
nkeynes@1
  1390
            break;
nkeynes@1
  1391
        case 14:/* 1110nnnniiiiiiii */
nkeynes@1
  1392
            /* MOV     imm8, Rn */
nkeynes@1
  1393
            RN(ir) = IMM8(ir);
nkeynes@1
  1394
            break;
nkeynes@1
  1395
        case 15:/* 1111xxxxxxxxxxxx */
nkeynes@1
  1396
            CHECKFPUEN();
nkeynes@84
  1397
	    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@84
  1398
		switch( ir&0x000F ) {
nkeynes@84
  1399
                case 0: /* FADD    FRm, FRn */
nkeynes@84
  1400
                    DRN(ir) += DRM(ir);
nkeynes@84
  1401
                    break;
nkeynes@84
  1402
                case 1: /* FSUB    FRm, FRn */
nkeynes@84
  1403
                    DRN(ir) -= DRM(ir);
nkeynes@84
  1404
                    break;
nkeynes@84
  1405
                case 2: /* FMUL    FRm, FRn */
nkeynes@84
  1406
                    DRN(ir) = DRN(ir) * DRM(ir);
nkeynes@84
  1407
                    break;
nkeynes@84
  1408
                case 3: /* FDIV    FRm, FRn */
nkeynes@84
  1409
                    DRN(ir) = DRN(ir) / DRM(ir);
nkeynes@84
  1410
                    break;
nkeynes@84
  1411
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@84
  1412
                    sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
nkeynes@84
  1413
                    break;
nkeynes@84
  1414
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@84
  1415
                    sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
nkeynes@84
  1416
                    break;
nkeynes@84
  1417
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@84
  1418
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@84
  1419
                    break;
nkeynes@84
  1420
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@84
  1421
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@84
  1422
                    break;
nkeynes@84
  1423
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@84
  1424
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1425
                    break;
nkeynes@84
  1426
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@84
  1427
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1428
                    RM(ir) += FP_WIDTH;
nkeynes@84
  1429
                    break;
nkeynes@84
  1430
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@84
  1431
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1432
                    break;
nkeynes@84
  1433
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@84
  1434
                    RN(ir) -= FP_WIDTH;
nkeynes@84
  1435
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1436
                    break;
nkeynes@84
  1437
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1438
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1439
			DRN(ir) = DRM(ir);
nkeynes@84
  1440
		    else
nkeynes@84
  1441
			FRN(ir) = FRM(ir);
nkeynes@84
  1442
                    break;
nkeynes@84
  1443
                case 13:
nkeynes@84
  1444
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1445
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1446
			FRN(ir) = FPULf;
nkeynes@84
  1447
			break;
nkeynes@84
  1448
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1449
			FPULf = FRN(ir);
nkeynes@84
  1450
			break;
nkeynes@84
  1451
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1452
			DRN(ir) = (float)FPULi;
nkeynes@84
  1453
			break;
nkeynes@84
  1454
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@123
  1455
			dtmp = DRN(ir);
nkeynes@123
  1456
			if( dtmp >= MAX_INTF )
nkeynes@123
  1457
			    FPULi = MAX_INT;
nkeynes@123
  1458
			else if( dtmp <= MIN_INTF )
nkeynes@123
  1459
			    FPULi = MIN_INT;
nkeynes@123
  1460
			else 
nkeynes@123
  1461
			    FPULi = (int32_t)dtmp;
nkeynes@84
  1462
			break;
nkeynes@84
  1463
		    case 4: /* FNEG    FRn */
nkeynes@84
  1464
			DRN(ir) = -DRN(ir);
nkeynes@84
  1465
			break;
nkeynes@84
  1466
		    case 5: /* FABS    FRn */
nkeynes@84
  1467
			DRN(ir) = fabs(DRN(ir));
nkeynes@84
  1468
			break;
nkeynes@84
  1469
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1470
			DRN(ir) = sqrt(DRN(ir));
nkeynes@84
  1471
			break;
nkeynes@84
  1472
		    case 7: /* FSRRA FRn */
nkeynes@181
  1473
			/* NO-OP when PR=1 */
nkeynes@84
  1474
			break;
nkeynes@84
  1475
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1476
			DRN(ir) = 0.0;
nkeynes@84
  1477
			break;
nkeynes@84
  1478
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1479
			DRN(ir) = 1.0;
nkeynes@84
  1480
			break;
nkeynes@84
  1481
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@181
  1482
			if( ! IS_FPU_DOUBLESIZE() )
nkeynes@181
  1483
			    DRN(ir) = (double)FPULf;
nkeynes@84
  1484
			break;
nkeynes@84
  1485
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@181
  1486
			if( ! IS_FPU_DOUBLESIZE() )
nkeynes@181
  1487
			    FPULf = (float)DRN(ir);
nkeynes@84
  1488
			break;
nkeynes@84
  1489
		    case 14:/* FIPR    FVm, FVn */
nkeynes@181
  1490
			/* NO-OP when PR=1 */
nkeynes@84
  1491
			break;
nkeynes@84
  1492
		    case 15:
nkeynes@84
  1493
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@181
  1494
			    /* NO-OP when PR=1 */
nkeynes@84
  1495
			    break;
nkeynes@84
  1496
			}
nkeynes@181
  1497
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
nkeynes@181
  1498
			    /* NO-OP when PR=1 */
nkeynes@84
  1499
			    break;
nkeynes@84
  1500
			}
nkeynes@84
  1501
			else if( ir == 0xFBFD ) {
nkeynes@84
  1502
			    /* FRCHG   */
nkeynes@84
  1503
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1504
			    break;
nkeynes@84
  1505
			}
nkeynes@84
  1506
			else if( ir == 0xF3FD ) {
nkeynes@84
  1507
			    /* FSCHG   */
nkeynes@84
  1508
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1509
			    break;
nkeynes@84
  1510
			}
nkeynes@84
  1511
		    default: UNDEF(ir);
nkeynes@84
  1512
                    }
nkeynes@84
  1513
                    break;
nkeynes@84
  1514
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@84
  1515
                    DRN(ir) += DRM(ir)*DR0;
nkeynes@84
  1516
                    break;
nkeynes@84
  1517
                default: UNDEF(ir);
nkeynes@84
  1518
		}
nkeynes@122
  1519
	    } else { /* Single precision */
nkeynes@84
  1520
		switch( ir&0x000F ) {
nkeynes@1
  1521
                case 0: /* FADD    FRm, FRn */
nkeynes@1
  1522
                    FRN(ir) += FRM(ir);
nkeynes@1
  1523
                    break;
nkeynes@1
  1524
                case 1: /* FSUB    FRm, FRn */
nkeynes@1
  1525
                    FRN(ir) -= FRM(ir);
nkeynes@1
  1526
                    break;
nkeynes@1
  1527
                case 2: /* FMUL    FRm, FRn */
nkeynes@1
  1528
                    FRN(ir) = FRN(ir) * FRM(ir);
nkeynes@1
  1529
                    break;
nkeynes@1
  1530
                case 3: /* FDIV    FRm, FRn */
nkeynes@1
  1531
                    FRN(ir) = FRN(ir) / FRM(ir);
nkeynes@1
  1532
                    break;
nkeynes@1
  1533
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@1
  1534
                    sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
nkeynes@1
  1535
                    break;
nkeynes@1
  1536
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@1
  1537
                    sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
nkeynes@1
  1538
                    break;
nkeynes@1
  1539
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@1
  1540
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@1
  1541
                    break;
nkeynes@1
  1542
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@1
  1543
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@1
  1544
                    break;
nkeynes@1
  1545
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@1
  1546
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1547
                    break;
nkeynes@1
  1548
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@1
  1549
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1550
                    RM(ir) += FP_WIDTH;
nkeynes@1
  1551
                    break;
nkeynes@1
  1552
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@1
  1553
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1554
                    break;
nkeynes@1
  1555
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@1
  1556
                    RN(ir) -= FP_WIDTH;
nkeynes@1
  1557
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1558
                    break;
nkeynes@1
  1559
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1560
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1561
			DRN(ir) = DRM(ir);
nkeynes@84
  1562
		    else
nkeynes@84
  1563
			FRN(ir) = FRM(ir);
nkeynes@1
  1564
                    break;
nkeynes@1
  1565
                case 13:
nkeynes@1
  1566
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1567
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1568
			FRN(ir) = FPULf;
nkeynes@84
  1569
			break;
nkeynes@84
  1570
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1571
			FPULf = FRN(ir);
nkeynes@84
  1572
			break;
nkeynes@84
  1573
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1574
			FRN(ir) = (float)FPULi;
nkeynes@84
  1575
			break;
nkeynes@84
  1576
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@123
  1577
			ftmp = FRN(ir);
nkeynes@123
  1578
			if( ftmp >= MAX_INTF )
nkeynes@123
  1579
			    FPULi = MAX_INT;
nkeynes@123
  1580
			else if( ftmp <= MIN_INTF )
nkeynes@123
  1581
			    FPULi = MIN_INT;
nkeynes@123
  1582
			else
nkeynes@123
  1583
			    FPULi = (int32_t)ftmp;
nkeynes@84
  1584
			break;
nkeynes@84
  1585
		    case 4: /* FNEG    FRn */
nkeynes@84
  1586
			FRN(ir) = -FRN(ir);
nkeynes@84
  1587
			break;
nkeynes@84
  1588
		    case 5: /* FABS    FRn */
nkeynes@84
  1589
			FRN(ir) = fabsf(FRN(ir));
nkeynes@84
  1590
			break;
nkeynes@84
  1591
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1592
			FRN(ir) = sqrtf(FRN(ir));
nkeynes@84
  1593
			break;
nkeynes@84
  1594
		    case 7: /* FSRRA FRn */
nkeynes@84
  1595
			FRN(ir) = 1.0/sqrtf(FRN(ir));
nkeynes@84
  1596
			break;
nkeynes@84
  1597
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1598
			FRN(ir) = 0.0;
nkeynes@84
  1599
			break;
nkeynes@84
  1600
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1601
			FRN(ir) = 1.0;
nkeynes@84
  1602
			break;
nkeynes@84
  1603
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@84
  1604
			break;
nkeynes@84
  1605
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@84
  1606
			break;
nkeynes@84
  1607
		    case 14:/* FIPR    FVm, FVn */
nkeynes@2
  1608
                            /* FIXME: This is not going to be entirely accurate
nkeynes@2
  1609
                             * as the SH4 instruction is less precise. Also
nkeynes@2
  1610
                             * need to check for 0s and infinities.
nkeynes@2
  1611
                             */
nkeynes@2
  1612
                        {
nkeynes@2
  1613
                            int tmp2 = FVN(ir);
nkeynes@2
  1614
                            tmp = FVM(ir);
nkeynes@84
  1615
                            FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@84
  1616
                                FR(tmp+1)*FR(tmp2+1) +
nkeynes@84
  1617
                                FR(tmp+2)*FR(tmp2+2) +
nkeynes@84
  1618
                                FR(tmp+3)*FR(tmp2+3);
nkeynes@1
  1619
                            break;
nkeynes@2
  1620
                        }
nkeynes@84
  1621
		    case 15:
nkeynes@84
  1622
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@84
  1623
			    tmp = FVN(ir);
nkeynes@84
  1624
			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
nkeynes@84
  1625
			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
nkeynes@84
  1626
				XF(8)*fv[2] + XF(12)*fv[3];
nkeynes@84
  1627
			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
nkeynes@84
  1628
				XF(9)*fv[2] + XF(13)*fv[3];
nkeynes@84
  1629
			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
nkeynes@84
  1630
				XF(10)*fv[2] + XF(14)*fv[3];
nkeynes@84
  1631
			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
nkeynes@84
  1632
				XF(11)*fv[2] + XF(15)*fv[3];
nkeynes@84
  1633
			    break;
nkeynes@84
  1634
			}
nkeynes@84
  1635
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
nkeynes@84
  1636
			    float angle = (((float)(short)(FPULi>>16)) +
nkeynes@122
  1637
					   (((float)(FPULi&0xFFFF))/65536.0)) *
nkeynes@84
  1638
				2 * M_PI;
nkeynes@84
  1639
			    int reg = FRNn(ir);
nkeynes@84
  1640
			    FR(reg) = sinf(angle);
nkeynes@84
  1641
			    FR(reg+1) = cosf(angle);
nkeynes@84
  1642
			    break;
nkeynes@84
  1643
			}
nkeynes@84
  1644
			else if( ir == 0xFBFD ) {
nkeynes@84
  1645
			    /* FRCHG   */
nkeynes@84
  1646
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1647
			    break;
nkeynes@84
  1648
			}
nkeynes@84
  1649
			else if( ir == 0xF3FD ) {
nkeynes@84
  1650
			    /* FSCHG   */
nkeynes@84
  1651
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1652
			    break;
nkeynes@84
  1653
			}
nkeynes@84
  1654
		    default: UNDEF(ir);
nkeynes@1
  1655
                    }
nkeynes@1
  1656
                    break;
nkeynes@1
  1657
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@1
  1658
                    FRN(ir) += FRM(ir)*FR0;
nkeynes@1
  1659
                    break;
nkeynes@1
  1660
                default: UNDEF(ir);
nkeynes@84
  1661
		}
nkeynes@84
  1662
	    }
nkeynes@84
  1663
	    break;
nkeynes@1
  1664
    }
nkeynes@1
  1665
    sh4r.pc = sh4r.new_pc;
nkeynes@1
  1666
    sh4r.new_pc += 2;
nkeynes@2
  1667
    sh4r.in_delay_slot = 0;
nkeynes@1
  1668
}
.