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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 991:60c7fab9c880
prev975:007bf7eb944f
next992:7c15f8a71995
author nkeynes
date Wed Mar 04 23:12:21 2009 +0000 (12 years ago)
permissions -rw-r--r--
last change Move xltcache to xlat/ src directory
Commit new and improved x86 opcode file - cleaned up and added support for amd64 extended registers
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T   REG_OFFSET(t)
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#define R_Q   REG_OFFSET(q)
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#define R_S   REG_OFFSET(s)
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#define R_M   REG_OFFSET(m)
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#define R_SR  REG_OFFSET(sr)
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#define R_GBR REG_OFFSET(gbr)
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#define R_SSR REG_OFFSET(ssr)
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#define R_SPC REG_OFFSET(spc)
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#define R_VBR REG_OFFSET(vbr)
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#define R_MACH REG_OFFSET(mac)+4
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#define R_MACL REG_OFFSET(mac)
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#define R_PC REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR REG_OFFSET(pr)
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#define R_SGR REG_OFFSET(sgr)
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#define R_FPUL REG_OFFSET(fpul)
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#define R_FPSCR REG_OFFSET(fpscr)
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#define R_DBR REG_OFFSET(dbr)
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg16s(x86reg,sh4reg)  MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define load_reg16u(x86reg,sh4reg)  MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define load_imm32(x86reg,value)    MOVL_imm32_r32(value,x86reg)
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#define load_imm64(x86reg,value)    MOVQ_imm64_r64(value,x86reg)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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#define load_spreg(x86reg, regoff)  MOVL_rbpdisp_r32( regoff, x86reg )
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#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_rbpdisp(R_FPUL)
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#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
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#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
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        } else { \
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            exit_block_exc(EXC_ILLEGAL, pc); \
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        } \
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        sh4_x86.branch_taken = TRUE; \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( REG_EAX, R_SR );\
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	ANDL_imms_r32( SR_FD, REG_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@991
   295
#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); }
nkeynes@953
   296
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@953
   297
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@953
   298
 */
nkeynes@953
   299
 
nkeynes@953
   300
#ifdef HAVE_FRAME_ADDRESS
nkeynes@953
   301
#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
nkeynes@991
   302
        call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
nkeynes@991
   303
        call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
nkeynes@953
   304
#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
nkeynes@991
   305
        call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
nkeynes@991
   306
        call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
nkeynes@953
   307
#else 
nkeynes@991
   308
#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg)
nkeynes@991
   309
#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
nkeynes@953
   310
#endif
nkeynes@953
   311
                
nkeynes@953
   312
#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
nkeynes@975
   313
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte_for_write); MEM_RESULT(value_reg)
nkeynes@953
   314
#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)
nkeynes@953
   315
#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)
nkeynes@953
   316
#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
nkeynes@953
   317
#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
nkeynes@953
   318
#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
nkeynes@953
   319
#define MEM_PREFETCH( addr_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, prefetch)
nkeynes@361
   320
nkeynes@956
   321
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   322
nkeynes@539
   323
/****** Import appropriate calling conventions ******/
nkeynes@675
   324
#if SIZEOF_VOID_P == 8
nkeynes@539
   325
#include "sh4/ia64abi.h"
nkeynes@675
   326
#else /* 32-bit system */
nkeynes@539
   327
#include "sh4/ia32abi.h"
nkeynes@539
   328
#endif
nkeynes@539
   329
nkeynes@901
   330
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   331
{
nkeynes@927
   332
    enter_block();
nkeynes@901
   333
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   334
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   335
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   336
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   337
    sh4_x86.block_start_pc = pc;
nkeynes@953
   338
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   340
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   341
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   342
}
nkeynes@901
   343
nkeynes@901
   344
nkeynes@593
   345
uint32_t sh4_translate_end_block_size()
nkeynes@593
   346
{
nkeynes@596
   347
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   348
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   349
    } else {
nkeynes@901
   350
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   351
    }
nkeynes@593
   352
}
nkeynes@593
   353
nkeynes@593
   354
nkeynes@590
   355
/**
nkeynes@590
   356
 * Embed a breakpoint into the generated code
nkeynes@590
   357
 */
nkeynes@586
   358
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   359
{
nkeynes@991
   360
    load_imm32( REG_EAX, pc );
nkeynes@991
   361
    call_func1( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   363
}
nkeynes@590
   364
nkeynes@601
   365
nkeynes@601
   366
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   367
nkeynes@590
   368
/**
nkeynes@590
   369
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   370
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   371
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   372
 *
nkeynes@601
   373
 * Performs:
nkeynes@601
   374
 *   Set PC = endpc
nkeynes@601
   375
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   376
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   377
 *   Call sh4_execute_instruction
nkeynes@601
   378
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   379
 */
nkeynes@601
   380
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   381
{
nkeynes@991
   382
    load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@991
   383
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   384
    
nkeynes@991
   385
    load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@991
   386
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@991
   387
    load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@991
   388
    store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   389
nkeynes@590
   390
    call_func0( sh4_execute_instruction );    
nkeynes@991
   391
    load_spreg( REG_EAX, R_PC );
nkeynes@590
   392
    if( sh4_x86.tlb_on ) {
nkeynes@991
   393
	call_func1(xlat_get_code_by_vma,REG_EAX);
nkeynes@590
   394
    } else {
nkeynes@991
   395
	call_func1(xlat_get_code,REG_EAX);
nkeynes@590
   396
    }
nkeynes@926
   397
    exit_block();
nkeynes@590
   398
} 
nkeynes@539
   399
nkeynes@359
   400
/**
nkeynes@359
   401
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   402
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   403
 * 
nkeynes@586
   404
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   405
 *
nkeynes@359
   406
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   407
 * (eg a branch or 
nkeynes@359
   408
 */
nkeynes@590
   409
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   410
{
nkeynes@388
   411
    uint32_t ir;
nkeynes@586
   412
    /* Read instruction from icache */
nkeynes@586
   413
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   414
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   415
    
nkeynes@586
   416
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   417
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   418
    }
nkeynes@359
   419
%%
nkeynes@359
   420
/* ALU operations */
nkeynes@359
   421
ADD Rm, Rn {:
nkeynes@671
   422
    COUNT_INST(I_ADD);
nkeynes@991
   423
    load_reg( REG_EAX, Rm );
nkeynes@991
   424
    load_reg( REG_ECX, Rn );
nkeynes@991
   425
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   426
    store_reg( REG_ECX, Rn );
nkeynes@417
   427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   428
:}
nkeynes@359
   429
ADD #imm, Rn {:  
nkeynes@671
   430
    COUNT_INST(I_ADDI);
nkeynes@991
   431
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   433
:}
nkeynes@359
   434
ADDC Rm, Rn {:
nkeynes@671
   435
    COUNT_INST(I_ADDC);
nkeynes@417
   436
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   437
        LDC_t();
nkeynes@417
   438
    }
nkeynes@991
   439
    load_reg( REG_EAX, Rm );
nkeynes@991
   440
    load_reg( REG_ECX, Rn );
nkeynes@991
   441
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   442
    store_reg( REG_ECX, Rn );
nkeynes@359
   443
    SETC_t();
nkeynes@417
   444
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   445
:}
nkeynes@359
   446
ADDV Rm, Rn {:
nkeynes@671
   447
    COUNT_INST(I_ADDV);
nkeynes@991
   448
    load_reg( REG_EAX, Rm );
nkeynes@991
   449
    load_reg( REG_ECX, Rn );
nkeynes@991
   450
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   451
    store_reg( REG_ECX, Rn );
nkeynes@359
   452
    SETO_t();
nkeynes@417
   453
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   454
:}
nkeynes@359
   455
AND Rm, Rn {:
nkeynes@671
   456
    COUNT_INST(I_AND);
nkeynes@991
   457
    load_reg( REG_EAX, Rm );
nkeynes@991
   458
    load_reg( REG_ECX, Rn );
nkeynes@991
   459
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   460
    store_reg( REG_ECX, Rn );
nkeynes@417
   461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   462
:}
nkeynes@359
   463
AND #imm, R0 {:  
nkeynes@671
   464
    COUNT_INST(I_ANDI);
nkeynes@991
   465
    load_reg( REG_EAX, 0 );
nkeynes@991
   466
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   467
    store_reg( REG_EAX, 0 );
nkeynes@417
   468
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   469
:}
nkeynes@359
   470
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   471
    COUNT_INST(I_ANDB);
nkeynes@991
   472
    load_reg( REG_EAX, 0 );
nkeynes@991
   473
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   474
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   475
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   476
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   477
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   478
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   480
:}
nkeynes@359
   481
CMP/EQ Rm, Rn {:  
nkeynes@671
   482
    COUNT_INST(I_CMPEQ);
nkeynes@991
   483
    load_reg( REG_EAX, Rm );
nkeynes@991
   484
    load_reg( REG_ECX, Rn );
nkeynes@991
   485
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   486
    SETE_t();
nkeynes@417
   487
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   488
:}
nkeynes@359
   489
CMP/EQ #imm, R0 {:  
nkeynes@671
   490
    COUNT_INST(I_CMPEQI);
nkeynes@991
   491
    load_reg( REG_EAX, 0 );
nkeynes@991
   492
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   493
    SETE_t();
nkeynes@417
   494
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   495
:}
nkeynes@359
   496
CMP/GE Rm, Rn {:  
nkeynes@671
   497
    COUNT_INST(I_CMPGE);
nkeynes@991
   498
    load_reg( REG_EAX, Rm );
nkeynes@991
   499
    load_reg( REG_ECX, Rn );
nkeynes@991
   500
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   501
    SETGE_t();
nkeynes@417
   502
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   503
:}
nkeynes@359
   504
CMP/GT Rm, Rn {: 
nkeynes@671
   505
    COUNT_INST(I_CMPGT);
nkeynes@991
   506
    load_reg( REG_EAX, Rm );
nkeynes@991
   507
    load_reg( REG_ECX, Rn );
nkeynes@991
   508
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   509
    SETG_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/HI Rm, Rn {:  
nkeynes@671
   513
    COUNT_INST(I_CMPHI);
nkeynes@991
   514
    load_reg( REG_EAX, Rm );
nkeynes@991
   515
    load_reg( REG_ECX, Rn );
nkeynes@991
   516
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   517
    SETA_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/HS Rm, Rn {: 
nkeynes@671
   521
    COUNT_INST(I_CMPHS);
nkeynes@991
   522
    load_reg( REG_EAX, Rm );
nkeynes@991
   523
    load_reg( REG_ECX, Rn );
nkeynes@991
   524
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   525
    SETAE_t();
nkeynes@417
   526
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   527
 :}
nkeynes@359
   528
CMP/PL Rn {: 
nkeynes@671
   529
    COUNT_INST(I_CMPPL);
nkeynes@991
   530
    load_reg( REG_EAX, Rn );
nkeynes@991
   531
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   532
    SETG_t();
nkeynes@417
   533
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   534
:}
nkeynes@359
   535
CMP/PZ Rn {:  
nkeynes@671
   536
    COUNT_INST(I_CMPPZ);
nkeynes@991
   537
    load_reg( REG_EAX, Rn );
nkeynes@991
   538
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   539
    SETGE_t();
nkeynes@417
   540
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   541
:}
nkeynes@361
   542
CMP/STR Rm, Rn {:  
nkeynes@671
   543
    COUNT_INST(I_CMPSTR);
nkeynes@991
   544
    load_reg( REG_EAX, Rm );
nkeynes@991
   545
    load_reg( REG_ECX, Rn );
nkeynes@991
   546
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   547
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   548
    JE_label(target1);
nkeynes@991
   549
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   550
    JE_label(target2);
nkeynes@991
   551
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   552
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   553
    JE_label(target3);
nkeynes@991
   554
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   555
    JMP_TARGET(target1);
nkeynes@380
   556
    JMP_TARGET(target2);
nkeynes@380
   557
    JMP_TARGET(target3);
nkeynes@368
   558
    SETE_t();
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   560
:}
nkeynes@361
   561
DIV0S Rm, Rn {:
nkeynes@671
   562
    COUNT_INST(I_DIV0S);
nkeynes@991
   563
    load_reg( REG_EAX, Rm );
nkeynes@991
   564
    load_reg( REG_ECX, Rn );
nkeynes@991
   565
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   566
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@991
   567
    store_spreg( REG_EAX, R_M );
nkeynes@991
   568
    store_spreg( REG_ECX, R_Q );
nkeynes@991
   569
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   570
    SETNE_t();
nkeynes@417
   571
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   572
:}
nkeynes@361
   573
DIV0U {:  
nkeynes@671
   574
    COUNT_INST(I_DIV0U);
nkeynes@991
   575
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
   576
    store_spreg( REG_EAX, R_Q );
nkeynes@991
   577
    store_spreg( REG_EAX, R_M );
nkeynes@991
   578
    store_spreg( REG_EAX, R_T );
nkeynes@417
   579
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   580
:}
nkeynes@386
   581
DIV1 Rm, Rn {:
nkeynes@671
   582
    COUNT_INST(I_DIV1);
nkeynes@991
   583
    load_spreg( REG_ECX, R_M );
nkeynes@991
   584
    load_reg( REG_EAX, Rn );
nkeynes@417
   585
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   586
	LDC_t();
nkeynes@417
   587
    }
nkeynes@991
   588
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   589
    SETC_r8( REG_DL ); // Q'
nkeynes@991
   590
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
   591
    JE_label(mqequal);
nkeynes@991
   592
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
   593
    JMP_label(end);
nkeynes@380
   594
    JMP_TARGET(mqequal);
nkeynes@991
   595
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
   596
    JMP_TARGET(end);
nkeynes@991
   597
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
   598
    SETC_r8(REG_AL); // tmp1
nkeynes@991
   599
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
   600
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@991
   601
    store_spreg( REG_ECX, R_Q );
nkeynes@991
   602
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
   603
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@991
   604
    store_spreg( REG_EAX, R_T );
nkeynes@417
   605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   606
:}
nkeynes@361
   607
DMULS.L Rm, Rn {:  
nkeynes@671
   608
    COUNT_INST(I_DMULS);
nkeynes@991
   609
    load_reg( REG_EAX, Rm );
nkeynes@991
   610
    load_reg( REG_ECX, Rn );
nkeynes@991
   611
    IMULL_r32(REG_ECX);
nkeynes@991
   612
    store_spreg( REG_EDX, R_MACH );
nkeynes@991
   613
    store_spreg( REG_EAX, R_MACL );
nkeynes@417
   614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   615
:}
nkeynes@361
   616
DMULU.L Rm, Rn {:  
nkeynes@671
   617
    COUNT_INST(I_DMULU);
nkeynes@991
   618
    load_reg( REG_EAX, Rm );
nkeynes@991
   619
    load_reg( REG_ECX, Rn );
nkeynes@991
   620
    MULL_r32(REG_ECX);
nkeynes@991
   621
    store_spreg( REG_EDX, R_MACH );
nkeynes@991
   622
    store_spreg( REG_EAX, R_MACL );    
nkeynes@417
   623
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   624
:}
nkeynes@359
   625
DT Rn {:  
nkeynes@671
   626
    COUNT_INST(I_DT);
nkeynes@991
   627
    load_reg( REG_EAX, Rn );
nkeynes@991
   628
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
   629
    store_reg( REG_EAX, Rn );
nkeynes@359
   630
    SETE_t();
nkeynes@417
   631
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   632
:}
nkeynes@359
   633
EXTS.B Rm, Rn {:  
nkeynes@671
   634
    COUNT_INST(I_EXTSB);
nkeynes@991
   635
    load_reg( REG_EAX, Rm );
nkeynes@991
   636
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   637
    store_reg( REG_EAX, Rn );
nkeynes@359
   638
:}
nkeynes@361
   639
EXTS.W Rm, Rn {:  
nkeynes@671
   640
    COUNT_INST(I_EXTSW);
nkeynes@991
   641
    load_reg( REG_EAX, Rm );
nkeynes@991
   642
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   643
    store_reg( REG_EAX, Rn );
nkeynes@361
   644
:}
nkeynes@361
   645
EXTU.B Rm, Rn {:  
nkeynes@671
   646
    COUNT_INST(I_EXTUB);
nkeynes@991
   647
    load_reg( REG_EAX, Rm );
nkeynes@991
   648
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   649
    store_reg( REG_EAX, Rn );
nkeynes@361
   650
:}
nkeynes@361
   651
EXTU.W Rm, Rn {:  
nkeynes@671
   652
    COUNT_INST(I_EXTUW);
nkeynes@991
   653
    load_reg( REG_EAX, Rm );
nkeynes@991
   654
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   655
    store_reg( REG_EAX, Rn );
nkeynes@361
   656
:}
nkeynes@586
   657
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   658
    COUNT_INST(I_MACL);
nkeynes@586
   659
    if( Rm == Rn ) {
nkeynes@991
   660
	load_reg( REG_EAX, Rm );
nkeynes@991
   661
	check_ralign32( REG_EAX );
nkeynes@991
   662
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   663
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   664
	load_reg( REG_EAX, Rm );
nkeynes@991
   665
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
   666
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   667
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   668
    } else {
nkeynes@991
   669
	load_reg( REG_EAX, Rm );
nkeynes@991
   670
	check_ralign32( REG_EAX );
nkeynes@991
   671
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   672
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   673
	load_reg( REG_EAX, Rn );
nkeynes@991
   674
	check_ralign32( REG_EAX );
nkeynes@991
   675
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   676
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
   677
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   678
    }
nkeynes@953
   679
    
nkeynes@991
   680
    IMULL_rspdisp( 0 );
nkeynes@991
   681
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
   682
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
   683
nkeynes@991
   684
    load_spreg( REG_ECX, R_S );
nkeynes@991
   685
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
   686
    JE_label( nosat );
nkeynes@386
   687
    call_func0( signsat48 );
nkeynes@386
   688
    JMP_TARGET( nosat );
nkeynes@417
   689
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   690
:}
nkeynes@386
   691
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   692
    COUNT_INST(I_MACW);
nkeynes@586
   693
    if( Rm == Rn ) {
nkeynes@991
   694
	load_reg( REG_EAX, Rm );
nkeynes@991
   695
	check_ralign16( REG_EAX );
nkeynes@991
   696
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   697
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   698
	load_reg( REG_EAX, Rm );
nkeynes@991
   699
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
   700
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   701
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   702
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   703
	// adding a page-boundary check to skip the second translation
nkeynes@586
   704
    } else {
nkeynes@991
   705
	load_reg( REG_EAX, Rm );
nkeynes@991
   706
	check_ralign16( REG_EAX );
nkeynes@991
   707
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   708
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   709
	load_reg( REG_EAX, Rn );
nkeynes@991
   710
	check_ralign16( REG_EAX );
nkeynes@991
   711
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   712
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
   713
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   714
    }
nkeynes@991
   715
    IMULL_rspdisp( 0 );
nkeynes@991
   716
    load_spreg( REG_ECX, R_S );
nkeynes@991
   717
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
   718
    JE_label( nosat );
nkeynes@386
   719
nkeynes@991
   720
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   721
    JNO_label( end );            // 2
nkeynes@991
   722
    load_imm32( REG_EDX, 1 );         // 5
nkeynes@991
   723
    store_spreg( REG_EDX, R_MACH );   // 6
nkeynes@991
   724
    JS_label( positive );        // 2
nkeynes@991
   725
    load_imm32( REG_EAX, 0x80000000 );// 5
nkeynes@991
   726
    store_spreg( REG_EAX, R_MACL );   // 6
nkeynes@991
   727
    JMP_label(end2);           // 2
nkeynes@386
   728
nkeynes@386
   729
    JMP_TARGET(positive);
nkeynes@991
   730
    load_imm32( REG_EAX, 0x7FFFFFFF );// 5
nkeynes@991
   731
    store_spreg( REG_EAX, R_MACL );   // 6
nkeynes@991
   732
    JMP_label(end3);            // 2
nkeynes@386
   733
nkeynes@386
   734
    JMP_TARGET(nosat);
nkeynes@991
   735
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   736
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
   737
    JMP_TARGET(end);
nkeynes@386
   738
    JMP_TARGET(end2);
nkeynes@386
   739
    JMP_TARGET(end3);
nkeynes@417
   740
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   741
:}
nkeynes@359
   742
MOVT Rn {:  
nkeynes@671
   743
    COUNT_INST(I_MOVT);
nkeynes@991
   744
    load_spreg( REG_EAX, R_T );
nkeynes@991
   745
    store_reg( REG_EAX, Rn );
nkeynes@359
   746
:}
nkeynes@361
   747
MUL.L Rm, Rn {:  
nkeynes@671
   748
    COUNT_INST(I_MULL);
nkeynes@991
   749
    load_reg( REG_EAX, Rm );
nkeynes@991
   750
    load_reg( REG_ECX, Rn );
nkeynes@991
   751
    MULL_r32( REG_ECX );
nkeynes@991
   752
    store_spreg( REG_EAX, R_MACL );
nkeynes@417
   753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   754
:}
nkeynes@374
   755
MULS.W Rm, Rn {:
nkeynes@671
   756
    COUNT_INST(I_MULSW);
nkeynes@991
   757
    load_reg16s( REG_EAX, Rm );
nkeynes@991
   758
    load_reg16s( REG_ECX, Rn );
nkeynes@991
   759
    MULL_r32( REG_ECX );
nkeynes@991
   760
    store_spreg( REG_EAX, R_MACL );
nkeynes@417
   761
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   762
:}
nkeynes@374
   763
MULU.W Rm, Rn {:  
nkeynes@671
   764
    COUNT_INST(I_MULUW);
nkeynes@991
   765
    load_reg16u( REG_EAX, Rm );
nkeynes@991
   766
    load_reg16u( REG_ECX, Rn );
nkeynes@991
   767
    MULL_r32( REG_ECX );
nkeynes@991
   768
    store_spreg( REG_EAX, R_MACL );
nkeynes@417
   769
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   770
:}
nkeynes@359
   771
NEG Rm, Rn {:
nkeynes@671
   772
    COUNT_INST(I_NEG);
nkeynes@991
   773
    load_reg( REG_EAX, Rm );
nkeynes@991
   774
    NEGL_r32( REG_EAX );
nkeynes@991
   775
    store_reg( REG_EAX, Rn );
nkeynes@417
   776
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   777
:}
nkeynes@359
   778
NEGC Rm, Rn {:  
nkeynes@671
   779
    COUNT_INST(I_NEGC);
nkeynes@991
   780
    load_reg( REG_EAX, Rm );
nkeynes@991
   781
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
   782
    LDC_t();
nkeynes@991
   783
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   784
    store_reg( REG_ECX, Rn );
nkeynes@359
   785
    SETC_t();
nkeynes@417
   786
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   787
:}
nkeynes@359
   788
NOT Rm, Rn {:  
nkeynes@671
   789
    COUNT_INST(I_NOT);
nkeynes@991
   790
    load_reg( REG_EAX, Rm );
nkeynes@991
   791
    NOTL_r32( REG_EAX );
nkeynes@991
   792
    store_reg( REG_EAX, Rn );
nkeynes@417
   793
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   794
:}
nkeynes@359
   795
OR Rm, Rn {:  
nkeynes@671
   796
    COUNT_INST(I_OR);
nkeynes@991
   797
    load_reg( REG_EAX, Rm );
nkeynes@991
   798
    load_reg( REG_ECX, Rn );
nkeynes@991
   799
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   800
    store_reg( REG_ECX, Rn );
nkeynes@417
   801
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   802
:}
nkeynes@359
   803
OR #imm, R0 {:
nkeynes@671
   804
    COUNT_INST(I_ORI);
nkeynes@991
   805
    load_reg( REG_EAX, 0 );
nkeynes@991
   806
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
   807
    store_reg( REG_EAX, 0 );
nkeynes@417
   808
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   809
:}
nkeynes@374
   810
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   811
    COUNT_INST(I_ORB);
nkeynes@991
   812
    load_reg( REG_EAX, 0 );
nkeynes@991
   813
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   814
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   815
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   816
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
   817
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
   818
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   819
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   820
:}
nkeynes@359
   821
ROTCL Rn {:
nkeynes@671
   822
    COUNT_INST(I_ROTCL);
nkeynes@991
   823
    load_reg( REG_EAX, Rn );
nkeynes@417
   824
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   825
	LDC_t();
nkeynes@417
   826
    }
nkeynes@991
   827
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   828
    store_reg( REG_EAX, Rn );
nkeynes@359
   829
    SETC_t();
nkeynes@417
   830
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   831
:}
nkeynes@359
   832
ROTCR Rn {:  
nkeynes@671
   833
    COUNT_INST(I_ROTCR);
nkeynes@991
   834
    load_reg( REG_EAX, Rn );
nkeynes@417
   835
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   836
	LDC_t();
nkeynes@417
   837
    }
nkeynes@991
   838
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
   839
    store_reg( REG_EAX, Rn );
nkeynes@359
   840
    SETC_t();
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   842
:}
nkeynes@359
   843
ROTL Rn {:  
nkeynes@671
   844
    COUNT_INST(I_ROTL);
nkeynes@991
   845
    load_reg( REG_EAX, Rn );
nkeynes@991
   846
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
   847
    store_reg( REG_EAX, Rn );
nkeynes@359
   848
    SETC_t();
nkeynes@417
   849
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   850
:}
nkeynes@359
   851
ROTR Rn {:  
nkeynes@671
   852
    COUNT_INST(I_ROTR);
nkeynes@991
   853
    load_reg( REG_EAX, Rn );
nkeynes@991
   854
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
   855
    store_reg( REG_EAX, Rn );
nkeynes@359
   856
    SETC_t();
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   858
:}
nkeynes@359
   859
SHAD Rm, Rn {:
nkeynes@671
   860
    COUNT_INST(I_SHAD);
nkeynes@359
   861
    /* Annoyingly enough, not directly convertible */
nkeynes@991
   862
    load_reg( REG_EAX, Rn );
nkeynes@991
   863
    load_reg( REG_ECX, Rm );
nkeynes@991
   864
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
   865
    JGE_label(doshl);
nkeynes@361
   866
                    
nkeynes@991
   867
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
   868
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
   869
    JE_label(emptysar);     // 2
nkeynes@991
   870
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
   871
    JMP_label(end);          // 2
nkeynes@386
   872
nkeynes@386
   873
    JMP_TARGET(emptysar);
nkeynes@991
   874
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
   875
    JMP_label(end2);
nkeynes@382
   876
nkeynes@380
   877
    JMP_TARGET(doshl);
nkeynes@991
   878
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
   879
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
   880
    JMP_TARGET(end);
nkeynes@386
   881
    JMP_TARGET(end2);
nkeynes@991
   882
    store_reg( REG_EAX, Rn );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@359
   885
SHLD Rm, Rn {:  
nkeynes@671
   886
    COUNT_INST(I_SHLD);
nkeynes@991
   887
    load_reg( REG_EAX, Rn );
nkeynes@991
   888
    load_reg( REG_ECX, Rm );
nkeynes@991
   889
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
   890
    JGE_label(doshl);
nkeynes@368
   891
nkeynes@991
   892
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
   893
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
   894
    JE_label(emptyshr );
nkeynes@991
   895
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
   896
    JMP_label(end);          // 2
nkeynes@386
   897
nkeynes@386
   898
    JMP_TARGET(emptyshr);
nkeynes@991
   899
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
   900
    JMP_label(end2);
nkeynes@382
   901
nkeynes@382
   902
    JMP_TARGET(doshl);
nkeynes@991
   903
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
   904
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
   905
    JMP_TARGET(end);
nkeynes@386
   906
    JMP_TARGET(end2);
nkeynes@991
   907
    store_reg( REG_EAX, Rn );
nkeynes@417
   908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   909
:}
nkeynes@359
   910
SHAL Rn {: 
nkeynes@671
   911
    COUNT_INST(I_SHAL);
nkeynes@991
   912
    load_reg( REG_EAX, Rn );
nkeynes@991
   913
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
   914
    SETC_t();
nkeynes@991
   915
    store_reg( REG_EAX, Rn );
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   917
:}
nkeynes@359
   918
SHAR Rn {:  
nkeynes@671
   919
    COUNT_INST(I_SHAR);
nkeynes@991
   920
    load_reg( REG_EAX, Rn );
nkeynes@991
   921
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
   922
    SETC_t();
nkeynes@991
   923
    store_reg( REG_EAX, Rn );
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   925
:}
nkeynes@359
   926
SHLL Rn {:  
nkeynes@671
   927
    COUNT_INST(I_SHLL);
nkeynes@991
   928
    load_reg( REG_EAX, Rn );
nkeynes@991
   929
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
   930
    SETC_t();
nkeynes@991
   931
    store_reg( REG_EAX, Rn );
nkeynes@417
   932
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   933
:}
nkeynes@359
   934
SHLL2 Rn {:
nkeynes@671
   935
    COUNT_INST(I_SHLL);
nkeynes@991
   936
    load_reg( REG_EAX, Rn );
nkeynes@991
   937
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
   938
    store_reg( REG_EAX, Rn );
nkeynes@417
   939
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   940
:}
nkeynes@359
   941
SHLL8 Rn {:  
nkeynes@671
   942
    COUNT_INST(I_SHLL);
nkeynes@991
   943
    load_reg( REG_EAX, Rn );
nkeynes@991
   944
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
   945
    store_reg( REG_EAX, Rn );
nkeynes@417
   946
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   947
:}
nkeynes@359
   948
SHLL16 Rn {:  
nkeynes@671
   949
    COUNT_INST(I_SHLL);
nkeynes@991
   950
    load_reg( REG_EAX, Rn );
nkeynes@991
   951
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
   952
    store_reg( REG_EAX, Rn );
nkeynes@417
   953
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   954
:}
nkeynes@359
   955
SHLR Rn {:  
nkeynes@671
   956
    COUNT_INST(I_SHLR);
nkeynes@991
   957
    load_reg( REG_EAX, Rn );
nkeynes@991
   958
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
   959
    SETC_t();
nkeynes@991
   960
    store_reg( REG_EAX, Rn );
nkeynes@417
   961
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   962
:}
nkeynes@359
   963
SHLR2 Rn {:  
nkeynes@671
   964
    COUNT_INST(I_SHLR);
nkeynes@991
   965
    load_reg( REG_EAX, Rn );
nkeynes@991
   966
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
   967
    store_reg( REG_EAX, Rn );
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   969
:}
nkeynes@359
   970
SHLR8 Rn {:  
nkeynes@671
   971
    COUNT_INST(I_SHLR);
nkeynes@991
   972
    load_reg( REG_EAX, Rn );
nkeynes@991
   973
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
   974
    store_reg( REG_EAX, Rn );
nkeynes@417
   975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   976
:}
nkeynes@359
   977
SHLR16 Rn {:  
nkeynes@671
   978
    COUNT_INST(I_SHLR);
nkeynes@991
   979
    load_reg( REG_EAX, Rn );
nkeynes@991
   980
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   981
    store_reg( REG_EAX, Rn );
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   983
:}
nkeynes@359
   984
SUB Rm, Rn {:  
nkeynes@671
   985
    COUNT_INST(I_SUB);
nkeynes@991
   986
    load_reg( REG_EAX, Rm );
nkeynes@991
   987
    load_reg( REG_ECX, Rn );
nkeynes@991
   988
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   989
    store_reg( REG_ECX, Rn );
nkeynes@417
   990
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   991
:}
nkeynes@359
   992
SUBC Rm, Rn {:  
nkeynes@671
   993
    COUNT_INST(I_SUBC);
nkeynes@991
   994
    load_reg( REG_EAX, Rm );
nkeynes@991
   995
    load_reg( REG_ECX, Rn );
nkeynes@417
   996
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   997
	LDC_t();
nkeynes@417
   998
    }
nkeynes@991
   999
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1000
    store_reg( REG_ECX, Rn );
nkeynes@394
  1001
    SETC_t();
nkeynes@417
  1002
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1003
:}
nkeynes@359
  1004
SUBV Rm, Rn {:  
nkeynes@671
  1005
    COUNT_INST(I_SUBV);
nkeynes@991
  1006
    load_reg( REG_EAX, Rm );
nkeynes@991
  1007
    load_reg( REG_ECX, Rn );
nkeynes@991
  1008
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1009
    store_reg( REG_ECX, Rn );
nkeynes@359
  1010
    SETO_t();
nkeynes@417
  1011
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1012
:}
nkeynes@359
  1013
SWAP.B Rm, Rn {:  
nkeynes@671
  1014
    COUNT_INST(I_SWAPB);
nkeynes@991
  1015
    load_reg( REG_EAX, Rm );
nkeynes@991
  1016
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1017
    store_reg( REG_EAX, Rn );
nkeynes@359
  1018
:}
nkeynes@359
  1019
SWAP.W Rm, Rn {:  
nkeynes@671
  1020
    COUNT_INST(I_SWAPB);
nkeynes@991
  1021
    load_reg( REG_EAX, Rm );
nkeynes@991
  1022
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1023
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1024
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1025
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1026
    store_reg( REG_ECX, Rn );
nkeynes@417
  1027
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1028
:}
nkeynes@361
  1029
TAS.B @Rn {:  
nkeynes@671
  1030
    COUNT_INST(I_TASB);
nkeynes@991
  1031
    load_reg( REG_EAX, Rn );
nkeynes@991
  1032
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1033
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1034
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1035
    SETE_t();
nkeynes@991
  1036
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1037
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1038
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1039
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1040
:}
nkeynes@361
  1041
TST Rm, Rn {:  
nkeynes@671
  1042
    COUNT_INST(I_TST);
nkeynes@991
  1043
    load_reg( REG_EAX, Rm );
nkeynes@991
  1044
    load_reg( REG_ECX, Rn );
nkeynes@991
  1045
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1046
    SETE_t();
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1048
:}
nkeynes@368
  1049
TST #imm, R0 {:  
nkeynes@671
  1050
    COUNT_INST(I_TSTI);
nkeynes@991
  1051
    load_reg( REG_EAX, 0 );
nkeynes@991
  1052
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1053
    SETE_t();
nkeynes@417
  1054
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1055
:}
nkeynes@368
  1056
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1057
    COUNT_INST(I_TSTB);
nkeynes@991
  1058
    load_reg( REG_EAX, 0);
nkeynes@991
  1059
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1060
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1061
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1062
    SETE_t();
nkeynes@417
  1063
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1064
:}
nkeynes@359
  1065
XOR Rm, Rn {:  
nkeynes@671
  1066
    COUNT_INST(I_XOR);
nkeynes@991
  1067
    load_reg( REG_EAX, Rm );
nkeynes@991
  1068
    load_reg( REG_ECX, Rn );
nkeynes@991
  1069
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1070
    store_reg( REG_ECX, Rn );
nkeynes@417
  1071
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1072
:}
nkeynes@359
  1073
XOR #imm, R0 {:  
nkeynes@671
  1074
    COUNT_INST(I_XORI);
nkeynes@991
  1075
    load_reg( REG_EAX, 0 );
nkeynes@991
  1076
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1077
    store_reg( REG_EAX, 0 );
nkeynes@417
  1078
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1079
:}
nkeynes@359
  1080
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1081
    COUNT_INST(I_XORB);
nkeynes@991
  1082
    load_reg( REG_EAX, 0 );
nkeynes@991
  1083
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1084
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1085
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1086
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1087
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1088
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1090
:}
nkeynes@361
  1091
XTRCT Rm, Rn {:
nkeynes@671
  1092
    COUNT_INST(I_XTRCT);
nkeynes@991
  1093
    load_reg( REG_EAX, Rm );
nkeynes@991
  1094
    load_reg( REG_ECX, Rn );
nkeynes@991
  1095
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1096
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1097
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1098
    store_reg( REG_ECX, Rn );
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1100
:}
nkeynes@359
  1101
nkeynes@359
  1102
/* Data move instructions */
nkeynes@359
  1103
MOV Rm, Rn {:  
nkeynes@671
  1104
    COUNT_INST(I_MOV);
nkeynes@991
  1105
    load_reg( REG_EAX, Rm );
nkeynes@991
  1106
    store_reg( REG_EAX, Rn );
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV #imm, Rn {:  
nkeynes@671
  1109
    COUNT_INST(I_MOVI);
nkeynes@991
  1110
    load_imm32( REG_EAX, imm );
nkeynes@991
  1111
    store_reg( REG_EAX, Rn );
nkeynes@359
  1112
:}
nkeynes@359
  1113
MOV.B Rm, @Rn {:  
nkeynes@671
  1114
    COUNT_INST(I_MOVB);
nkeynes@991
  1115
    load_reg( REG_EAX, Rn );
nkeynes@991
  1116
    load_reg( REG_EDX, Rm );
nkeynes@991
  1117
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1118
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1119
:}
nkeynes@359
  1120
MOV.B Rm, @-Rn {:  
nkeynes@671
  1121
    COUNT_INST(I_MOVB);
nkeynes@991
  1122
    load_reg( REG_EAX, Rn );
nkeynes@991
  1123
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1124
    load_reg( REG_EDX, Rm );
nkeynes@991
  1125
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1126
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1127
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1128
:}
nkeynes@359
  1129
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1130
    COUNT_INST(I_MOVB);
nkeynes@991
  1131
    load_reg( REG_EAX, 0 );
nkeynes@991
  1132
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1133
    load_reg( REG_EDX, Rm );
nkeynes@991
  1134
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1136
:}
nkeynes@359
  1137
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1138
    COUNT_INST(I_MOVB);
nkeynes@991
  1139
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1140
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1141
    load_reg( REG_EDX, 0 );
nkeynes@991
  1142
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1143
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1144
:}
nkeynes@359
  1145
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1146
    COUNT_INST(I_MOVB);
nkeynes@991
  1147
    load_reg( REG_EAX, Rn );
nkeynes@991
  1148
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1149
    load_reg( REG_EDX, 0 );
nkeynes@991
  1150
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1151
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1152
:}
nkeynes@359
  1153
MOV.B @Rm, Rn {:  
nkeynes@671
  1154
    COUNT_INST(I_MOVB);
nkeynes@991
  1155
    load_reg( REG_EAX, Rm );
nkeynes@991
  1156
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1157
    store_reg( REG_EAX, Rn );
nkeynes@417
  1158
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1159
:}
nkeynes@359
  1160
MOV.B @Rm+, Rn {:  
nkeynes@671
  1161
    COUNT_INST(I_MOVB);
nkeynes@991
  1162
    load_reg( REG_EAX, Rm );
nkeynes@991
  1163
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@953
  1164
    if( Rm != Rn ) {
nkeynes@991
  1165
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@953
  1166
    }
nkeynes@991
  1167
    store_reg( REG_EAX, Rn );
nkeynes@417
  1168
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1169
:}
nkeynes@359
  1170
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1171
    COUNT_INST(I_MOVB);
nkeynes@991
  1172
    load_reg( REG_EAX, 0 );
nkeynes@991
  1173
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1174
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1175
    store_reg( REG_EAX, Rn );
nkeynes@417
  1176
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1177
:}
nkeynes@359
  1178
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1179
    COUNT_INST(I_MOVB);
nkeynes@991
  1180
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1181
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1182
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1183
    store_reg( REG_EAX, 0 );
nkeynes@417
  1184
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1185
:}
nkeynes@359
  1186
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1187
    COUNT_INST(I_MOVB);
nkeynes@991
  1188
    load_reg( REG_EAX, Rm );
nkeynes@991
  1189
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1190
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1191
    store_reg( REG_EAX, 0 );
nkeynes@417
  1192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1193
:}
nkeynes@374
  1194
MOV.L Rm, @Rn {:
nkeynes@671
  1195
    COUNT_INST(I_MOVL);
nkeynes@991
  1196
    load_reg( REG_EAX, Rn );
nkeynes@991
  1197
    check_walign32(REG_EAX);
nkeynes@991
  1198
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1199
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1200
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1201
    JNE_label( notsq );
nkeynes@991
  1202
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1203
    load_reg( REG_EDX, Rm );
nkeynes@991
  1204
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1205
    JMP_label(end);
nkeynes@953
  1206
    JMP_TARGET(notsq);
nkeynes@991
  1207
    load_reg( REG_EDX, Rm );
nkeynes@991
  1208
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1209
    JMP_TARGET(end);
nkeynes@417
  1210
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1211
:}
nkeynes@361
  1212
MOV.L Rm, @-Rn {:  
nkeynes@671
  1213
    COUNT_INST(I_MOVL);
nkeynes@991
  1214
    load_reg( REG_EAX, Rn );
nkeynes@991
  1215
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1216
    check_walign32( REG_EAX );
nkeynes@991
  1217
    load_reg( REG_EDX, Rm );
nkeynes@991
  1218
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1219
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1220
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1221
:}
nkeynes@361
  1222
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1223
    COUNT_INST(I_MOVL);
nkeynes@991
  1224
    load_reg( REG_EAX, 0 );
nkeynes@991
  1225
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1226
    check_walign32( REG_EAX );
nkeynes@991
  1227
    load_reg( REG_EDX, Rm );
nkeynes@991
  1228
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1229
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1230
:}
nkeynes@361
  1231
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1232
    COUNT_INST(I_MOVL);
nkeynes@991
  1233
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1234
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1235
    check_walign32( REG_EAX );
nkeynes@991
  1236
    load_reg( REG_EDX, 0 );
nkeynes@991
  1237
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1238
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1239
:}
nkeynes@361
  1240
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1241
    COUNT_INST(I_MOVL);
nkeynes@991
  1242
    load_reg( REG_EAX, Rn );
nkeynes@991
  1243
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1244
    check_walign32( REG_EAX );
nkeynes@991
  1245
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1246
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1247
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1248
    JNE_label( notsq );
nkeynes@991
  1249
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1250
    load_reg( REG_EDX, Rm );
nkeynes@991
  1251
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1252
    JMP_label(end);
nkeynes@953
  1253
    JMP_TARGET(notsq);
nkeynes@991
  1254
    load_reg( REG_EDX, Rm );
nkeynes@991
  1255
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1256
    JMP_TARGET(end);
nkeynes@417
  1257
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1258
:}
nkeynes@361
  1259
MOV.L @Rm, Rn {:  
nkeynes@671
  1260
    COUNT_INST(I_MOVL);
nkeynes@991
  1261
    load_reg( REG_EAX, Rm );
nkeynes@991
  1262
    check_ralign32( REG_EAX );
nkeynes@991
  1263
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1264
    store_reg( REG_EAX, Rn );
nkeynes@417
  1265
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1266
:}
nkeynes@361
  1267
MOV.L @Rm+, Rn {:  
nkeynes@671
  1268
    COUNT_INST(I_MOVL);
nkeynes@991
  1269
    load_reg( REG_EAX, Rm );
nkeynes@991
  1270
    check_ralign32( REG_EAX );
nkeynes@991
  1271
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@953
  1272
    if( Rm != Rn ) {
nkeynes@991
  1273
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@953
  1274
    }
nkeynes@991
  1275
    store_reg( REG_EAX, Rn );
nkeynes@417
  1276
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1277
:}
nkeynes@361
  1278
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1279
    COUNT_INST(I_MOVL);
nkeynes@991
  1280
    load_reg( REG_EAX, 0 );
nkeynes@991
  1281
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1282
    check_ralign32( REG_EAX );
nkeynes@991
  1283
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1284
    store_reg( REG_EAX, Rn );
nkeynes@417
  1285
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1286
:}
nkeynes@361
  1287
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1288
    COUNT_INST(I_MOVL);
nkeynes@991
  1289
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1290
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1291
    check_ralign32( REG_EAX );
nkeynes@991
  1292
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1293
    store_reg( REG_EAX, 0 );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1295
:}
nkeynes@361
  1296
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1297
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1298
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1299
	SLOTILLEGAL();
nkeynes@374
  1300
    } else {
nkeynes@388
  1301
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1302
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1303
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1304
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1305
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1306
nkeynes@586
  1307
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1308
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1309
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1310
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1311
	    // behaviour though.
nkeynes@586
  1312
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1313
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1314
	} else {
nkeynes@586
  1315
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1316
	    // different virtual address than the translation was done with,
nkeynes@586
  1317
	    // but we can safely assume that the low bits are the same.
nkeynes@991
  1318
	    load_imm32( REG_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@991
  1319
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1320
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1321
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1322
	}
nkeynes@991
  1323
	store_reg( REG_EAX, Rn );
nkeynes@374
  1324
    }
nkeynes@361
  1325
:}
nkeynes@361
  1326
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1327
    COUNT_INST(I_MOVL);
nkeynes@991
  1328
    load_reg( REG_EAX, Rm );
nkeynes@991
  1329
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1330
    check_ralign32( REG_EAX );
nkeynes@991
  1331
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1332
    store_reg( REG_EAX, Rn );
nkeynes@417
  1333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1334
:}
nkeynes@361
  1335
MOV.W Rm, @Rn {:  
nkeynes@671
  1336
    COUNT_INST(I_MOVW);
nkeynes@991
  1337
    load_reg( REG_EAX, Rn );
nkeynes@991
  1338
    check_walign16( REG_EAX );
nkeynes@991
  1339
    load_reg( REG_EDX, Rm );
nkeynes@991
  1340
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1342
:}
nkeynes@361
  1343
MOV.W Rm, @-Rn {:  
nkeynes@671
  1344
    COUNT_INST(I_MOVW);
nkeynes@991
  1345
    load_reg( REG_EAX, Rn );
nkeynes@991
  1346
    check_walign16( REG_EAX );
nkeynes@991
  1347
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1348
    load_reg( REG_EDX, Rm );
nkeynes@991
  1349
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1350
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1351
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1352
:}
nkeynes@361
  1353
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1354
    COUNT_INST(I_MOVW);
nkeynes@991
  1355
    load_reg( REG_EAX, 0 );
nkeynes@991
  1356
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1357
    check_walign16( REG_EAX );
nkeynes@991
  1358
    load_reg( REG_EDX, Rm );
nkeynes@991
  1359
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1361
:}
nkeynes@361
  1362
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1363
    COUNT_INST(I_MOVW);
nkeynes@991
  1364
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1365
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1366
    check_walign16( REG_EAX );
nkeynes@991
  1367
    load_reg( REG_EDX, 0 );
nkeynes@991
  1368
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1370
:}
nkeynes@361
  1371
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1372
    COUNT_INST(I_MOVW);
nkeynes@991
  1373
    load_reg( REG_EAX, Rn );
nkeynes@991
  1374
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1375
    check_walign16( REG_EAX );
nkeynes@991
  1376
    load_reg( REG_EDX, 0 );
nkeynes@991
  1377
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1379
:}
nkeynes@361
  1380
MOV.W @Rm, Rn {:  
nkeynes@671
  1381
    COUNT_INST(I_MOVW);
nkeynes@991
  1382
    load_reg( REG_EAX, Rm );
nkeynes@991
  1383
    check_ralign16( REG_EAX );
nkeynes@991
  1384
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1385
    store_reg( REG_EAX, Rn );
nkeynes@417
  1386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1387
:}
nkeynes@361
  1388
MOV.W @Rm+, Rn {:  
nkeynes@671
  1389
    COUNT_INST(I_MOVW);
nkeynes@991
  1390
    load_reg( REG_EAX, Rm );
nkeynes@991
  1391
    check_ralign16( REG_EAX );
nkeynes@991
  1392
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@953
  1393
    if( Rm != Rn ) {
nkeynes@991
  1394
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@953
  1395
    }
nkeynes@991
  1396
    store_reg( REG_EAX, Rn );
nkeynes@417
  1397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1398
:}
nkeynes@361
  1399
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1400
    COUNT_INST(I_MOVW);
nkeynes@991
  1401
    load_reg( REG_EAX, 0 );
nkeynes@991
  1402
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1403
    check_ralign16( REG_EAX );
nkeynes@991
  1404
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1405
    store_reg( REG_EAX, Rn );
nkeynes@417
  1406
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1407
:}
nkeynes@361
  1408
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1409
    COUNT_INST(I_MOVW);
nkeynes@991
  1410
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  1411
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1412
    check_ralign16( REG_EAX );
nkeynes@991
  1413
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1414
    store_reg( REG_EAX, 0 );
nkeynes@417
  1415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1416
:}
nkeynes@361
  1417
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1418
    COUNT_INST(I_MOVW);
nkeynes@374
  1419
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1420
	SLOTILLEGAL();
nkeynes@374
  1421
    } else {
nkeynes@586
  1422
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1423
	uint32_t target = pc + disp + 4;
nkeynes@586
  1424
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1425
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1426
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1427
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1428
	} else {
nkeynes@991
  1429
	    load_imm32( REG_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@991
  1430
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1431
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1432
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1433
	}
nkeynes@991
  1434
	store_reg( REG_EAX, Rn );
nkeynes@374
  1435
    }
nkeynes@361
  1436
:}
nkeynes@361
  1437
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1438
    COUNT_INST(I_MOVW);
nkeynes@991
  1439
    load_reg( REG_EAX, Rm );
nkeynes@991
  1440
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1441
    check_ralign16( REG_EAX );
nkeynes@991
  1442
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1443
    store_reg( REG_EAX, 0 );
nkeynes@417
  1444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1445
:}
nkeynes@361
  1446
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1447
    COUNT_INST(I_MOVA);
nkeynes@374
  1448
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1449
	SLOTILLEGAL();
nkeynes@374
  1450
    } else {
nkeynes@991
  1451
	load_imm32( REG_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@991
  1452
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1453
	store_reg( REG_ECX, 0 );
nkeynes@586
  1454
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1455
    }
nkeynes@361
  1456
:}
nkeynes@361
  1457
MOVCA.L R0, @Rn {:  
nkeynes@671
  1458
    COUNT_INST(I_MOVCA);
nkeynes@991
  1459
    load_reg( REG_EAX, Rn );
nkeynes@991
  1460
    check_walign32( REG_EAX );
nkeynes@991
  1461
    load_reg( REG_EDX, 0 );
nkeynes@991
  1462
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1464
:}
nkeynes@359
  1465
nkeynes@359
  1466
/* Control transfer instructions */
nkeynes@374
  1467
BF disp {:
nkeynes@671
  1468
    COUNT_INST(I_BF);
nkeynes@374
  1469
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1470
	SLOTILLEGAL();
nkeynes@374
  1471
    } else {
nkeynes@586
  1472
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1473
	JT_label( nottaken );
nkeynes@586
  1474
	exit_block_rel(target, pc+2 );
nkeynes@380
  1475
	JMP_TARGET(nottaken);
nkeynes@408
  1476
	return 2;
nkeynes@374
  1477
    }
nkeynes@374
  1478
:}
nkeynes@374
  1479
BF/S disp {:
nkeynes@671
  1480
    COUNT_INST(I_BFS);
nkeynes@374
  1481
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1482
	SLOTILLEGAL();
nkeynes@374
  1483
    } else {
nkeynes@590
  1484
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1485
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1486
	    load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@991
  1487
	    JT_label(nottaken);
nkeynes@991
  1488
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1489
	    JMP_TARGET(nottaken);
nkeynes@991
  1490
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1491
	    store_spreg( REG_EAX, R_NEW_PC );
nkeynes@601
  1492
	    exit_block_emu(pc+2);
nkeynes@601
  1493
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1494
	    return 2;
nkeynes@601
  1495
	} else {
nkeynes@601
  1496
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1497
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1498
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1499
	    }
nkeynes@601
  1500
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1501
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1502
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1503
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1504
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1505
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1506
	    
nkeynes@601
  1507
	    // not taken
nkeynes@601
  1508
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1509
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1510
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1511
	    return 4;
nkeynes@417
  1512
	}
nkeynes@374
  1513
    }
nkeynes@374
  1514
:}
nkeynes@374
  1515
BRA disp {:  
nkeynes@671
  1516
    COUNT_INST(I_BRA);
nkeynes@374
  1517
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1518
	SLOTILLEGAL();
nkeynes@374
  1519
    } else {
nkeynes@590
  1520
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1521
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1522
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1523
	    load_spreg( REG_EAX, R_PC );
nkeynes@991
  1524
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1525
	    store_spreg( REG_EAX, R_NEW_PC );
nkeynes@601
  1526
	    exit_block_emu(pc+2);
nkeynes@601
  1527
	    return 2;
nkeynes@601
  1528
	} else {
nkeynes@601
  1529
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1530
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1531
	    return 4;
nkeynes@601
  1532
	}
nkeynes@374
  1533
    }
nkeynes@374
  1534
:}
nkeynes@374
  1535
BRAF Rn {:  
nkeynes@671
  1536
    COUNT_INST(I_BRAF);
nkeynes@374
  1537
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1538
	SLOTILLEGAL();
nkeynes@374
  1539
    } else {
nkeynes@991
  1540
	load_spreg( REG_EAX, R_PC );
nkeynes@991
  1541
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1542
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1543
	store_spreg( REG_EAX, R_NEW_PC );
nkeynes@590
  1544
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1545
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1546
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1547
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1548
	    exit_block_emu(pc+2);
nkeynes@601
  1549
	    return 2;
nkeynes@601
  1550
	} else {
nkeynes@601
  1551
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1552
	    exit_block_newpcset(pc+4);
nkeynes@601
  1553
	    return 4;
nkeynes@601
  1554
	}
nkeynes@374
  1555
    }
nkeynes@374
  1556
:}
nkeynes@374
  1557
BSR disp {:  
nkeynes@671
  1558
    COUNT_INST(I_BSR);
nkeynes@374
  1559
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1560
	SLOTILLEGAL();
nkeynes@374
  1561
    } else {
nkeynes@991
  1562
	load_spreg( REG_EAX, R_PC );
nkeynes@991
  1563
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1564
	store_spreg( REG_EAX, R_PR );
nkeynes@590
  1565
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1566
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1567
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1568
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1569
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1570
	    store_spreg( REG_EAX, R_NEW_PC );
nkeynes@601
  1571
	    exit_block_emu(pc+2);
nkeynes@601
  1572
	    return 2;
nkeynes@601
  1573
	} else {
nkeynes@601
  1574
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1575
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1576
	    return 4;
nkeynes@601
  1577
	}
nkeynes@374
  1578
    }
nkeynes@374
  1579
:}
nkeynes@374
  1580
BSRF Rn {:  
nkeynes@671
  1581
    COUNT_INST(I_BSRF);
nkeynes@374
  1582
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1583
	SLOTILLEGAL();
nkeynes@374
  1584
    } else {
nkeynes@991
  1585
	load_spreg( REG_EAX, R_PC );
nkeynes@991
  1586
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1587
	store_spreg( REG_EAX, R_PR );
nkeynes@991
  1588
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1589
	store_spreg( REG_EAX, R_NEW_PC );
nkeynes@590
  1590
nkeynes@601
  1591
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1592
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1593
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1594
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1595
	    exit_block_emu(pc+2);
nkeynes@601
  1596
	    return 2;
nkeynes@601
  1597
	} else {
nkeynes@601
  1598
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1599
	    exit_block_newpcset(pc+4);
nkeynes@601
  1600
	    return 4;
nkeynes@601
  1601
	}
nkeynes@374
  1602
    }
nkeynes@374
  1603
:}
nkeynes@374
  1604
BT disp {:
nkeynes@671
  1605
    COUNT_INST(I_BT);
nkeynes@374
  1606
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1607
	SLOTILLEGAL();
nkeynes@374
  1608
    } else {
nkeynes@586
  1609
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1610
	JF_label( nottaken );
nkeynes@586
  1611
	exit_block_rel(target, pc+2 );
nkeynes@380
  1612
	JMP_TARGET(nottaken);
nkeynes@408
  1613
	return 2;
nkeynes@374
  1614
    }
nkeynes@374
  1615
:}
nkeynes@374
  1616
BT/S disp {:
nkeynes@671
  1617
    COUNT_INST(I_BTS);
nkeynes@374
  1618
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1619
	SLOTILLEGAL();
nkeynes@374
  1620
    } else {
nkeynes@590
  1621
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1622
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1623
	    load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@991
  1624
	    JF_label(nottaken);
nkeynes@991
  1625
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1626
	    JMP_TARGET(nottaken);
nkeynes@991
  1627
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1628
	    store_spreg( REG_EAX, R_NEW_PC );
nkeynes@601
  1629
	    exit_block_emu(pc+2);
nkeynes@601
  1630
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1631
	    return 2;
nkeynes@601
  1632
	} else {
nkeynes@601
  1633
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1634
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1635
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1636
	    }
nkeynes@991
  1637
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  1638
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  1639
nkeynes@879
  1640
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1641
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1642
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1643
	    // not taken
nkeynes@601
  1644
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1645
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1646
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1647
	    return 4;
nkeynes@417
  1648
	}
nkeynes@374
  1649
    }
nkeynes@374
  1650
:}
nkeynes@374
  1651
JMP @Rn {:  
nkeynes@671
  1652
    COUNT_INST(I_JMP);
nkeynes@374
  1653
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1654
	SLOTILLEGAL();
nkeynes@374
  1655
    } else {
nkeynes@991
  1656
	load_reg( REG_ECX, Rn );
nkeynes@991
  1657
	store_spreg( REG_ECX, R_NEW_PC );
nkeynes@590
  1658
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1659
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1660
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1661
	    exit_block_emu(pc+2);
nkeynes@601
  1662
	    return 2;
nkeynes@601
  1663
	} else {
nkeynes@601
  1664
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1665
	    exit_block_newpcset(pc+4);
nkeynes@601
  1666
	    return 4;
nkeynes@601
  1667
	}
nkeynes@374
  1668
    }
nkeynes@374
  1669
:}
nkeynes@374
  1670
JSR @Rn {:  
nkeynes@671
  1671
    COUNT_INST(I_JSR);
nkeynes@374
  1672
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1673
	SLOTILLEGAL();
nkeynes@374
  1674
    } else {
nkeynes@991
  1675
	load_spreg( REG_EAX, R_PC );
nkeynes@991
  1676
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1677
	store_spreg( REG_EAX, R_PR );
nkeynes@991
  1678
	load_reg( REG_ECX, Rn );
nkeynes@991
  1679
	store_spreg( REG_ECX, R_NEW_PC );
nkeynes@601
  1680
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1681
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1682
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1683
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1684
	    exit_block_emu(pc+2);
nkeynes@601
  1685
	    return 2;
nkeynes@601
  1686
	} else {
nkeynes@601
  1687
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1688
	    exit_block_newpcset(pc+4);
nkeynes@601
  1689
	    return 4;
nkeynes@601
  1690
	}
nkeynes@374
  1691
    }
nkeynes@374
  1692
:}
nkeynes@374
  1693
RTE {:  
nkeynes@671
  1694
    COUNT_INST(I_RTE);
nkeynes@374
  1695
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1696
	SLOTILLEGAL();
nkeynes@374
  1697
    } else {
nkeynes@408
  1698
	check_priv();
nkeynes@991
  1699
	load_spreg( REG_ECX, R_SPC );
nkeynes@991
  1700
	store_spreg( REG_ECX, R_NEW_PC );
nkeynes@991
  1701
	load_spreg( REG_EAX, R_SSR );
nkeynes@991
  1702
	call_func1( sh4_write_sr, REG_EAX );
nkeynes@590
  1703
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1704
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1705
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1706
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1707
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1708
	    exit_block_emu(pc+2);
nkeynes@601
  1709
	    return 2;
nkeynes@601
  1710
	} else {
nkeynes@601
  1711
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1712
	    exit_block_newpcset(pc+4);
nkeynes@601
  1713
	    return 4;
nkeynes@601
  1714
	}
nkeynes@374
  1715
    }
nkeynes@374
  1716
:}
nkeynes@374
  1717
RTS {:  
nkeynes@671
  1718
    COUNT_INST(I_RTS);
nkeynes@374
  1719
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1720
	SLOTILLEGAL();
nkeynes@374
  1721
    } else {
nkeynes@991
  1722
	load_spreg( REG_ECX, R_PR );
nkeynes@991
  1723
	store_spreg( REG_ECX, R_NEW_PC );
nkeynes@590
  1724
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1725
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1726
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1727
	    exit_block_emu(pc+2);
nkeynes@601
  1728
	    return 2;
nkeynes@601
  1729
	} else {
nkeynes@601
  1730
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1731
	    exit_block_newpcset(pc+4);
nkeynes@601
  1732
	    return 4;
nkeynes@601
  1733
	}
nkeynes@374
  1734
    }
nkeynes@374
  1735
:}
nkeynes@374
  1736
TRAPA #imm {:  
nkeynes@671
  1737
    COUNT_INST(I_TRAPA);
nkeynes@374
  1738
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1739
	SLOTILLEGAL();
nkeynes@374
  1740
    } else {
nkeynes@991
  1741
	load_imm32( REG_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@991
  1742
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@991
  1743
	load_imm32( REG_EAX, imm );
nkeynes@991
  1744
	call_func1( sh4_raise_trap, REG_EAX );
nkeynes@417
  1745
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  1746
	exit_block_pcset(pc+2);
nkeynes@409
  1747
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1748
	return 2;
nkeynes@374
  1749
    }
nkeynes@374
  1750
:}
nkeynes@374
  1751
UNDEF {:  
nkeynes@671
  1752
    COUNT_INST(I_UNDEF);
nkeynes@374
  1753
    if( sh4_x86.in_delay_slot ) {
nkeynes@956
  1754
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
nkeynes@374
  1755
    } else {
nkeynes@956
  1756
	exit_block_exc(EXC_ILLEGAL, pc);    
nkeynes@408
  1757
	return 2;
nkeynes@374
  1758
    }
nkeynes@368
  1759
:}
nkeynes@374
  1760
nkeynes@374
  1761
CLRMAC {:  
nkeynes@671
  1762
    COUNT_INST(I_CLRMAC);
nkeynes@991
  1763
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@991
  1764
    store_spreg( REG_EAX, R_MACL );
nkeynes@991
  1765
    store_spreg( REG_EAX, R_MACH );
nkeynes@417
  1766
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1767
:}
nkeynes@374
  1768
CLRS {:
nkeynes@671
  1769
    COUNT_INST(I_CLRS);
nkeynes@374
  1770
    CLC();
nkeynes@991
  1771
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1772
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1773
:}
nkeynes@374
  1774
CLRT {:  
nkeynes@671
  1775
    COUNT_INST(I_CLRT);
nkeynes@374
  1776
    CLC();
nkeynes@374
  1777
    SETC_t();
nkeynes@417
  1778
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1779
:}
nkeynes@374
  1780
SETS {:  
nkeynes@671
  1781
    COUNT_INST(I_SETS);
nkeynes@374
  1782
    STC();
nkeynes@991
  1783
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1784
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1785
:}
nkeynes@374
  1786
SETT {:  
nkeynes@671
  1787
    COUNT_INST(I_SETT);
nkeynes@374
  1788
    STC();
nkeynes@374
  1789
    SETC_t();
nkeynes@417
  1790
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1791
:}
nkeynes@359
  1792
nkeynes@375
  1793
/* Floating point moves */
nkeynes@375
  1794
FMOV FRm, FRn {:  
nkeynes@671
  1795
    COUNT_INST(I_FMOV1);
nkeynes@377
  1796
    check_fpuen();
nkeynes@901
  1797
    if( sh4_x86.double_size ) {
nkeynes@991
  1798
        load_dr0( REG_EAX, FRm );
nkeynes@991
  1799
        load_dr1( REG_ECX, FRm );
nkeynes@991
  1800
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1801
        store_dr1( REG_ECX, FRn );
nkeynes@901
  1802
    } else {
nkeynes@991
  1803
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  1804
        store_fr( REG_EAX, FRn );
nkeynes@901
  1805
    }
nkeynes@375
  1806
:}
nkeynes@416
  1807
FMOV FRm, @Rn {: 
nkeynes@671
  1808
    COUNT_INST(I_FMOV2);
nkeynes@586
  1809
    check_fpuen();
nkeynes@991
  1810
    load_reg( REG_EAX, Rn );
nkeynes@901
  1811
    if( sh4_x86.double_size ) {
nkeynes@991
  1812
        check_walign64( REG_EAX );
nkeynes@991
  1813
        load_dr0( REG_EDX, FRm );
nkeynes@991
  1814
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1815
        load_reg( REG_EAX, Rn );
nkeynes@991
  1816
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1817
        load_dr1( REG_EDX, FRm );
nkeynes@991
  1818
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  1819
    } else {
nkeynes@991
  1820
        check_walign32( REG_EAX );
nkeynes@991
  1821
        load_fr( REG_EDX, FRm );
nkeynes@991
  1822
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  1823
    }
nkeynes@417
  1824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1825
:}
nkeynes@375
  1826
FMOV @Rm, FRn {:  
nkeynes@671
  1827
    COUNT_INST(I_FMOV5);
nkeynes@586
  1828
    check_fpuen();
nkeynes@991
  1829
    load_reg( REG_EAX, Rm );
nkeynes@901
  1830
    if( sh4_x86.double_size ) {
nkeynes@991
  1831
        check_ralign64( REG_EAX );
nkeynes@991
  1832
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1833
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1834
        load_reg( REG_EAX, Rm );
nkeynes@991
  1835
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1836
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1837
        store_dr1( REG_EAX, FRn );
nkeynes@901
  1838
    } else {
nkeynes@991
  1839
        check_ralign32( REG_EAX );
nkeynes@991
  1840
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1841
        store_fr( REG_EAX, FRn );
nkeynes@901
  1842
    }
nkeynes@417
  1843
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1844
:}
nkeynes@377
  1845
FMOV FRm, @-Rn {:  
nkeynes@671
  1846
    COUNT_INST(I_FMOV3);
nkeynes@586
  1847
    check_fpuen();
nkeynes@991
  1848
    load_reg( REG_EAX, Rn );
nkeynes@901
  1849
    if( sh4_x86.double_size ) {
nkeynes@991
  1850
        check_walign64( REG_EAX );
nkeynes@991
  1851
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  1852
        load_dr0( REG_EDX, FRm );
nkeynes@991
  1853
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1854
        load_reg( REG_EAX, Rn );
nkeynes@991
  1855
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  1856
        load_dr1( REG_EDX, FRm );
nkeynes@991
  1857
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1858
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1859
    } else {
nkeynes@991
  1860
        check_walign32( REG_EAX );
nkeynes@991
  1861
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  1862
        load_fr( REG_EDX, FRm );
nkeynes@991
  1863
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1864
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1865
    }
nkeynes@417
  1866
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1867
:}
nkeynes@416
  1868
FMOV @Rm+, FRn {:
nkeynes@671
  1869
    COUNT_INST(I_FMOV6);
nkeynes@586
  1870
    check_fpuen();
nkeynes@991
  1871
    load_reg( REG_EAX, Rm );
nkeynes@901
  1872
    if( sh4_x86.double_size ) {
nkeynes@991
  1873
        check_ralign64( REG_EAX );
nkeynes@991
  1874
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1875
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1876
        load_reg( REG_EAX, Rm );
nkeynes@991
  1877
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1878
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1879
        store_dr1( REG_EAX, FRn );
nkeynes@991
  1880
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1881
    } else {
nkeynes@991
  1882
        check_ralign32( REG_EAX );
nkeynes@991
  1883
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1884
        store_fr( REG_EAX, FRn );
nkeynes@991
  1885
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1886
    }
nkeynes@417
  1887
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1888
:}
nkeynes@377
  1889
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1890
    COUNT_INST(I_FMOV4);
nkeynes@586
  1891
    check_fpuen();
nkeynes@991
  1892
    load_reg( REG_EAX, Rn );
nkeynes@991
  1893
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  1894
    if( sh4_x86.double_size ) {
nkeynes@991
  1895
        check_walign64( REG_EAX );
nkeynes@991
  1896
        load_dr0( REG_EDX, FRm );
nkeynes@991
  1897
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1898
        load_reg( REG_EAX, Rn );
nkeynes@991
  1899
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  1900
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1901
        load_dr1( REG_EDX, FRm );
nkeynes@991
  1902
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  1903
    } else {
nkeynes@991
  1904
        check_walign32( REG_EAX );
nkeynes@991
  1905
        load_fr( REG_EDX, FRm );
nkeynes@991
  1906
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  1907
    }
nkeynes@417
  1908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1909
:}
nkeynes@377
  1910
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1911
    COUNT_INST(I_FMOV7);
nkeynes@586
  1912
    check_fpuen();
nkeynes@991
  1913
    load_reg( REG_EAX, Rm );
nkeynes@991
  1914
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  1915
    if( sh4_x86.double_size ) {
nkeynes@991
  1916
        check_ralign64( REG_EAX );
nkeynes@991
  1917
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1918
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1919
        load_reg( REG_EAX, Rm );
nkeynes@991
  1920
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  1921
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1922
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1923
        store_dr1( REG_EAX, FRn );
nkeynes@901
  1924
    } else {
nkeynes@991
  1925
        check_ralign32( REG_EAX );
nkeynes@991
  1926
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1927
        store_fr( REG_EAX, FRn );
nkeynes@901
  1928
    }
nkeynes@417
  1929
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1930
:}
nkeynes@377
  1931
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1932
    COUNT_INST(I_FLDI0);
nkeynes@377
  1933
    check_fpuen();
nkeynes@901
  1934
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  1935
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1936
        store_fr( REG_EAX, FRn );
nkeynes@901
  1937
    }
nkeynes@417
  1938
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1939
:}
nkeynes@377
  1940
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1941
    COUNT_INST(I_FLDI1);
nkeynes@377
  1942
    check_fpuen();
nkeynes@901
  1943
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  1944
        load_imm32(REG_EAX, 0x3F800000);
nkeynes@991
  1945
        store_fr( REG_EAX, FRn );
nkeynes@901
  1946
    }
nkeynes@377
  1947
:}
nkeynes@377
  1948
nkeynes@377
  1949
FLOAT FPUL, FRn {:  
nkeynes@671
  1950
    COUNT_INST(I_FLOAT);
nkeynes@377
  1951
    check_fpuen();
nkeynes@991
  1952
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  1953
    if( sh4_x86.double_prec ) {
nkeynes@901
  1954
        pop_dr( FRn );
nkeynes@901
  1955
    } else {
nkeynes@901
  1956
        pop_fr( FRn );
nkeynes@901
  1957
    }
nkeynes@377
  1958
:}
nkeynes@377
  1959
FTRC FRm, FPUL {:  
nkeynes@671
  1960
    COUNT_INST(I_FTRC);
nkeynes@377
  1961
    check_fpuen();
nkeynes@901
  1962
    if( sh4_x86.double_prec ) {
nkeynes@901
  1963
        push_dr( FRm );
nkeynes@901
  1964
    } else {
nkeynes@901
  1965
        push_fr( FRm );
nkeynes@901
  1966
    }
nkeynes@991
  1967
    load_ptr( REG_ECX, &max_int );
nkeynes@991
  1968
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  1969
    FCOMIP_st(1);
nkeynes@991
  1970
    JNA_label( sat );
nkeynes@991
  1971
    load_ptr( REG_ECX, &min_int );  // 5
nkeynes@991
  1972
    FILD_r32disp( REG_ECX, 0 );           // 2
nkeynes@388
  1973
    FCOMIP_st(1);                   // 2
nkeynes@991
  1974
    JAE_label( sat2 );            // 2
nkeynes@991
  1975
    load_ptr( REG_EAX, &save_fcw );
nkeynes@991
  1976
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@991
  1977
    load_ptr( REG_EDX, &trunc_fcw );
nkeynes@991
  1978
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@991
  1979
    FISTP_rbpdisp(R_FPUL);             // 3
nkeynes@991
  1980
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@991
  1981
    JMP_label(end);             // 2
nkeynes@388
  1982
nkeynes@388
  1983
    JMP_TARGET(sat);
nkeynes@388
  1984
    JMP_TARGET(sat2);
nkeynes@991
  1985
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@991
  1986
    store_spreg( REG_ECX, R_FPUL );
nkeynes@388
  1987
    FPOP_st();
nkeynes@388
  1988
    JMP_TARGET(end);
nkeynes@417
  1989
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1990
:}
nkeynes@377
  1991
FLDS FRm, FPUL {:  
nkeynes@671
  1992
    COUNT_INST(I_FLDS);
nkeynes@377
  1993
    check_fpuen();
nkeynes@991
  1994
    load_fr( REG_EAX, FRm );
nkeynes@991
  1995
    store_spreg( REG_EAX, R_FPUL );
nkeynes@377
  1996
:}
nkeynes@377
  1997
FSTS FPUL, FRn {:  
nkeynes@671
  1998
    COUNT_INST(I_FSTS);
nkeynes@377
  1999
    check_fpuen();
nkeynes@991
  2000
    load_spreg( REG_EAX, R_FPUL );
nkeynes@991
  2001
    store_fr( REG_EAX, FRn );
nkeynes@377
  2002
:}
nkeynes@377
  2003
FCNVDS FRm, FPUL {:  
nkeynes@671
  2004
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2005
    check_fpuen();
nkeynes@901
  2006
    if( sh4_x86.double_prec ) {
nkeynes@901
  2007
        push_dr( FRm );
nkeynes@901
  2008
        pop_fpul();
nkeynes@901
  2009
    }
nkeynes@377
  2010
:}
nkeynes@377
  2011
FCNVSD FPUL, FRn {:  
nkeynes@671
  2012
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2013
    check_fpuen();
nkeynes@901
  2014
    if( sh4_x86.double_prec ) {
nkeynes@901
  2015
        push_fpul();
nkeynes@901
  2016
        pop_dr( FRn );
nkeynes@901
  2017
    }
nkeynes@377
  2018
:}
nkeynes@375
  2019
nkeynes@359
  2020
/* Floating point instructions */
nkeynes@374
  2021
FABS FRn {:  
nkeynes@671
  2022
    COUNT_INST(I_FABS);
nkeynes@377
  2023
    check_fpuen();
nkeynes@901
  2024
    if( sh4_x86.double_prec ) {
nkeynes@901
  2025
        push_dr(FRn);
nkeynes@901
  2026
        FABS_st0();
nkeynes@901
  2027
        pop_dr(FRn);
nkeynes@901
  2028
    } else {
nkeynes@901
  2029
        push_fr(FRn);
nkeynes@901
  2030
        FABS_st0();
nkeynes@901
  2031
        pop_fr(FRn);
nkeynes@901
  2032
    }
nkeynes@374
  2033
:}
nkeynes@377
  2034
FADD FRm, FRn {:  
nkeynes@671
  2035
    COUNT_INST(I_FADD);
nkeynes@377
  2036
    check_fpuen();
nkeynes@901
  2037
    if( sh4_x86.double_prec ) {
nkeynes@901
  2038
        push_dr(FRm);
nkeynes@901
  2039
        push_dr(FRn);
nkeynes@901
  2040
        FADDP_st(1);
nkeynes@901
  2041
        pop_dr(FRn);
nkeynes@901
  2042
    } else {
nkeynes@901
  2043
        push_fr(FRm);
nkeynes@901
  2044
        push_fr(FRn);
nkeynes@901
  2045
        FADDP_st(1);
nkeynes@901
  2046
        pop_fr(FRn);
nkeynes@901
  2047
    }
nkeynes@375
  2048
:}
nkeynes@377
  2049
FDIV FRm, FRn {:  
nkeynes@671
  2050
    COUNT_INST(I_FDIV);
nkeynes@377
  2051
    check_fpuen();
nkeynes@901
  2052
    if( sh4_x86.double_prec ) {
nkeynes@901
  2053
        push_dr(FRn);
nkeynes@901
  2054
        push_dr(FRm);
nkeynes@901
  2055
        FDIVP_st(1);
nkeynes@901
  2056
        pop_dr(FRn);
nkeynes@901
  2057
    } else {
nkeynes@901
  2058
        push_fr(FRn);
nkeynes@901
  2059
        push_fr(FRm);
nkeynes@901
  2060
        FDIVP_st(1);
nkeynes@901
  2061
        pop_fr(FRn);
nkeynes@901
  2062
    }
nkeynes@375
  2063
:}
nkeynes@375
  2064
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2065
    COUNT_INST(I_FMAC);
nkeynes@377
  2066
    check_fpuen();
nkeynes@901
  2067
    if( sh4_x86.double_prec ) {
nkeynes@901
  2068
        push_dr( 0 );
nkeynes@901
  2069
        push_dr( FRm );
nkeynes@901
  2070
        FMULP_st(1);
nkeynes@901
  2071
        push_dr( FRn );
nkeynes@901
  2072
        FADDP_st(1);
nkeynes@901
  2073
        pop_dr( FRn );
nkeynes@901
  2074
    } else {
nkeynes@901
  2075
        push_fr( 0 );
nkeynes@901
  2076
        push_fr( FRm );
nkeynes@901
  2077
        FMULP_st(1);
nkeynes@901
  2078
        push_fr( FRn );
nkeynes@901
  2079
        FADDP_st(1);
nkeynes@901
  2080
        pop_fr( FRn );
nkeynes@901
  2081
    }
nkeynes@375
  2082
:}
nkeynes@375
  2083
nkeynes@377
  2084
FMUL FRm, FRn {:  
nkeynes@671
  2085
    COUNT_INST(I_FMUL);
nkeynes@377
  2086
    check_fpuen();
nkeynes@901
  2087
    if( sh4_x86.double_prec ) {
nkeynes@901
  2088
        push_dr(FRm);
nkeynes@901
  2089
        push_dr(FRn);
nkeynes@901
  2090
        FMULP_st(1);
nkeynes@901
  2091
        pop_dr(FRn);
nkeynes@901
  2092
    } else {
nkeynes@901
  2093
        push_fr(FRm);
nkeynes@901
  2094
        push_fr(FRn);
nkeynes@901
  2095
        FMULP_st(1);
nkeynes@901
  2096
        pop_fr(FRn);
nkeynes@901
  2097
    }
nkeynes@377
  2098
:}
nkeynes@377
  2099
FNEG FRn {:  
nkeynes@671
  2100
    COUNT_INST(I_FNEG);
nkeynes@377
  2101
    check_fpuen();
nkeynes@901
  2102
    if( sh4_x86.double_prec ) {
nkeynes@901
  2103
        push_dr(FRn);
nkeynes@901
  2104
        FCHS_st0();
nkeynes@901
  2105
        pop_dr(FRn);
nkeynes@901
  2106
    } else {
nkeynes@901
  2107
        push_fr(FRn);
nkeynes@901
  2108
        FCHS_st0();
nkeynes@901
  2109
        pop_fr(FRn);
nkeynes@901
  2110
    }
nkeynes@377
  2111
:}
nkeynes@377
  2112
FSRRA FRn {:  
nkeynes@671
  2113
    COUNT_INST(I_FSRRA);
nkeynes@377
  2114
    check_fpuen();
nkeynes@901
  2115
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2116
        FLD1_st0();
nkeynes@901
  2117
        push_fr(FRn);
nkeynes@901
  2118
        FSQRT_st0();
nkeynes@901
  2119
        FDIVP_st(1);
nkeynes@901
  2120
        pop_fr(FRn);
nkeynes@901
  2121
    }
nkeynes@377
  2122
:}
nkeynes@377
  2123
FSQRT FRn {:  
nkeynes@671
  2124
    COUNT_INST(I_FSQRT);
nkeynes@377
  2125
    check_fpuen();
nkeynes@901
  2126
    if( sh4_x86.double_prec ) {
nkeynes@901
  2127
        push_dr(FRn);
nkeynes@901
  2128
        FSQRT_st0();
nkeynes@901
  2129
        pop_dr(FRn);
nkeynes@901
  2130
    } else {
nkeynes@901
  2131
        push_fr(FRn);
nkeynes@901
  2132
        FSQRT_st0();
nkeynes@901
  2133
        pop_fr(FRn);
nkeynes@901
  2134
    }
nkeynes@377
  2135
:}
nkeynes@377
  2136
FSUB FRm, FRn {:  
nkeynes@671
  2137
    COUNT_INST(I_FSUB);
nkeynes@377
  2138
    check_fpuen();
nkeynes@901
  2139
    if( sh4_x86.double_prec ) {
nkeynes@901
  2140
        push_dr(FRn);
nkeynes@901
  2141
        push_dr(FRm);
nkeynes@901
  2142
        FSUBP_st(1);
nkeynes@901
  2143
        pop_dr(FRn);
nkeynes@901
  2144
    } else {
nkeynes@901
  2145
        push_fr(FRn);
nkeynes@901
  2146
        push_fr(FRm);
nkeynes@901
  2147
        FSUBP_st(1);
nkeynes@901
  2148
        pop_fr(FRn);
nkeynes@901
  2149
    }
nkeynes@377
  2150
:}
nkeynes@377
  2151
nkeynes@377
  2152
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2153
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2154
    check_fpuen();
nkeynes@901
  2155
    if( sh4_x86.double_prec ) {
nkeynes@901
  2156
        push_dr(FRm);
nkeynes@901
  2157
        push_dr(FRn);
nkeynes@901
  2158
    } else {
nkeynes@901
  2159
        push_fr(FRm);
nkeynes@901
  2160
        push_fr(FRn);
nkeynes@901
  2161
    }
nkeynes@377
  2162
    FCOMIP_st(1);
nkeynes@377
  2163
    SETE_t();
nkeynes@377
  2164
    FPOP_st();
nkeynes@901
  2165
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2166
:}
nkeynes@377
  2167
FCMP/GT FRm, FRn {:  
nkeynes@671
  2168
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2169
    check_fpuen();
nkeynes@901
  2170
    if( sh4_x86.double_prec ) {
nkeynes@901
  2171
        push_dr(FRm);
nkeynes@901
  2172
        push_dr(FRn);
nkeynes@901
  2173
    } else {
nkeynes@901
  2174
        push_fr(FRm);
nkeynes@901
  2175
        push_fr(FRn);
nkeynes@901
  2176
    }
nkeynes@377
  2177
    FCOMIP_st(1);
nkeynes@377
  2178
    SETA_t();
nkeynes@377
  2179
    FPOP_st();
nkeynes@901
  2180
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2181
:}
nkeynes@377
  2182
nkeynes@377
  2183
FSCA FPUL, FRn {:  
nkeynes@671
  2184
    COUNT_INST(I_FSCA);
nkeynes@377
  2185
    check_fpuen();
nkeynes@901
  2186
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2187
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@991
  2188
        load_spreg( REG_EAX, R_FPUL );
nkeynes@991
  2189
        call_func2( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2190
    }
nkeynes@417
  2191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2192
:}
nkeynes@377
  2193
FIPR FVm, FVn {:  
nkeynes@671
  2194
    COUNT_INST(I_FIPR);
nkeynes@377
  2195
    check_fpuen();
nkeynes@901
  2196
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2197
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2198
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2199
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2200
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2201
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2202
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2203
        } else {
nkeynes@904
  2204
            push_fr( FVm<<2 );
nkeynes@903
  2205
            push_fr( FVn<<2 );
nkeynes@903
  2206
            FMULP_st(1);
nkeynes@903
  2207
            push_fr( (FVm<<2)+1);
nkeynes@903
  2208
            push_fr( (FVn<<2)+1);
nkeynes@903
  2209
            FMULP_st(1);
nkeynes@903
  2210
            FADDP_st(1);
nkeynes@903
  2211
            push_fr( (FVm<<2)+2);
nkeynes@903
  2212
            push_fr( (FVn<<2)+2);
nkeynes@903
  2213
            FMULP_st(1);
nkeynes@903
  2214
            FADDP_st(1);
nkeynes@903
  2215
            push_fr( (FVm<<2)+3);
nkeynes@903
  2216
            push_fr( (FVn<<2)+3);
nkeynes@903
  2217
            FMULP_st(1);
nkeynes@903
  2218
            FADDP_st(1);
nkeynes@903
  2219
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2220
        }
nkeynes@901
  2221
    }
nkeynes@377
  2222
:}
nkeynes@377
  2223
FTRV XMTRX, FVn {:  
nkeynes@671
  2224
    COUNT_INST(I_FTRV);
nkeynes@377
  2225
    check_fpuen();
nkeynes@901
  2226
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2227
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2228
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2229
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2230
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2231
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2232
nkeynes@991
  2233
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2234
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2235
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2236
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2237
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2238
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2239
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2240
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2241
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2242
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2243
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2244
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2245
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2246
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2247
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2248
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2249
        } else {
nkeynes@991
  2250
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@991
  2251
            call_func1( sh4_ftrv, REG_EAX );
nkeynes@903
  2252
        }
nkeynes@901
  2253
    }
nkeynes@417
  2254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2255
:}
nkeynes@377
  2256
nkeynes@377
  2257
FRCHG {:  
nkeynes@671
  2258
    COUNT_INST(I_FRCHG);
nkeynes@377
  2259
    check_fpuen();
nkeynes@991
  2260
    XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
nkeynes@669
  2261
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2263
:}
nkeynes@377
  2264
FSCHG {:  
nkeynes@671
  2265
    COUNT_INST(I_FSCHG);
nkeynes@377
  2266
    check_fpuen();
nkeynes@991
  2267
    XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
nkeynes@991
  2268
    XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2269
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2270
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2271
:}
nkeynes@359
  2272
nkeynes@359
  2273
/* Processor control instructions */
nkeynes@368
  2274
LDC Rm, SR {:
nkeynes@671
  2275
    COUNT_INST(I_LDCSR);
nkeynes@386
  2276
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2277
	SLOTILLEGAL();
nkeynes@386
  2278
    } else {
nkeynes@386
  2279
	check_priv();
nkeynes@991
  2280
	load_reg( REG_EAX, Rm );
nkeynes@991
  2281
	call_func1( sh4_write_sr, REG_EAX );
nkeynes@386
  2282
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2283
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2284
	return 2;
nkeynes@386
  2285
    }
nkeynes@368
  2286
:}
nkeynes@359
  2287
LDC Rm, GBR {: 
nkeynes@671
  2288
    COUNT_INST(I_LDC);
nkeynes@991
  2289
    load_reg( REG_EAX, Rm );
nkeynes@991
  2290
    store_spreg( REG_EAX, R_GBR );
nkeynes@359
  2291
:}
nkeynes@359
  2292
LDC Rm, VBR {:  
nkeynes@671
  2293
    COUNT_INST(I_LDC);
nkeynes@386
  2294
    check_priv();
nkeynes@991
  2295
    load_reg( REG_EAX, Rm );
nkeynes@991
  2296
    store_spreg( REG_EAX, R_VBR );
nkeynes@417
  2297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2298
:}
nkeynes@359
  2299
LDC Rm, SSR {:  
nkeynes@671
  2300
    COUNT_INST(I_LDC);
nkeynes@386
  2301
    check_priv();
nkeynes@991
  2302
    load_reg( REG_EAX, Rm );
nkeynes@991
  2303
    store_spreg( REG_EAX, R_SSR );
nkeynes@417
  2304
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2305
:}
nkeynes@359
  2306
LDC Rm, SGR {:  
nkeynes@671
  2307
    COUNT_INST(I_LDC);
nkeynes@386
  2308
    check_priv();
nkeynes@991
  2309
    load_reg( REG_EAX, Rm );
nkeynes@991
  2310
    store_spreg( REG_EAX, R_SGR );
nkeynes@417
  2311
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2312
:}
nkeynes@359
  2313
LDC Rm, SPC {:  
nkeynes@671
  2314
    COUNT_INST(I_LDC);
nkeynes@386
  2315
    check_priv();
nkeynes@991
  2316
    load_reg( REG_EAX, Rm );
nkeynes@991
  2317
    store_spreg( REG_EAX, R_SPC );
nkeynes@417
  2318
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2319
:}
nkeynes@359
  2320
LDC Rm, DBR {:  
nkeynes@671
  2321
    COUNT_INST(I_LDC);
nkeynes@386
  2322
    check_priv();
nkeynes@991
  2323
    load_reg( REG_EAX, Rm );
nkeynes@991
  2324
    store_spreg( REG_EAX, R_DBR );
nkeynes@417
  2325
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2326
:}
nkeynes@374
  2327
LDC Rm, Rn_BANK {:  
nkeynes@671
  2328
    COUNT_INST(I_LDC);
nkeynes@386
  2329
    check_priv();
nkeynes@991
  2330
    load_reg( REG_EAX, Rm );
nkeynes@991
  2331
    store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2332
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2333
:}
nkeynes@359
  2334
LDC.L @Rm+, GBR {:  
nkeynes@671
  2335
    COUNT_INST(I_LDCM);
nkeynes@991
  2336
    load_reg( REG_EAX, Rm );
nkeynes@991
  2337
    check_ralign32( REG_EAX );
nkeynes@991
  2338
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2339
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2340
    store_spreg( REG_EAX, R_GBR );
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2342
:}
nkeynes@368
  2343
LDC.L @Rm+, SR {:
nkeynes@671
  2344
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2345
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2346
	SLOTILLEGAL();
nkeynes@386
  2347
    } else {
nkeynes@586
  2348
	check_priv();
nkeynes@991
  2349
	load_reg( REG_EAX, Rm );
nkeynes@991
  2350
	check_ralign32( REG_EAX );
nkeynes@991
  2351
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2352
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2353
	call_func1( sh4_write_sr, REG_EAX );
nkeynes@386
  2354
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2355
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2356
	return 2;
nkeynes@386
  2357
    }
nkeynes@359
  2358
:}
nkeynes@359
  2359
LDC.L @Rm+, VBR {:  
nkeynes@671
  2360
    COUNT_INST(I_LDCM);
nkeynes@586
  2361
    check_priv();
nkeynes@991
  2362
    load_reg( REG_EAX, Rm );
nkeynes@991
  2363
    check_ralign32( REG_EAX );
nkeynes@991
  2364
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2365
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2366
    store_spreg( REG_EAX, R_VBR );
nkeynes@417
  2367
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2368
:}
nkeynes@359
  2369
LDC.L @Rm+, SSR {:
nkeynes@671
  2370
    COUNT_INST(I_LDCM);
nkeynes@586
  2371
    check_priv();
nkeynes@991
  2372
    load_reg( REG_EAX, Rm );
nkeynes@991
  2373
    check_ralign32( REG_EAX );
nkeynes@991
  2374
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2375
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2376
    store_spreg( REG_EAX, R_SSR );
nkeynes@417
  2377
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2378
:}
nkeynes@359
  2379
LDC.L @Rm+, SGR {:  
nkeynes@671
  2380
    COUNT_INST(I_LDCM);
nkeynes@586
  2381
    check_priv();
nkeynes@991
  2382
    load_reg( REG_EAX, Rm );
nkeynes@991
  2383
    check_ralign32( REG_EAX );
nkeynes@991
  2384
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2385
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2386
    store_spreg( REG_EAX, R_SGR );
nkeynes@417
  2387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2388
:}
nkeynes@359
  2389
LDC.L @Rm+, SPC {:  
nkeynes@671
  2390
    COUNT_INST(I_LDCM);
nkeynes@586
  2391
    check_priv();
nkeynes@991
  2392
    load_reg( REG_EAX, Rm );
nkeynes@991
  2393
    check_ralign32( REG_EAX );
nkeynes@991
  2394
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2395
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2396
    store_spreg( REG_EAX, R_SPC );
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2398
:}
nkeynes@359
  2399
LDC.L @Rm+, DBR {:  
nkeynes@671
  2400
    COUNT_INST(I_LDCM);
nkeynes@586
  2401
    check_priv();
nkeynes@991
  2402
    load_reg( REG_EAX, Rm );
nkeynes@991
  2403
    check_ralign32( REG_EAX );
nkeynes@991
  2404
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2405
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2406
    store_spreg( REG_EAX, R_DBR );
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2408
:}
nkeynes@359
  2409
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2410
    COUNT_INST(I_LDCM);
nkeynes@586
  2411
    check_priv();
nkeynes@991
  2412
    load_reg( REG_EAX, Rm );
nkeynes@991
  2413
    check_ralign32( REG_EAX );
nkeynes@991
  2414
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2415
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2416
    store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2418
:}
nkeynes@626
  2419
LDS Rm, FPSCR {:
nkeynes@673
  2420
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2421
    check_fpuen();
nkeynes@991
  2422
    load_reg( REG_EAX, Rm );
nkeynes@991
  2423
    call_func1( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2425
    return 2;
nkeynes@359
  2426
:}
nkeynes@359
  2427
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2428
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2429
    check_fpuen();
nkeynes@991
  2430
    load_reg( REG_EAX, Rm );
nkeynes@991
  2431
    check_ralign32( REG_EAX );
nkeynes@991
  2432
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2433
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2434
    call_func1( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2435
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2436
    return 2;
nkeynes@359
  2437
:}
nkeynes@359
  2438
LDS Rm, FPUL {:  
nkeynes@671
  2439
    COUNT_INST(I_LDS);
nkeynes@626
  2440
    check_fpuen();
nkeynes@991
  2441
    load_reg( REG_EAX, Rm );
nkeynes@991
  2442
    store_spreg( REG_EAX, R_FPUL );
nkeynes@359
  2443
:}
nkeynes@359
  2444
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2445
    COUNT_INST(I_LDSM);
nkeynes@626
  2446
    check_fpuen();
nkeynes@991
  2447
    load_reg( REG_EAX, Rm );
nkeynes@991
  2448
    check_ralign32( REG_EAX );
nkeynes@991
  2449
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2450
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2451
    store_spreg( REG_EAX, R_FPUL );
nkeynes@417
  2452
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2453
:}
nkeynes@359
  2454
LDS Rm, MACH {: 
nkeynes@671
  2455
    COUNT_INST(I_LDS);
nkeynes@991
  2456
    load_reg( REG_EAX, Rm );
nkeynes@991
  2457
    store_spreg( REG_EAX, R_MACH );
nkeynes@359
  2458
:}
nkeynes@359
  2459
LDS.L @Rm+, MACH {:  
nkeynes@671
  2460
    COUNT_INST(I_LDSM);
nkeynes@991
  2461
    load_reg( REG_EAX, Rm );
nkeynes@991
  2462
    check_ralign32( REG_EAX );
nkeynes@991
  2463
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2464
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2465
    store_spreg( REG_EAX, R_MACH );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2467
:}
nkeynes@359
  2468
LDS Rm, MACL {:  
nkeynes@671
  2469
    COUNT_INST(I_LDS);
nkeynes@991
  2470
    load_reg( REG_EAX, Rm );
nkeynes@991
  2471
    store_spreg( REG_EAX, R_MACL );
nkeynes@359
  2472
:}
nkeynes@359
  2473
LDS.L @Rm+, MACL {:  
nkeynes@671
  2474
    COUNT_INST(I_LDSM);
nkeynes@991
  2475
    load_reg( REG_EAX, Rm );
nkeynes@991
  2476
    check_ralign32( REG_EAX );
nkeynes@991
  2477
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2478
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2479
    store_spreg( REG_EAX, R_MACL );
nkeynes@417
  2480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2481
:}
nkeynes@359
  2482
LDS Rm, PR {:  
nkeynes@671
  2483
    COUNT_INST(I_LDS);
nkeynes@991
  2484
    load_reg( REG_EAX, Rm );
nkeynes@991
  2485
    store_spreg( REG_EAX, R_PR );
nkeynes@359
  2486
:}
nkeynes@359
  2487
LDS.L @Rm+, PR {:  
nkeynes@671
  2488
    COUNT_INST(I_LDSM);
nkeynes@991
  2489
    load_reg( REG_EAX, Rm );
nkeynes@991
  2490
    check_ralign32( REG_EAX );
nkeynes@991
  2491
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2492
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@991
  2493
    store_spreg( REG_EAX, R_PR );
nkeynes@417
  2494
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2495
:}
nkeynes@550
  2496
LDTLB {:  
nkeynes@671
  2497
    COUNT_INST(I_LDTLB);
nkeynes@553
  2498
    call_func0( MMU_ldtlb );
nkeynes@875
  2499
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2500
:}
nkeynes@671
  2501
OCBI @Rn {:
nkeynes@671
  2502
    COUNT_INST(I_OCBI);
nkeynes@671
  2503
:}
nkeynes@671
  2504
OCBP @Rn {:
nkeynes@671
  2505
    COUNT_INST(I_OCBP);
nkeynes@671
  2506
:}
nkeynes@671
  2507
OCBWB @Rn {:
nkeynes@671
  2508
    COUNT_INST(I_OCBWB);
nkeynes@671
  2509
:}
nkeynes@374
  2510
PREF @Rn {:
nkeynes@671
  2511
    COUNT_INST(I_PREF);
nkeynes@991
  2512
    load_reg( REG_EAX, Rn );
nkeynes@991
  2513
    MEM_PREFETCH( REG_EAX );
nkeynes@417
  2514
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2515
:}
nkeynes@388
  2516
SLEEP {: 
nkeynes@671
  2517
    COUNT_INST(I_SLEEP);
nkeynes@388
  2518
    check_priv();
nkeynes@388
  2519
    call_func0( sh4_sleep );
nkeynes@417
  2520
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2521
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2522
    return 2;
nkeynes@388
  2523
:}
nkeynes@386
  2524
STC SR, Rn {:
nkeynes@671
  2525
    COUNT_INST(I_STCSR);
nkeynes@386
  2526
    check_priv();
nkeynes@386
  2527
    call_func0(sh4_read_sr);
nkeynes@991
  2528
    store_reg( REG_EAX, Rn );
nkeynes@417
  2529
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2530
:}
nkeynes@359
  2531
STC GBR, Rn {:  
nkeynes@671
  2532
    COUNT_INST(I_STC);
nkeynes@991
  2533
    load_spreg( REG_EAX, R_GBR );
nkeynes@991
  2534
    store_reg( REG_EAX, Rn );
nkeynes@359
  2535
:}
nkeynes@359
  2536
STC VBR, Rn {:  
nkeynes@671
  2537
    COUNT_INST(I_STC);
nkeynes@386
  2538
    check_priv();
nkeynes@991
  2539
    load_spreg( REG_EAX, R_VBR );
nkeynes@991
  2540
    store_reg( REG_EAX, Rn );
nkeynes@417
  2541
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2542
:}
nkeynes@359
  2543
STC SSR, Rn {:  
nkeynes@671
  2544
    COUNT_INST(I_STC);
nkeynes@386
  2545
    check_priv();
nkeynes@991
  2546
    load_spreg( REG_EAX, R_SSR );
nkeynes@991
  2547
    store_reg( REG_EAX, Rn );
nkeynes@417
  2548
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2549
:}
nkeynes@359
  2550
STC SPC, Rn {:  
nkeynes@671
  2551
    COUNT_INST(I_STC);
nkeynes@386
  2552
    check_priv();
nkeynes@991
  2553
    load_spreg( REG_EAX, R_SPC );
nkeynes@991
  2554
    store_reg( REG_EAX, Rn );
nkeynes@417
  2555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2556
:}
nkeynes@359
  2557
STC SGR, Rn {:  
nkeynes@671
  2558
    COUNT_INST(I_STC);
nkeynes@386
  2559
    check_priv();
nkeynes@991
  2560
    load_spreg( REG_EAX, R_SGR );
nkeynes@991
  2561
    store_reg( REG_EAX, Rn );
nkeynes@417
  2562
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2563
:}
nkeynes@359
  2564
STC DBR, Rn {:  
nkeynes@671
  2565
    COUNT_INST(I_STC);
nkeynes@386
  2566
    check_priv();
nkeynes@991
  2567
    load_spreg( REG_EAX, R_DBR );
nkeynes@991
  2568
    store_reg( REG_EAX, Rn );
nkeynes@417
  2569
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2570
:}
nkeynes@374
  2571
STC Rm_BANK, Rn {:
nkeynes@671
  2572
    COUNT_INST(I_STC);
nkeynes@386
  2573
    check_priv();
nkeynes@991
  2574
    load_spreg( REG_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@991
  2575
    store_reg( REG_EAX, Rn );
nkeynes@417
  2576
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2577
:}
nkeynes@374
  2578
STC.L SR, @-Rn {:
nkeynes@671
  2579
    COUNT_INST(I_STCSRM);
nkeynes@586
  2580
    check_priv();
nkeynes@953
  2581
    call_func0( sh4_read_sr );
nkeynes@991
  2582
    MOVL_r32_r32( REG_EAX, REG_EDX );
nkeynes@991
  2583
    load_reg( REG_EAX, Rn );
nkeynes@991
  2584
    check_walign32( REG_EAX );
nkeynes@991
  2585
    LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2586
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2587
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2588
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2589
:}
nkeynes@359
  2590
STC.L VBR, @-Rn {:  
nkeynes@671
  2591
    COUNT_INST(I_STCM);
nkeynes@586
  2592
    check_priv();
nkeynes@991
  2593
    load_reg( REG_EAX, Rn );
nkeynes@991
  2594
    check_walign32( REG_EAX );
nkeynes@991
  2595
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2596
    load_spreg( REG_EDX, R_VBR );
nkeynes@991
  2597
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2598
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2600
:}
nkeynes@359
  2601
STC.L SSR, @-Rn {:  
nkeynes@671
  2602
    COUNT_INST(I_STCM);
nkeynes@586
  2603
    check_priv();
nkeynes@991
  2604
    load_reg( REG_EAX, Rn );
nkeynes@991
  2605
    check_walign32( REG_EAX );
nkeynes@991
  2606
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2607
    load_spreg( REG_EDX, R_SSR );
nkeynes@991
  2608
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2609
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2610
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2611
:}
nkeynes@416
  2612
STC.L SPC, @-Rn {:
nkeynes@671
  2613
    COUNT_INST(I_STCM);
nkeynes@586
  2614
    check_priv();
nkeynes@991
  2615
    load_reg( REG_EAX, Rn );
nkeynes@991
  2616
    check_walign32( REG_EAX );
nkeynes@991
  2617
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2618
    load_spreg( REG_EDX, R_SPC );
nkeynes@991
  2619
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2620
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2622
:}
nkeynes@359
  2623
STC.L SGR, @-Rn {:  
nkeynes@671
  2624
    COUNT_INST(I_STCM);
nkeynes@586
  2625
    check_priv();
nkeynes@991
  2626
    load_reg( REG_EAX, Rn );
nkeynes@991
  2627
    check_walign32( REG_EAX );
nkeynes@991
  2628
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2629
    load_spreg( REG_EDX, R_SGR );
nkeynes@991
  2630
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2631
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2632
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2633
:}
nkeynes@359
  2634
STC.L DBR, @-Rn {:  
nkeynes@671
  2635
    COUNT_INST(I_STCM);
nkeynes@586
  2636
    check_priv();
nkeynes@991
  2637
    load_reg( REG_EAX, Rn );
nkeynes@991
  2638
    check_walign32( REG_EAX );
nkeynes@991
  2639
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2640
    load_spreg( REG_EDX, R_DBR );
nkeynes@991
  2641
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2642
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2643
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2644
:}
nkeynes@374
  2645
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2646
    COUNT_INST(I_STCM);
nkeynes@586
  2647
    check_priv();
nkeynes@991
  2648
    load_reg( REG_EAX, Rn );
nkeynes@991
  2649
    check_walign32( REG_EAX );
nkeynes@991
  2650
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2651
    load_spreg( REG_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@991
  2652
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2653
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2654
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2655
:}
nkeynes@359
  2656
STC.L GBR, @-Rn {:  
nkeynes@671
  2657
    COUNT_INST(I_STCM);
nkeynes@991
  2658
    load_reg( REG_EAX, Rn );
nkeynes@991
  2659
    check_walign32( REG_EAX );
nkeynes@991
  2660
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2661
    load_spreg( REG_EDX, R_GBR );
nkeynes@991
  2662
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2663
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2664
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2665
:}
nkeynes@359
  2666
STS FPSCR, Rn {:  
nkeynes@673
  2667
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2668
    check_fpuen();
nkeynes@991
  2669
    load_spreg( REG_EAX, R_FPSCR );
nkeynes@991
  2670
    store_reg( REG_EAX, Rn );
nkeynes@359
  2671
:}
nkeynes@359
  2672
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2673
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2674
    check_fpuen();
nkeynes@991
  2675
    load_reg( REG_EAX, Rn );
nkeynes@991
  2676
    check_walign32( REG_EAX );
nkeynes@991
  2677
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2678
    load_spreg( REG_EDX, R_FPSCR );
nkeynes@991
  2679
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2680
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2681
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2682
:}
nkeynes@359
  2683
STS FPUL, Rn {:  
nkeynes@671
  2684
    COUNT_INST(I_STS);
nkeynes@626
  2685
    check_fpuen();
nkeynes@991
  2686
    load_spreg( REG_EAX, R_FPUL );
nkeynes@991
  2687
    store_reg( REG_EAX, Rn );
nkeynes@359
  2688
:}
nkeynes@359
  2689
STS.L FPUL, @-Rn {:  
nkeynes@671
  2690
    COUNT_INST(I_STSM);
nkeynes@626
  2691
    check_fpuen();
nkeynes@991
  2692
    load_reg( REG_EAX, Rn );
nkeynes@991
  2693
    check_walign32( REG_EAX );
nkeynes@991
  2694
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2695
    load_spreg( REG_EDX, R_FPUL );
nkeynes@991
  2696
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2697
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2698
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2699
:}
nkeynes@359
  2700
STS MACH, Rn {:  
nkeynes@671
  2701
    COUNT_INST(I_STS);
nkeynes@991
  2702
    load_spreg( REG_EAX, R_MACH );
nkeynes@991
  2703
    store_reg( REG_EAX, Rn );
nkeynes@359
  2704
:}
nkeynes@359
  2705
STS.L MACH, @-Rn {:  
nkeynes@671
  2706
    COUNT_INST(I_STSM);
nkeynes@991
  2707
    load_reg( REG_EAX, Rn );
nkeynes@991
  2708
    check_walign32( REG_EAX );
nkeynes@991
  2709
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2710
    load_spreg( REG_EDX, R_MACH );
nkeynes@991
  2711
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2712
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2714
:}
nkeynes@359
  2715
STS MACL, Rn {:  
nkeynes@671
  2716
    COUNT_INST(I_STS);
nkeynes@991
  2717
    load_spreg( REG_EAX, R_MACL );
nkeynes@991
  2718
    store_reg( REG_EAX, Rn );
nkeynes@359
  2719
:}
nkeynes@359
  2720
STS.L MACL, @-Rn {:  
nkeynes@671
  2721
    COUNT_INST(I_STSM);
nkeynes@991
  2722
    load_reg( REG_EAX, Rn );
nkeynes@991
  2723
    check_walign32( REG_EAX );
nkeynes@991
  2724
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2725
    load_spreg( REG_EDX, R_MACL );
nkeynes@991
  2726
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2727
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2728
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2729
:}
nkeynes@359
  2730
STS PR, Rn {:  
nkeynes@671
  2731
    COUNT_INST(I_STS);
nkeynes@991
  2732
    load_spreg( REG_EAX, R_PR );
nkeynes@991
  2733
    store_reg( REG_EAX, Rn );
nkeynes@359
  2734
:}
nkeynes@359
  2735
STS.L PR, @-Rn {:  
nkeynes@671
  2736
    COUNT_INST(I_STSM);
nkeynes@991
  2737
    load_reg( REG_EAX, Rn );
nkeynes@991
  2738
    check_walign32( REG_EAX );
nkeynes@991
  2739
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  2740
    load_spreg( REG_EDX, R_PR );
nkeynes@991
  2741
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2742
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2743
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2744
:}
nkeynes@359
  2745
nkeynes@671
  2746
NOP {: 
nkeynes@671
  2747
    COUNT_INST(I_NOP);
nkeynes@671
  2748
    /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ 
nkeynes@671
  2749
:}
nkeynes@359
  2750
%%
nkeynes@590
  2751
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359
  2752
    return 0;
nkeynes@359