/**

 * $Id$

 * 

 * SH4 => x86 translation. This version does no real optimization, it just

 * outputs straight-line x86 code - it mainly exists to provide a baseline

 * to test the optimizing versions against.

 *

 * Copyright (c) 2007 Nathan Keynes.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <assert.h>

#include <math.h>

#ifndef NDEBUG

#define DEBUG_JUMPS 1

#endif

#include "lxdream.h"

#include "sh4/sh4core.h"

#include "sh4/sh4trans.h"

#include "sh4/sh4stat.h"

#include "sh4/sh4mmio.h"

#include "sh4/mmu.h"

#include "xlat/xltcache.h"

#include "xlat/x86/x86op.h"

#include "clock.h"

#define DEFAULT_BACKPATCH_SIZE 4096

/* Offset of a reg relative to the sh4r structure */

#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)

#define R_T   REG_OFFSET(t)

#define R_Q   REG_OFFSET(q)

#define R_S   REG_OFFSET(s)

#define R_M   REG_OFFSET(m)

#define R_SR  REG_OFFSET(sr)

#define R_GBR REG_OFFSET(gbr)

#define R_SSR REG_OFFSET(ssr)

#define R_SPC REG_OFFSET(spc)

#define R_VBR REG_OFFSET(vbr)

#define R_MACH REG_OFFSET(mac)+4

#define R_MACL REG_OFFSET(mac)

#define R_PC REG_OFFSET(pc)

#define R_NEW_PC REG_OFFSET(new_pc)

#define R_PR REG_OFFSET(pr)

#define R_SGR REG_OFFSET(sgr)

#define R_FPUL REG_OFFSET(fpul)

#define R_FPSCR REG_OFFSET(fpscr)

#define R_DBR REG_OFFSET(dbr)

struct backpatch_record {

    uint32_t fixup_offset;

    uint32_t fixup_icount;

    int32_t exc_code;

};

#define DELAY_NONE 0

#define DELAY_PC 1

#define DELAY_PC_PR 2

/** 

 * Struct to manage internal translation state. This state is not saved -

 * it is only valid between calls to sh4_translate_begin_block() and

 * sh4_translate_end_block()

 */

struct sh4_x86_state {

    int in_delay_slot;

    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */

    gboolean branch_taken; /* true if we branched unconditionally */

    gboolean double_prec; /* true if FPU is in double-precision mode */

    gboolean double_size; /* true if FPU is in double-size mode */

    gboolean sse3_enabled; /* true if host supports SSE3 instructions */

    uint32_t block_start_pc;

    uint32_t stack_posn;   /* Trace stack height for alignment purposes */

    int tstate;

    /* mode flags */

    gboolean tlb_on; /* True if tlb translation is active */

    /* Allocated memory for the (block-wide) back-patch list */

    struct backpatch_record *backpatch_list;

    uint32_t backpatch_posn;

    uint32_t backpatch_size;

};

static struct sh4_x86_state sh4_x86;

static uint32_t max_int = 0x7FFFFFFF;

static uint32_t min_int = 0x80000000;

static uint32_t save_fcw; /* save value for fpu control word */

static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */

gboolean is_sse3_supported()

{

    uint32_t features;

    __asm__ __volatile__(

        "mov $0x01, %%eax\n\t"

        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");

    return (features & 1) ? TRUE : FALSE;

}

void sh4_translate_init(void)

{

    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);

    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);

    sh4_x86.sse3_enabled = is_sse3_supported();

}

static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )

{

    int reloc_size = 4;

    if( exc_code == -2 ) {

        reloc_size = sizeof(void *);

    }

    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {

	sh4_x86.backpatch_size <<= 1;

	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 

					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));

	assert( sh4_x86.backpatch_list != NULL );

    }

    if( sh4_x86.in_delay_slot ) {

	fixup_pc -= 2;

    }

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 

	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;

    sh4_x86.backpatch_posn++;

}

#define TSTATE_NONE -1

#define TSTATE_O    0

#define TSTATE_C    2

#define TSTATE_E    4

#define TSTATE_NE   5

#define TSTATE_G    0xF

#define TSTATE_GE   0xD

#define TSTATE_A    7

#define TSTATE_AE   3

#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)

#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)

/* Convenience instructions */

#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()

#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)

#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)

#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)

#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)

#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)

#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)

#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)

#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)

#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)

#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)

#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)

#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)

#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)

#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)

#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)

#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)

#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)

#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)

/** Branch if T is set (either in the current cflags, or in sh4r.t) */

#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \

	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \

    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)

/** Branch if T is clear (either in the current cflags or in sh4r.t) */

#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \

	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \

    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)

#define load_reg16s(x86reg,sh4reg)  MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )

#define load_reg16u(x86reg,sh4reg)  MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )

#define load_imm32(x86reg,value)    MOVL_imm32_r32(value,x86reg)

#define load_imm64(x86reg,value)    MOVQ_imm64_r64(value,x86reg)

#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )

#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )

#define load_spreg(x86reg, regoff)  MOVL_rbpdisp_r32( regoff, x86reg )

#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff )

/**

 * Load an FR register (single-precision floating point) into an integer x86

 * register (eg for register-to-register moves)

 */

#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )

#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )

/**

 * Load the low half of a DR register (DR or XD) into an integer x86 register 

 */

#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )

#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )

/**

 * Store an FR register (single-precision floating point) from an integer x86+

 * register (eg for register-to-register moves)

 */

#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )

#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )

#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )

#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )

#define push_fpul()  FLDF_rbpdisp(R_FPUL)

#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)

#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )

#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )

#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )

#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )

#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )

#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )

#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )

#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )

#ifdef ENABLE_SH4STATS

#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE

#else

#define COUNT_INST(id)

#endif

/* Exception checks - Note that all exception checks will clobber EAX */

#define check_priv( ) \

    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \

        if( sh4_x86.in_delay_slot ) { \

            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \

        } else { \

            exit_block_exc(EXC_ILLEGAL, pc); \

        } \

        sh4_x86.branch_taken = TRUE; \

        sh4_x86.in_delay_slot = DELAY_NONE; \

        return 2; \

    }

#define check_fpuen( ) \

    if( !sh4_x86.fpuen_checked ) {\

	sh4_x86.fpuen_checked = TRUE;\

	load_spreg( REG_EAX, R_SR );\

	ANDL_imms_r32( SR_FD, REG_EAX );\

	if( sh4_x86.in_delay_slot ) {\

	    JNE_exc(EXC_SLOT_FPU_DISABLED);\

	} else {\

	    JNE_exc(EXC_FPU_DISABLED);\

	}\

	sh4_x86.tstate = TSTATE_NONE; \

    }

#define check_ralign16( x86reg ) \

    TESTL_imms_r32( 0x00000001, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_READ)

#define check_walign16( x86reg ) \

    TESTL_imms_r32( 0x00000001, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_WRITE);

#define check_ralign32( x86reg ) \

    TESTL_imms_r32( 0x00000003, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_READ)

#define check_walign32( x86reg ) \

    TESTL_imms_r32( 0x00000003, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_WRITE);

#define check_ralign64( x86reg ) \

    TESTL_imms_r32( 0x00000007, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_READ)

#define check_walign64( x86reg ) \

    TESTL_imms_r32( 0x00000007, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_WRITE);

#define UNDEF(ir)

#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )

#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); }

/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 

 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.

 */

#ifdef HAVE_FRAME_ADDRESS

#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \

        call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \

        call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 

#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \

        call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \

        call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }

#else 

#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg)

#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)

#endif

#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)

#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte_for_write); MEM_RESULT(value_reg)

#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)

#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)

#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)

#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)

#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)

#define MEM_PREFETCH( addr_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, prefetch)

#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;

/****** Import appropriate calling conventions ******/

#if SIZEOF_VOID_P == 8

#include "sh4/ia64abi.h"

#else /* 32-bit system */

#include "sh4/ia32abi.h"

#endif

void sh4_translate_begin_block( sh4addr_t pc ) 

{

    enter_block();

    sh4_x86.in_delay_slot = FALSE;

    sh4_x86.fpuen_checked = FALSE;

    sh4_x86.branch_taken = FALSE;

    sh4_x86.backpatch_posn = 0;

    sh4_x86.block_start_pc = pc;

    sh4_x86.tlb_on = IS_TLB_ENABLED();

    sh4_x86.tstate = TSTATE_NONE;

    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;

    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;

}

uint32_t sh4_translate_end_block_size()

{

    if( sh4_x86.backpatch_posn <= 3 ) {

        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);

    } else {

        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;

    }

}

/**

 * Embed a breakpoint into the generated code

 */

void sh4_translate_emit_breakpoint( sh4vma_t pc )

{

    load_imm32( REG_EAX, pc );

    call_func1( sh4_translate_breakpoint_hit, REG_EAX );

    sh4_x86.tstate = TSTATE_NONE;

}

#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)

/**

 * Embed a call to sh4_execute_instruction for situations that we

 * can't translate (just page-crossing delay slots at the moment).

 * Caller is responsible for setting new_pc before calling this function.

 *

 * Performs:

 *   Set PC = endpc

 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot

 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)

 *   Call sh4_execute_instruction

 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit

 */

void exit_block_emu( sh4vma_t endpc )

{

    load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc );   // 5

    ADDL_r32_rbpdisp( REG_ECX, R_PC );

    load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5

    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6

    load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 );

    store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) );

    call_func0( sh4_execute_instruction );    

    load_spreg( REG_EAX, R_PC );

    if( sh4_x86.tlb_on ) {

	call_func1(xlat_get_code_by_vma,REG_EAX);

    } else {

	call_func1(xlat_get_code,REG_EAX);

    }

    exit_block();

} 

/**

 * Translate a single instruction. Delayed branches are handled specially

 * by translating both branch and delayed instruction as a single unit (as

 * 

 * The instruction MUST be in the icache (assert check)

 *

 * @return true if the instruction marks the end of a basic block

 * (eg a branch or 

 */

uint32_t sh4_translate_instruction( sh4vma_t pc )

{

    uint32_t ir;

    /* Read instruction from icache */

    assert( IS_IN_ICACHE(pc) );

    ir = *(uint16_t *)GET_ICACHE_PTR(pc);

    if( !sh4_x86.in_delay_slot ) {

	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );

    }

%%

/* ALU operations */

ADD Rm, Rn {:

    COUNT_INST(I_ADD);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    ADDL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

ADD #imm, Rn {:  

    COUNT_INST(I_ADDI);

    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );

    sh4_x86.tstate = TSTATE_NONE;

:}

ADDC Rm, Rn {:

    COUNT_INST(I_ADDC);

    if( sh4_x86.tstate != TSTATE_C ) {

        LDC_t();

    }

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    ADCL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

ADDV Rm, Rn {:

    COUNT_INST(I_ADDV);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    ADDL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    SETO_t();

    sh4_x86.tstate = TSTATE_O;

:}

AND Rm, Rn {:

    COUNT_INST(I_AND);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    ANDL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

AND #imm, R0 {:  

    COUNT_INST(I_ANDI);

    load_reg( REG_EAX, 0 );

    ANDL_imms_r32(imm, REG_EAX); 

    store_reg( REG_EAX, 0 );

    sh4_x86.tstate = TSTATE_NONE;

:}

AND.B #imm, @(R0, GBR) {: 

    COUNT_INST(I_ANDB);

    load_reg( REG_EAX, 0 );

    ADDL_rbpdisp_r32( R_GBR, REG_EAX );

    MOVL_r32_rspdisp(REG_EAX, 0);

    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );

    MOVL_rspdisp_r32(0, REG_EAX);

    ANDL_imms_r32(imm, REG_EDX );

    MEM_WRITE_BYTE( REG_EAX, REG_EDX );

    sh4_x86.tstate = TSTATE_NONE;

:}

CMP/EQ Rm, Rn {:  

    COUNT_INST(I_CMPEQ);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETE_t();

    sh4_x86.tstate = TSTATE_E;

:}

CMP/EQ #imm, R0 {:  

    COUNT_INST(I_CMPEQI);

    load_reg( REG_EAX, 0 );

    CMPL_imms_r32(imm, REG_EAX);

    SETE_t();

    sh4_x86.tstate = TSTATE_E;

:}

CMP/GE Rm, Rn {:  

    COUNT_INST(I_CMPGE);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETGE_t();

    sh4_x86.tstate = TSTATE_GE;

:}

CMP/GT Rm, Rn {: 

    COUNT_INST(I_CMPGT);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETG_t();

    sh4_x86.tstate = TSTATE_G;

:}

CMP/HI Rm, Rn {:  

    COUNT_INST(I_CMPHI);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETA_t();

    sh4_x86.tstate = TSTATE_A;

:}

CMP/HS Rm, Rn {: 

    COUNT_INST(I_CMPHS);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETAE_t();

    sh4_x86.tstate = TSTATE_AE;

 :}

CMP/PL Rn {: 

    COUNT_INST(I_CMPPL);

    load_reg( REG_EAX, Rn );

    CMPL_imms_r32( 0, REG_EAX );

    SETG_t();

    sh4_x86.tstate = TSTATE_G;

:}

CMP/PZ Rn {:  

    COUNT_INST(I_CMPPZ);

    load_reg( REG_EAX, Rn );

    CMPL_imms_r32( 0, REG_EAX );

    SETGE_t();

    sh4_x86.tstate = TSTATE_GE;

:}

CMP/STR Rm, Rn {:  

    COUNT_INST(I_CMPSTR);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    XORL_r32_r32( REG_ECX, REG_EAX );

    TESTB_r8_r8( REG_AL, REG_AL );

    JE_label(target1);

    TESTB_r8_r8( REG_AH, REG_AH );

    JE_label(target2);

    SHRL_imm_r32( 16, REG_EAX );

    TESTB_r8_r8( REG_AL, REG_AL );

    JE_label(target3);

    TESTB_r8_r8( REG_AH, REG_AH );

    JMP_TARGET(target1);

    JMP_TARGET(target2);

    JMP_TARGET(target3);

    SETE_t();

    sh4_x86.tstate = TSTATE_E;

:}

DIV0S Rm, Rn {:

    COUNT_INST(I_DIV0S);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    SHRL_imm_r32( 31, REG_EAX );

    SHRL_imm_r32( 31, REG_ECX );

    store_spreg( REG_EAX, R_M );

    store_spreg( REG_ECX, R_Q );

    CMPL_r32_r32( REG_EAX, REG_ECX );

    SETNE_t();

    sh4_x86.tstate = TSTATE_NE;

:}

DIV0U {:  

    COUNT_INST(I_DIV0U);

    XORL_r32_r32( REG_EAX, REG_EAX );

    store_spreg( REG_EAX, R_Q );

    store_spreg( REG_EAX, R_M );

    store_spreg( REG_EAX, R_T );

    sh4_x86.tstate = TSTATE_C; // works for DIV1

:}

DIV1 Rm, Rn {:

    COUNT_INST(I_DIV1);

    load_spreg( REG_ECX, R_M );

    load_reg( REG_EAX, Rn );

    if( sh4_x86.tstate != TSTATE_C ) {

	LDC_t();

    }

    RCLL_imm_r32( 1, REG_EAX );

    SETC_r8( REG_DL ); // Q'

    CMPL_rbpdisp_r32( R_Q, REG_ECX );

    JE_label(mqequal);

    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );

    JMP_label(end);

    JMP_TARGET(mqequal);

    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );

    JMP_TARGET(end);

    store_reg( REG_EAX, Rn ); // Done with Rn now

    SETC_r8(REG_AL); // tmp1

    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1

    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M

    store_spreg( REG_ECX, R_Q );

    XORL_imms_r32( 1, REG_AL );   // T = !Q'

    MOVZXL_r8_r32( REG_AL, REG_EAX );

    store_spreg( REG_EAX, R_T );

    sh4_x86.tstate = TSTATE_NONE;

:}

DMULS.L Rm, Rn {:  

    COUNT_INST(I_DMULS);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    IMULL_r32(REG_ECX);

    store_spreg( REG_EDX, R_MACH );

    store_spreg( REG_EAX, R_MACL );

    sh4_x86.tstate = TSTATE_NONE;

:}

DMULU.L Rm, Rn {:  

    COUNT_INST(I_DMULU);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    MULL_r32(REG_ECX);

    store_spreg( REG_EDX, R_MACH );

    store_spreg( REG_EAX, R_MACL );    

    sh4_x86.tstate = TSTATE_NONE;

:}

DT Rn {:  

    COUNT_INST(I_DT);

    load_reg( REG_EAX, Rn );

    ADDL_imms_r32( -1, REG_EAX );

    store_reg( REG_EAX, Rn );

    SETE_t();

    sh4_x86.tstate = TSTATE_E;

:}

EXTS.B Rm, Rn {:  

    COUNT_INST(I_EXTSB);

    load_reg( REG_EAX, Rm );

    MOVSXL_r8_r32( REG_EAX, REG_EAX );

    store_reg( REG_EAX, Rn );

:}

EXTS.W Rm, Rn {:  

    COUNT_INST(I_EXTSW);

    load_reg( REG_EAX, Rm );

    MOVSXL_r16_r32( REG_EAX, REG_EAX );

    store_reg( REG_EAX, Rn );

:}

EXTU.B Rm, Rn {:  

    COUNT_INST(I_EXTUB);

    load_reg( REG_EAX, Rm );

    MOVZXL_r8_r32( REG_EAX, REG_EAX );

    store_reg( REG_EAX, Rn );

:}

EXTU.W Rm, Rn {:  

    COUNT_INST(I_EXTUW);

    load_reg( REG_EAX, Rm );

    MOVZXL_r16_r32( REG_EAX, REG_EAX );

    store_reg( REG_EAX, Rn );

:}

MAC.L @Rm+, @Rn+ {:

    COUNT_INST(I_MACL);

    if( Rm == Rn ) {

	load_reg( REG_EAX, Rm );

	check_ralign32( REG_EAX );

	MEM_READ_LONG( REG_EAX, REG_EAX );

	MOVL_r32_rspdisp(REG_EAX, 0);

	load_reg( REG_EAX, Rm );

	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );

	MEM_READ_LONG( REG_EAX, REG_EAX );

        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );

    } else {

	load_reg( REG_EAX, Rm );

	check_ralign32( REG_EAX );

	MEM_READ_LONG( REG_EAX, REG_EAX );

	MOVL_r32_rspdisp( REG_EAX, 0 );

	load_reg( REG_EAX, Rn );

	check_ralign32( REG_EAX );

	MEM_READ_LONG( REG_EAX, REG_EAX );

	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );

	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );

    }

    IMULL_rspdisp( 0 );

    ADDL_r32_rbpdisp( REG_EAX, R_MACL );

    ADCL_r32_rbpdisp( REG_EDX, R_MACH );

    load_spreg( REG_ECX, R_S );

    TESTL_r32_r32(REG_ECX, REG_ECX);

    JE_label( nosat );

    call_func0( signsat48 );

    JMP_TARGET( nosat );

    sh4_x86.tstate = TSTATE_NONE;

:}

MAC.W @Rm+, @Rn+ {:  

    COUNT_INST(I_MACW);

    if( Rm == Rn ) {

	load_reg( REG_EAX, Rm );

	check_ralign16( REG_EAX );

	MEM_READ_WORD( REG_EAX, REG_EAX );

        MOVL_r32_rspdisp( REG_EAX, 0 );

	load_reg( REG_EAX, Rm );

	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );

	MEM_READ_WORD( REG_EAX, REG_EAX );

	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );

	// Note translate twice in case of page boundaries. Maybe worth

	// adding a page-boundary check to skip the second translation

    } else {

	load_reg( REG_EAX, Rm );

	check_ralign16( REG_EAX );

	MEM_READ_WORD( REG_EAX, REG_EAX );

        MOVL_r32_rspdisp( REG_EAX, 0 );

	load_reg( REG_EAX, Rn );

	check_ralign16( REG_EAX );

	MEM_READ_WORD( REG_EAX, REG_EAX );

	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );

	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );

    }

    IMULL_rspdisp( 0 );

    load_spreg( REG_ECX, R_S );

    TESTL_r32_r32( REG_ECX, REG_ECX );

    JE_label( nosat );

    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6

    JNO_label( end );            // 2

    load_imm32( REG_EDX, 1 );         // 5

    store_spreg( REG_EDX, R_MACH );   // 6

    JS_label( positive );        // 2

    load_imm32( REG_EAX, 0x80000000 );// 5

    store_spreg( REG_EAX, R_MACL );   // 6

    JMP_label(end2);           // 2

    JMP_TARGET(positive);

    load_imm32( REG_EAX, 0x7FFFFFFF );// 5

    store_spreg( REG_EAX, R_MACL );   // 6

    JMP_label(end3);            // 2

    JMP_TARGET(nosat);

    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6

    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6

    JMP_TARGET(end);

    JMP_TARGET(end2);

    JMP_TARGET(end3);

    sh4_x86.tstate = TSTATE_NONE;

:}

MOVT Rn {:  

    COUNT_INST(I_MOVT);

    load_spreg( REG_EAX, R_T );

    store_reg( REG_EAX, Rn );

:}

MUL.L Rm, Rn {:  

    COUNT_INST(I_MULL);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    MULL_r32( REG_ECX );

    store_spreg( REG_EAX, R_MACL );

    sh4_x86.tstate = TSTATE_NONE;

:}

MULS.W Rm, Rn {:

    COUNT_INST(I_MULSW);

    load_reg16s( REG_EAX, Rm );

    load_reg16s( REG_ECX, Rn );

    MULL_r32( REG_ECX );

    store_spreg( REG_EAX, R_MACL );

    sh4_x86.tstate = TSTATE_NONE;

:}

MULU.W Rm, Rn {:  

    COUNT_INST(I_MULUW);

    load_reg16u( REG_EAX, Rm );

    load_reg16u( REG_ECX, Rn );

    MULL_r32( REG_ECX );

    store_spreg( REG_EAX, R_MACL );

    sh4_x86.tstate = TSTATE_NONE;

:}

NEG Rm, Rn {:

    COUNT_INST(I_NEG);

    load_reg( REG_EAX, Rm );

    NEGL_r32( REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

NEGC Rm, Rn {:  

    COUNT_INST(I_NEGC);

    load_reg( REG_EAX, Rm );

    XORL_r32_r32( REG_ECX, REG_ECX );

    LDC_t();

    SBBL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

NOT Rm, Rn {:  

    COUNT_INST(I_NOT);

    load_reg( REG_EAX, Rm );

    NOTL_r32( REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

OR Rm, Rn {:  

    COUNT_INST(I_OR);

    load_reg( REG_EAX, Rm );

    load_reg( REG_ECX, Rn );

    ORL_r32_r32( REG_EAX, REG_ECX );

    store_reg( REG_ECX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

OR #imm, R0 {:

    COUNT_INST(I_ORI);

    load_reg( REG_EAX, 0 );

    ORL_imms_r32(imm, REG_EAX);

    store_reg( REG_EAX, 0 );

    sh4_x86.tstate = TSTATE_NONE;

:}

OR.B #imm, @(R0, GBR) {:  

    COUNT_INST(I_ORB);

    load_reg( REG_EAX, 0 );

    ADDL_rbpdisp_r32( R_GBR, REG_EAX );

    MOVL_r32_rspdisp( REG_EAX, 0 );

    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );

    MOVL_rspdisp_r32( 0, REG_EAX );

    ORL_imms_r32(imm, REG_EDX );

    MEM_WRITE_BYTE( REG_EAX, REG_EDX );

    sh4_x86.tstate = TSTATE_NONE;

:}

ROTCL Rn {:

    COUNT_INST(I_ROTCL);

    load_reg( REG_EAX, Rn );

    if( sh4_x86.tstate != TSTATE_C ) {

	LDC_t();

    }

    RCLL_imm_r32( 1, REG_EAX );

    store_reg( REG_EAX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

ROTCR Rn {:  

    COUNT_INST(I_ROTCR);

    load_reg( REG_EAX, Rn );

    if( sh4_x86.tstate != TSTATE_C ) {

	LDC_t();

    }

    RCRL_imm_r32( 1, REG_EAX );

    store_reg( REG_EAX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

ROTL Rn {:  

    COUNT_INST(I_ROTL);

    load_reg( REG_EAX, Rn );

    ROLL_imm_r32( 1, REG_EAX );

    store_reg( REG_EAX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

ROTR Rn {:  

    COUNT_INST(I_ROTR);

    load_reg( REG_EAX, Rn );

    RORL_imm_r32( 1, REG_EAX );

    store_reg( REG_EAX, Rn );

    SETC_t();

    sh4_x86.tstate = TSTATE_C;

:}

SHAD Rm, Rn {:

    COUNT_INST(I_SHAD);

    /* Annoyingly enough, not directly convertible */

    load_reg( REG_EAX, Rn );

    load_reg( REG_ECX, Rm );

    CMPL_imms_r32( 0, REG_ECX );

    JGE_label(doshl);

    NEGL_r32( REG_ECX );      // 2

    ANDB_imms_r8( 0x1F, REG_CL ); // 3

    JE_label(emptysar);     // 2

    SARL_cl_r32( REG_EAX );       // 2

    JMP_label(end);          // 2

    JMP_TARGET(emptysar);

    SARL_imm_r32(31, REG_EAX );  // 3

    JMP_label(end2);

    JMP_TARGET(doshl);

    ANDB_imms_r8( 0x1F, REG_CL ); // 3

    SHLL_cl_r32( REG_EAX );       // 2

    JMP_TARGET(end);

    JMP_TARGET(end2);

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLD Rm, Rn {:  

    COUNT_INST(I_SHLD);

    load_reg( REG_EAX, Rn );

    load_reg( REG_ECX, Rm );

    CMPL_imms_r32( 0, REG_ECX );

    JGE_label(doshl);

    NEGL_r32( REG_ECX );      // 2

    ANDB_imms_r8( 0x1F, REG_CL ); // 3

    JE_label(emptyshr );

    SHRL_cl_r32( REG_EAX );       // 2

    JMP_label(end);          // 2

    JMP_TARGET(emptyshr);

    XORL_r32_r32( REG_EAX, REG_EAX );

    JMP_label(end2);

    JMP_TARGET(doshl);

    ANDB_imms_r8( 0x1F, REG_CL ); // 3

    SHLL_cl_r32( REG_EAX );       // 2

    JMP_TARGET(end);

    JMP_TARGET(end2);

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHAL Rn {: 

    COUNT_INST(I_SHAL);

    load_reg( REG_EAX, Rn );

    SHLL_imm_r32( 1, REG_EAX );

    SETC_t();

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_C;

:}

SHAR Rn {:  

    COUNT_INST(I_SHAR);

    load_reg( REG_EAX, Rn );

    SARL_imm_r32( 1, REG_EAX );

    SETC_t();

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_C;

:}

SHLL Rn {:  

    COUNT_INST(I_SHLL);

    load_reg( REG_EAX, Rn );

    SHLL_imm_r32( 1, REG_EAX );

    SETC_t();

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_C;

:}

SHLL2 Rn {:

    COUNT_INST(I_SHLL);

    load_reg( REG_EAX, Rn );

    SHLL_imm_r32( 2, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLL8 Rn {:  

    COUNT_INST(I_SHLL);

    load_reg( REG_EAX, Rn );

    SHLL_imm_r32( 8, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLL16 Rn {:  

    COUNT_INST(I_SHLL);

    load_reg( REG_EAX, Rn );

    SHLL_imm_r32( 16, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLR Rn {:  

    COUNT_INST(I_SHLR);

    load_reg( REG_EAX, Rn );

    SHRL_imm_r32( 1, REG_EAX );

    SETC_t();

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_C;

:}

SHLR2 Rn {:  

    COUNT_INST(I_SHLR);

    load_reg( REG_EAX, Rn );

    SHRL_imm_r32( 2, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLR8 Rn {:  

    COUNT_INST(I_SHLR);

    load_reg( REG_EAX, Rn );

    SHRL_imm_r32( 8, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SHLR16 Rn {:  

    COUNT_INST(I_SHLR);

    load_reg( REG_EAX, Rn );

    SHRL_imm_r32( 16, REG_EAX );

    store_reg( REG_EAX, Rn );

    sh4_x86.tstate = TSTATE_NONE;

:}

SUB Rm, Rn {:  

    COUNT_INST(I_SUB);

    load_reg( REG_EAX, Rm );