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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 189:615b70cfd729
prev161:408b9210395f
next191:df4441cf3128
author nkeynes
date Wed Aug 02 04:06:45 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Issue 0003: TA Vertex compiler
Initial implementation of the TA.
Renderer hooked up to the TA "properly" now as well
file annotate diff log raw
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     1
/**
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 * $Id: pvr2.c,v 1.28 2006-08-02 04:06:45 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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    17
 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    50
    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 32000 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    gboolean retrace;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.retrace = FALSE;
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    pvr2_state.timing = ntsc_timing;
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    video_buffer_idx = 0;
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    90
    
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return 0;
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_state.line_remainder += nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
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	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
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	pvr2_state.line_count++;
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	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
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	    asic_event( EVENT_RETRACE );
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	    pvr2_state.line_count = 0;
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	    pvr2_state.retrace = TRUE;
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	}
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   120
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	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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	    asic_event( EVENT_SCANLINE1 );
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	} 
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	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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	}
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	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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	    if( pvr2_state.retrace ) {
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		pvr2_display_frame();
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		pvr2_state.retrace = FALSE;
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	    }
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	}
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    }
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    return nanosecs;
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   136
}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
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   151
    
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    int dispsize = MMIO_READ( PVR2, DISPSIZE );
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    int dispmode = MMIO_READ( PVR2, DISPMODE );
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    int vidcfg = MMIO_READ( PVR2, DISPCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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						buffer->colour_format );
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	}
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	if( !bEnabled ) {
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	    display_driver->display_blank_frame( 0 );
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	} else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
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	    uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
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	    display_driver->display_blank_frame( colour );
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	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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	    display_driver->display_frame( buffer );
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	}
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    }
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    pvr2_state.frame_count++;
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}
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        /* I don't want to hear about these */
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        return;
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    }
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    switch(reg) {
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    case PVRID:
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    case PVRVER:
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    case GUNPOS:
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    case TA_POLYPOS:
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    case TA_LISTPOS:
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	/* Readonly registers */
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	break;
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    case RENDSTART:
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	if( val == 0xFFFFFFFF )
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	    pvr2_render_scene();
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	break;
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    case DISPADDR1:
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	val &= 0x00FFFFFC;
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	MMIO_WRITE( PVR2, reg, val );
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	if( pvr2_state.retrace ) {
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	    pvr2_display_frame();
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	    pvr2_state.retrace = FALSE;
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	}
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	break;
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    case HCLIP:
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	MMIO_WRITE( PVR2, reg, val & 0x07FF07FF );
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	break;
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   240
    case VCLIP:
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	MMIO_WRITE( PVR2, reg, val & 0x03FF03FF );
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	break;
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   243
    case HPOS_IRQ:
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	MMIO_WRITE( PVR2, reg, val & 0x03FF33FF );
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	break;
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    case VPOS_IRQ:
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	val = val & 0x03FF03FF;
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	pvr2_state.irq_vpos1 = (val >> 16);
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	pvr2_state.irq_vpos2 = val & 0x03FF;
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	MMIO_WRITE( PVR2, reg, val );
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	break;
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   252
    case TA_TILEBASE:
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    case TA_TILEEND:
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    case TA_LISTBASE:
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	MMIO_WRITE( PVR2, reg, val & 0x00FFFFE0 );
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	break;
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    case TA_POLYBASE:
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    case TA_POLYEND:
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	MMIO_WRITE( PVR2, reg, val & 0x00FFFFFC );
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	break;
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   261
    case TA_TILESIZE:
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   262
	MMIO_WRITE( PVR2, reg, val & 0x000F003F );
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	break;
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   264
    case TA_TILECFG:
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	MMIO_WRITE( PVR2, reg, val & 0x00133333 );
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	break;
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   267
    case TA_INIT:
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   268
	if( val & 0x80000000 )
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	    pvr2_ta_init();
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   270
	break;
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   271
	
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    default:
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	MMIO_WRITE( PVR2, reg, val );
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   274
    }
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}
nkeynes@1
   276
nkeynes@1
   277
MMIO_REGION_READ_FN( PVR2, reg )
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{
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   279
    switch( reg ) {
nkeynes@1
   280
        case BEAMPOS:
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   281
            return sh4r.icount&0x20 ? 0x2000 : 1;
nkeynes@1
   282
        default:
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   283
            return MMIO_READ( PVR2, reg );
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   284
    }
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   285
}
nkeynes@19
   286
nkeynes@85
   287
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   288
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   289
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   290
{
nkeynes@19
   291
    mmio_region_PVR2_write( DISPADDR1, base );
nkeynes@19
   292
}
nkeynes@56
   293
nkeynes@56
   294
nkeynes@65
   295
nkeynes@98
   296
nkeynes@56
   297
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   298
{
nkeynes@56
   299
    return 0xFFFFFFFF;
nkeynes@56
   300
}
nkeynes@56
   301
nkeynes@56
   302
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   303
{
nkeynes@189
   304
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   305
}
nkeynes@56
   306
nkeynes@85
   307
nkeynes@103
   308
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   309
{
nkeynes@103
   310
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   311
    uint32_t *banks[2];
nkeynes@103
   312
    uint32_t *dwsrc;
nkeynes@103
   313
    int i;
nkeynes@65
   314
nkeynes@103
   315
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   316
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   317
	length = 0x800000 - destaddr;
nkeynes@103
   318
    }
nkeynes@103
   319
nkeynes@103
   320
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   321
	texcache_invalidate_page( i );
nkeynes@103
   322
    }
nkeynes@103
   323
nkeynes@108
   324
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
nkeynes@103
   325
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   326
    if( bank_flag ) 
nkeynes@108
   327
	banks[0]++;
nkeynes@103
   328
    
nkeynes@103
   329
    /* Handle non-aligned start of source */
nkeynes@103
   330
    if( destaddr & 0x03 ) {
nkeynes@103
   331
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   332
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   333
	    *dest++ = *src++;
nkeynes@103
   334
	}
nkeynes@103
   335
	bank_flag = !bank_flag;
nkeynes@103
   336
    }
nkeynes@103
   337
nkeynes@103
   338
    dwsrc = (uint32_t *)src;
nkeynes@103
   339
    while( length >= 4 ) {
nkeynes@103
   340
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   341
	bank_flag = !bank_flag;
nkeynes@103
   342
	length -= 4;
nkeynes@103
   343
    }
nkeynes@103
   344
    
nkeynes@103
   345
    /* Handle non-aligned end of source */
nkeynes@103
   346
    if( length ) {
nkeynes@103
   347
	src = (char *)dwsrc;
nkeynes@103
   348
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   349
	while( length-- > 0 ) {
nkeynes@103
   350
	    *dest++ = *src++;
nkeynes@103
   351
	}
nkeynes@103
   352
    }  
nkeynes@103
   353
nkeynes@103
   354
}
nkeynes@103
   355
nkeynes@103
   356
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   357
{
nkeynes@103
   358
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   359
    uint32_t *banks[2];
nkeynes@103
   360
    uint32_t *dwdest;
nkeynes@103
   361
    int i;
nkeynes@103
   362
nkeynes@103
   363
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   364
    if( srcaddr + length > 0x800000 )
nkeynes@103
   365
	length = 0x800000 - srcaddr;
nkeynes@103
   366
nkeynes@108
   367
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   368
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   369
    if( bank_flag )
nkeynes@108
   370
	banks[0]++;
nkeynes@103
   371
    
nkeynes@103
   372
    /* Handle non-aligned start of source */
nkeynes@103
   373
    if( srcaddr & 0x03 ) {
nkeynes@103
   374
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   375
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   376
	    *dest++ = *src++;
nkeynes@103
   377
	}
nkeynes@103
   378
	bank_flag = !bank_flag;
nkeynes@103
   379
    }
nkeynes@103
   380
nkeynes@103
   381
    dwdest = (uint32_t *)dest;
nkeynes@103
   382
    while( length >= 4 ) {
nkeynes@103
   383
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   384
	bank_flag = !bank_flag;
nkeynes@103
   385
	length -= 4;
nkeynes@103
   386
    }
nkeynes@103
   387
    
nkeynes@103
   388
    /* Handle non-aligned end of source */
nkeynes@103
   389
    if( length ) {
nkeynes@103
   390
	dest = (char *)dwdest;
nkeynes@103
   391
	char *src = (char *)banks[bank_flag];
nkeynes@103
   392
	while( length-- > 0 ) {
nkeynes@103
   393
	    *dest++ = *src++;
nkeynes@103
   394
	}
nkeynes@103
   395
    }
nkeynes@103
   396
}
nkeynes@127
   397
nkeynes@127
   398
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   399
{
nkeynes@127
   400
    char tmp[length];
nkeynes@127
   401
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   402
    fwrite_dump( tmp, length, f );
nkeynes@127
   403
}
.