filename | src/pvr2/pvr2.h |
changeset | 189:615b70cfd729 |
prev | 161:408b9210395f |
next | 219:dfd3292143f2 |
author | nkeynes |
date | Wed Aug 02 04:06:45 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Issue 0003: TA Vertex compiler Initial implementation of the TA. Renderer hooked up to the TA "properly" now as well |
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nkeynes@31 | 1 | /** |
nkeynes@189 | 2 | * $Id: pvr2.h,v 1.15 2006-08-02 04:06:45 nkeynes Exp $ |
nkeynes@31 | 3 | * |
nkeynes@103 | 4 | * PVR2 (video chip) functions and macros. |
nkeynes@31 | 5 | * |
nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@31 | 7 | * |
nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify |
nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by |
nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@31 | 11 | * (at your option) any later version. |
nkeynes@31 | 12 | * |
nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful, |
nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@31 | 16 | * GNU General Public License for more details. |
nkeynes@31 | 17 | */ |
nkeynes@31 | 18 | |
nkeynes@103 | 19 | #include "dream.h" |
nkeynes@103 | 20 | #include "mem.h" |
nkeynes@144 | 21 | #include "display.h" |
nkeynes@103 | 22 | #include "pvr2/pvr2mmio.h" |
nkeynes@103 | 23 | #include <GL/gl.h> |
nkeynes@1 | 24 | |
nkeynes@189 | 25 | typedef unsigned int pvraddr_t; |
nkeynes@189 | 26 | typedef unsigned int pvr64addr_t; |
nkeynes@1 | 27 | |
nkeynes@1 | 28 | #define DISPMODE_DE 0x00000001 /* Display enable */ |
nkeynes@1 | 29 | #define DISPMODE_SD 0x00000002 /* Scan double */ |
nkeynes@1 | 30 | #define DISPMODE_COL 0x0000000C /* Colour mode */ |
nkeynes@1 | 31 | #define DISPMODE_CD 0x08000000 /* Clock double */ |
nkeynes@1 | 32 | |
nkeynes@94 | 33 | #define COLFMT_RGB15 0x00000000 |
nkeynes@94 | 34 | #define COLFMT_RGB16 0x00000004 |
nkeynes@94 | 35 | #define COLFMT_RGB24 0x00000008 |
nkeynes@94 | 36 | #define COLFMT_RGB32 0x0000000C |
nkeynes@1 | 37 | |
nkeynes@1 | 38 | #define DISPSIZE_MODULO 0x3FF00000 /* line skip +1 (32-bit words)*/ |
nkeynes@1 | 39 | #define DISPSIZE_LPF 0x000FFC00 /* lines per field */ |
nkeynes@1 | 40 | #define DISPSIZE_PPL 0x000003FF /* pixel words (32 bit) per line */ |
nkeynes@1 | 41 | |
nkeynes@103 | 42 | #define DISPCFG_VP 0x00000001 /* V-sync polarity */ |
nkeynes@103 | 43 | #define DISPCFG_HP 0x00000002 /* H-sync polarity */ |
nkeynes@103 | 44 | #define DISPCFG_I 0x00000010 /* Interlace enable */ |
nkeynes@103 | 45 | #define DISPCFG_BS 0x000000C0 /* Broadcast standard */ |
nkeynes@103 | 46 | #define DISPCFG_VO 0x00000100 /* Video output enable */ |
nkeynes@1 | 47 | |
nkeynes@1 | 48 | #define BS_NTSC 0x00000000 |
nkeynes@1 | 49 | #define BS_PAL 0x00000040 |
nkeynes@1 | 50 | #define BS_PALM 0x00000080 /* ? */ |
nkeynes@1 | 51 | #define BS_PALN 0x000000C0 /* ? */ |
nkeynes@1 | 52 | |
nkeynes@103 | 53 | #define PVR2_RAM_BASE 0x05000000 |
nkeynes@103 | 54 | #define PVR2_RAM_BASE_INT 0x04000000 |
nkeynes@103 | 55 | #define PVR2_RAM_SIZE (8 * 1024 * 1024) |
nkeynes@103 | 56 | #define PVR2_RAM_PAGES (PVR2_RAM_SIZE>>12) |
nkeynes@189 | 57 | #define PVR2_RAM_MASK 0x7FFFFF |
nkeynes@103 | 58 | |
nkeynes@1 | 59 | void pvr2_next_frame( void ); |
nkeynes@19 | 60 | void pvr2_set_base_address( uint32_t ); |
nkeynes@133 | 61 | int pvr2_get_frame_count( void ); |
nkeynes@56 | 62 | |
nkeynes@103 | 63 | #define PVR2_CMD_END_OF_LIST 0x00 |
nkeynes@103 | 64 | #define PVR2_CMD_USER_CLIP 0x20 |
nkeynes@103 | 65 | #define PVR2_CMD_POLY_OPAQUE 0x80 |
nkeynes@103 | 66 | #define PVR2_CMD_MOD_OPAQUE 0x81 |
nkeynes@103 | 67 | #define PVR2_CMD_POLY_TRANS 0x82 |
nkeynes@103 | 68 | #define PVR2_CMD_MOD_TRANS 0x83 |
nkeynes@103 | 69 | #define PVR2_CMD_POLY_PUNCHOUT 0x84 |
nkeynes@103 | 70 | #define PVR2_CMD_VERTEX 0xE0 |
nkeynes@103 | 71 | #define PVR2_CMD_VERTEX_LAST 0xF0 |
nkeynes@103 | 72 | |
nkeynes@103 | 73 | #define PVR2_POLY_TEXTURED 0x00000008 |
nkeynes@103 | 74 | #define PVR2_POLY_SPECULAR 0x00000004 |
nkeynes@103 | 75 | #define PVR2_POLY_SHADED 0x00000002 |
nkeynes@103 | 76 | #define PVR2_POLY_UV_16BIT 0x00000001 |
nkeynes@103 | 77 | |
nkeynes@133 | 78 | #define PVR2_POLY_MODE_CLAMP_RGB 0x00200000 |
nkeynes@133 | 79 | #define PVR2_POLY_MODE_ALPHA 0x00100000 |
nkeynes@133 | 80 | #define PVR2_POLY_MODE_TEXALPHA 0x00080000 |
nkeynes@133 | 81 | #define PVR2_POLY_MODE_FLIP_S 0x00040000 |
nkeynes@133 | 82 | #define PVR2_POLY_MODE_FLIP_T 0x00020000 |
nkeynes@133 | 83 | #define PVR2_POLY_MODE_CLAMP_S 0x00010000 |
nkeynes@133 | 84 | #define PVR2_POLY_MODE_CLAMP_T 0x00008000 |
nkeynes@133 | 85 | |
nkeynes@103 | 86 | #define PVR2_TEX_FORMAT_ARGB1555 0x00000000 |
nkeynes@103 | 87 | #define PVR2_TEX_FORMAT_RGB565 0x08000000 |
nkeynes@103 | 88 | #define PVR2_TEX_FORMAT_ARGB4444 0x10000000 |
nkeynes@103 | 89 | #define PVR2_TEX_FORMAT_YUV422 0x18000000 |
nkeynes@103 | 90 | #define PVR2_TEX_FORMAT_BUMPMAP 0x20000000 |
nkeynes@103 | 91 | #define PVR2_TEX_FORMAT_IDX4 0x28000000 |
nkeynes@103 | 92 | #define PVR2_TEX_FORMAT_IDX8 0x30000000 |
nkeynes@103 | 93 | |
nkeynes@103 | 94 | #define PVR2_TEX_MIPMAP 0x80000000 |
nkeynes@103 | 95 | #define PVR2_TEX_COMPRESSED 0x40000000 |
nkeynes@103 | 96 | #define PVR2_TEX_FORMAT_MASK 0x38000000 |
nkeynes@103 | 97 | #define PVR2_TEX_UNTWIDDLED 0x04000000 |
nkeynes@103 | 98 | |
nkeynes@108 | 99 | #define PVR2_TEX_ADDR(x) ( ((x)&0x01FFFFF)<<3 ); |
nkeynes@103 | 100 | #define PVR2_TEX_IS_MIPMAPPED(x) ( (x) & PVR2_TEX_MIPMAP ) |
nkeynes@103 | 101 | #define PVR2_TEX_IS_COMPRESSED(x) ( (x) & PVR2_TEX_COMPRESSED ) |
nkeynes@103 | 102 | #define PVR2_TEX_IS_TWIDDLED(x) (((x) & PVR2_TEX_UNTWIDDLED) == 0) |
nkeynes@103 | 103 | |
nkeynes@103 | 104 | /****************************** Frame Buffer *****************************/ |
nkeynes@103 | 105 | |
nkeynes@103 | 106 | /** |
nkeynes@103 | 107 | * Write to the interleaved memory address space (aka 64-bit address space). |
nkeynes@103 | 108 | */ |
nkeynes@103 | 109 | void pvr2_vram64_write( sh4addr_t dest, char *src, uint32_t length ); |
nkeynes@103 | 110 | |
nkeynes@103 | 111 | /** |
nkeynes@103 | 112 | * Read from the interleaved memory address space (aka 64-bit address space) |
nkeynes@103 | 113 | */ |
nkeynes@103 | 114 | void pvr2_vram64_read( char *dest, sh4addr_t src, uint32_t length ); |
nkeynes@103 | 115 | |
nkeynes@127 | 116 | /** |
nkeynes@127 | 117 | * Dump a portion of vram to a stream from the interleaved memory address |
nkeynes@127 | 118 | * space. |
nkeynes@127 | 119 | */ |
nkeynes@127 | 120 | void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ); |
nkeynes@127 | 121 | |
nkeynes@103 | 122 | /**************************** Tile Accelerator ***************************/ |
nkeynes@56 | 123 | /** |
nkeynes@56 | 124 | * Process the data in the supplied buffer as an array of TA command lists. |
nkeynes@56 | 125 | * Any excess bytes are held pending until a complete list is sent |
nkeynes@56 | 126 | */ |
nkeynes@100 | 127 | void pvr2_ta_write( char *buf, uint32_t length ); |
nkeynes@100 | 128 | |
nkeynes@100 | 129 | |
nkeynes@103 | 130 | /** |
nkeynes@103 | 131 | * (Re)initialize the tile accelerator in preparation for the next scene. |
nkeynes@103 | 132 | * Normally called immediately before commencing polygon transmission. |
nkeynes@103 | 133 | */ |
nkeynes@103 | 134 | void pvr2_ta_init( void ); |
nkeynes@103 | 135 | |
nkeynes@103 | 136 | /********************************* Renderer ******************************/ |
nkeynes@103 | 137 | |
nkeynes@103 | 138 | /** |
nkeynes@103 | 139 | * Initialize the rendering pipeline. |
nkeynes@103 | 140 | * @return TRUE on success, FALSE on failure. |
nkeynes@103 | 141 | */ |
nkeynes@103 | 142 | gboolean pvr2_render_init( void ); |
nkeynes@103 | 143 | |
nkeynes@103 | 144 | /** |
nkeynes@161 | 145 | * Invalidate any caching on the supplied SH4 address |
nkeynes@161 | 146 | */ |
nkeynes@161 | 147 | gboolean pvr2_render_invalidate( sh4addr_t addr ); |
nkeynes@161 | 148 | |
nkeynes@161 | 149 | /** |
nkeynes@103 | 150 | * Render the current scene stored in PVR ram to the GL back buffer. |
nkeynes@103 | 151 | */ |
nkeynes@100 | 152 | void pvr2_render_scene( void ); |
nkeynes@103 | 153 | |
nkeynes@103 | 154 | /** |
nkeynes@103 | 155 | * Display the scene rendered to the supplied address. |
nkeynes@103 | 156 | * @return TRUE if there was an available render that was displayed, |
nkeynes@103 | 157 | * otherwise FALSE (and no action was taken) |
nkeynes@103 | 158 | */ |
nkeynes@103 | 159 | gboolean pvr2_render_display_frame( uint32_t address ); |
nkeynes@103 | 160 | |
nkeynes@103 | 161 | /****************************** Texture Cache ****************************/ |
nkeynes@103 | 162 | |
nkeynes@103 | 163 | /** |
nkeynes@108 | 164 | * Initialize the texture cache. |
nkeynes@103 | 165 | */ |
nkeynes@103 | 166 | void texcache_init( void ); |
nkeynes@103 | 167 | |
nkeynes@108 | 168 | /** |
nkeynes@108 | 169 | * Initialize the GL side of the texture cache (texture ids and such). |
nkeynes@108 | 170 | */ |
nkeynes@108 | 171 | void texcache_gl_init( void ); |
nkeynes@103 | 172 | |
nkeynes@103 | 173 | /** |
nkeynes@103 | 174 | * Flush all textures and delete. The cache will be non-functional until |
nkeynes@103 | 175 | * the next call to texcache_init(). This would typically be done if |
nkeynes@103 | 176 | * switching GL targets. |
nkeynes@103 | 177 | */ |
nkeynes@103 | 178 | void texcache_shutdown( void ); |
nkeynes@103 | 179 | |
nkeynes@103 | 180 | /** |
nkeynes@103 | 181 | * Evict all textures contained in the page identified by a texture address. |
nkeynes@103 | 182 | */ |
nkeynes@103 | 183 | void texcache_invalidate_page( uint32_t texture_addr ); |
nkeynes@103 | 184 | |
nkeynes@103 | 185 | /** |
nkeynes@103 | 186 | * Return a texture ID for the texture specified at the supplied address |
nkeynes@103 | 187 | * and given parameters (the same sequence of bytes could in theory have |
nkeynes@103 | 188 | * multiple interpretations). We use the texture address as the primary |
nkeynes@103 | 189 | * index, but allow for multiple instances at each address. The texture |
nkeynes@103 | 190 | * will be bound to the GL_TEXTURE_2D target before being returned. |
nkeynes@103 | 191 | * |
nkeynes@103 | 192 | * If the texture has already been bound, return the ID to which it was |
nkeynes@103 | 193 | * bound. Otherwise obtain an unused texture ID and set it up appropriately. |
nkeynes@103 | 194 | */ |
nkeynes@103 | 195 | GLuint texcache_get_texture( uint32_t texture_addr, int width, int height, |
nkeynes@103 | 196 | int mode ); |
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