nkeynes@359 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@417 | 28 | #include "sh4/xltcache.h"
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nkeynes@368 | 29 | #include "sh4/sh4core.h"
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nkeynes@368 | 30 | #include "sh4/sh4trans.h"
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nkeynes@671 | 31 | #include "sh4/sh4stat.h"
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nkeynes@388 | 32 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 33 | #include "sh4/x86op.h"
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nkeynes@368 | 34 | #include "clock.h"
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nkeynes@368 | 35 |
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nkeynes@368 | 36 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 37 |
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nkeynes@586 | 38 | struct backpatch_record {
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nkeynes@604 | 39 | uint32_t fixup_offset;
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nkeynes@586 | 40 | uint32_t fixup_icount;
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nkeynes@596 | 41 | int32_t exc_code;
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nkeynes@586 | 42 | };
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nkeynes@586 | 43 |
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nkeynes@590 | 44 | #define DELAY_NONE 0
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nkeynes@590 | 45 | #define DELAY_PC 1
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nkeynes@590 | 46 | #define DELAY_PC_PR 2
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nkeynes@590 | 47 |
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nkeynes@368 | 48 | /**
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nkeynes@368 | 49 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 50 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 51 | * sh4_translate_end_block()
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nkeynes@368 | 52 | */
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nkeynes@368 | 53 | struct sh4_x86_state {
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nkeynes@590 | 54 | int in_delay_slot;
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nkeynes@368 | 55 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 56 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 57 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 58 | uint32_t block_start_pc;
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nkeynes@547 | 59 | uint32_t stack_posn; /* Trace stack height for alignment purposes */
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nkeynes@417 | 60 | int tstate;
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nkeynes@368 | 61 |
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nkeynes@586 | 62 | /* mode flags */
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nkeynes@586 | 63 | gboolean tlb_on; /* True if tlb translation is active */
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nkeynes@586 | 64 |
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nkeynes@368 | 65 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@586 | 66 | struct backpatch_record *backpatch_list;
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nkeynes@368 | 67 | uint32_t backpatch_posn;
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nkeynes@368 | 68 | uint32_t backpatch_size;
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nkeynes@368 | 69 | };
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nkeynes@368 | 70 |
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nkeynes@417 | 71 | #define TSTATE_NONE -1
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nkeynes@417 | 72 | #define TSTATE_O 0
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nkeynes@417 | 73 | #define TSTATE_C 2
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nkeynes@417 | 74 | #define TSTATE_E 4
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nkeynes@417 | 75 | #define TSTATE_NE 5
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nkeynes@417 | 76 | #define TSTATE_G 0xF
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nkeynes@417 | 77 | #define TSTATE_GE 0xD
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nkeynes@417 | 78 | #define TSTATE_A 7
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nkeynes@417 | 79 | #define TSTATE_AE 3
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nkeynes@417 | 80 |
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nkeynes@671 | 81 | #ifdef ENABLE_SH4STATS
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nkeynes@671 | 82 | #define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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nkeynes@671 | 83 | #else
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nkeynes@671 | 84 | #define COUNT_INST(id)
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nkeynes@671 | 85 | #endif
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nkeynes@671 | 86 |
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nkeynes@417 | 87 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
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nkeynes@669 | 88 | #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 89 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@669 | 90 | OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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nkeynes@669 | 91 |
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nkeynes@417 | 92 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
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nkeynes@669 | 93 | #define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 94 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@669 | 95 | OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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nkeynes@417 | 96 |
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nkeynes@368 | 97 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 98 |
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nkeynes@388 | 99 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 100 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 101 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 102 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 103 |
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nkeynes@669 | 104 | void sh4_translate_init(void)
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nkeynes@368 | 105 | {
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nkeynes@368 | 106 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@586 | 107 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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nkeynes@368 | 108 | }
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nkeynes@368 | 109 |
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nkeynes@368 | 110 |
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nkeynes@586 | 111 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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nkeynes@368 | 112 | {
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nkeynes@368 | 113 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 114 | sh4_x86.backpatch_size <<= 1;
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nkeynes@586 | 115 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
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nkeynes@586 | 116 | sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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nkeynes@368 | 117 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 118 | }
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nkeynes@586 | 119 | if( sh4_x86.in_delay_slot ) {
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nkeynes@586 | 120 | fixup_pc -= 2;
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nkeynes@586 | 121 | }
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nkeynes@604 | 122 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =
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nkeynes@604 | 123 | ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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nkeynes@586 | 124 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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nkeynes@586 | 125 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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nkeynes@586 | 126 | sh4_x86.backpatch_posn++;
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nkeynes@368 | 127 | }
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nkeynes@368 | 128 |
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nkeynes@359 | 129 | /**
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nkeynes@359 | 130 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 131 | */
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nkeynes@359 | 132 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 133 | {
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nkeynes@359 | 134 | /* mov [bp+n], reg */
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nkeynes@361 | 135 | OP(0x8B);
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nkeynes@361 | 136 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 137 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 138 | }
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nkeynes@359 | 139 |
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nkeynes@374 | 140 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 141 | {
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nkeynes@374 | 142 | OP(0x0F);
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nkeynes@374 | 143 | OP(0xBF);
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nkeynes@374 | 144 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 145 | }
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nkeynes@368 | 146 |
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nkeynes@374 | 147 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 148 | {
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nkeynes@374 | 149 | OP(0x0F);
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nkeynes@374 | 150 | OP(0xB7);
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nkeynes@374 | 151 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 152 |
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nkeynes@368 | 153 | }
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nkeynes@368 | 154 |
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nkeynes@380 | 155 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 156 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 157 | /**
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nkeynes@359 | 158 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 159 | */
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nkeynes@359 | 160 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 161 | /* mov #value, reg */
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nkeynes@359 | 162 | OP(0xB8 + x86reg);
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nkeynes@359 | 163 | OP32(value);
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nkeynes@359 | 164 | }
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nkeynes@359 | 165 |
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nkeynes@359 | 166 | /**
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nkeynes@527 | 167 | * Load an immediate 64-bit quantity (note: x86-64 only)
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nkeynes@527 | 168 | */
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nkeynes@527 | 169 | static inline void load_imm64( int x86reg, uint32_t value ) {
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nkeynes@527 | 170 | /* mov #value, reg */
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nkeynes@527 | 171 | REXW();
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nkeynes@527 | 172 | OP(0xB8 + x86reg);
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nkeynes@527 | 173 | OP64(value);
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nkeynes@527 | 174 | }
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nkeynes@527 | 175 |
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nkeynes@527 | 176 | /**
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nkeynes@359 | 177 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 178 | */
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nkeynes@359 | 179 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 180 | /* mov reg, [bp+n] */
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nkeynes@361 | 181 | OP(0x89);
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nkeynes@361 | 182 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 183 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 184 | }
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nkeynes@374 | 185 |
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nkeynes@375 | 186 | /**
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nkeynes@375 | 187 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 188 | * register (eg for register-to-register moves)
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nkeynes@375 | 189 | */
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nkeynes@669 | 190 | #define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 191 | #define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@375 | 192 |
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nkeynes@375 | 193 | /**
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nkeynes@669 | 194 | * Load the low half of a DR register (DR or XD) into an integer x86 register
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nkeynes@669 | 195 | */
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nkeynes@669 | 196 | #define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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nkeynes@669 | 197 | #define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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nkeynes@669 | 198 |
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nkeynes@669 | 199 | /**
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nkeynes@669 | 200 | * Store an FR register (single-precision floating point) from an integer x86+
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nkeynes@375 | 201 | * register (eg for register-to-register moves)
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nkeynes@375 | 202 | */
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nkeynes@669 | 203 | #define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 204 | #define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@375 | 205 |
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nkeynes@669 | 206 | #define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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nkeynes@669 | 207 | #define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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nkeynes@375 | 208 |
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nkeynes@374 | 209 |
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nkeynes@669 | 210 | #define push_fpul() FLDF_sh4r(R_FPUL)
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nkeynes@669 | 211 | #define pop_fpul() FSTPF_sh4r(R_FPUL)
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nkeynes@669 | 212 | #define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 213 | #define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 214 | #define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@669 | 215 | #define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@669 | 216 | #define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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nkeynes@669 | 217 | #define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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nkeynes@669 | 218 | #define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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nkeynes@669 | 219 | #define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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nkeynes@377 | 220 |
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nkeynes@377 | 221 |
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nkeynes@374 | 222 |
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nkeynes@368 | 223 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@416 | 224 |
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nkeynes@416 | 225 | #define check_priv( ) \
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nkeynes@416 | 226 | if( !sh4_x86.priv_checked ) { \
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nkeynes@416 | 227 | sh4_x86.priv_checked = TRUE;\
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nkeynes@416 | 228 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 229 | AND_imm32_r32( SR_MD, R_EAX );\
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nkeynes@416 | 230 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 231 | JE_exc( EXC_SLOT_ILLEGAL );\
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nkeynes@416 | 232 | } else {\
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nkeynes@586 | 233 | JE_exc( EXC_ILLEGAL );\
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nkeynes@416 | 234 | }\
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nkeynes@416 | 235 | }\
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nkeynes@416 | 236 |
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nkeynes@416 | 237 | #define check_fpuen( ) \
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nkeynes@416 | 238 | if( !sh4_x86.fpuen_checked ) {\
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nkeynes@416 | 239 | sh4_x86.fpuen_checked = TRUE;\
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nkeynes@416 | 240 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 241 | AND_imm32_r32( SR_FD, R_EAX );\
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nkeynes@416 | 242 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 243 | JNE_exc(EXC_SLOT_FPU_DISABLED);\
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nkeynes@416 | 244 | } else {\
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nkeynes@586 | 245 | JNE_exc(EXC_FPU_DISABLED);\
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nkeynes@416 | 246 | }\
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nkeynes@416 | 247 | }
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nkeynes@416 | 248 |
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nkeynes@586 | 249 | #define check_ralign16( x86reg ) \
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nkeynes@586 | 250 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 251 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@416 | 252 |
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nkeynes@586 | 253 | #define check_walign16( x86reg ) \
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nkeynes@586 | 254 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 255 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 256 |
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nkeynes@586 | 257 | #define check_ralign32( x86reg ) \
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nkeynes@586 | 258 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 259 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@368 | 260 |
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nkeynes@586 | 261 | #define check_walign32( x86reg ) \
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nkeynes@586 | 262 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 263 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 264 |
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nkeynes@732 | 265 | #define check_ralign64( x86reg ) \
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nkeynes@732 | 266 | TEST_imm32_r32( 0x00000007, x86reg ); \
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nkeynes@732 | 267 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@732 | 268 |
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nkeynes@732 | 269 | #define check_walign64( x86reg ) \
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nkeynes@732 | 270 | TEST_imm32_r32( 0x00000007, x86reg ); \
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nkeynes@732 | 271 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@732 | 272 |
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nkeynes@361 | 273 | #define UNDEF()
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nkeynes@361 | 274 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 275 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 276 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 277 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 278 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 279 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 280 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 281 |
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nkeynes@586 | 282 | /**
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nkeynes@586 | 283 | * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned
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nkeynes@586 | 284 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 285 | */
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nkeynes@586 | 286 | #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@596 | 287 |
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nkeynes@596 | 288 | #define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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nkeynes@586 | 289 | /**
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nkeynes@586 | 290 | * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned
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nkeynes@586 | 291 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 292 | */
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nkeynes@586 | 293 | #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@368 | 294 |
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nkeynes@586 | 295 | #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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nkeynes@586 | 296 | #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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nkeynes@586 | 297 | #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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nkeynes@586 | 298 |
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nkeynes@590 | 299 | #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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nkeynes@388 | 300 |
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nkeynes@539 | 301 | /****** Import appropriate calling conventions ******/
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nkeynes@675 | 302 | #if SIZEOF_VOID_P == 8
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nkeynes@539 | 303 | #include "sh4/ia64abi.h"
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nkeynes@675 | 304 | #else /* 32-bit system */
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nkeynes@539 | 305 | #ifdef APPLE_BUILD
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nkeynes@539 | 306 | #include "sh4/ia32mac.h"
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nkeynes@539 | 307 | #else
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nkeynes@539 | 308 | #include "sh4/ia32abi.h"
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nkeynes@539 | 309 | #endif
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nkeynes@539 | 310 | #endif
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nkeynes@539 | 311 |
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nkeynes@593 | 312 | uint32_t sh4_translate_end_block_size()
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nkeynes@593 | 313 | {
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nkeynes@596 | 314 | if( sh4_x86.backpatch_posn <= 3 ) {
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nkeynes@596 | 315 | return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
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nkeynes@596 | 316 | } else {
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nkeynes@596 | 317 | return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
|
nkeynes@596 | 318 | }
|
nkeynes@593 | 319 | }
|
nkeynes@593 | 320 |
|
nkeynes@593 | 321 |
|
nkeynes@590 | 322 | /**
|
nkeynes@590 | 323 | * Embed a breakpoint into the generated code
|
nkeynes@590 | 324 | */
|
nkeynes@586 | 325 | void sh4_translate_emit_breakpoint( sh4vma_t pc )
|
nkeynes@586 | 326 | {
|
nkeynes@591 | 327 | load_imm32( R_EAX, pc );
|
nkeynes@591 | 328 | call_func1( sh4_translate_breakpoint_hit, R_EAX );
|
nkeynes@586 | 329 | }
|
nkeynes@590 | 330 |
|
nkeynes@601 | 331 |
|
nkeynes@601 | 332 | #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
|
nkeynes@601 | 333 |
|
nkeynes@590 | 334 | /**
|
nkeynes@590 | 335 | * Embed a call to sh4_execute_instruction for situations that we
|
nkeynes@601 | 336 | * can't translate (just page-crossing delay slots at the moment).
|
nkeynes@601 | 337 | * Caller is responsible for setting new_pc before calling this function.
|
nkeynes@601 | 338 | *
|
nkeynes@601 | 339 | * Performs:
|
nkeynes@601 | 340 | * Set PC = endpc
|
nkeynes@601 | 341 | * Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
|
nkeynes@601 | 342 | * Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
|
nkeynes@601 | 343 | * Call sh4_execute_instruction
|
nkeynes@601 | 344 | * Call xlat_get_code_by_vma / xlat_get_code as for normal exit
|
nkeynes@590 | 345 | */
|
nkeynes@601 | 346 | void exit_block_emu( sh4vma_t endpc )
|
nkeynes@590 | 347 | {
|
nkeynes@590 | 348 | load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5
|
nkeynes@590 | 349 | ADD_r32_sh4r( R_ECX, R_PC );
|
nkeynes@586 | 350 |
|
nkeynes@601 | 351 | load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
|
nkeynes@590 | 352 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@590 | 353 | load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
|
nkeynes@590 | 354 | store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
|
nkeynes@590 | 355 |
|
nkeynes@590 | 356 | call_func0( sh4_execute_instruction );
|
nkeynes@601 | 357 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 358 | if( sh4_x86.tlb_on ) {
|
nkeynes@590 | 359 | call_func1(xlat_get_code_by_vma,R_EAX);
|
nkeynes@590 | 360 | } else {
|
nkeynes@590 | 361 | call_func1(xlat_get_code,R_EAX);
|
nkeynes@590 | 362 | }
|
nkeynes@601 | 363 | AND_imm8s_rptr( 0xFC, R_EAX );
|
nkeynes@590 | 364 | POP_r32(R_EBP);
|
nkeynes@590 | 365 | RET();
|
nkeynes@590 | 366 | }
|
nkeynes@539 | 367 |
|
nkeynes@359 | 368 | /**
|
nkeynes@359 | 369 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 370 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 371 | *
|
nkeynes@586 | 372 | * The instruction MUST be in the icache (assert check)
|
nkeynes@359 | 373 | *
|
nkeynes@359 | 374 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 375 | * (eg a branch or
|
nkeynes@359 | 376 | */
|
nkeynes@590 | 377 | uint32_t sh4_translate_instruction( sh4vma_t pc )
|
nkeynes@359 | 378 | {
|
nkeynes@388 | 379 | uint32_t ir;
|
nkeynes@586 | 380 | /* Read instruction from icache */
|
nkeynes@586 | 381 | assert( IS_IN_ICACHE(pc) );
|
nkeynes@586 | 382 | ir = *(uint16_t *)GET_ICACHE_PTR(pc);
|
nkeynes@586 | 383 |
|
nkeynes@586 | 384 | /* PC is not in the current icache - this usually means we're running
|
nkeynes@586 | 385 | * with MMU on, and we've gone past the end of the page. And since
|
nkeynes@586 | 386 | * sh4_translate_block is pretty careful about this, it means we're
|
nkeynes@586 | 387 | * almost certainly in a delay slot.
|
nkeynes@586 | 388 | *
|
nkeynes@586 | 389 | * Since we can't assume the page is present (and we can't fault it in
|
nkeynes@586 | 390 | * at this point, inline a call to sh4_execute_instruction (with a few
|
nkeynes@586 | 391 | * small repairs to cope with the different environment).
|
nkeynes@586 | 392 | */
|
nkeynes@586 | 393 |
|
nkeynes@586 | 394 | if( !sh4_x86.in_delay_slot ) {
|
nkeynes@596 | 395 | sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
|
nkeynes@388 | 396 | }
|
nkeynes@359 | 397 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 398 | case 0x0:
|
nkeynes@359 | 399 | switch( ir&0xF ) {
|
nkeynes@359 | 400 | case 0x2:
|
nkeynes@359 | 401 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 402 | case 0x0:
|
nkeynes@359 | 403 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 404 | case 0x0:
|
nkeynes@359 | 405 | { /* STC SR, Rn */
|
nkeynes@359 | 406 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 407 | COUNT_INST(I_STCSR);
|
nkeynes@386 | 408 | check_priv();
|
nkeynes@374 | 409 | call_func0(sh4_read_sr);
|
nkeynes@368 | 410 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 411 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 412 | }
|
nkeynes@359 | 413 | break;
|
nkeynes@359 | 414 | case 0x1:
|
nkeynes@359 | 415 | { /* STC GBR, Rn */
|
nkeynes@359 | 416 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 417 | COUNT_INST(I_STC);
|
nkeynes@359 | 418 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 419 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 420 | }
|
nkeynes@359 | 421 | break;
|
nkeynes@359 | 422 | case 0x2:
|
nkeynes@359 | 423 | { /* STC VBR, Rn */
|
nkeynes@359 | 424 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 425 | COUNT_INST(I_STC);
|
nkeynes@386 | 426 | check_priv();
|
nkeynes@359 | 427 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 428 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 429 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 430 | }
|
nkeynes@359 | 431 | break;
|
nkeynes@359 | 432 | case 0x3:
|
nkeynes@359 | 433 | { /* STC SSR, Rn */
|
nkeynes@359 | 434 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 435 | COUNT_INST(I_STC);
|
nkeynes@386 | 436 | check_priv();
|
nkeynes@359 | 437 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 438 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 439 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 440 | }
|
nkeynes@359 | 441 | break;
|
nkeynes@359 | 442 | case 0x4:
|
nkeynes@359 | 443 | { /* STC SPC, Rn */
|
nkeynes@359 | 444 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 445 | COUNT_INST(I_STC);
|
nkeynes@386 | 446 | check_priv();
|
nkeynes@359 | 447 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 448 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 449 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 450 | }
|
nkeynes@359 | 451 | break;
|
nkeynes@359 | 452 | default:
|
nkeynes@359 | 453 | UNDEF();
|
nkeynes@359 | 454 | break;
|
nkeynes@359 | 455 | }
|
nkeynes@359 | 456 | break;
|
nkeynes@359 | 457 | case 0x1:
|
nkeynes@359 | 458 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 459 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@671 | 460 | COUNT_INST(I_STC);
|
nkeynes@386 | 461 | check_priv();
|
nkeynes@374 | 462 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 463 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 464 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 465 | }
|
nkeynes@359 | 466 | break;
|
nkeynes@359 | 467 | }
|
nkeynes@359 | 468 | break;
|
nkeynes@359 | 469 | case 0x3:
|
nkeynes@359 | 470 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 471 | case 0x0:
|
nkeynes@359 | 472 | { /* BSRF Rn */
|
nkeynes@359 | 473 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 474 | COUNT_INST(I_BSRF);
|
nkeynes@374 | 475 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 476 | SLOTILLEGAL();
|
nkeynes@374 | 477 | } else {
|
nkeynes@590 | 478 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 479 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@590 | 480 | store_spreg( R_EAX, R_PR );
|
nkeynes@590 | 481 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
|
nkeynes@590 | 482 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 483 |
|
nkeynes@601 | 484 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 485 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 486 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 487 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 488 | exit_block_emu(pc+2);
|
nkeynes@601 | 489 | return 2;
|
nkeynes@601 | 490 | } else {
|
nkeynes@601 | 491 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 492 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 493 | return 4;
|
nkeynes@601 | 494 | }
|
nkeynes@374 | 495 | }
|
nkeynes@359 | 496 | }
|
nkeynes@359 | 497 | break;
|
nkeynes@359 | 498 | case 0x2:
|
nkeynes@359 | 499 | { /* BRAF Rn */
|
nkeynes@359 | 500 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 501 | COUNT_INST(I_BRAF);
|
nkeynes@374 | 502 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 503 | SLOTILLEGAL();
|
nkeynes@374 | 504 | } else {
|
nkeynes@590 | 505 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 506 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@590 | 507 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
|
nkeynes@590 | 508 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 509 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 510 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 511 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 512 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 513 | exit_block_emu(pc+2);
|
nkeynes@601 | 514 | return 2;
|
nkeynes@601 | 515 | } else {
|
nkeynes@601 | 516 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 517 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 518 | return 4;
|
nkeynes@601 | 519 | }
|
nkeynes@374 | 520 | }
|
nkeynes@359 | 521 | }
|
nkeynes@359 | 522 | break;
|
nkeynes@359 | 523 | case 0x8:
|
nkeynes@359 | 524 | { /* PREF @Rn */
|
nkeynes@359 | 525 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 526 | COUNT_INST(I_PREF);
|
nkeynes@374 | 527 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 528 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 529 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 530 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@669 | 531 | JNE_rel8(end);
|
nkeynes@532 | 532 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@586 | 533 | TEST_r32_r32( R_EAX, R_EAX );
|
nkeynes@586 | 534 | JE_exc(-1);
|
nkeynes@380 | 535 | JMP_TARGET(end);
|
nkeynes@417 | 536 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 537 | }
|
nkeynes@359 | 538 | break;
|
nkeynes@359 | 539 | case 0x9:
|
nkeynes@359 | 540 | { /* OCBI @Rn */
|
nkeynes@359 | 541 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 542 | COUNT_INST(I_OCBI);
|
nkeynes@359 | 543 | }
|
nkeynes@359 | 544 | break;
|
nkeynes@359 | 545 | case 0xA:
|
nkeynes@359 | 546 | { /* OCBP @Rn */
|
nkeynes@359 | 547 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 548 | COUNT_INST(I_OCBP);
|
nkeynes@359 | 549 | }
|
nkeynes@359 | 550 | break;
|
nkeynes@359 | 551 | case 0xB:
|
nkeynes@359 | 552 | { /* OCBWB @Rn */
|
nkeynes@359 | 553 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 554 | COUNT_INST(I_OCBWB);
|
nkeynes@359 | 555 | }
|
nkeynes@359 | 556 | break;
|
nkeynes@359 | 557 | case 0xC:
|
nkeynes@359 | 558 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 559 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 560 | COUNT_INST(I_MOVCA);
|
nkeynes@586 | 561 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 562 | check_walign32( R_EAX );
|
nkeynes@586 | 563 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 564 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 565 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 566 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 567 | }
|
nkeynes@359 | 568 | break;
|
nkeynes@359 | 569 | default:
|
nkeynes@359 | 570 | UNDEF();
|
nkeynes@359 | 571 | break;
|
nkeynes@359 | 572 | }
|
nkeynes@359 | 573 | break;
|
nkeynes@359 | 574 | case 0x4:
|
nkeynes@359 | 575 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 576 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 577 | COUNT_INST(I_MOVB);
|
nkeynes@359 | 578 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 579 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 580 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 581 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 582 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 583 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 584 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 585 | }
|
nkeynes@359 | 586 | break;
|
nkeynes@359 | 587 | case 0x5:
|
nkeynes@359 | 588 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 589 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 590 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 591 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 592 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 593 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 594 | check_walign16( R_EAX );
|
nkeynes@586 | 595 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 596 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 597 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 598 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 599 | }
|
nkeynes@359 | 600 | break;
|
nkeynes@359 | 601 | case 0x6:
|
nkeynes@359 | 602 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 603 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 604 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 605 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 606 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 607 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 608 | check_walign32( R_EAX );
|
nkeynes@586 | 609 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 610 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 611 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 612 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 613 | }
|
nkeynes@359 | 614 | break;
|
nkeynes@359 | 615 | case 0x7:
|
nkeynes@359 | 616 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 617 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 618 | COUNT_INST(I_MULL);
|
nkeynes@361 | 619 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 620 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 621 | MUL_r32( R_ECX );
|
nkeynes@361 | 622 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 623 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 624 | }
|
nkeynes@359 | 625 | break;
|
nkeynes@359 | 626 | case 0x8:
|
nkeynes@359 | 627 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 628 | case 0x0:
|
nkeynes@359 | 629 | { /* CLRT */
|
nkeynes@671 | 630 | COUNT_INST(I_CLRT);
|
nkeynes@374 | 631 | CLC();
|
nkeynes@374 | 632 | SETC_t();
|
nkeynes@417 | 633 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 634 | }
|
nkeynes@359 | 635 | break;
|
nkeynes@359 | 636 | case 0x1:
|
nkeynes@359 | 637 | { /* SETT */
|
nkeynes@671 | 638 | COUNT_INST(I_SETT);
|
nkeynes@374 | 639 | STC();
|
nkeynes@374 | 640 | SETC_t();
|
nkeynes@417 | 641 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 642 | }
|
nkeynes@359 | 643 | break;
|
nkeynes@359 | 644 | case 0x2:
|
nkeynes@359 | 645 | { /* CLRMAC */
|
nkeynes@671 | 646 | COUNT_INST(I_CLRMAC);
|
nkeynes@374 | 647 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 648 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 649 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 650 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 651 | }
|
nkeynes@359 | 652 | break;
|
nkeynes@359 | 653 | case 0x3:
|
nkeynes@359 | 654 | { /* LDTLB */
|
nkeynes@671 | 655 | COUNT_INST(I_LDTLB);
|
nkeynes@553 | 656 | call_func0( MMU_ldtlb );
|
nkeynes@359 | 657 | }
|
nkeynes@359 | 658 | break;
|
nkeynes@359 | 659 | case 0x4:
|
nkeynes@359 | 660 | { /* CLRS */
|
nkeynes@671 | 661 | COUNT_INST(I_CLRS);
|
nkeynes@374 | 662 | CLC();
|
nkeynes@374 | 663 | SETC_sh4r(R_S);
|
nkeynes@417 | 664 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 665 | }
|
nkeynes@359 | 666 | break;
|
nkeynes@359 | 667 | case 0x5:
|
nkeynes@359 | 668 | { /* SETS */
|
nkeynes@671 | 669 | COUNT_INST(I_SETS);
|
nkeynes@374 | 670 | STC();
|
nkeynes@374 | 671 | SETC_sh4r(R_S);
|
nkeynes@417 | 672 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 673 | }
|
nkeynes@359 | 674 | break;
|
nkeynes@359 | 675 | default:
|
nkeynes@359 | 676 | UNDEF();
|
nkeynes@359 | 677 | break;
|
nkeynes@359 | 678 | }
|
nkeynes@359 | 679 | break;
|
nkeynes@359 | 680 | case 0x9:
|
nkeynes@359 | 681 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 682 | case 0x0:
|
nkeynes@359 | 683 | { /* NOP */
|
nkeynes@671 | 684 | COUNT_INST(I_NOP);
|
nkeynes@359 | 685 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 686 | }
|
nkeynes@359 | 687 | break;
|
nkeynes@359 | 688 | case 0x1:
|
nkeynes@359 | 689 | { /* DIV0U */
|
nkeynes@671 | 690 | COUNT_INST(I_DIV0U);
|
nkeynes@361 | 691 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 692 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 693 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 694 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 695 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@359 | 696 | }
|
nkeynes@359 | 697 | break;
|
nkeynes@359 | 698 | case 0x2:
|
nkeynes@359 | 699 | { /* MOVT Rn */
|
nkeynes@359 | 700 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 701 | COUNT_INST(I_MOVT);
|
nkeynes@359 | 702 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 703 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 704 | }
|
nkeynes@359 | 705 | break;
|
nkeynes@359 | 706 | default:
|
nkeynes@359 | 707 | UNDEF();
|
nkeynes@359 | 708 | break;
|
nkeynes@359 | 709 | }
|
nkeynes@359 | 710 | break;
|
nkeynes@359 | 711 | case 0xA:
|
nkeynes@359 | 712 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 713 | case 0x0:
|
nkeynes@359 | 714 | { /* STS MACH, Rn */
|
nkeynes@359 | 715 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 716 | COUNT_INST(I_STS);
|
nkeynes@359 | 717 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 718 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 719 | }
|
nkeynes@359 | 720 | break;
|
nkeynes@359 | 721 | case 0x1:
|
nkeynes@359 | 722 | { /* STS MACL, Rn */
|
nkeynes@359 | 723 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 724 | COUNT_INST(I_STS);
|
nkeynes@359 | 725 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 726 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 727 | }
|
nkeynes@359 | 728 | break;
|
nkeynes@359 | 729 | case 0x2:
|
nkeynes@359 | 730 | { /* STS PR, Rn */
|
nkeynes@359 | 731 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 732 | COUNT_INST(I_STS);
|
nkeynes@359 | 733 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 734 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 735 | }
|
nkeynes@359 | 736 | break;
|
nkeynes@359 | 737 | case 0x3:
|
nkeynes@359 | 738 | { /* STC SGR, Rn */
|
nkeynes@359 | 739 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 740 | COUNT_INST(I_STC);
|
nkeynes@386 | 741 | check_priv();
|
nkeynes@359 | 742 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 743 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 744 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 745 | }
|
nkeynes@359 | 746 | break;
|
nkeynes@359 | 747 | case 0x5:
|
nkeynes@359 | 748 | { /* STS FPUL, Rn */
|
nkeynes@359 | 749 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 750 | COUNT_INST(I_STS);
|
nkeynes@626 | 751 | check_fpuen();
|
nkeynes@359 | 752 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 753 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 754 | }
|
nkeynes@359 | 755 | break;
|
nkeynes@359 | 756 | case 0x6:
|
nkeynes@359 | 757 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 758 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@673 | 759 | COUNT_INST(I_STSFPSCR);
|
nkeynes@626 | 760 | check_fpuen();
|
nkeynes@359 | 761 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 762 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 763 | }
|
nkeynes@359 | 764 | break;
|
nkeynes@359 | 765 | case 0xF:
|
nkeynes@359 | 766 | { /* STC DBR, Rn */
|
nkeynes@359 | 767 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 768 | COUNT_INST(I_STC);
|
nkeynes@386 | 769 | check_priv();
|
nkeynes@359 | 770 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 771 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 772 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 773 | }
|
nkeynes@359 | 774 | break;
|
nkeynes@359 | 775 | default:
|
nkeynes@359 | 776 | UNDEF();
|
nkeynes@359 | 777 | break;
|
nkeynes@359 | 778 | }
|
nkeynes@359 | 779 | break;
|
nkeynes@359 | 780 | case 0xB:
|
nkeynes@359 | 781 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 782 | case 0x0:
|
nkeynes@359 | 783 | { /* RTS */
|
nkeynes@671 | 784 | COUNT_INST(I_RTS);
|
nkeynes@374 | 785 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 786 | SLOTILLEGAL();
|
nkeynes@374 | 787 | } else {
|
nkeynes@408 | 788 | load_spreg( R_ECX, R_PR );
|
nkeynes@590 | 789 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 790 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 791 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 792 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 793 | exit_block_emu(pc+2);
|
nkeynes@601 | 794 | return 2;
|
nkeynes@601 | 795 | } else {
|
nkeynes@601 | 796 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 797 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 798 | return 4;
|
nkeynes@601 | 799 | }
|
nkeynes@374 | 800 | }
|
nkeynes@359 | 801 | }
|
nkeynes@359 | 802 | break;
|
nkeynes@359 | 803 | case 0x1:
|
nkeynes@359 | 804 | { /* SLEEP */
|
nkeynes@671 | 805 | COUNT_INST(I_SLEEP);
|
nkeynes@388 | 806 | check_priv();
|
nkeynes@388 | 807 | call_func0( sh4_sleep );
|
nkeynes@417 | 808 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@590 | 809 | sh4_x86.in_delay_slot = DELAY_NONE;
|
nkeynes@408 | 810 | return 2;
|
nkeynes@359 | 811 | }
|
nkeynes@359 | 812 | break;
|
nkeynes@359 | 813 | case 0x2:
|
nkeynes@359 | 814 | { /* RTE */
|
nkeynes@671 | 815 | COUNT_INST(I_RTE);
|
nkeynes@374 | 816 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 817 | SLOTILLEGAL();
|
nkeynes@374 | 818 | } else {
|
nkeynes@408 | 819 | check_priv();
|
nkeynes@408 | 820 | load_spreg( R_ECX, R_SPC );
|
nkeynes@590 | 821 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@374 | 822 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 823 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@590 | 824 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@377 | 825 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 826 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 827 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 828 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 829 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 830 | exit_block_emu(pc+2);
|
nkeynes@601 | 831 | return 2;
|
nkeynes@601 | 832 | } else {
|
nkeynes@601 | 833 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 834 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 835 | return 4;
|
nkeynes@601 | 836 | }
|
nkeynes@374 | 837 | }
|
nkeynes@359 | 838 | }
|
nkeynes@359 | 839 | break;
|
nkeynes@359 | 840 | default:
|
nkeynes@359 | 841 | UNDEF();
|
nkeynes@359 | 842 | break;
|
nkeynes@359 | 843 | }
|
nkeynes@359 | 844 | break;
|
nkeynes@359 | 845 | case 0xC:
|
nkeynes@359 | 846 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 847 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 848 | COUNT_INST(I_MOVB);
|
nkeynes@359 | 849 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 850 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 851 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 852 | MMU_TRANSLATE_READ( R_EAX )
|
nkeynes@586 | 853 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 854 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 855 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 856 | }
|
nkeynes@359 | 857 | break;
|
nkeynes@359 | 858 | case 0xD:
|
nkeynes@359 | 859 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 860 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 861 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 862 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 863 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 864 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 865 | check_ralign16( R_EAX );
|
nkeynes@586 | 866 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 867 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 868 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 869 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 870 | }
|
nkeynes@359 | 871 | break;
|
nkeynes@359 | 872 | case 0xE:
|
nkeynes@359 | 873 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 874 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 875 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 876 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 877 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 878 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 879 | check_ralign32( R_EAX );
|
nkeynes@586 | 880 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 881 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 882 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 883 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 884 | }
|
nkeynes@359 | 885 | break;
|
nkeynes@359 | 886 | case 0xF:
|
nkeynes@359 | 887 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 888 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 889 | COUNT_INST(I_MACL);
|
nkeynes@586 | 890 | if( Rm == Rn ) {
|
nkeynes@586 | 891 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 892 | check_ralign32( R_EAX );
|
nkeynes@586 | 893 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 894 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 895 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 896 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@596 | 897 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 898 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 899 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 900 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 901 | } else {
|
nkeynes@586 | 902 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 903 | check_ralign32( R_EAX );
|
nkeynes@586 | 904 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 905 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 906 | check_ralign32( R_ECX );
|
nkeynes@586 | 907 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 908 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 909 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 910 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 911 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 912 | }
|
nkeynes@586 | 913 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 914 | POP_r32( R_ECX );
|
nkeynes@586 | 915 | PUSH_r32( R_EAX );
|
nkeynes@386 | 916 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@547 | 917 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 918 |
|
nkeynes@386 | 919 | IMUL_r32( R_ECX );
|
nkeynes@386 | 920 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 921 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 922 |
|
nkeynes@386 | 923 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 924 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@669 | 925 | JE_rel8( nosat );
|
nkeynes@386 | 926 | call_func0( signsat48 );
|
nkeynes@386 | 927 | JMP_TARGET( nosat );
|
nkeynes@417 | 928 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 929 | }
|
nkeynes@359 | 930 | break;
|
nkeynes@359 | 931 | default:
|
nkeynes@359 | 932 | UNDEF();
|
nkeynes@359 | 933 | break;
|
nkeynes@359 | 934 | }
|
nkeynes@359 | 935 | break;
|
nkeynes@359 | 936 | case 0x1:
|
nkeynes@359 | 937 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 938 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@671 | 939 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 940 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 941 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 942 | check_walign32( R_EAX );
|
nkeynes@586 | 943 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 944 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 945 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 946 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 947 | }
|
nkeynes@359 | 948 | break;
|
nkeynes@359 | 949 | case 0x2:
|
nkeynes@359 | 950 | switch( ir&0xF ) {
|
nkeynes@359 | 951 | case 0x0:
|
nkeynes@359 | 952 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 953 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 954 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 955 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 956 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 957 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 958 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 959 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 960 | }
|
nkeynes@359 | 961 | break;
|
nkeynes@359 | 962 | case 0x1:
|
nkeynes@359 | 963 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 964 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 965 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 966 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 967 | check_walign16( R_EAX );
|
nkeynes@586 | 968 | MMU_TRANSLATE_WRITE( R_EAX )
|
nkeynes@586 | 969 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 970 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 971 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 972 | }
|
nkeynes@359 | 973 | break;
|
nkeynes@359 | 974 | case 0x2:
|
nkeynes@359 | 975 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 976 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 977 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 978 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 979 | check_walign32(R_EAX);
|
nkeynes@586 | 980 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 981 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 982 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 983 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 984 | }
|
nkeynes@359 | 985 | break;
|
nkeynes@359 | 986 | case 0x4:
|
nkeynes@359 | 987 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 988 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 989 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 990 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 991 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@586 | 992 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 993 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 994 | ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 995 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 996 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 997 | }
|
nkeynes@359 | 998 | break;
|
nkeynes@359 | 999 | case 0x5:
|
nkeynes@359 | 1000 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 1001 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1002 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1003 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1004 | ADD_imm8s_r32( -2, R_EAX );
|
nkeynes@586 | 1005 | check_walign16( R_EAX );
|
nkeynes@586 | 1006 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1007 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1008 | ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1009 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1010 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1011 | }
|
nkeynes@359 | 1012 | break;
|
nkeynes@359 | 1013 | case 0x6:
|
nkeynes@359 | 1014 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 1015 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1016 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1017 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1018 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1019 | check_walign32( R_EAX );
|
nkeynes@586 | 1020 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1021 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1022 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1023 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1024 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1025 | }
|
nkeynes@359 | 1026 | break;
|
nkeynes@359 | 1027 | case 0x7:
|
nkeynes@359 | 1028 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 1029 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1030 | COUNT_INST(I_DIV0S);
|
nkeynes@361 | 1031 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 1032 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1033 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 1034 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 1035 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 1036 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 1037 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1038 | SETNE_t();
|
nkeynes@417 | 1039 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@359 | 1040 | }
|
nkeynes@359 | 1041 | break;
|
nkeynes@359 | 1042 | case 0x8:
|
nkeynes@359 | 1043 | { /* TST Rm, Rn */
|
nkeynes@359 | 1044 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1045 | COUNT_INST(I_TST);
|
nkeynes@361 | 1046 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1047 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1048 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1049 | SETE_t();
|
nkeynes@417 | 1050 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1051 | }
|
nkeynes@359 | 1052 | break;
|
nkeynes@359 | 1053 | case 0x9:
|
nkeynes@359 | 1054 | { /* AND Rm, Rn */
|
nkeynes@359 | 1055 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1056 | COUNT_INST(I_AND);
|
nkeynes@359 | 1057 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1058 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1059 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1060 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1061 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1062 | }
|
nkeynes@359 | 1063 | break;
|
nkeynes@359 | 1064 | case 0xA:
|
nkeynes@359 | 1065 | { /* XOR Rm, Rn */
|
nkeynes@359 | 1066 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1067 | COUNT_INST(I_XOR);
|
nkeynes@359 | 1068 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1069 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1070 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1071 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1072 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1073 | }
|
nkeynes@359 | 1074 | break;
|
nkeynes@359 | 1075 | case 0xB:
|
nkeynes@359 | 1076 | { /* OR Rm, Rn */
|
nkeynes@359 | 1077 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1078 | COUNT_INST(I_OR);
|
nkeynes@359 | 1079 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1080 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1081 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1082 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1083 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1084 | }
|
nkeynes@359 | 1085 | break;
|
nkeynes@359 | 1086 | case 0xC:
|
nkeynes@359 | 1087 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 1088 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1089 | COUNT_INST(I_CMPSTR);
|
nkeynes@368 | 1090 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1091 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1092 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 1093 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@669 | 1094 | JE_rel8(target1);
|
nkeynes@669 | 1095 | TEST_r8_r8( R_AH, R_AH );
|
nkeynes@669 | 1096 | JE_rel8(target2);
|
nkeynes@669 | 1097 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@669 | 1098 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@669 | 1099 | JE_rel8(target3);
|
nkeynes@669 | 1100 | TEST_r8_r8( R_AH, R_AH );
|
nkeynes@380 | 1101 | JMP_TARGET(target1);
|
nkeynes@380 | 1102 | JMP_TARGET(target2);
|
nkeynes@380 | 1103 | JMP_TARGET(target3);
|
nkeynes@368 | 1104 | SETE_t();
|
nkeynes@417 | 1105 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1106 | }
|
nkeynes@359 | 1107 | break;
|
nkeynes@359 | 1108 | case 0xD:
|
nkeynes@359 | 1109 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1110 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1111 | COUNT_INST(I_XTRCT);
|
nkeynes@361 | 1112 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1113 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1114 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1115 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1116 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1117 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1118 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1119 | }
|
nkeynes@359 | 1120 | break;
|
nkeynes@359 | 1121 | case 0xE:
|
nkeynes@359 | 1122 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1123 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1124 | COUNT_INST(I_MULUW);
|
nkeynes@374 | 1125 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1126 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1127 | MUL_r32( R_ECX );
|
nkeynes@374 | 1128 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1129 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1130 | }
|
nkeynes@359 | 1131 | break;
|
nkeynes@359 | 1132 | case 0xF:
|
nkeynes@359 | 1133 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1134 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1135 | COUNT_INST(I_MULSW);
|
nkeynes@374 | 1136 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1137 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1138 | MUL_r32( R_ECX );
|
nkeynes@374 | 1139 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1140 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1141 | }
|
nkeynes@359 | 1142 | break;
|
nkeynes@359 | 1143 | default:
|
nkeynes@359 | 1144 | UNDEF();
|
nkeynes@359 | 1145 | break;
|
nkeynes@359 | 1146 | }
|
nkeynes@359 | 1147 | break;
|
nkeynes@359 | 1148 | case 0x3:
|
nkeynes@359 | 1149 | switch( ir&0xF ) {
|
nkeynes@359 | 1150 | case 0x0:
|
nkeynes@359 | 1151 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1152 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1153 | COUNT_INST(I_CMPEQ);
|
nkeynes@359 | 1154 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1155 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1156 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1157 | SETE_t();
|
nkeynes@417 | 1158 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1159 | }
|
nkeynes@359 | 1160 | break;
|
nkeynes@359 | 1161 | case 0x2:
|
nkeynes@359 | 1162 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1163 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1164 | COUNT_INST(I_CMPHS);
|
nkeynes@359 | 1165 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1166 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1167 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1168 | SETAE_t();
|
nkeynes@417 | 1169 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 1170 | }
|
nkeynes@359 | 1171 | break;
|
nkeynes@359 | 1172 | case 0x3:
|
nkeynes@359 | 1173 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1174 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1175 | COUNT_INST(I_CMPGE);
|
nkeynes@359 | 1176 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1177 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1178 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1179 | SETGE_t();
|
nkeynes@417 | 1180 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1181 | }
|
nkeynes@359 | 1182 | break;
|
nkeynes@359 | 1183 | case 0x4:
|
nkeynes@359 | 1184 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1185 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1186 | COUNT_INST(I_DIV1);
|
nkeynes@386 | 1187 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1188 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1189 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1190 | LDC_t();
|
nkeynes@417 | 1191 | }
|
nkeynes@386 | 1192 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1193 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1194 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@669 | 1195 | JE_rel8(mqequal);
|
nkeynes@386 | 1196 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@669 | 1197 | JMP_rel8(end);
|
nkeynes@380 | 1198 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1199 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1200 | JMP_TARGET(end);
|
nkeynes@386 | 1201 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1202 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1203 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1204 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1205 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1206 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1207 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1208 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 1209 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1210 | }
|
nkeynes@359 | 1211 | break;
|
nkeynes@359 | 1212 | case 0x5:
|
nkeynes@359 | 1213 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1214 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1215 | COUNT_INST(I_DMULU);
|
nkeynes@361 | 1216 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1217 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1218 | MUL_r32(R_ECX);
|
nkeynes@361 | 1219 | store_spreg( R_EDX, R_MACH );
|
nkeynes@417 | 1220 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1221 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1222 | }
|
nkeynes@359 | 1223 | break;
|
nkeynes@359 | 1224 | case 0x6:
|
nkeynes@359 | 1225 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1226 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1227 | COUNT_INST(I_CMPHI);
|
nkeynes@359 | 1228 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1229 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1230 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1231 | SETA_t();
|
nkeynes@417 | 1232 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 1233 | }
|
nkeynes@359 | 1234 | break;
|
nkeynes@359 | 1235 | case 0x7:
|
nkeynes@359 | 1236 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1237 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1238 | COUNT_INST(I_CMPGT);
|
nkeynes@359 | 1239 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1240 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1241 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1242 | SETG_t();
|
nkeynes@417 | 1243 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1244 | }
|
nkeynes@359 | 1245 | break;
|
nkeynes@359 | 1246 | case 0x8:
|
nkeynes@359 | 1247 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1248 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1249 | COUNT_INST(I_SUB);
|
nkeynes@359 | 1250 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1251 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1252 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1253 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1254 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1255 | }
|
nkeynes@359 | 1256 | break;
|
nkeynes@359 | 1257 | case 0xA:
|
nkeynes@359 | 1258 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1259 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1260 | COUNT_INST(I_SUBC);
|
nkeynes@359 | 1261 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1262 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 1263 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1264 | LDC_t();
|
nkeynes@417 | 1265 | }
|
nkeynes@359 | 1266 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1267 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1268 | SETC_t();
|
nkeynes@417 | 1269 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1270 | }
|
nkeynes@359 | 1271 | break;
|
nkeynes@359 | 1272 | case 0xB:
|
nkeynes@359 | 1273 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1274 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1275 | COUNT_INST(I_SUBV);
|
nkeynes@359 | 1276 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1277 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1278 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1279 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1280 | SETO_t();
|
nkeynes@417 | 1281 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1282 | }
|
nkeynes@359 | 1283 | break;
|
nkeynes@359 | 1284 | case 0xC:
|
nkeynes@359 | 1285 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1286 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1287 | COUNT_INST(I_ADD);
|
nkeynes@359 | 1288 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1289 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1290 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1291 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1292 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1293 | }
|
nkeynes@359 | 1294 | break;
|
nkeynes@359 | 1295 | case 0xD:
|
nkeynes@359 | 1296 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1297 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1298 | COUNT_INST(I_DMULS);
|
nkeynes@361 | 1299 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1300 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1301 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1302 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1303 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1304 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1305 | }
|
nkeynes@359 | 1306 | break;
|
nkeynes@359 | 1307 | case 0xE:
|
nkeynes@359 | 1308 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1309 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1310 | COUNT_INST(I_ADDC);
|
nkeynes@417 | 1311 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1312 | LDC_t();
|
nkeynes@417 | 1313 | }
|
nkeynes@359 | 1314 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1315 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1316 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1317 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1318 | SETC_t();
|
nkeynes@417 | 1319 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1320 | }
|
nkeynes@359 | 1321 | break;
|
nkeynes@359 | 1322 | case 0xF:
|
nkeynes@359 | 1323 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1324 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 1325 | COUNT_INST(I_ADDV);
|
nkeynes@359 | 1326 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1327 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1328 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1329 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1330 | SETO_t();
|
nkeynes@417 | 1331 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1332 | }
|
nkeynes@359 | 1333 | break;
|
nkeynes@359 | 1334 | default:
|
nkeynes@359 | 1335 | UNDEF();
|
nkeynes@359 | 1336 | break;
|
nkeynes@359 | 1337 | }
|
nkeynes@359 | 1338 | break;
|
nkeynes@359 | 1339 | case 0x4:
|
nkeynes@359 | 1340 | switch( ir&0xF ) {
|
nkeynes@359 | 1341 | case 0x0:
|
nkeynes@359 | 1342 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1343 | case 0x0:
|
nkeynes@359 | 1344 | { /* SHLL Rn */
|
nkeynes@359 | 1345 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1346 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 1347 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1348 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1349 | SETC_t();
|
nkeynes@359 | 1350 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1351 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1352 | }
|
nkeynes@359 | 1353 | break;
|
nkeynes@359 | 1354 | case 0x1:
|
nkeynes@359 | 1355 | { /* DT Rn */
|
nkeynes@359 | 1356 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1357 | COUNT_INST(I_DT);
|
nkeynes@359 | 1358 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1359 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1360 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1361 | SETE_t();
|
nkeynes@417 | 1362 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1363 | }
|
nkeynes@359 | 1364 | break;
|
nkeynes@359 | 1365 | case 0x2:
|
nkeynes@359 | 1366 | { /* SHAL Rn */
|
nkeynes@359 | 1367 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1368 | COUNT_INST(I_SHAL);
|
nkeynes@359 | 1369 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1370 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1371 | SETC_t();
|
nkeynes@359 | 1372 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1373 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1374 | }
|
nkeynes@359 | 1375 | break;
|
nkeynes@359 | 1376 | default:
|
nkeynes@359 | 1377 | UNDEF();
|
nkeynes@359 | 1378 | break;
|
nkeynes@359 | 1379 | }
|
nkeynes@359 | 1380 | break;
|
nkeynes@359 | 1381 | case 0x1:
|
nkeynes@359 | 1382 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1383 | case 0x0:
|
nkeynes@359 | 1384 | { /* SHLR Rn */
|
nkeynes@359 | 1385 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1386 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 1387 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1388 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1389 | SETC_t();
|
nkeynes@359 | 1390 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1391 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1392 | }
|
nkeynes@359 | 1393 | break;
|
nkeynes@359 | 1394 | case 0x1:
|
nkeynes@359 | 1395 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1396 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1397 | COUNT_INST(I_CMPPZ);
|
nkeynes@359 | 1398 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1399 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1400 | SETGE_t();
|
nkeynes@417 | 1401 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1402 | }
|
nkeynes@359 | 1403 | break;
|
nkeynes@359 | 1404 | case 0x2:
|
nkeynes@359 | 1405 | { /* SHAR Rn */
|
nkeynes@359 | 1406 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1407 | COUNT_INST(I_SHAR);
|
nkeynes@359 | 1408 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1409 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1410 | SETC_t();
|
nkeynes@359 | 1411 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1412 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1413 | }
|
nkeynes@359 | 1414 | break;
|
nkeynes@359 | 1415 | default:
|
nkeynes@359 | 1416 | UNDEF();
|
nkeynes@359 | 1417 | break;
|
nkeynes@359 | 1418 | }
|
nkeynes@359 | 1419 | break;
|
nkeynes@359 | 1420 | case 0x2:
|
nkeynes@359 | 1421 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1422 | case 0x0:
|
nkeynes@359 | 1423 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1424 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1425 | COUNT_INST(I_STSM);
|
nkeynes@586 | 1426 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1427 | check_walign32( R_EAX );
|
nkeynes@586 | 1428 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1429 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1430 | load_spreg( R_EDX, R_MACH );
|
nkeynes@586 | 1431 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1432 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1433 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1434 | }
|
nkeynes@359 | 1435 | break;
|
nkeynes@359 | 1436 | case 0x1:
|
nkeynes@359 | 1437 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1438 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1439 | COUNT_INST(I_STSM);
|
nkeynes@586 | 1440 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1441 | check_walign32( R_EAX );
|
nkeynes@586 | 1442 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1443 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1444 | load_spreg( R_EDX, R_MACL );
|
nkeynes@586 | 1445 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1446 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1447 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1448 | }
|
nkeynes@359 | 1449 | break;
|
nkeynes@359 | 1450 | case 0x2:
|
nkeynes@359 | 1451 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1452 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1453 | COUNT_INST(I_STSM);
|
nkeynes@586 | 1454 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1455 | check_walign32( R_EAX );
|
nkeynes@586 | 1456 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1457 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1458 | load_spreg( R_EDX, R_PR );
|
nkeynes@586 | 1459 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1460 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1461 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1462 | }
|
nkeynes@359 | 1463 | break;
|
nkeynes@359 | 1464 | case 0x3:
|
nkeynes@359 | 1465 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1466 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1467 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1468 | check_priv();
|
nkeynes@586 | 1469 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1470 | check_walign32( R_EAX );
|
nkeynes@586 | 1471 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1472 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1473 | load_spreg( R_EDX, R_SGR );
|
nkeynes@586 | 1474 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1475 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1476 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1477 | }
|
nkeynes@359 | 1478 | break;
|
nkeynes@359 | 1479 | case 0x5:
|
nkeynes@359 | 1480 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1481 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1482 | COUNT_INST(I_STSM);
|
nkeynes@626 | 1483 | check_fpuen();
|
nkeynes@586 | 1484 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1485 | check_walign32( R_EAX );
|
nkeynes@586 | 1486 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1487 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1488 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@586 | 1489 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1490 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1491 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1492 | }
|
nkeynes@359 | 1493 | break;
|
nkeynes@359 | 1494 | case 0x6:
|
nkeynes@359 | 1495 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1496 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@673 | 1497 | COUNT_INST(I_STSFPSCRM);
|
nkeynes@626 | 1498 | check_fpuen();
|
nkeynes@586 | 1499 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1500 | check_walign32( R_EAX );
|
nkeynes@586 | 1501 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1502 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1503 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@586 | 1504 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1505 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1506 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1507 | }
|
nkeynes@359 | 1508 | break;
|
nkeynes@359 | 1509 | case 0xF:
|
nkeynes@359 | 1510 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1511 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1512 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1513 | check_priv();
|
nkeynes@586 | 1514 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1515 | check_walign32( R_EAX );
|
nkeynes@586 | 1516 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1517 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1518 | load_spreg( R_EDX, R_DBR );
|
nkeynes@586 | 1519 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1520 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1521 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1522 | }
|
nkeynes@359 | 1523 | break;
|
nkeynes@359 | 1524 | default:
|
nkeynes@359 | 1525 | UNDEF();
|
nkeynes@359 | 1526 | break;
|
nkeynes@359 | 1527 | }
|
nkeynes@359 | 1528 | break;
|
nkeynes@359 | 1529 | case 0x3:
|
nkeynes@359 | 1530 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1531 | case 0x0:
|
nkeynes@359 | 1532 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1533 | case 0x0:
|
nkeynes@359 | 1534 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1535 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1536 | COUNT_INST(I_STCSRM);
|
nkeynes@586 | 1537 | check_priv();
|
nkeynes@586 | 1538 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1539 | check_walign32( R_EAX );
|
nkeynes@586 | 1540 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1541 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1542 | PUSH_realigned_r32( R_EAX );
|
nkeynes@395 | 1543 | call_func0( sh4_read_sr );
|
nkeynes@586 | 1544 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 1545 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@374 | 1546 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1547 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1548 | }
|
nkeynes@359 | 1549 | break;
|
nkeynes@359 | 1550 | case 0x1:
|
nkeynes@359 | 1551 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1552 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1553 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1554 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1555 | check_walign32( R_EAX );
|
nkeynes@586 | 1556 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1557 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1558 | load_spreg( R_EDX, R_GBR );
|
nkeynes@586 | 1559 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1560 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1561 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1562 | }
|
nkeynes@359 | 1563 | break;
|
nkeynes@359 | 1564 | case 0x2:
|
nkeynes@359 | 1565 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1566 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1567 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1568 | check_priv();
|
nkeynes@586 | 1569 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1570 | check_walign32( R_EAX );
|
nkeynes@586 | 1571 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1572 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1573 | load_spreg( R_EDX, R_VBR );
|
nkeynes@586 | 1574 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1575 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1576 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1577 | }
|
nkeynes@359 | 1578 | break;
|
nkeynes@359 | 1579 | case 0x3:
|
nkeynes@359 | 1580 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1581 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1582 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1583 | check_priv();
|
nkeynes@586 | 1584 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1585 | check_walign32( R_EAX );
|
nkeynes@586 | 1586 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1587 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1588 | load_spreg( R_EDX, R_SSR );
|
nkeynes@586 | 1589 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1590 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1591 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1592 | }
|
nkeynes@359 | 1593 | break;
|
nkeynes@359 | 1594 | case 0x4:
|
nkeynes@359 | 1595 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1596 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1597 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1598 | check_priv();
|
nkeynes@586 | 1599 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1600 | check_walign32( R_EAX );
|
nkeynes@586 | 1601 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1602 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1603 | load_spreg( R_EDX, R_SPC );
|
nkeynes@586 | 1604 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1605 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1606 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1607 | }
|
nkeynes@359 | 1608 | break;
|
nkeynes@359 | 1609 | default:
|
nkeynes@359 | 1610 | UNDEF();
|
nkeynes@359 | 1611 | break;
|
nkeynes@359 | 1612 | }
|
nkeynes@359 | 1613 | break;
|
nkeynes@359 | 1614 | case 0x1:
|
nkeynes@359 | 1615 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1616 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@671 | 1617 | COUNT_INST(I_STCM);
|
nkeynes@586 | 1618 | check_priv();
|
nkeynes@586 | 1619 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1620 | check_walign32( R_EAX );
|
nkeynes@586 | 1621 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1622 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1623 | load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@586 | 1624 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1625 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1626 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1627 | }
|
nkeynes@359 | 1628 | break;
|
nkeynes@359 | 1629 | }
|
nkeynes@359 | 1630 | break;
|
nkeynes@359 | 1631 | case 0x4:
|
nkeynes@359 | 1632 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1633 | case 0x0:
|
nkeynes@359 | 1634 | { /* ROTL Rn */
|
nkeynes@359 | 1635 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1636 | COUNT_INST(I_ROTL);
|
nkeynes@359 | 1637 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1638 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1639 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1640 | SETC_t();
|
nkeynes@417 | 1641 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1642 | }
|
nkeynes@359 | 1643 | break;
|
nkeynes@359 | 1644 | case 0x2:
|
nkeynes@359 | 1645 | { /* ROTCL Rn */
|
nkeynes@359 | 1646 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1647 | COUNT_INST(I_ROTCL);
|
nkeynes@359 | 1648 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1649 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1650 | LDC_t();
|
nkeynes@417 | 1651 | }
|
nkeynes@359 | 1652 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1653 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1654 | SETC_t();
|
nkeynes@417 | 1655 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1656 | }
|
nkeynes@359 | 1657 | break;
|
nkeynes@359 | 1658 | default:
|
nkeynes@359 | 1659 | UNDEF();
|
nkeynes@359 | 1660 | break;
|
nkeynes@359 | 1661 | }
|
nkeynes@359 | 1662 | break;
|
nkeynes@359 | 1663 | case 0x5:
|
nkeynes@359 | 1664 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1665 | case 0x0:
|
nkeynes@359 | 1666 | { /* ROTR Rn */
|
nkeynes@359 | 1667 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1668 | COUNT_INST(I_ROTR);
|
nkeynes@359 | 1669 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1670 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1671 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1672 | SETC_t();
|
nkeynes@417 | 1673 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1674 | }
|
nkeynes@359 | 1675 | break;
|
nkeynes@359 | 1676 | case 0x1:
|
nkeynes@359 | 1677 | { /* CMP/PL Rn */
|
nkeynes@359 | 1678 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1679 | COUNT_INST(I_CMPPL);
|
nkeynes@359 | 1680 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1681 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1682 | SETG_t();
|
nkeynes@417 | 1683 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1684 | }
|
nkeynes@359 | 1685 | break;
|
nkeynes@359 | 1686 | case 0x2:
|
nkeynes@359 | 1687 | { /* ROTCR Rn */
|
nkeynes@359 | 1688 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1689 | COUNT_INST(I_ROTCR);
|
nkeynes@359 | 1690 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1691 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1692 | LDC_t();
|
nkeynes@417 | 1693 | }
|
nkeynes@359 | 1694 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1695 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1696 | SETC_t();
|
nkeynes@417 | 1697 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1698 | }
|
nkeynes@359 | 1699 | break;
|
nkeynes@359 | 1700 | default:
|
nkeynes@359 | 1701 | UNDEF();
|
nkeynes@359 | 1702 | break;
|
nkeynes@359 | 1703 | }
|
nkeynes@359 | 1704 | break;
|
nkeynes@359 | 1705 | case 0x6:
|
nkeynes@359 | 1706 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1707 | case 0x0:
|
nkeynes@359 | 1708 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1709 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1710 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 1711 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1712 | check_ralign32( R_EAX );
|
nkeynes@586 | 1713 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1714 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1715 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1716 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1717 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1718 | }
|
nkeynes@359 | 1719 | break;
|
nkeynes@359 | 1720 | case 0x1:
|
nkeynes@359 | 1721 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1722 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1723 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 1724 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1725 | check_ralign32( R_EAX );
|
nkeynes@586 | 1726 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1727 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1728 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1729 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1730 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1731 | }
|
nkeynes@359 | 1732 | break;
|
nkeynes@359 | 1733 | case 0x2:
|
nkeynes@359 | 1734 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1735 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1736 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 1737 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1738 | check_ralign32( R_EAX );
|
nkeynes@586 | 1739 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1740 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1741 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1742 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 1743 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1744 | }
|
nkeynes@359 | 1745 | break;
|
nkeynes@359 | 1746 | case 0x3:
|
nkeynes@359 | 1747 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1748 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1749 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1750 | check_priv();
|
nkeynes@359 | 1751 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1752 | check_ralign32( R_EAX );
|
nkeynes@586 | 1753 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1754 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1755 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1756 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1757 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1758 | }
|
nkeynes@359 | 1759 | break;
|
nkeynes@359 | 1760 | case 0x5:
|
nkeynes@359 | 1761 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1762 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1763 | COUNT_INST(I_LDSM);
|
nkeynes@626 | 1764 | check_fpuen();
|
nkeynes@359 | 1765 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1766 | check_ralign32( R_EAX );
|
nkeynes@586 | 1767 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1768 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1769 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1770 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 1771 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1772 | }
|
nkeynes@359 | 1773 | break;
|
nkeynes@359 | 1774 | case 0x6:
|
nkeynes@359 | 1775 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1776 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@673 | 1777 | COUNT_INST(I_LDSFPSCRM);
|
nkeynes@626 | 1778 | check_fpuen();
|
nkeynes@359 | 1779 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1780 | check_ralign32( R_EAX );
|
nkeynes@586 | 1781 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1782 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1783 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 1784 | call_func1( sh4_write_fpscr, R_EAX );
|
nkeynes@417 | 1785 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1786 | }
|
nkeynes@359 | 1787 | break;
|
nkeynes@359 | 1788 | case 0xF:
|
nkeynes@359 | 1789 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1790 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1791 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1792 | check_priv();
|
nkeynes@359 | 1793 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1794 | check_ralign32( R_EAX );
|
nkeynes@586 | 1795 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1796 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1797 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1798 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1799 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1800 | }
|
nkeynes@359 | 1801 | break;
|
nkeynes@359 | 1802 | default:
|
nkeynes@359 | 1803 | UNDEF();
|
nkeynes@359 | 1804 | break;
|
nkeynes@359 | 1805 | }
|
nkeynes@359 | 1806 | break;
|
nkeynes@359 | 1807 | case 0x7:
|
nkeynes@359 | 1808 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1809 | case 0x0:
|
nkeynes@359 | 1810 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1811 | case 0x0:
|
nkeynes@359 | 1812 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1813 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1814 | COUNT_INST(I_LDCSRM);
|
nkeynes@386 | 1815 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1816 | SLOTILLEGAL();
|
nkeynes@386 | 1817 | } else {
|
nkeynes@586 | 1818 | check_priv();
|
nkeynes@386 | 1819 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1820 | check_ralign32( R_EAX );
|
nkeynes@586 | 1821 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1822 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1823 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@386 | 1824 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1825 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1826 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1827 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 1828 | }
|
nkeynes@359 | 1829 | }
|
nkeynes@359 | 1830 | break;
|
nkeynes@359 | 1831 | case 0x1:
|
nkeynes@359 | 1832 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1833 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1834 | COUNT_INST(I_LDCM);
|
nkeynes@359 | 1835 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1836 | check_ralign32( R_EAX );
|
nkeynes@586 | 1837 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1838 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1839 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1840 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 1841 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1842 | }
|
nkeynes@359 | 1843 | break;
|
nkeynes@359 | 1844 | case 0x2:
|
nkeynes@359 | 1845 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1846 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1847 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1848 | check_priv();
|
nkeynes@359 | 1849 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1850 | check_ralign32( R_EAX );
|
nkeynes@586 | 1851 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1852 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1853 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1854 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 1855 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1856 | }
|
nkeynes@359 | 1857 | break;
|
nkeynes@359 | 1858 | case 0x3:
|
nkeynes@359 | 1859 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1860 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1861 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1862 | check_priv();
|
nkeynes@359 | 1863 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1864 | check_ralign32( R_EAX );
|
nkeynes@586 | 1865 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1866 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1867 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1868 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 1869 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1870 | }
|
nkeynes@359 | 1871 | break;
|
nkeynes@359 | 1872 | case 0x4:
|
nkeynes@359 | 1873 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1874 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1875 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1876 | check_priv();
|
nkeynes@359 | 1877 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1878 | check_ralign32( R_EAX );
|
nkeynes@586 | 1879 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1880 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1881 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1882 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 1883 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1884 | }
|
nkeynes@359 | 1885 | break;
|
nkeynes@359 | 1886 | default:
|
nkeynes@359 | 1887 | UNDEF();
|
nkeynes@359 | 1888 | break;
|
nkeynes@359 | 1889 | }
|
nkeynes@359 | 1890 | break;
|
nkeynes@359 | 1891 | case 0x1:
|
nkeynes@359 | 1892 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1893 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@671 | 1894 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 1895 | check_priv();
|
nkeynes@374 | 1896 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1897 | check_ralign32( R_EAX );
|
nkeynes@586 | 1898 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1899 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1900 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@374 | 1901 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 1902 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1903 | }
|
nkeynes@359 | 1904 | break;
|
nkeynes@359 | 1905 | }
|
nkeynes@359 | 1906 | break;
|
nkeynes@359 | 1907 | case 0x8:
|
nkeynes@359 | 1908 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1909 | case 0x0:
|
nkeynes@359 | 1910 | { /* SHLL2 Rn */
|
nkeynes@359 | 1911 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1912 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 1913 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1914 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1915 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1916 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1917 | }
|
nkeynes@359 | 1918 | break;
|
nkeynes@359 | 1919 | case 0x1:
|
nkeynes@359 | 1920 | { /* SHLL8 Rn */
|
nkeynes@359 | 1921 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1922 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 1923 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1924 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1925 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1926 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1927 | }
|
nkeynes@359 | 1928 | break;
|
nkeynes@359 | 1929 | case 0x2:
|
nkeynes@359 | 1930 | { /* SHLL16 Rn */
|
nkeynes@359 | 1931 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1932 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 1933 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1934 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1935 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1936 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1937 | }
|
nkeynes@359 | 1938 | break;
|
nkeynes@359 | 1939 | default:
|
nkeynes@359 | 1940 | UNDEF();
|
nkeynes@359 | 1941 | break;
|
nkeynes@359 | 1942 | }
|
nkeynes@359 | 1943 | break;
|
nkeynes@359 | 1944 | case 0x9:
|
nkeynes@359 | 1945 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1946 | case 0x0:
|
nkeynes@359 | 1947 | { /* SHLR2 Rn */
|
nkeynes@359 | 1948 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1949 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 1950 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1951 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1952 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1953 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1954 | }
|
nkeynes@359 | 1955 | break;
|
nkeynes@359 | 1956 | case 0x1:
|
nkeynes@359 | 1957 | { /* SHLR8 Rn */
|
nkeynes@359 | 1958 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1959 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 1960 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1961 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1962 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1963 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1964 | }
|
nkeynes@359 | 1965 | break;
|
nkeynes@359 | 1966 | case 0x2:
|
nkeynes@359 | 1967 | { /* SHLR16 Rn */
|
nkeynes@359 | 1968 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 1969 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 1970 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1971 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1972 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1973 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1974 | }
|
nkeynes@359 | 1975 | break;
|
nkeynes@359 | 1976 | default:
|
nkeynes@359 | 1977 | UNDEF();
|
nkeynes@359 | 1978 | break;
|
nkeynes@359 | 1979 | }
|
nkeynes@359 | 1980 | break;
|
nkeynes@359 | 1981 | case 0xA:
|
nkeynes@359 | 1982 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1983 | case 0x0:
|
nkeynes@359 | 1984 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1985 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1986 | COUNT_INST(I_LDS);
|
nkeynes@359 | 1987 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1988 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1989 | }
|
nkeynes@359 | 1990 | break;
|
nkeynes@359 | 1991 | case 0x1:
|
nkeynes@359 | 1992 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1993 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 1994 | COUNT_INST(I_LDS);
|
nkeynes@359 | 1995 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1996 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1997 | }
|
nkeynes@359 | 1998 | break;
|
nkeynes@359 | 1999 | case 0x2:
|
nkeynes@359 | 2000 | { /* LDS Rm, PR */
|
nkeynes@359 | 2001 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2002 | COUNT_INST(I_LDS);
|
nkeynes@359 | 2003 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2004 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2005 | }
|
nkeynes@359 | 2006 | break;
|
nkeynes@359 | 2007 | case 0x3:
|
nkeynes@359 | 2008 | { /* LDC Rm, SGR */
|
nkeynes@359 | 2009 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2010 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2011 | check_priv();
|
nkeynes@359 | 2012 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2013 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 2014 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2015 | }
|
nkeynes@359 | 2016 | break;
|
nkeynes@359 | 2017 | case 0x5:
|
nkeynes@359 | 2018 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 2019 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2020 | COUNT_INST(I_LDS);
|
nkeynes@626 | 2021 | check_fpuen();
|
nkeynes@359 | 2022 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2023 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2024 | }
|
nkeynes@359 | 2025 | break;
|
nkeynes@359 | 2026 | case 0x6:
|
nkeynes@359 | 2027 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 2028 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@673 | 2029 | COUNT_INST(I_LDSFPSCR);
|
nkeynes@626 | 2030 | check_fpuen();
|
nkeynes@359 | 2031 | load_reg( R_EAX, Rm );
|
nkeynes@669 | 2032 | call_func1( sh4_write_fpscr, R_EAX );
|
nkeynes@417 | 2033 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2034 | }
|
nkeynes@359 | 2035 | break;
|
nkeynes@359 | 2036 | case 0xF:
|
nkeynes@359 | 2037 | { /* LDC Rm, DBR */
|
nkeynes@359 | 2038 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2039 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2040 | check_priv();
|
nkeynes@359 | 2041 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2042 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 2043 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2044 | }
|
nkeynes@359 | 2045 | break;
|
nkeynes@359 | 2046 | default:
|
nkeynes@359 | 2047 | UNDEF();
|
nkeynes@359 | 2048 | break;
|
nkeynes@359 | 2049 | }
|
nkeynes@359 | 2050 | break;
|
nkeynes@359 | 2051 | case 0xB:
|
nkeynes@359 | 2052 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 2053 | case 0x0:
|
nkeynes@359 | 2054 | { /* JSR @Rn */
|
nkeynes@359 | 2055 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 2056 | COUNT_INST(I_JSR);
|
nkeynes@374 | 2057 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2058 | SLOTILLEGAL();
|
nkeynes@374 | 2059 | } else {
|
nkeynes@590 | 2060 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 2061 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 2062 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 2063 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 2064 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@601 | 2065 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 2066 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2067 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@601 | 2068 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2069 | exit_block_emu(pc+2);
|
nkeynes@601 | 2070 | return 2;
|
nkeynes@601 | 2071 | } else {
|
nkeynes@601 | 2072 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2073 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 2074 | return 4;
|
nkeynes@601 | 2075 | }
|
nkeynes@374 | 2076 | }
|
nkeynes@359 | 2077 | }
|
nkeynes@359 | 2078 | break;
|
nkeynes@359 | 2079 | case 0x1:
|
nkeynes@359 | 2080 | { /* TAS.B @Rn */
|
nkeynes@359 | 2081 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 2082 | COUNT_INST(I_TASB);
|
nkeynes@586 | 2083 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2084 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2085 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 2086 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@361 | 2087 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 2088 | SETE_t();
|
nkeynes@361 | 2089 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@586 | 2090 | POP_realigned_r32( R_ECX );
|
nkeynes@361 | 2091 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2092 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2093 | }
|
nkeynes@359 | 2094 | break;
|
nkeynes@359 | 2095 | case 0x2:
|
nkeynes@359 | 2096 | { /* JMP @Rn */
|
nkeynes@359 | 2097 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@671 | 2098 | COUNT_INST(I_JMP);
|
nkeynes@374 | 2099 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2100 | SLOTILLEGAL();
|
nkeynes@374 | 2101 | } else {
|
nkeynes@408 | 2102 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 2103 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 2104 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 2105 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2106 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2107 | exit_block_emu(pc+2);
|
nkeynes@601 | 2108 | return 2;
|
nkeynes@601 | 2109 | } else {
|
nkeynes@601 | 2110 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2111 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 2112 | return 4;
|
nkeynes@601 | 2113 | }
|
nkeynes@374 | 2114 | }
|
nkeynes@359 | 2115 | }
|
nkeynes@359 | 2116 | break;
|
nkeynes@359 | 2117 | default:
|
nkeynes@359 | 2118 | UNDEF();
|
nkeynes@359 | 2119 | break;
|
nkeynes@359 | 2120 | }
|
nkeynes@359 | 2121 | break;
|
nkeynes@359 | 2122 | case 0xC:
|
nkeynes@359 | 2123 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 2124 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2125 | COUNT_INST(I_SHAD);
|
nkeynes@359 | 2126 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 2127 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 2128 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2129 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@669 | 2130 | JGE_rel8(doshl);
|
nkeynes@361 | 2131 |
|
nkeynes@361 | 2132 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 2133 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@669 | 2134 | JE_rel8(emptysar); // 2
|
nkeynes@361 | 2135 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@669 | 2136 | JMP_rel8(end); // 2
|
nkeynes@386 | 2137 |
|
nkeynes@386 | 2138 | JMP_TARGET(emptysar);
|
nkeynes@386 | 2139 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@669 | 2140 | JMP_rel8(end2);
|
nkeynes@386 | 2141 |
|
nkeynes@380 | 2142 | JMP_TARGET(doshl);
|
nkeynes@361 | 2143 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 2144 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 2145 | JMP_TARGET(end);
|
nkeynes@386 | 2146 | JMP_TARGET(end2);
|
nkeynes@361 | 2147 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2148 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2149 | }
|
nkeynes@359 | 2150 | break;
|
nkeynes@359 | 2151 | case 0xD:
|
nkeynes@359 | 2152 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 2153 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2154 | COUNT_INST(I_SHLD);
|
nkeynes@368 | 2155 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 2156 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2157 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@669 | 2158 | JGE_rel8(doshl);
|
nkeynes@368 | 2159 |
|
nkeynes@386 | 2160 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 2161 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@669 | 2162 | JE_rel8(emptyshr );
|
nkeynes@386 | 2163 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@669 | 2164 | JMP_rel8(end); // 2
|
nkeynes@386 | 2165 |
|
nkeynes@386 | 2166 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 2167 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@669 | 2168 | JMP_rel8(end2);
|
nkeynes@386 | 2169 |
|
nkeynes@386 | 2170 | JMP_TARGET(doshl);
|
nkeynes@386 | 2171 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2172 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2173 | JMP_TARGET(end);
|
nkeynes@386 | 2174 | JMP_TARGET(end2);
|
nkeynes@368 | 2175 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2176 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2177 | }
|
nkeynes@359 | 2178 | break;
|
nkeynes@359 | 2179 | case 0xE:
|
nkeynes@359 | 2180 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 2181 | case 0x0:
|
nkeynes@359 | 2182 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 2183 | case 0x0:
|
nkeynes@359 | 2184 | { /* LDC Rm, SR */
|
nkeynes@359 | 2185 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2186 | COUNT_INST(I_LDCSR);
|
nkeynes@386 | 2187 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2188 | SLOTILLEGAL();
|
nkeynes@386 | 2189 | } else {
|
nkeynes@386 | 2190 | check_priv();
|
nkeynes@386 | 2191 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2192 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2193 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2194 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2195 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2196 | }
|
nkeynes@359 | 2197 | }
|
nkeynes@359 | 2198 | break;
|
nkeynes@359 | 2199 | case 0x1:
|
nkeynes@359 | 2200 | { /* LDC Rm, GBR */
|
nkeynes@359 | 2201 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2202 | COUNT_INST(I_LDC);
|
nkeynes@359 | 2203 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2204 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2205 | }
|
nkeynes@359 | 2206 | break;
|
nkeynes@359 | 2207 | case 0x2:
|
nkeynes@359 | 2208 | { /* LDC Rm, VBR */
|
nkeynes@359 | 2209 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2210 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2211 | check_priv();
|
nkeynes@359 | 2212 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2213 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2214 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2215 | }
|
nkeynes@359 | 2216 | break;
|
nkeynes@359 | 2217 | case 0x3:
|
nkeynes@359 | 2218 | { /* LDC Rm, SSR */
|
nkeynes@359 | 2219 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2220 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2221 | check_priv();
|
nkeynes@359 | 2222 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2223 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2224 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2225 | }
|
nkeynes@359 | 2226 | break;
|
nkeynes@359 | 2227 | case 0x4:
|
nkeynes@359 | 2228 | { /* LDC Rm, SPC */
|
nkeynes@359 | 2229 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@671 | 2230 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2231 | check_priv();
|
nkeynes@359 | 2232 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2233 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2234 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2235 | }
|
nkeynes@359 | 2236 | break;
|
nkeynes@359 | 2237 | default:
|
nkeynes@359 | 2238 | UNDEF();
|
nkeynes@359 | 2239 | break;
|
nkeynes@359 | 2240 | }
|
nkeynes@359 | 2241 | break;
|
nkeynes@359 | 2242 | case 0x1:
|
nkeynes@359 | 2243 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2244 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@671 | 2245 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2246 | check_priv();
|
nkeynes@374 | 2247 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2248 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2249 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2250 | }
|
nkeynes@359 | 2251 | break;
|
nkeynes@359 | 2252 | }
|
nkeynes@359 | 2253 | break;
|
nkeynes@359 | 2254 | case 0xF:
|
nkeynes@359 | 2255 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2256 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2257 | COUNT_INST(I_MACW);
|
nkeynes@586 | 2258 | if( Rm == Rn ) {
|
nkeynes@586 | 2259 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2260 | check_ralign16( R_EAX );
|
nkeynes@586 | 2261 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2262 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 2263 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2264 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@596 | 2265 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 2266 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2267 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 2268 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 2269 | } else {
|
nkeynes@586 | 2270 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2271 | check_ralign16( R_EAX );
|
nkeynes@586 | 2272 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 2273 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 2274 | check_ralign16( R_ECX );
|
nkeynes@586 | 2275 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 2276 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 2277 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2278 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2279 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2280 | }
|
nkeynes@586 | 2281 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2282 | POP_r32( R_ECX );
|
nkeynes@586 | 2283 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2284 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@547 | 2285 | POP_realigned_r32( R_ECX );
|
nkeynes@386 | 2286 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2287 |
|
nkeynes@386 | 2288 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2289 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@669 | 2290 | JE_rel8( nosat );
|
nkeynes@386 | 2291 |
|
nkeynes@386 | 2292 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 2293 | JNO_rel8( end ); // 2
|
nkeynes@386 | 2294 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2295 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@669 | 2296 | JS_rel8( positive ); // 2
|
nkeynes@386 | 2297 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2298 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 2299 | JMP_rel8(end2); // 2
|
nkeynes@386 | 2300 |
|
nkeynes@386 | 2301 | JMP_TARGET(positive);
|
nkeynes@386 | 2302 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2303 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 2304 | JMP_rel8(end3); // 2
|
nkeynes@386 | 2305 |
|
nkeynes@386 | 2306 | JMP_TARGET(nosat);
|
nkeynes@386 | 2307 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2308 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2309 | JMP_TARGET(end);
|
nkeynes@386 | 2310 | JMP_TARGET(end2);
|
nkeynes@386 | 2311 | JMP_TARGET(end3);
|
nkeynes@417 | 2312 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2313 | }
|
nkeynes@359 | 2314 | break;
|
nkeynes@359 | 2315 | }
|
nkeynes@359 | 2316 | break;
|
nkeynes@359 | 2317 | case 0x5:
|
nkeynes@359 | 2318 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2319 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@671 | 2320 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 2321 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2322 | ADD_imm8s_r32( disp, R_EAX );
|
nkeynes@586 | 2323 | check_ralign32( R_EAX );
|
nkeynes@586 | 2324 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2325 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2326 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2327 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2328 | }
|
nkeynes@359 | 2329 | break;
|
nkeynes@359 | 2330 | case 0x6:
|
nkeynes@359 | 2331 | switch( ir&0xF ) {
|
nkeynes@359 | 2332 | case 0x0:
|
nkeynes@359 | 2333 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2334 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2335 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2336 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2337 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2338 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@386 | 2339 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2340 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2341 | }
|
nkeynes@359 | 2342 | break;
|
nkeynes@359 | 2343 | case 0x1:
|
nkeynes@359 | 2344 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2345 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2346 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 2347 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2348 | check_ralign16( R_EAX );
|
nkeynes@586 | 2349 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2350 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2351 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2352 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2353 | }
|
nkeynes@359 | 2354 | break;
|
nkeynes@359 | 2355 | case 0x2:
|
nkeynes@359 | 2356 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2357 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2358 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 2359 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2360 | check_ralign32( R_EAX );
|
nkeynes@586 | 2361 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2362 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2363 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2364 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2365 | }
|
nkeynes@359 | 2366 | break;
|
nkeynes@359 | 2367 | case 0x3:
|
nkeynes@359 | 2368 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2369 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2370 | COUNT_INST(I_MOV);
|
nkeynes@359 | 2371 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2372 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2373 | }
|
nkeynes@359 | 2374 | break;
|
nkeynes@359 | 2375 | case 0x4:
|
nkeynes@359 | 2376 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2377 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2378 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2379 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2380 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2381 | ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2382 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2383 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2384 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2385 | }
|
nkeynes@359 | 2386 | break;
|
nkeynes@359 | 2387 | case 0x5:
|
nkeynes@359 | 2388 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2389 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2390 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 2391 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2392 | check_ralign16( R_EAX );
|
nkeynes@586 | 2393 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2394 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2395 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2396 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2397 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2398 | }
|
nkeynes@359 | 2399 | break;
|
nkeynes@359 | 2400 | case 0x6:
|
nkeynes@359 | 2401 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2402 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2403 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 2404 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2405 | check_ralign32( R_EAX );
|
nkeynes@586 | 2406 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2407 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2408 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2409 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2410 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2411 | }
|
nkeynes@359 | 2412 | break;
|
nkeynes@359 | 2413 | case 0x7:
|
nkeynes@359 | 2414 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2415 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2416 | COUNT_INST(I_NOT);
|
nkeynes@359 | 2417 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2418 | NOT_r32( R_EAX );
|
nkeynes@359 | 2419 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2420 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2421 | }
|
nkeynes@359 | 2422 | break;
|
nkeynes@359 | 2423 | case 0x8:
|
nkeynes@359 | 2424 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2425 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2426 | COUNT_INST(I_SWAPB);
|
nkeynes@359 | 2427 | load_reg( R_EAX, Rm );
|
nkeynes@601 | 2428 | XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
|
nkeynes@359 | 2429 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2430 | }
|
nkeynes@359 | 2431 | break;
|
nkeynes@359 | 2432 | case 0x9:
|
nkeynes@359 | 2433 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2434 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2435 | COUNT_INST(I_SWAPB);
|
nkeynes@359 | 2436 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2437 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2438 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2439 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2440 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2441 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 2442 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2443 | }
|
nkeynes@359 | 2444 | break;
|
nkeynes@359 | 2445 | case 0xA:
|
nkeynes@359 | 2446 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2447 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2448 | COUNT_INST(I_NEGC);
|
nkeynes@359 | 2449 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2450 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2451 | LDC_t();
|
nkeynes@359 | 2452 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2453 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2454 | SETC_t();
|
nkeynes@417 | 2455 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 2456 | }
|
nkeynes@359 | 2457 | break;
|
nkeynes@359 | 2458 | case 0xB:
|
nkeynes@359 | 2459 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2460 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2461 | COUNT_INST(I_NEG);
|
nkeynes@359 | 2462 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2463 | NEG_r32( R_EAX );
|
nkeynes@359 | 2464 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2465 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2466 | }
|
nkeynes@359 | 2467 | break;
|
nkeynes@359 | 2468 | case 0xC:
|
nkeynes@359 | 2469 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2470 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2471 | COUNT_INST(I_EXTUB);
|
nkeynes@361 | 2472 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2473 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2474 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2475 | }
|
nkeynes@359 | 2476 | break;
|
nkeynes@359 | 2477 | case 0xD:
|
nkeynes@359 | 2478 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2479 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2480 | COUNT_INST(I_EXTUW);
|
nkeynes@361 | 2481 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2482 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2483 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2484 | }
|
nkeynes@359 | 2485 | break;
|
nkeynes@359 | 2486 | case 0xE:
|
nkeynes@359 | 2487 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2488 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2489 | COUNT_INST(I_EXTSB);
|
nkeynes@359 | 2490 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2491 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2492 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2493 | }
|
nkeynes@359 | 2494 | break;
|
nkeynes@359 | 2495 | case 0xF:
|
nkeynes@359 | 2496 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2497 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 2498 | COUNT_INST(I_EXTSW);
|
nkeynes@361 | 2499 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2500 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2501 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2502 | }
|
nkeynes@359 | 2503 | break;
|
nkeynes@359 | 2504 | }
|
nkeynes@359 | 2505 | break;
|
nkeynes@359 | 2506 | case 0x7:
|
nkeynes@359 | 2507 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2508 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@671 | 2509 | COUNT_INST(I_ADDI);
|
nkeynes@359 | 2510 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2511 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2512 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2513 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2514 | }
|
nkeynes@359 | 2515 | break;
|
nkeynes@359 | 2516 | case 0x8:
|
nkeynes@359 | 2517 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2518 | case 0x0:
|
nkeynes@359 | 2519 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2520 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@671 | 2521 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2522 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2523 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2524 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2525 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2526 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2527 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2528 | }
|
nkeynes@359 | 2529 | break;
|
nkeynes@359 | 2530 | case 0x1:
|
nkeynes@359 | 2531 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2532 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@671 | 2533 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 2534 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2535 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2536 | check_walign16( R_EAX );
|
nkeynes@586 | 2537 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2538 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2539 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2540 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2541 | }
|
nkeynes@359 | 2542 | break;
|
nkeynes@359 | 2543 | case 0x4:
|
nkeynes@359 | 2544 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2545 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@671 | 2546 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2547 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2548 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2549 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2550 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2551 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2552 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2553 | }
|
nkeynes@359 | 2554 | break;
|
nkeynes@359 | 2555 | case 0x5:
|
nkeynes@359 | 2556 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2557 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@671 | 2558 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 2559 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2560 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2561 | check_ralign16( R_EAX );
|
nkeynes@586 | 2562 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2563 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2564 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2565 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2566 | }
|
nkeynes@359 | 2567 | break;
|
nkeynes@359 | 2568 | case 0x8:
|
nkeynes@359 | 2569 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2570 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@671 | 2571 | COUNT_INST(I_CMPEQI);
|
nkeynes@359 | 2572 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2573 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2574 | SETE_t();
|
nkeynes@417 | 2575 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2576 | }
|
nkeynes@359 | 2577 | break;
|
nkeynes@359 | 2578 | case 0x9:
|
nkeynes@359 | 2579 | { /* BT disp */
|
nkeynes@359 | 2580 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@671 | 2581 | COUNT_INST(I_BT);
|
nkeynes@374 | 2582 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2583 | SLOTILLEGAL();
|
nkeynes@374 | 2584 | } else {
|
nkeynes@586 | 2585 | sh4vma_t target = disp + pc + 4;
|
nkeynes@669 | 2586 | JF_rel8( nottaken );
|
nkeynes@586 | 2587 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2588 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2589 | return 2;
|
nkeynes@374 | 2590 | }
|
nkeynes@359 | 2591 | }
|
nkeynes@359 | 2592 | break;
|
nkeynes@359 | 2593 | case 0xB:
|
nkeynes@359 | 2594 | { /* BF disp */
|
nkeynes@359 | 2595 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@671 | 2596 | COUNT_INST(I_BF);
|
nkeynes@374 | 2597 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2598 | SLOTILLEGAL();
|
nkeynes@374 | 2599 | } else {
|
nkeynes@586 | 2600 | sh4vma_t target = disp + pc + 4;
|
nkeynes@669 | 2601 | JT_rel8( nottaken );
|
nkeynes@586 | 2602 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2603 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2604 | return 2;
|
nkeynes@374 | 2605 | }
|
nkeynes@359 | 2606 | }
|
nkeynes@359 | 2607 | break;
|
nkeynes@359 | 2608 | case 0xD:
|
nkeynes@359 | 2609 | { /* BT/S disp */
|
nkeynes@359 | 2610 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@671 | 2611 | COUNT_INST(I_BTS);
|
nkeynes@374 | 2612 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2613 | SLOTILLEGAL();
|
nkeynes@374 | 2614 | } else {
|
nkeynes@590 | 2615 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@601 | 2616 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2617 | load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
|
nkeynes@669 | 2618 | JF_rel8(nottaken);
|
nkeynes@601 | 2619 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 2620 | JMP_TARGET(nottaken);
|
nkeynes@601 | 2621 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@601 | 2622 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 2623 | exit_block_emu(pc+2);
|
nkeynes@601 | 2624 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2625 | return 2;
|
nkeynes@601 | 2626 | } else {
|
nkeynes@601 | 2627 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@601 | 2628 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@601 | 2629 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@601 | 2630 | }
|
nkeynes@601 | 2631 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
|
nkeynes@601 | 2632 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2633 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 2634 | // not taken
|
nkeynes@601 | 2635 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@601 | 2636 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2637 | return 4;
|
nkeynes@417 | 2638 | }
|
nkeynes@374 | 2639 | }
|
nkeynes@359 | 2640 | }
|
nkeynes@359 | 2641 | break;
|
nkeynes@359 | 2642 | case 0xF:
|
nkeynes@359 | 2643 | { /* BF/S disp */
|
nkeynes@359 | 2644 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@671 | 2645 | COUNT_INST(I_BFS);
|
nkeynes@374 | 2646 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2647 | SLOTILLEGAL();
|
nkeynes@374 | 2648 | } else {
|
nkeynes@590 | 2649 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@601 | 2650 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2651 | load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
|
nkeynes@669 | 2652 | JT_rel8(nottaken);
|
nkeynes@601 | 2653 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 2654 | JMP_TARGET(nottaken);
|
nkeynes@601 | 2655 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@601 | 2656 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 2657 | exit_block_emu(pc+2);
|
nkeynes@601 | 2658 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2659 | return 2;
|
nkeynes@601 | 2660 | } else {
|
nkeynes@601 | 2661 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@601 | 2662 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@601 | 2663 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@601 | 2664 | }
|
nkeynes@601 | 2665 | sh4vma_t target = disp + pc + 4;
|
nkeynes@601 | 2666 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
|
nkeynes@601 | 2667 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2668 | exit_block_rel( target, pc+4 );
|
nkeynes@601 | 2669 |
|
nkeynes@601 | 2670 | // not taken
|
nkeynes@601 | 2671 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@601 | 2672 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 2673 | return 4;
|
nkeynes@417 | 2674 | }
|
nkeynes@374 | 2675 | }
|
nkeynes@359 | 2676 | }
|
nkeynes@359 | 2677 | break;
|
nkeynes@359 | 2678 | default:
|
nkeynes@359 | 2679 | UNDEF();
|
nkeynes@359 | 2680 | break;
|
nkeynes@359 | 2681 | }
|
nkeynes@359 | 2682 | break;
|
nkeynes@359 | 2683 | case 0x9:
|
nkeynes@359 | 2684 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2685 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@671 | 2686 | COUNT_INST(I_MOVW);
|
nkeynes@374 | 2687 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2688 | SLOTILLEGAL();
|
nkeynes@374 | 2689 | } else {
|
nkeynes@586 | 2690 | // See comments for MOV.L @(disp, PC), Rn
|
nkeynes@586 | 2691 | uint32_t target = pc + disp + 4;
|
nkeynes@586 | 2692 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2693 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@586 | 2694 | MOV_moff32_EAX( ptr );
|
nkeynes@586 | 2695 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@586 | 2696 | } else {
|
nkeynes@586 | 2697 | load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
|
nkeynes@586 | 2698 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 2699 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2700 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2701 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@586 | 2702 | }
|
nkeynes@374 | 2703 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2704 | }
|
nkeynes@359 | 2705 | }
|
nkeynes@359 | 2706 | break;
|
nkeynes@359 | 2707 | case 0xA:
|
nkeynes@359 | 2708 | { /* BRA disp */
|
nkeynes@359 | 2709 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@671 | 2710 | COUNT_INST(I_BRA);
|
nkeynes@374 | 2711 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2712 | SLOTILLEGAL();
|
nkeynes@374 | 2713 | } else {
|
nkeynes@590 | 2714 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 2715 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2716 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2717 | load_spreg( R_EAX, R_PC );
|
nkeynes@601 | 2718 | ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@601 | 2719 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 2720 | exit_block_emu(pc+2);
|
nkeynes@601 | 2721 | return 2;
|
nkeynes@601 | 2722 | } else {
|
nkeynes@601 | 2723 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 2724 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 2725 | return 4;
|
nkeynes@601 | 2726 | }
|
nkeynes@374 | 2727 | }
|
nkeynes@359 | 2728 | }
|
nkeynes@359 | 2729 | break;
|
nkeynes@359 | 2730 | case 0xB:
|
nkeynes@359 | 2731 | { /* BSR disp */
|
nkeynes@359 | 2732 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@671 | 2733 | COUNT_INST(I_BSR);
|
nkeynes@374 | 2734 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2735 | SLOTILLEGAL();
|
nkeynes@374 | 2736 | } else {
|
nkeynes@590 | 2737 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 2738 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 2739 | store_spreg( R_EAX, R_PR );
|
nkeynes@590 | 2740 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 2741 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 2742 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@601 | 2743 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 2744 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 2745 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 2746 | exit_block_emu(pc+2);
|
nkeynes@601 | 2747 | return 2;
|
nkeynes@601 | 2748 | } else {
|
nkeynes@601 | 2749 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 2750 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 2751 | return 4;
|
nkeynes@601 | 2752 | }
|
nkeynes@374 | 2753 | }
|
nkeynes@359 | 2754 | }
|
nkeynes@359 | 2755 | break;
|
nkeynes@359 | 2756 | case 0xC:
|
nkeynes@359 | 2757 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2758 | case 0x0:
|
nkeynes@359 | 2759 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2760 | uint32_t disp = (ir&0xFF);
|
nkeynes@671 | 2761 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2762 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2763 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2764 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2765 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2766 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2767 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2768 | }
|
nkeynes@359 | 2769 | break;
|
nkeynes@359 | 2770 | case 0x1:
|
nkeynes@359 | 2771 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2772 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@671 | 2773 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 2774 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2775 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2776 | check_walign16( R_EAX );
|
nkeynes@586 | 2777 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2778 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2779 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2780 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2781 | }
|
nkeynes@359 | 2782 | break;
|
nkeynes@359 | 2783 | case 0x2:
|
nkeynes@359 | 2784 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2785 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@671 | 2786 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 2787 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2788 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2789 | check_walign32( R_EAX );
|
nkeynes@586 | 2790 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2791 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2792 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2793 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2794 | }
|
nkeynes@359 | 2795 | break;
|
nkeynes@359 | 2796 | case 0x3:
|
nkeynes@359 | 2797 | { /* TRAPA #imm */
|
nkeynes@359 | 2798 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2799 | COUNT_INST(I_TRAPA);
|
nkeynes@374 | 2800 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2801 | SLOTILLEGAL();
|
nkeynes@374 | 2802 | } else {
|
nkeynes@590 | 2803 | load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5
|
nkeynes@590 | 2804 | ADD_r32_sh4r( R_ECX, R_PC );
|
nkeynes@527 | 2805 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 2806 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@417 | 2807 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 2808 | exit_block_pcset(pc);
|
nkeynes@409 | 2809 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2810 | return 2;
|
nkeynes@374 | 2811 | }
|
nkeynes@359 | 2812 | }
|
nkeynes@359 | 2813 | break;
|
nkeynes@359 | 2814 | case 0x4:
|
nkeynes@359 | 2815 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2816 | uint32_t disp = (ir&0xFF);
|
nkeynes@671 | 2817 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 2818 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2819 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2820 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2821 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2822 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2823 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2824 | }
|
nkeynes@359 | 2825 | break;
|
nkeynes@359 | 2826 | case 0x5:
|
nkeynes@359 | 2827 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2828 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@671 | 2829 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 2830 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2831 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2832 | check_ralign16( R_EAX );
|
nkeynes@586 | 2833 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2834 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2835 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2836 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2837 | }
|
nkeynes@359 | 2838 | break;
|
nkeynes@359 | 2839 | case 0x6:
|
nkeynes@359 | 2840 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2841 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@671 | 2842 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 2843 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2844 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2845 | check_ralign32( R_EAX );
|
nkeynes@586 | 2846 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2847 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2848 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2849 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2850 | }
|
nkeynes@359 | 2851 | break;
|
nkeynes@359 | 2852 | case 0x7:
|
nkeynes@359 | 2853 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2854 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@671 | 2855 | COUNT_INST(I_MOVA);
|
nkeynes@374 | 2856 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2857 | SLOTILLEGAL();
|
nkeynes@374 | 2858 | } else {
|
nkeynes@586 | 2859 | load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 2860 | ADD_sh4r_r32( R_PC, R_ECX );
|
nkeynes@374 | 2861 | store_reg( R_ECX, 0 );
|
nkeynes@586 | 2862 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2863 | }
|
nkeynes@359 | 2864 | }
|
nkeynes@359 | 2865 | break;
|
nkeynes@359 | 2866 | case 0x8:
|
nkeynes@359 | 2867 | { /* TST #imm, R0 */
|
nkeynes@359 | 2868 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2869 | COUNT_INST(I_TSTI);
|
nkeynes@368 | 2870 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2871 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2872 | SETE_t();
|
nkeynes@417 | 2873 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2874 | }
|
nkeynes@359 | 2875 | break;
|
nkeynes@359 | 2876 | case 0x9:
|
nkeynes@359 | 2877 | { /* AND #imm, R0 */
|
nkeynes@359 | 2878 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2879 | COUNT_INST(I_ANDI);
|
nkeynes@359 | 2880 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2881 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2882 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2883 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2884 | }
|
nkeynes@359 | 2885 | break;
|
nkeynes@359 | 2886 | case 0xA:
|
nkeynes@359 | 2887 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2888 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2889 | COUNT_INST(I_XORI);
|
nkeynes@359 | 2890 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2891 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2892 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2893 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2894 | }
|
nkeynes@359 | 2895 | break;
|
nkeynes@359 | 2896 | case 0xB:
|
nkeynes@359 | 2897 | { /* OR #imm, R0 */
|
nkeynes@359 | 2898 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2899 | COUNT_INST(I_ORI);
|
nkeynes@359 | 2900 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2901 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2902 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2903 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2904 | }
|
nkeynes@359 | 2905 | break;
|
nkeynes@359 | 2906 | case 0xC:
|
nkeynes@359 | 2907 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2908 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2909 | COUNT_INST(I_TSTB);
|
nkeynes@368 | 2910 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2911 | load_reg( R_ECX, R_GBR);
|
nkeynes@586 | 2912 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2913 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2914 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@394 | 2915 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2916 | SETE_t();
|
nkeynes@417 | 2917 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2918 | }
|
nkeynes@359 | 2919 | break;
|
nkeynes@359 | 2920 | case 0xD:
|
nkeynes@359 | 2921 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2922 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2923 | COUNT_INST(I_ANDB);
|
nkeynes@359 | 2924 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2925 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2926 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2927 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2928 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2929 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2930 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2931 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2932 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2933 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2934 | }
|
nkeynes@359 | 2935 | break;
|
nkeynes@359 | 2936 | case 0xE:
|
nkeynes@359 | 2937 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2938 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2939 | COUNT_INST(I_XORB);
|
nkeynes@359 | 2940 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2941 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2942 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2943 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2944 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2945 | MEM_READ_BYTE(R_EAX, R_EAX);
|
nkeynes@547 | 2946 | POP_realigned_r32(R_ECX);
|
nkeynes@359 | 2947 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2948 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2949 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2950 | }
|
nkeynes@359 | 2951 | break;
|
nkeynes@359 | 2952 | case 0xF:
|
nkeynes@359 | 2953 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2954 | uint32_t imm = (ir&0xFF);
|
nkeynes@671 | 2955 | COUNT_INST(I_ORB);
|
nkeynes@374 | 2956 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2957 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2958 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2959 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2960 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2961 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2962 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2963 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2964 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2965 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2966 | }
|
nkeynes@359 | 2967 | break;
|
nkeynes@359 | 2968 | }
|
nkeynes@359 | 2969 | break;
|
nkeynes@359 | 2970 | case 0xD:
|
nkeynes@359 | 2971 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2972 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@671 | 2973 | COUNT_INST(I_MOVLPC);
|
nkeynes@374 | 2974 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2975 | SLOTILLEGAL();
|
nkeynes@374 | 2976 | } else {
|
nkeynes@388 | 2977 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@586 | 2978 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2979 | // If the target address is in the same page as the code, it's
|
nkeynes@586 | 2980 | // pretty safe to just ref it directly and circumvent the whole
|
nkeynes@586 | 2981 | // memory subsystem. (this is a big performance win)
|
nkeynes@586 | 2982 |
|
nkeynes@586 | 2983 | // FIXME: There's a corner-case that's not handled here when
|
nkeynes@586 | 2984 | // the current code-page is in the ITLB but not in the UTLB.
|
nkeynes@586 | 2985 | // (should generate a TLB miss although need to test SH4
|
nkeynes@586 | 2986 | // behaviour to confirm) Unlikely to be anyone depending on this
|
nkeynes@586 | 2987 | // behaviour though.
|
nkeynes@586 | 2988 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@527 | 2989 | MOV_moff32_EAX( ptr );
|
nkeynes@388 | 2990 | } else {
|
nkeynes@586 | 2991 | // Note: we use sh4r.pc for the calc as we could be running at a
|
nkeynes@586 | 2992 | // different virtual address than the translation was done with,
|
nkeynes@586 | 2993 | // but we can safely assume that the low bits are the same.
|
nkeynes@586 | 2994 | load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 2995 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 2996 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2997 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 2998 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 2999 | }
|
nkeynes@386 | 3000 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 3001 | }
|
nkeynes@359 | 3002 | }
|
nkeynes@359 | 3003 | break;
|
nkeynes@359 | 3004 | case 0xE:
|
nkeynes@359 | 3005 | { /* MOV #imm, Rn */
|
nkeynes@359 | 3006 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@671 | 3007 | COUNT_INST(I_MOVI);
|
nkeynes@359 | 3008 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 3009 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 3010 | }
|
nkeynes@359 | 3011 | break;
|
nkeynes@359 | 3012 | case 0xF:
|
nkeynes@359 | 3013 | switch( ir&0xF ) {
|
nkeynes@359 | 3014 | case 0x0:
|
nkeynes@359 | 3015 | { /* FADD FRm, FRn */
|
nkeynes@359 | 3016 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3017 | COUNT_INST(I_FADD);
|
nkeynes@377 | 3018 | check_fpuen();
|
nkeynes@377 | 3019 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3020 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3021 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3022 | push_fr(FRm);
|
nkeynes@669 | 3023 | push_fr(FRn);
|
nkeynes@377 | 3024 | FADDP_st(1);
|
nkeynes@669 | 3025 | pop_fr(FRn);
|
nkeynes@669 | 3026 | JMP_rel8(end);
|
nkeynes@380 | 3027 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3028 | push_dr(FRm);
|
nkeynes@669 | 3029 | push_dr(FRn);
|
nkeynes@377 | 3030 | FADDP_st(1);
|
nkeynes@669 | 3031 | pop_dr(FRn);
|
nkeynes@380 | 3032 | JMP_TARGET(end);
|
nkeynes@417 | 3033 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3034 | }
|
nkeynes@359 | 3035 | break;
|
nkeynes@359 | 3036 | case 0x1:
|
nkeynes@359 | 3037 | { /* FSUB FRm, FRn */
|
nkeynes@359 | 3038 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3039 | COUNT_INST(I_FSUB);
|
nkeynes@377 | 3040 | check_fpuen();
|
nkeynes@377 | 3041 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3042 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3043 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3044 | push_fr(FRn);
|
nkeynes@669 | 3045 | push_fr(FRm);
|
nkeynes@388 | 3046 | FSUBP_st(1);
|
nkeynes@669 | 3047 | pop_fr(FRn);
|
nkeynes@669 | 3048 | JMP_rel8(end);
|
nkeynes@380 | 3049 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3050 | push_dr(FRn);
|
nkeynes@669 | 3051 | push_dr(FRm);
|
nkeynes@388 | 3052 | FSUBP_st(1);
|
nkeynes@669 | 3053 | pop_dr(FRn);
|
nkeynes@380 | 3054 | JMP_TARGET(end);
|
nkeynes@417 | 3055 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3056 | }
|
nkeynes@359 | 3057 | break;
|
nkeynes@359 | 3058 | case 0x2:
|
nkeynes@359 | 3059 | { /* FMUL FRm, FRn */
|
nkeynes@359 | 3060 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3061 | COUNT_INST(I_FMUL);
|
nkeynes@377 | 3062 | check_fpuen();
|
nkeynes@377 | 3063 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3064 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3065 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3066 | push_fr(FRm);
|
nkeynes@669 | 3067 | push_fr(FRn);
|
nkeynes@377 | 3068 | FMULP_st(1);
|
nkeynes@669 | 3069 | pop_fr(FRn);
|
nkeynes@669 | 3070 | JMP_rel8(end);
|
nkeynes@380 | 3071 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3072 | push_dr(FRm);
|
nkeynes@669 | 3073 | push_dr(FRn);
|
nkeynes@377 | 3074 | FMULP_st(1);
|
nkeynes@669 | 3075 | pop_dr(FRn);
|
nkeynes@380 | 3076 | JMP_TARGET(end);
|
nkeynes@417 | 3077 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3078 | }
|
nkeynes@359 | 3079 | break;
|
nkeynes@359 | 3080 | case 0x3:
|
nkeynes@359 | 3081 | { /* FDIV FRm, FRn */
|
nkeynes@359 | 3082 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3083 | COUNT_INST(I_FDIV);
|
nkeynes@377 | 3084 | check_fpuen();
|
nkeynes@377 | 3085 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3086 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3087 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3088 | push_fr(FRn);
|
nkeynes@669 | 3089 | push_fr(FRm);
|
nkeynes@377 | 3090 | FDIVP_st(1);
|
nkeynes@669 | 3091 | pop_fr(FRn);
|
nkeynes@669 | 3092 | JMP_rel8(end);
|
nkeynes@380 | 3093 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3094 | push_dr(FRn);
|
nkeynes@669 | 3095 | push_dr(FRm);
|
nkeynes@377 | 3096 | FDIVP_st(1);
|
nkeynes@669 | 3097 | pop_dr(FRn);
|
nkeynes@380 | 3098 | JMP_TARGET(end);
|
nkeynes@417 | 3099 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3100 | }
|
nkeynes@359 | 3101 | break;
|
nkeynes@359 | 3102 | case 0x4:
|
nkeynes@359 | 3103 | { /* FCMP/EQ FRm, FRn */
|
nkeynes@359 | 3104 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3105 | COUNT_INST(I_FCMPEQ);
|
nkeynes@377 | 3106 | check_fpuen();
|
nkeynes@377 | 3107 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3108 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3109 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3110 | push_fr(FRm);
|
nkeynes@669 | 3111 | push_fr(FRn);
|
nkeynes@669 | 3112 | JMP_rel8(end);
|
nkeynes@380 | 3113 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3114 | push_dr(FRm);
|
nkeynes@669 | 3115 | push_dr(FRn);
|
nkeynes@386 | 3116 | JMP_TARGET(end);
|
nkeynes@377 | 3117 | FCOMIP_st(1);
|
nkeynes@377 | 3118 | SETE_t();
|
nkeynes@377 | 3119 | FPOP_st();
|
nkeynes@417 | 3120 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3121 | }
|
nkeynes@359 | 3122 | break;
|
nkeynes@359 | 3123 | case 0x5:
|
nkeynes@359 | 3124 | { /* FCMP/GT FRm, FRn */
|
nkeynes@359 | 3125 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3126 | COUNT_INST(I_FCMPGT);
|
nkeynes@377 | 3127 | check_fpuen();
|
nkeynes@377 | 3128 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3129 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3130 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3131 | push_fr(FRm);
|
nkeynes@669 | 3132 | push_fr(FRn);
|
nkeynes@669 | 3133 | JMP_rel8(end);
|
nkeynes@380 | 3134 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3135 | push_dr(FRm);
|
nkeynes@669 | 3136 | push_dr(FRn);
|
nkeynes@380 | 3137 | JMP_TARGET(end);
|
nkeynes@377 | 3138 | FCOMIP_st(1);
|
nkeynes@377 | 3139 | SETA_t();
|
nkeynes@377 | 3140 | FPOP_st();
|
nkeynes@417 | 3141 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3142 | }
|
nkeynes@359 | 3143 | break;
|
nkeynes@359 | 3144 | case 0x6:
|
nkeynes@359 | 3145 | { /* FMOV @(R0, Rm), FRn */
|
nkeynes@359 | 3146 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 3147 | COUNT_INST(I_FMOV7);
|
nkeynes@586 | 3148 | check_fpuen();
|
nkeynes@586 | 3149 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 3150 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@416 | 3151 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3152 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3153 | JNE_rel8(doublesize);
|
nkeynes@669 | 3154 |
|
nkeynes@732 | 3155 | check_ralign32( R_EAX );
|
nkeynes@732 | 3156 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 3157 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 3158 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 3159 | JMP_rel8(end);
|
nkeynes@669 | 3160 |
|
nkeynes@669 | 3161 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3162 | check_ralign64( R_EAX );
|
nkeynes@732 | 3163 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@669 | 3164 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 3165 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 3166 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 3167 | JMP_TARGET(end);
|
nkeynes@669 | 3168 |
|
nkeynes@417 | 3169 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 3170 | }
|
nkeynes@377 | 3171 | break;
|
nkeynes@377 | 3172 | case 0x7:
|
nkeynes@377 | 3173 | { /* FMOV FRm, @(R0, Rn) */
|
nkeynes@377 | 3174 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3175 | COUNT_INST(I_FMOV4);
|
nkeynes@586 | 3176 | check_fpuen();
|
nkeynes@586 | 3177 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 3178 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@416 | 3179 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3180 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3181 | JNE_rel8(doublesize);
|
nkeynes@669 | 3182 |
|
nkeynes@732 | 3183 | check_walign32( R_EAX );
|
nkeynes@732 | 3184 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3185 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 3186 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@669 | 3187 | JMP_rel8(end);
|
nkeynes@669 | 3188 |
|
nkeynes@669 | 3189 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3190 | check_walign64( R_EAX );
|
nkeynes@732 | 3191 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3192 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 3193 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 3194 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 3195 | JMP_TARGET(end);
|
nkeynes@669 | 3196 |
|
nkeynes@417 | 3197 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 3198 | }
|
nkeynes@377 | 3199 | break;
|
nkeynes@377 | 3200 | case 0x8:
|
nkeynes@377 | 3201 | { /* FMOV @Rm, FRn */
|
nkeynes@377 | 3202 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 3203 | COUNT_INST(I_FMOV5);
|
nkeynes@586 | 3204 | check_fpuen();
|
nkeynes@586 | 3205 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 3206 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3207 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3208 | JNE_rel8(doublesize);
|
nkeynes@669 | 3209 |
|
nkeynes@732 | 3210 | check_ralign32( R_EAX );
|
nkeynes@732 | 3211 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 3212 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 3213 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 3214 | JMP_rel8(end);
|
nkeynes@669 | 3215 |
|
nkeynes@669 | 3216 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3217 | check_ralign64( R_EAX );
|
nkeynes@732 | 3218 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@669 | 3219 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 3220 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 3221 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 3222 | JMP_TARGET(end);
|
nkeynes@417 | 3223 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3224 | }
|
nkeynes@359 | 3225 | break;
|
nkeynes@359 | 3226 | case 0x9:
|
nkeynes@359 | 3227 | { /* FMOV @Rm+, FRn */
|
nkeynes@359 | 3228 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@671 | 3229 | COUNT_INST(I_FMOV6);
|
nkeynes@586 | 3230 | check_fpuen();
|
nkeynes@586 | 3231 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 3232 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3233 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3234 | JNE_rel8(doublesize);
|
nkeynes@669 | 3235 |
|
nkeynes@732 | 3236 | check_ralign32( R_EAX );
|
nkeynes@732 | 3237 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 3238 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 3239 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 3240 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 3241 | JMP_rel8(end);
|
nkeynes@669 | 3242 |
|
nkeynes@669 | 3243 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3244 | check_ralign64( R_EAX );
|
nkeynes@732 | 3245 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@669 | 3246 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
|
nkeynes@669 | 3247 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 3248 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 3249 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 3250 | JMP_TARGET(end);
|
nkeynes@669 | 3251 |
|
nkeynes@417 | 3252 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3253 | }
|
nkeynes@359 | 3254 | break;
|
nkeynes@359 | 3255 | case 0xA:
|
nkeynes@359 | 3256 | { /* FMOV FRm, @Rn */
|
nkeynes@359 | 3257 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3258 | COUNT_INST(I_FMOV2);
|
nkeynes@586 | 3259 | check_fpuen();
|
nkeynes@586 | 3260 | load_reg( R_EAX, Rn );
|
nkeynes@416 | 3261 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3262 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3263 | JNE_rel8(doublesize);
|
nkeynes@669 | 3264 |
|
nkeynes@732 | 3265 | check_walign32( R_EAX );
|
nkeynes@732 | 3266 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3267 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 3268 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@669 | 3269 | JMP_rel8(end);
|
nkeynes@669 | 3270 |
|
nkeynes@669 | 3271 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3272 | check_walign64( R_EAX );
|
nkeynes@732 | 3273 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3274 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 3275 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 3276 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 3277 | JMP_TARGET(end);
|
nkeynes@417 | 3278 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3279 | }
|
nkeynes@359 | 3280 | break;
|
nkeynes@359 | 3281 | case 0xB:
|
nkeynes@359 | 3282 | { /* FMOV FRm, @-Rn */
|
nkeynes@359 | 3283 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3284 | COUNT_INST(I_FMOV3);
|
nkeynes@586 | 3285 | check_fpuen();
|
nkeynes@586 | 3286 | load_reg( R_EAX, Rn );
|
nkeynes@416 | 3287 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3288 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 3289 | JNE_rel8(doublesize);
|
nkeynes@669 | 3290 |
|
nkeynes@732 | 3291 | check_walign32( R_EAX );
|
nkeynes@586 | 3292 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 3293 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3294 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 3295 | ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
|
nkeynes@669 | 3296 | MEM_WRITE_LONG( R_EAX, R_ECX );
|
nkeynes@669 | 3297 | JMP_rel8(end);
|
nkeynes@669 | 3298 |
|
nkeynes@669 | 3299 | JMP_TARGET(doublesize);
|
nkeynes@732 | 3300 | check_walign64( R_EAX );
|
nkeynes@669 | 3301 | ADD_imm8s_r32(-8,R_EAX);
|
nkeynes@669 | 3302 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 3303 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 3304 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 3305 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
|
nkeynes@669 | 3306 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 3307 | JMP_TARGET(end);
|
nkeynes@669 | 3308 |
|
nkeynes@417 | 3309 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3310 | }
|
nkeynes@359 | 3311 | break;
|
nkeynes@359 | 3312 | case 0xC:
|
nkeynes@359 | 3313 | { /* FMOV FRm, FRn */
|
nkeynes@359 | 3314 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3315 | COUNT_INST(I_FMOV1);
|
nkeynes@377 | 3316 | check_fpuen();
|
nkeynes@375 | 3317 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 3318 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@669 | 3319 | JNE_rel8(doublesize);
|
nkeynes@673 | 3320 | load_fr( R_EAX, FRm ); // SZ=0 branch
|
nkeynes@669 | 3321 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 3322 | JMP_rel8(end);
|
nkeynes@669 | 3323 | JMP_TARGET(doublesize);
|
nkeynes@669 | 3324 | load_dr0( R_EAX, FRm );
|
nkeynes@669 | 3325 | load_dr1( R_ECX, FRm );
|
nkeynes@669 | 3326 | store_dr0( R_EAX, FRn );
|
nkeynes@669 | 3327 | store_dr1( R_ECX, FRn );
|
nkeynes@669 | 3328 | JMP_TARGET(end);
|
nkeynes@417 | 3329 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3330 | }
|
nkeynes@359 | 3331 | break;
|
nkeynes@359 | 3332 | case 0xD:
|
nkeynes@359 | 3333 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 3334 | case 0x0:
|
nkeynes@359 | 3335 | { /* FSTS FPUL, FRn */
|
nkeynes@359 | 3336 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3337 | COUNT_INST(I_FSTS);
|
nkeynes@377 | 3338 | check_fpuen();
|
nkeynes@377 | 3339 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@669 | 3340 | store_fr( R_EAX, FRn );
|
nkeynes@417 | 3341 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3342 | }
|
nkeynes@359 | 3343 | break;
|
nkeynes@359 | 3344 | case 0x1:
|
nkeynes@359 | 3345 | { /* FLDS FRm, FPUL */
|
nkeynes@359 | 3346 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@671 | 3347 | COUNT_INST(I_FLDS);
|
nkeynes@377 | 3348 | check_fpuen();
|
nkeynes@669 | 3349 | load_fr( R_EAX, FRm );
|
nkeynes@377 | 3350 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 3351 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3352 | }
|
nkeynes@359 | 3353 | break;
|
nkeynes@359 | 3354 | case 0x2:
|
nkeynes@359 | 3355 | { /* FLOAT FPUL, FRn */
|
nkeynes@359 | 3356 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3357 | COUNT_INST(I_FLOAT);
|
nkeynes@377 | 3358 | check_fpuen();
|
nkeynes@377 | 3359 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3360 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 3361 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3362 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3363 | pop_fr( FRn );
|
nkeynes@669 | 3364 | JMP_rel8(end);
|
nkeynes@380 | 3365 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3366 | pop_dr( FRn );
|
nkeynes@380 | 3367 | JMP_TARGET(end);
|
nkeynes@417 | 3368 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3369 | }
|
nkeynes@359 | 3370 | break;
|
nkeynes@359 | 3371 | case 0x3:
|
nkeynes@359 | 3372 | { /* FTRC FRm, FPUL */
|
nkeynes@359 | 3373 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@671 | 3374 | COUNT_INST(I_FTRC);
|
nkeynes@377 | 3375 | check_fpuen();
|
nkeynes@388 | 3376 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3377 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3378 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3379 | push_fr( FRm );
|
nkeynes@669 | 3380 | JMP_rel8(doop);
|
nkeynes@388 | 3381 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3382 | push_dr( FRm );
|
nkeynes@388 | 3383 | JMP_TARGET( doop );
|
nkeynes@388 | 3384 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 3385 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 3386 | FCOMIP_st(1);
|
nkeynes@669 | 3387 | JNA_rel8( sat );
|
nkeynes@388 | 3388 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 3389 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 3390 | FCOMIP_st(1); // 2
|
nkeynes@669 | 3391 | JAE_rel8( sat2 ); // 2
|
nkeynes@394 | 3392 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 3393 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 3394 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 3395 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 3396 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 3397 | FLDCW_r32ind( R_EAX );
|
nkeynes@669 | 3398 | JMP_rel8(end); // 2
|
nkeynes@388 | 3399 |
|
nkeynes@388 | 3400 | JMP_TARGET(sat);
|
nkeynes@388 | 3401 | JMP_TARGET(sat2);
|
nkeynes@388 | 3402 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 3403 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 3404 | FPOP_st();
|
nkeynes@388 | 3405 | JMP_TARGET(end);
|
nkeynes@417 | 3406 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3407 | }
|
nkeynes@359 | 3408 | break;
|
nkeynes@359 | 3409 | case 0x4:
|
nkeynes@359 | 3410 | { /* FNEG FRn */
|
nkeynes@359 | 3411 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3412 | COUNT_INST(I_FNEG);
|
nkeynes@377 | 3413 | check_fpuen();
|
nkeynes@377 | 3414 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3415 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3416 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3417 | push_fr(FRn);
|
nkeynes@377 | 3418 | FCHS_st0();
|
nkeynes@669 | 3419 | pop_fr(FRn);
|
nkeynes@669 | 3420 | JMP_rel8(end);
|
nkeynes@380 | 3421 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3422 | push_dr(FRn);
|
nkeynes@377 | 3423 | FCHS_st0();
|
nkeynes@669 | 3424 | pop_dr(FRn);
|
nkeynes@380 | 3425 | JMP_TARGET(end);
|
nkeynes@417 | 3426 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3427 | }
|
nkeynes@359 | 3428 | break;
|
nkeynes@359 | 3429 | case 0x5:
|
nkeynes@359 | 3430 | { /* FABS FRn */
|
nkeynes@359 | 3431 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3432 | COUNT_INST(I_FABS);
|
nkeynes@377 | 3433 | check_fpuen();
|
nkeynes@374 | 3434 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@374 | 3435 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3436 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3437 | push_fr(FRn); // 6
|
nkeynes@374 | 3438 | FABS_st0(); // 2
|
nkeynes@669 | 3439 | pop_fr(FRn); //6
|
nkeynes@669 | 3440 | JMP_rel8(end); // 2
|
nkeynes@380 | 3441 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3442 | push_dr(FRn);
|
nkeynes@374 | 3443 | FABS_st0();
|
nkeynes@669 | 3444 | pop_dr(FRn);
|
nkeynes@380 | 3445 | JMP_TARGET(end);
|
nkeynes@417 | 3446 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3447 | }
|
nkeynes@359 | 3448 | break;
|
nkeynes@359 | 3449 | case 0x6:
|
nkeynes@359 | 3450 | { /* FSQRT FRn */
|
nkeynes@359 | 3451 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3452 | COUNT_INST(I_FSQRT);
|
nkeynes@377 | 3453 | check_fpuen();
|
nkeynes@377 | 3454 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3455 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3456 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3457 | push_fr(FRn);
|
nkeynes@377 | 3458 | FSQRT_st0();
|
nkeynes@669 | 3459 | pop_fr(FRn);
|
nkeynes@669 | 3460 | JMP_rel8(end);
|
nkeynes@380 | 3461 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3462 | push_dr(FRn);
|
nkeynes@377 | 3463 | FSQRT_st0();
|
nkeynes@669 | 3464 | pop_dr(FRn);
|
nkeynes@380 | 3465 | JMP_TARGET(end);
|
nkeynes@417 | 3466 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3467 | }
|
nkeynes@359 | 3468 | break;
|
nkeynes@359 | 3469 | case 0x7:
|
nkeynes@359 | 3470 | { /* FSRRA FRn */
|
nkeynes@359 | 3471 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3472 | COUNT_INST(I_FSRRA);
|
nkeynes@377 | 3473 | check_fpuen();
|
nkeynes@377 | 3474 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3475 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3476 | JNE_rel8(end); // PR=0 only
|
nkeynes@377 | 3477 | FLD1_st0();
|
nkeynes@669 | 3478 | push_fr(FRn);
|
nkeynes@377 | 3479 | FSQRT_st0();
|
nkeynes@377 | 3480 | FDIVP_st(1);
|
nkeynes@669 | 3481 | pop_fr(FRn);
|
nkeynes@380 | 3482 | JMP_TARGET(end);
|
nkeynes@417 | 3483 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3484 | }
|
nkeynes@359 | 3485 | break;
|
nkeynes@359 | 3486 | case 0x8:
|
nkeynes@359 | 3487 | { /* FLDI0 FRn */
|
nkeynes@359 | 3488 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3489 | /* IFF PR=0 */
|
nkeynes@671 | 3490 | COUNT_INST(I_FLDI0);
|
nkeynes@377 | 3491 | check_fpuen();
|
nkeynes@377 | 3492 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3493 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3494 | JNE_rel8(end);
|
nkeynes@377 | 3495 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@669 | 3496 | store_fr( R_EAX, FRn );
|
nkeynes@380 | 3497 | JMP_TARGET(end);
|
nkeynes@417 | 3498 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3499 | }
|
nkeynes@359 | 3500 | break;
|
nkeynes@359 | 3501 | case 0x9:
|
nkeynes@359 | 3502 | { /* FLDI1 FRn */
|
nkeynes@359 | 3503 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3504 | /* IFF PR=0 */
|
nkeynes@671 | 3505 | COUNT_INST(I_FLDI1);
|
nkeynes@377 | 3506 | check_fpuen();
|
nkeynes@377 | 3507 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3508 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3509 | JNE_rel8(end);
|
nkeynes@377 | 3510 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@669 | 3511 | store_fr( R_EAX, FRn );
|
nkeynes@380 | 3512 | JMP_TARGET(end);
|
nkeynes@417 | 3513 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3514 | }
|
nkeynes@359 | 3515 | break;
|
nkeynes@359 | 3516 | case 0xA:
|
nkeynes@359 | 3517 | { /* FCNVSD FPUL, FRn */
|
nkeynes@359 | 3518 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@671 | 3519 | COUNT_INST(I_FCNVSD);
|
nkeynes@377 | 3520 | check_fpuen();
|
nkeynes@377 | 3521 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3522 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3523 | JE_rel8(end); // only when PR=1
|
nkeynes@377 | 3524 | push_fpul();
|
nkeynes@669 | 3525 | pop_dr( FRn );
|
nkeynes@380 | 3526 | JMP_TARGET(end);
|
nkeynes@417 | 3527 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3528 | }
|
nkeynes@359 | 3529 | break;
|
nkeynes@359 | 3530 | case 0xB:
|
nkeynes@359 | 3531 | { /* FCNVDS FRm, FPUL */
|
nkeynes@359 | 3532 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@671 | 3533 | COUNT_INST(I_FCNVDS);
|
nkeynes@377 | 3534 | check_fpuen();
|
nkeynes@377 | 3535 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3536 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3537 | JE_rel8(end); // only when PR=1
|
nkeynes@669 | 3538 | push_dr( FRm );
|
nkeynes@377 | 3539 | pop_fpul();
|
nkeynes@380 | 3540 | JMP_TARGET(end);
|
nkeynes@417 | 3541 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3542 | }
|
nkeynes@359 | 3543 | break;
|
nkeynes@359 | 3544 | case 0xE:
|
nkeynes@359 | 3545 | { /* FIPR FVm, FVn */
|
nkeynes@359 | 3546 | uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
|
nkeynes@671 | 3547 | COUNT_INST(I_FIPR);
|
nkeynes@377 | 3548 | check_fpuen();
|
nkeynes@388 | 3549 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3550 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3551 | JNE_rel8( doubleprec);
|
nkeynes@388 | 3552 |
|
nkeynes@669 | 3553 | push_fr( FVm<<2 );
|
nkeynes@669 | 3554 | push_fr( FVn<<2 );
|
nkeynes@388 | 3555 | FMULP_st(1);
|
nkeynes@669 | 3556 | push_fr( (FVm<<2)+1);
|
nkeynes@669 | 3557 | push_fr( (FVn<<2)+1);
|
nkeynes@388 | 3558 | FMULP_st(1);
|
nkeynes@388 | 3559 | FADDP_st(1);
|
nkeynes@669 | 3560 | push_fr( (FVm<<2)+2);
|
nkeynes@669 | 3561 | push_fr( (FVn<<2)+2);
|
nkeynes@388 | 3562 | FMULP_st(1);
|
nkeynes@388 | 3563 | FADDP_st(1);
|
nkeynes@669 | 3564 | push_fr( (FVm<<2)+3);
|
nkeynes@669 | 3565 | push_fr( (FVn<<2)+3);
|
nkeynes@388 | 3566 | FMULP_st(1);
|
nkeynes@388 | 3567 | FADDP_st(1);
|
nkeynes@669 | 3568 | pop_fr( (FVn<<2)+3);
|
nkeynes@388 | 3569 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3570 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3571 | }
|
nkeynes@359 | 3572 | break;
|
nkeynes@359 | 3573 | case 0xF:
|
nkeynes@359 | 3574 | switch( (ir&0x100) >> 8 ) {
|
nkeynes@359 | 3575 | case 0x0:
|
nkeynes@359 | 3576 | { /* FSCA FPUL, FRn */
|
nkeynes@359 | 3577 | uint32_t FRn = ((ir>>9)&0x7)<<1;
|
nkeynes@671 | 3578 | COUNT_INST(I_FSCA);
|
nkeynes@377 | 3579 | check_fpuen();
|
nkeynes@388 | 3580 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3581 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3582 | JNE_rel8(doubleprec );
|
nkeynes@669 | 3583 | LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
|
nkeynes@388 | 3584 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 3585 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 3586 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3587 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3588 | }
|
nkeynes@359 | 3589 | break;
|
nkeynes@359 | 3590 | case 0x1:
|
nkeynes@359 | 3591 | switch( (ir&0x200) >> 9 ) {
|
nkeynes@359 | 3592 | case 0x0:
|
nkeynes@359 | 3593 | { /* FTRV XMTRX, FVn */
|
nkeynes@359 | 3594 | uint32_t FVn = ((ir>>10)&0x3);
|
nkeynes@671 | 3595 | COUNT_INST(I_FTRV);
|
nkeynes@377 | 3596 | check_fpuen();
|
nkeynes@388 | 3597 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3598 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3599 | JNE_rel8( doubleprec );
|
nkeynes@669 | 3600 | LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
|
nkeynes@669 | 3601 | call_func1( sh4_ftrv, R_EDX ); // 12
|
nkeynes@388 | 3602 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3603 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3604 | }
|
nkeynes@359 | 3605 | break;
|
nkeynes@359 | 3606 | case 0x1:
|
nkeynes@359 | 3607 | switch( (ir&0xC00) >> 10 ) {
|
nkeynes@359 | 3608 | case 0x0:
|
nkeynes@359 | 3609 | { /* FSCHG */
|
nkeynes@671 | 3610 | COUNT_INST(I_FSCHG);
|
nkeynes@377 | 3611 | check_fpuen();
|
nkeynes@377 | 3612 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3613 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 3614 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@417 | 3615 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3616 | }
|
nkeynes@359 | 3617 | break;
|
nkeynes@359 | 3618 | case 0x2:
|
nkeynes@359 | 3619 | { /* FRCHG */
|
nkeynes@671 | 3620 | COUNT_INST(I_FRCHG);
|
nkeynes@377 | 3621 | check_fpuen();
|
nkeynes@377 | 3622 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3623 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 3624 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@669 | 3625 | call_func0( sh4_switch_fr_banks );
|
nkeynes@417 | 3626 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3627 | }
|
nkeynes@359 | 3628 | break;
|
nkeynes@359 | 3629 | case 0x3:
|
nkeynes@359 | 3630 | { /* UNDEF */
|
nkeynes@671 | 3631 | COUNT_INST(I_UNDEF);
|
nkeynes@374 | 3632 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 3633 | SLOTILLEGAL();
|
nkeynes@374 | 3634 | } else {
|
nkeynes@586 | 3635 | JMP_exc(EXC_ILLEGAL);
|
nkeynes@408 | 3636 | return 2;
|
nkeynes@374 | 3637 | }
|
nkeynes@359 | 3638 | }
|
nkeynes@359 | 3639 | break;
|
nkeynes@359 | 3640 | default:
|
nkeynes@359 | 3641 | UNDEF();
|
nkeynes@359 | 3642 | break;
|
nkeynes@359 | 3643 | }
|
nkeynes@359 | 3644 | break;
|
nkeynes@359 | 3645 | }
|
nkeynes@359 | 3646 | break;
|
nkeynes@359 | 3647 | }
|
nkeynes@359 | 3648 | break;
|
nkeynes@359 | 3649 | default:
|
nkeynes@359 | 3650 | UNDEF();
|
nkeynes@359 | 3651 | break;
|
nkeynes@359 | 3652 | }
|
nkeynes@359 | 3653 | break;
|
nkeynes@359 | 3654 | case 0xE:
|
nkeynes@359 | 3655 | { /* FMAC FR0, FRm, FRn */
|
nkeynes@359 | 3656 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@671 | 3657 | COUNT_INST(I_FMAC);
|
nkeynes@377 | 3658 | check_fpuen();
|
nkeynes@377 | 3659 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3660 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 3661 | JNE_rel8(doubleprec);
|
nkeynes@669 | 3662 | push_fr( 0 );
|
nkeynes@669 | 3663 | push_fr( FRm );
|
nkeynes@377 | 3664 | FMULP_st(1);
|
nkeynes@669 | 3665 | push_fr( FRn );
|
nkeynes@377 | 3666 | FADDP_st(1);
|
nkeynes@669 | 3667 | pop_fr( FRn );
|
nkeynes@669 | 3668 | JMP_rel8(end);
|
nkeynes@380 | 3669 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 3670 | push_dr( 0 );
|
nkeynes@669 | 3671 | push_dr( FRm );
|
nkeynes@377 | 3672 | FMULP_st(1);
|
nkeynes@669 | 3673 | push_dr( FRn );
|
nkeynes@377 | 3674 | FADDP_st(1);
|
nkeynes@669 | 3675 | pop_dr( FRn );
|
nkeynes@380 | 3676 | JMP_TARGET(end);
|
nkeynes@417 | 3677 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3678 | }
|
nkeynes@359 | 3679 | break;
|
nkeynes@359 | 3680 | default:
|
nkeynes@359 | 3681 | UNDEF();
|
nkeynes@359 | 3682 | break;
|
nkeynes@359 | 3683 | }
|
nkeynes@359 | 3684 | break;
|
nkeynes@359 | 3685 | }
|
nkeynes@359 | 3686 |
|
nkeynes@590 | 3687 | sh4_x86.in_delay_slot = DELAY_NONE;
|
nkeynes@359 | 3688 | return 0;
|
nkeynes@359 | 3689 | }
|