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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 733:633ee022f52e
prev732:f05753bbe723
next789:7e7ec23217fc
author nkeynes
date Fri Jul 11 04:02:25 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Bug 60: Fix off-by-one in recovery list size
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SIZEOF_VOID_P == 8
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#include "sh4/ia64abi.h"
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#else /* 32-bit system */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
nkeynes@539
   310
#endif
nkeynes@539
   311
nkeynes@593
   312
uint32_t sh4_translate_end_block_size()
nkeynes@593
   313
{
nkeynes@596
   314
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   315
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   316
    } else {
nkeynes@596
   317
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   318
    }
nkeynes@593
   319
}
nkeynes@593
   320
nkeynes@593
   321
nkeynes@590
   322
/**
nkeynes@590
   323
 * Embed a breakpoint into the generated code
nkeynes@590
   324
 */
nkeynes@586
   325
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   326
{
nkeynes@591
   327
    load_imm32( R_EAX, pc );
nkeynes@591
   328
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   329
}
nkeynes@590
   330
nkeynes@601
   331
nkeynes@601
   332
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   333
nkeynes@590
   334
/**
nkeynes@590
   335
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   336
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   337
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   338
 *
nkeynes@601
   339
 * Performs:
nkeynes@601
   340
 *   Set PC = endpc
nkeynes@601
   341
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   342
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   343
 *   Call sh4_execute_instruction
nkeynes@601
   344
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   345
 */
nkeynes@601
   346
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   347
{
nkeynes@590
   348
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   349
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   350
    
nkeynes@601
   351
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   352
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   353
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   354
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   355
nkeynes@590
   356
    call_func0( sh4_execute_instruction );    
nkeynes@601
   357
    load_spreg( R_EAX, R_PC );
nkeynes@590
   358
    if( sh4_x86.tlb_on ) {
nkeynes@590
   359
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   360
    } else {
nkeynes@590
   361
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   362
    }
nkeynes@601
   363
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   364
    POP_r32(R_EBP);
nkeynes@590
   365
    RET();
nkeynes@590
   366
} 
nkeynes@539
   367
nkeynes@359
   368
/**
nkeynes@359
   369
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   370
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   371
 * 
nkeynes@586
   372
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   373
 *
nkeynes@359
   374
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   375
 * (eg a branch or 
nkeynes@359
   376
 */
nkeynes@590
   377
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   378
{
nkeynes@388
   379
    uint32_t ir;
nkeynes@586
   380
    /* Read instruction from icache */
nkeynes@586
   381
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   382
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   383
    
nkeynes@586
   384
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   385
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   386
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   387
	 * almost certainly in a delay slot.
nkeynes@586
   388
	 *
nkeynes@586
   389
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   390
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   391
	 * small repairs to cope with the different environment).
nkeynes@586
   392
	 */
nkeynes@586
   393
nkeynes@586
   394
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   395
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   396
    }
nkeynes@359
   397
%%
nkeynes@359
   398
/* ALU operations */
nkeynes@359
   399
ADD Rm, Rn {:
nkeynes@671
   400
    COUNT_INST(I_ADD);
nkeynes@359
   401
    load_reg( R_EAX, Rm );
nkeynes@359
   402
    load_reg( R_ECX, Rn );
nkeynes@359
   403
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   404
    store_reg( R_ECX, Rn );
nkeynes@417
   405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   406
:}
nkeynes@359
   407
ADD #imm, Rn {:  
nkeynes@671
   408
    COUNT_INST(I_ADDI);
nkeynes@359
   409
    load_reg( R_EAX, Rn );
nkeynes@359
   410
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   411
    store_reg( R_EAX, Rn );
nkeynes@417
   412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   413
:}
nkeynes@359
   414
ADDC Rm, Rn {:
nkeynes@671
   415
    COUNT_INST(I_ADDC);
nkeynes@417
   416
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   417
	LDC_t();
nkeynes@417
   418
    }
nkeynes@359
   419
    load_reg( R_EAX, Rm );
nkeynes@359
   420
    load_reg( R_ECX, Rn );
nkeynes@359
   421
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   422
    store_reg( R_ECX, Rn );
nkeynes@359
   423
    SETC_t();
nkeynes@417
   424
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   425
:}
nkeynes@359
   426
ADDV Rm, Rn {:
nkeynes@671
   427
    COUNT_INST(I_ADDV);
nkeynes@359
   428
    load_reg( R_EAX, Rm );
nkeynes@359
   429
    load_reg( R_ECX, Rn );
nkeynes@359
   430
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   431
    store_reg( R_ECX, Rn );
nkeynes@359
   432
    SETO_t();
nkeynes@417
   433
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   434
:}
nkeynes@359
   435
AND Rm, Rn {:
nkeynes@671
   436
    COUNT_INST(I_AND);
nkeynes@359
   437
    load_reg( R_EAX, Rm );
nkeynes@359
   438
    load_reg( R_ECX, Rn );
nkeynes@359
   439
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   440
    store_reg( R_ECX, Rn );
nkeynes@417
   441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   442
:}
nkeynes@359
   443
AND #imm, R0 {:  
nkeynes@671
   444
    COUNT_INST(I_ANDI);
nkeynes@359
   445
    load_reg( R_EAX, 0 );
nkeynes@359
   446
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   447
    store_reg( R_EAX, 0 );
nkeynes@417
   448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   449
:}
nkeynes@359
   450
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   451
    COUNT_INST(I_ANDB);
nkeynes@359
   452
    load_reg( R_EAX, 0 );
nkeynes@359
   453
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   454
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   455
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   456
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   457
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   458
    POP_realigned_r32(R_ECX);
nkeynes@386
   459
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   460
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   462
:}
nkeynes@359
   463
CMP/EQ Rm, Rn {:  
nkeynes@671
   464
    COUNT_INST(I_CMPEQ);
nkeynes@359
   465
    load_reg( R_EAX, Rm );
nkeynes@359
   466
    load_reg( R_ECX, Rn );
nkeynes@359
   467
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   468
    SETE_t();
nkeynes@417
   469
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   470
:}
nkeynes@359
   471
CMP/EQ #imm, R0 {:  
nkeynes@671
   472
    COUNT_INST(I_CMPEQI);
nkeynes@359
   473
    load_reg( R_EAX, 0 );
nkeynes@359
   474
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   475
    SETE_t();
nkeynes@417
   476
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   477
:}
nkeynes@359
   478
CMP/GE Rm, Rn {:  
nkeynes@671
   479
    COUNT_INST(I_CMPGE);
nkeynes@359
   480
    load_reg( R_EAX, Rm );
nkeynes@359
   481
    load_reg( R_ECX, Rn );
nkeynes@359
   482
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   483
    SETGE_t();
nkeynes@417
   484
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   485
:}
nkeynes@359
   486
CMP/GT Rm, Rn {: 
nkeynes@671
   487
    COUNT_INST(I_CMPGT);
nkeynes@359
   488
    load_reg( R_EAX, Rm );
nkeynes@359
   489
    load_reg( R_ECX, Rn );
nkeynes@359
   490
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   491
    SETG_t();
nkeynes@417
   492
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   493
:}
nkeynes@359
   494
CMP/HI Rm, Rn {:  
nkeynes@671
   495
    COUNT_INST(I_CMPHI);
nkeynes@359
   496
    load_reg( R_EAX, Rm );
nkeynes@359
   497
    load_reg( R_ECX, Rn );
nkeynes@359
   498
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   499
    SETA_t();
nkeynes@417
   500
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   501
:}
nkeynes@359
   502
CMP/HS Rm, Rn {: 
nkeynes@671
   503
    COUNT_INST(I_CMPHS);
nkeynes@359
   504
    load_reg( R_EAX, Rm );
nkeynes@359
   505
    load_reg( R_ECX, Rn );
nkeynes@359
   506
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   507
    SETAE_t();
nkeynes@417
   508
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   509
 :}
nkeynes@359
   510
CMP/PL Rn {: 
nkeynes@671
   511
    COUNT_INST(I_CMPPL);
nkeynes@359
   512
    load_reg( R_EAX, Rn );
nkeynes@359
   513
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   514
    SETG_t();
nkeynes@417
   515
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   516
:}
nkeynes@359
   517
CMP/PZ Rn {:  
nkeynes@671
   518
    COUNT_INST(I_CMPPZ);
nkeynes@359
   519
    load_reg( R_EAX, Rn );
nkeynes@359
   520
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   521
    SETGE_t();
nkeynes@417
   522
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   523
:}
nkeynes@361
   524
CMP/STR Rm, Rn {:  
nkeynes@671
   525
    COUNT_INST(I_CMPSTR);
nkeynes@368
   526
    load_reg( R_EAX, Rm );
nkeynes@368
   527
    load_reg( R_ECX, Rn );
nkeynes@368
   528
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   529
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   530
    JE_rel8(target1);
nkeynes@669
   531
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   532
    JE_rel8(target2);
nkeynes@669
   533
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   534
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   535
    JE_rel8(target3);
nkeynes@669
   536
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   537
    JMP_TARGET(target1);
nkeynes@380
   538
    JMP_TARGET(target2);
nkeynes@380
   539
    JMP_TARGET(target3);
nkeynes@368
   540
    SETE_t();
nkeynes@417
   541
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   542
:}
nkeynes@361
   543
DIV0S Rm, Rn {:
nkeynes@671
   544
    COUNT_INST(I_DIV0S);
nkeynes@361
   545
    load_reg( R_EAX, Rm );
nkeynes@386
   546
    load_reg( R_ECX, Rn );
nkeynes@361
   547
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   548
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   549
    store_spreg( R_EAX, R_M );
nkeynes@361
   550
    store_spreg( R_ECX, R_Q );
nkeynes@361
   551
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   552
    SETNE_t();
nkeynes@417
   553
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   554
:}
nkeynes@361
   555
DIV0U {:  
nkeynes@671
   556
    COUNT_INST(I_DIV0U);
nkeynes@361
   557
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   558
    store_spreg( R_EAX, R_Q );
nkeynes@361
   559
    store_spreg( R_EAX, R_M );
nkeynes@361
   560
    store_spreg( R_EAX, R_T );
nkeynes@417
   561
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   562
:}
nkeynes@386
   563
DIV1 Rm, Rn {:
nkeynes@671
   564
    COUNT_INST(I_DIV1);
nkeynes@386
   565
    load_spreg( R_ECX, R_M );
nkeynes@386
   566
    load_reg( R_EAX, Rn );
nkeynes@417
   567
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   568
	LDC_t();
nkeynes@417
   569
    }
nkeynes@386
   570
    RCL1_r32( R_EAX );
nkeynes@386
   571
    SETC_r8( R_DL ); // Q'
nkeynes@386
   572
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   573
    JE_rel8(mqequal);
nkeynes@386
   574
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   575
    JMP_rel8(end);
nkeynes@380
   576
    JMP_TARGET(mqequal);
nkeynes@386
   577
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   578
    JMP_TARGET(end);
nkeynes@386
   579
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   580
    SETC_r8(R_AL); // tmp1
nkeynes@386
   581
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   582
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   583
    store_spreg( R_ECX, R_Q );
nkeynes@386
   584
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   585
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   586
    store_spreg( R_EAX, R_T );
nkeynes@417
   587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   588
:}
nkeynes@361
   589
DMULS.L Rm, Rn {:  
nkeynes@671
   590
    COUNT_INST(I_DMULS);
nkeynes@361
   591
    load_reg( R_EAX, Rm );
nkeynes@361
   592
    load_reg( R_ECX, Rn );
nkeynes@361
   593
    IMUL_r32(R_ECX);
nkeynes@361
   594
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   595
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   597
:}
nkeynes@361
   598
DMULU.L Rm, Rn {:  
nkeynes@671
   599
    COUNT_INST(I_DMULU);
nkeynes@361
   600
    load_reg( R_EAX, Rm );
nkeynes@361
   601
    load_reg( R_ECX, Rn );
nkeynes@361
   602
    MUL_r32(R_ECX);
nkeynes@361
   603
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   604
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   606
:}
nkeynes@359
   607
DT Rn {:  
nkeynes@671
   608
    COUNT_INST(I_DT);
nkeynes@359
   609
    load_reg( R_EAX, Rn );
nkeynes@382
   610
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   611
    store_reg( R_EAX, Rn );
nkeynes@359
   612
    SETE_t();
nkeynes@417
   613
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   614
:}
nkeynes@359
   615
EXTS.B Rm, Rn {:  
nkeynes@671
   616
    COUNT_INST(I_EXTSB);
nkeynes@359
   617
    load_reg( R_EAX, Rm );
nkeynes@359
   618
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   619
    store_reg( R_EAX, Rn );
nkeynes@359
   620
:}
nkeynes@361
   621
EXTS.W Rm, Rn {:  
nkeynes@671
   622
    COUNT_INST(I_EXTSW);
nkeynes@361
   623
    load_reg( R_EAX, Rm );
nkeynes@361
   624
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   625
    store_reg( R_EAX, Rn );
nkeynes@361
   626
:}
nkeynes@361
   627
EXTU.B Rm, Rn {:  
nkeynes@671
   628
    COUNT_INST(I_EXTUB);
nkeynes@361
   629
    load_reg( R_EAX, Rm );
nkeynes@361
   630
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   631
    store_reg( R_EAX, Rn );
nkeynes@361
   632
:}
nkeynes@361
   633
EXTU.W Rm, Rn {:  
nkeynes@671
   634
    COUNT_INST(I_EXTUW);
nkeynes@361
   635
    load_reg( R_EAX, Rm );
nkeynes@361
   636
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   637
    store_reg( R_EAX, Rn );
nkeynes@361
   638
:}
nkeynes@586
   639
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   640
    COUNT_INST(I_MACL);
nkeynes@586
   641
    if( Rm == Rn ) {
nkeynes@586
   642
	load_reg( R_EAX, Rm );
nkeynes@586
   643
	check_ralign32( R_EAX );
nkeynes@586
   644
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   645
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   646
	load_reg( R_EAX, Rn );
nkeynes@586
   647
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   648
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   649
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   650
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   651
	// adding a page-boundary check to skip the second translation
nkeynes@586
   652
    } else {
nkeynes@586
   653
	load_reg( R_EAX, Rm );
nkeynes@586
   654
	check_ralign32( R_EAX );
nkeynes@586
   655
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   656
	load_reg( R_ECX, Rn );
nkeynes@596
   657
	check_ralign32( R_ECX );
nkeynes@586
   658
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   659
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   660
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   661
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   662
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   663
    }
nkeynes@586
   664
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   665
    POP_r32( R_ECX );
nkeynes@586
   666
    PUSH_r32( R_EAX );
nkeynes@386
   667
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   668
    POP_realigned_r32( R_ECX );
nkeynes@586
   669
nkeynes@386
   670
    IMUL_r32( R_ECX );
nkeynes@386
   671
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   672
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   673
nkeynes@386
   674
    load_spreg( R_ECX, R_S );
nkeynes@386
   675
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   676
    JE_rel8( nosat );
nkeynes@386
   677
    call_func0( signsat48 );
nkeynes@386
   678
    JMP_TARGET( nosat );
nkeynes@417
   679
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   680
:}
nkeynes@386
   681
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   682
    COUNT_INST(I_MACW);
nkeynes@586
   683
    if( Rm == Rn ) {
nkeynes@586
   684
	load_reg( R_EAX, Rm );
nkeynes@586
   685
	check_ralign16( R_EAX );
nkeynes@586
   686
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   687
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   688
	load_reg( R_EAX, Rn );
nkeynes@586
   689
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   690
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   691
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   692
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   693
	// adding a page-boundary check to skip the second translation
nkeynes@586
   694
    } else {
nkeynes@586
   695
	load_reg( R_EAX, Rm );
nkeynes@586
   696
	check_ralign16( R_EAX );
nkeynes@586
   697
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   698
	load_reg( R_ECX, Rn );
nkeynes@596
   699
	check_ralign16( R_ECX );
nkeynes@586
   700
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   701
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   702
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   703
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   704
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   705
    }
nkeynes@586
   706
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   707
    POP_r32( R_ECX );
nkeynes@586
   708
    PUSH_r32( R_EAX );
nkeynes@386
   709
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   710
    POP_realigned_r32( R_ECX );
nkeynes@386
   711
    IMUL_r32( R_ECX );
nkeynes@386
   712
nkeynes@386
   713
    load_spreg( R_ECX, R_S );
nkeynes@386
   714
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   715
    JE_rel8( nosat );
nkeynes@386
   716
nkeynes@386
   717
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   718
    JNO_rel8( end );            // 2
nkeynes@386
   719
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   720
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   721
    JS_rel8( positive );        // 2
nkeynes@386
   722
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   723
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   724
    JMP_rel8(end2);           // 2
nkeynes@386
   725
nkeynes@386
   726
    JMP_TARGET(positive);
nkeynes@386
   727
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   728
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   729
    JMP_rel8(end3);            // 2
nkeynes@386
   730
nkeynes@386
   731
    JMP_TARGET(nosat);
nkeynes@386
   732
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   733
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   734
    JMP_TARGET(end);
nkeynes@386
   735
    JMP_TARGET(end2);
nkeynes@386
   736
    JMP_TARGET(end3);
nkeynes@417
   737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   738
:}
nkeynes@359
   739
MOVT Rn {:  
nkeynes@671
   740
    COUNT_INST(I_MOVT);
nkeynes@359
   741
    load_spreg( R_EAX, R_T );
nkeynes@359
   742
    store_reg( R_EAX, Rn );
nkeynes@359
   743
:}
nkeynes@361
   744
MUL.L Rm, Rn {:  
nkeynes@671
   745
    COUNT_INST(I_MULL);
nkeynes@361
   746
    load_reg( R_EAX, Rm );
nkeynes@361
   747
    load_reg( R_ECX, Rn );
nkeynes@361
   748
    MUL_r32( R_ECX );
nkeynes@361
   749
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   750
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   751
:}
nkeynes@374
   752
MULS.W Rm, Rn {:
nkeynes@671
   753
    COUNT_INST(I_MULSW);
nkeynes@374
   754
    load_reg16s( R_EAX, Rm );
nkeynes@374
   755
    load_reg16s( R_ECX, Rn );
nkeynes@374
   756
    MUL_r32( R_ECX );
nkeynes@374
   757
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   758
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   759
:}
nkeynes@374
   760
MULU.W Rm, Rn {:  
nkeynes@671
   761
    COUNT_INST(I_MULUW);
nkeynes@374
   762
    load_reg16u( R_EAX, Rm );
nkeynes@374
   763
    load_reg16u( R_ECX, Rn );
nkeynes@374
   764
    MUL_r32( R_ECX );
nkeynes@374
   765
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   766
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   767
:}
nkeynes@359
   768
NEG Rm, Rn {:
nkeynes@671
   769
    COUNT_INST(I_NEG);
nkeynes@359
   770
    load_reg( R_EAX, Rm );
nkeynes@359
   771
    NEG_r32( R_EAX );
nkeynes@359
   772
    store_reg( R_EAX, Rn );
nkeynes@417
   773
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   774
:}
nkeynes@359
   775
NEGC Rm, Rn {:  
nkeynes@671
   776
    COUNT_INST(I_NEGC);
nkeynes@359
   777
    load_reg( R_EAX, Rm );
nkeynes@359
   778
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   779
    LDC_t();
nkeynes@359
   780
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   781
    store_reg( R_ECX, Rn );
nkeynes@359
   782
    SETC_t();
nkeynes@417
   783
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   784
:}
nkeynes@359
   785
NOT Rm, Rn {:  
nkeynes@671
   786
    COUNT_INST(I_NOT);
nkeynes@359
   787
    load_reg( R_EAX, Rm );
nkeynes@359
   788
    NOT_r32( R_EAX );
nkeynes@359
   789
    store_reg( R_EAX, Rn );
nkeynes@417
   790
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   791
:}
nkeynes@359
   792
OR Rm, Rn {:  
nkeynes@671
   793
    COUNT_INST(I_OR);
nkeynes@359
   794
    load_reg( R_EAX, Rm );
nkeynes@359
   795
    load_reg( R_ECX, Rn );
nkeynes@359
   796
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   797
    store_reg( R_ECX, Rn );
nkeynes@417
   798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   799
:}
nkeynes@359
   800
OR #imm, R0 {:
nkeynes@671
   801
    COUNT_INST(I_ORI);
nkeynes@359
   802
    load_reg( R_EAX, 0 );
nkeynes@359
   803
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   804
    store_reg( R_EAX, 0 );
nkeynes@417
   805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   806
:}
nkeynes@374
   807
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   808
    COUNT_INST(I_ORB);
nkeynes@374
   809
    load_reg( R_EAX, 0 );
nkeynes@374
   810
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   811
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   812
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   813
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   814
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   815
    POP_realigned_r32(R_ECX);
nkeynes@386
   816
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   817
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   818
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   819
:}
nkeynes@359
   820
ROTCL Rn {:
nkeynes@671
   821
    COUNT_INST(I_ROTCL);
nkeynes@359
   822
    load_reg( R_EAX, Rn );
nkeynes@417
   823
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   824
	LDC_t();
nkeynes@417
   825
    }
nkeynes@359
   826
    RCL1_r32( R_EAX );
nkeynes@359
   827
    store_reg( R_EAX, Rn );
nkeynes@359
   828
    SETC_t();
nkeynes@417
   829
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   830
:}
nkeynes@359
   831
ROTCR Rn {:  
nkeynes@671
   832
    COUNT_INST(I_ROTCR);
nkeynes@359
   833
    load_reg( R_EAX, Rn );
nkeynes@417
   834
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   835
	LDC_t();
nkeynes@417
   836
    }
nkeynes@359
   837
    RCR1_r32( R_EAX );
nkeynes@359
   838
    store_reg( R_EAX, Rn );
nkeynes@359
   839
    SETC_t();
nkeynes@417
   840
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   841
:}
nkeynes@359
   842
ROTL Rn {:  
nkeynes@671
   843
    COUNT_INST(I_ROTL);
nkeynes@359
   844
    load_reg( R_EAX, Rn );
nkeynes@359
   845
    ROL1_r32( R_EAX );
nkeynes@359
   846
    store_reg( R_EAX, Rn );
nkeynes@359
   847
    SETC_t();
nkeynes@417
   848
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   849
:}
nkeynes@359
   850
ROTR Rn {:  
nkeynes@671
   851
    COUNT_INST(I_ROTR);
nkeynes@359
   852
    load_reg( R_EAX, Rn );
nkeynes@359
   853
    ROR1_r32( R_EAX );
nkeynes@359
   854
    store_reg( R_EAX, Rn );
nkeynes@359
   855
    SETC_t();
nkeynes@417
   856
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   857
:}
nkeynes@359
   858
SHAD Rm, Rn {:
nkeynes@671
   859
    COUNT_INST(I_SHAD);
nkeynes@359
   860
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   861
    load_reg( R_EAX, Rn );
nkeynes@361
   862
    load_reg( R_ECX, Rm );
nkeynes@361
   863
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   864
    JGE_rel8(doshl);
nkeynes@361
   865
                    
nkeynes@361
   866
    NEG_r32( R_ECX );      // 2
nkeynes@361
   867
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   868
    JE_rel8(emptysar);     // 2
nkeynes@361
   869
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   870
    JMP_rel8(end);          // 2
nkeynes@386
   871
nkeynes@386
   872
    JMP_TARGET(emptysar);
nkeynes@386
   873
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   874
    JMP_rel8(end2);
nkeynes@382
   875
nkeynes@380
   876
    JMP_TARGET(doshl);
nkeynes@361
   877
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   878
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   879
    JMP_TARGET(end);
nkeynes@386
   880
    JMP_TARGET(end2);
nkeynes@361
   881
    store_reg( R_EAX, Rn );
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   883
:}
nkeynes@359
   884
SHLD Rm, Rn {:  
nkeynes@671
   885
    COUNT_INST(I_SHLD);
nkeynes@368
   886
    load_reg( R_EAX, Rn );
nkeynes@368
   887
    load_reg( R_ECX, Rm );
nkeynes@382
   888
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   889
    JGE_rel8(doshl);
nkeynes@368
   890
nkeynes@382
   891
    NEG_r32( R_ECX );      // 2
nkeynes@382
   892
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   893
    JE_rel8(emptyshr );
nkeynes@382
   894
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   895
    JMP_rel8(end);          // 2
nkeynes@386
   896
nkeynes@386
   897
    JMP_TARGET(emptyshr);
nkeynes@386
   898
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   899
    JMP_rel8(end2);
nkeynes@382
   900
nkeynes@382
   901
    JMP_TARGET(doshl);
nkeynes@382
   902
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   903
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   904
    JMP_TARGET(end);
nkeynes@386
   905
    JMP_TARGET(end2);
nkeynes@368
   906
    store_reg( R_EAX, Rn );
nkeynes@417
   907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   908
:}
nkeynes@359
   909
SHAL Rn {: 
nkeynes@671
   910
    COUNT_INST(I_SHAL);
nkeynes@359
   911
    load_reg( R_EAX, Rn );
nkeynes@359
   912
    SHL1_r32( R_EAX );
nkeynes@397
   913
    SETC_t();
nkeynes@359
   914
    store_reg( R_EAX, Rn );
nkeynes@417
   915
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   916
:}
nkeynes@359
   917
SHAR Rn {:  
nkeynes@671
   918
    COUNT_INST(I_SHAR);
nkeynes@359
   919
    load_reg( R_EAX, Rn );
nkeynes@359
   920
    SAR1_r32( R_EAX );
nkeynes@397
   921
    SETC_t();
nkeynes@359
   922
    store_reg( R_EAX, Rn );
nkeynes@417
   923
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   924
:}
nkeynes@359
   925
SHLL Rn {:  
nkeynes@671
   926
    COUNT_INST(I_SHLL);
nkeynes@359
   927
    load_reg( R_EAX, Rn );
nkeynes@359
   928
    SHL1_r32( R_EAX );
nkeynes@397
   929
    SETC_t();
nkeynes@359
   930
    store_reg( R_EAX, Rn );
nkeynes@417
   931
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   932
:}
nkeynes@359
   933
SHLL2 Rn {:
nkeynes@671
   934
    COUNT_INST(I_SHLL);
nkeynes@359
   935
    load_reg( R_EAX, Rn );
nkeynes@359
   936
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   937
    store_reg( R_EAX, Rn );
nkeynes@417
   938
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   939
:}
nkeynes@359
   940
SHLL8 Rn {:  
nkeynes@671
   941
    COUNT_INST(I_SHLL);
nkeynes@359
   942
    load_reg( R_EAX, Rn );
nkeynes@359
   943
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   944
    store_reg( R_EAX, Rn );
nkeynes@417
   945
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   946
:}
nkeynes@359
   947
SHLL16 Rn {:  
nkeynes@671
   948
    COUNT_INST(I_SHLL);
nkeynes@359
   949
    load_reg( R_EAX, Rn );
nkeynes@359
   950
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   951
    store_reg( R_EAX, Rn );
nkeynes@417
   952
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   953
:}
nkeynes@359
   954
SHLR Rn {:  
nkeynes@671
   955
    COUNT_INST(I_SHLR);
nkeynes@359
   956
    load_reg( R_EAX, Rn );
nkeynes@359
   957
    SHR1_r32( R_EAX );
nkeynes@397
   958
    SETC_t();
nkeynes@359
   959
    store_reg( R_EAX, Rn );
nkeynes@417
   960
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   961
:}
nkeynes@359
   962
SHLR2 Rn {:  
nkeynes@671
   963
    COUNT_INST(I_SHLR);
nkeynes@359
   964
    load_reg( R_EAX, Rn );
nkeynes@359
   965
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   966
    store_reg( R_EAX, Rn );
nkeynes@417
   967
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   968
:}
nkeynes@359
   969
SHLR8 Rn {:  
nkeynes@671
   970
    COUNT_INST(I_SHLR);
nkeynes@359
   971
    load_reg( R_EAX, Rn );
nkeynes@359
   972
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   973
    store_reg( R_EAX, Rn );
nkeynes@417
   974
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   975
:}
nkeynes@359
   976
SHLR16 Rn {:  
nkeynes@671
   977
    COUNT_INST(I_SHLR);
nkeynes@359
   978
    load_reg( R_EAX, Rn );
nkeynes@359
   979
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   980
    store_reg( R_EAX, Rn );
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   982
:}
nkeynes@359
   983
SUB Rm, Rn {:  
nkeynes@671
   984
    COUNT_INST(I_SUB);
nkeynes@359
   985
    load_reg( R_EAX, Rm );
nkeynes@359
   986
    load_reg( R_ECX, Rn );
nkeynes@359
   987
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   988
    store_reg( R_ECX, Rn );
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   990
:}
nkeynes@359
   991
SUBC Rm, Rn {:  
nkeynes@671
   992
    COUNT_INST(I_SUBC);
nkeynes@359
   993
    load_reg( R_EAX, Rm );
nkeynes@359
   994
    load_reg( R_ECX, Rn );
nkeynes@417
   995
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   996
	LDC_t();
nkeynes@417
   997
    }
nkeynes@359
   998
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   999
    store_reg( R_ECX, Rn );
nkeynes@394
  1000
    SETC_t();
nkeynes@417
  1001
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1002
:}
nkeynes@359
  1003
SUBV Rm, Rn {:  
nkeynes@671
  1004
    COUNT_INST(I_SUBV);
nkeynes@359
  1005
    load_reg( R_EAX, Rm );
nkeynes@359
  1006
    load_reg( R_ECX, Rn );
nkeynes@359
  1007
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1008
    store_reg( R_ECX, Rn );
nkeynes@359
  1009
    SETO_t();
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1011
:}
nkeynes@359
  1012
SWAP.B Rm, Rn {:  
nkeynes@671
  1013
    COUNT_INST(I_SWAPB);
nkeynes@359
  1014
    load_reg( R_EAX, Rm );
nkeynes@601
  1015
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1016
    store_reg( R_EAX, Rn );
nkeynes@359
  1017
:}
nkeynes@359
  1018
SWAP.W Rm, Rn {:  
nkeynes@671
  1019
    COUNT_INST(I_SWAPB);
nkeynes@359
  1020
    load_reg( R_EAX, Rm );
nkeynes@359
  1021
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1022
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1023
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1024
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1025
    store_reg( R_ECX, Rn );
nkeynes@417
  1026
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1027
:}
nkeynes@361
  1028
TAS.B @Rn {:  
nkeynes@671
  1029
    COUNT_INST(I_TASB);
nkeynes@586
  1030
    load_reg( R_EAX, Rn );
nkeynes@586
  1031
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1032
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1033
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1034
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1035
    SETE_t();
nkeynes@361
  1036
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1037
    POP_realigned_r32( R_ECX );
nkeynes@361
  1038
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1039
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1040
:}
nkeynes@361
  1041
TST Rm, Rn {:  
nkeynes@671
  1042
    COUNT_INST(I_TST);
nkeynes@361
  1043
    load_reg( R_EAX, Rm );
nkeynes@361
  1044
    load_reg( R_ECX, Rn );
nkeynes@361
  1045
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1046
    SETE_t();
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1048
:}
nkeynes@368
  1049
TST #imm, R0 {:  
nkeynes@671
  1050
    COUNT_INST(I_TSTI);
nkeynes@368
  1051
    load_reg( R_EAX, 0 );
nkeynes@368
  1052
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1053
    SETE_t();
nkeynes@417
  1054
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1055
:}
nkeynes@368
  1056
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1057
    COUNT_INST(I_TSTB);
nkeynes@368
  1058
    load_reg( R_EAX, 0);
nkeynes@368
  1059
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1060
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1061
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1062
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1063
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1064
    SETE_t();
nkeynes@417
  1065
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1066
:}
nkeynes@359
  1067
XOR Rm, Rn {:  
nkeynes@671
  1068
    COUNT_INST(I_XOR);
nkeynes@359
  1069
    load_reg( R_EAX, Rm );
nkeynes@359
  1070
    load_reg( R_ECX, Rn );
nkeynes@359
  1071
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1072
    store_reg( R_ECX, Rn );
nkeynes@417
  1073
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1074
:}
nkeynes@359
  1075
XOR #imm, R0 {:  
nkeynes@671
  1076
    COUNT_INST(I_XORI);
nkeynes@359
  1077
    load_reg( R_EAX, 0 );
nkeynes@359
  1078
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1079
    store_reg( R_EAX, 0 );
nkeynes@417
  1080
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1081
:}
nkeynes@359
  1082
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1083
    COUNT_INST(I_XORB);
nkeynes@359
  1084
    load_reg( R_EAX, 0 );
nkeynes@359
  1085
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1086
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1087
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1088
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1089
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1090
    POP_realigned_r32(R_ECX);
nkeynes@359
  1091
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1092
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1093
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1094
:}
nkeynes@361
  1095
XTRCT Rm, Rn {:
nkeynes@671
  1096
    COUNT_INST(I_XTRCT);
nkeynes@361
  1097
    load_reg( R_EAX, Rm );
nkeynes@394
  1098
    load_reg( R_ECX, Rn );
nkeynes@394
  1099
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1100
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1101
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1102
    store_reg( R_ECX, Rn );
nkeynes@417
  1103
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1104
:}
nkeynes@359
  1105
nkeynes@359
  1106
/* Data move instructions */
nkeynes@359
  1107
MOV Rm, Rn {:  
nkeynes@671
  1108
    COUNT_INST(I_MOV);
nkeynes@359
  1109
    load_reg( R_EAX, Rm );
nkeynes@359
  1110
    store_reg( R_EAX, Rn );
nkeynes@359
  1111
:}
nkeynes@359
  1112
MOV #imm, Rn {:  
nkeynes@671
  1113
    COUNT_INST(I_MOVI);
nkeynes@359
  1114
    load_imm32( R_EAX, imm );
nkeynes@359
  1115
    store_reg( R_EAX, Rn );
nkeynes@359
  1116
:}
nkeynes@359
  1117
MOV.B Rm, @Rn {:  
nkeynes@671
  1118
    COUNT_INST(I_MOVB);
nkeynes@586
  1119
    load_reg( R_EAX, Rn );
nkeynes@586
  1120
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1121
    load_reg( R_EDX, Rm );
nkeynes@586
  1122
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1124
:}
nkeynes@359
  1125
MOV.B Rm, @-Rn {:  
nkeynes@671
  1126
    COUNT_INST(I_MOVB);
nkeynes@586
  1127
    load_reg( R_EAX, Rn );
nkeynes@586
  1128
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1129
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1130
    load_reg( R_EDX, Rm );
nkeynes@586
  1131
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1132
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1133
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1134
:}
nkeynes@359
  1135
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1136
    COUNT_INST(I_MOVB);
nkeynes@359
  1137
    load_reg( R_EAX, 0 );
nkeynes@359
  1138
    load_reg( R_ECX, Rn );
nkeynes@586
  1139
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1140
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1141
    load_reg( R_EDX, Rm );
nkeynes@586
  1142
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1143
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1144
:}
nkeynes@359
  1145
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1146
    COUNT_INST(I_MOVB);
nkeynes@586
  1147
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1148
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1149
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1150
    load_reg( R_EDX, 0 );
nkeynes@586
  1151
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1152
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
:}
nkeynes@359
  1154
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1155
    COUNT_INST(I_MOVB);
nkeynes@586
  1156
    load_reg( R_EAX, Rn );
nkeynes@586
  1157
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1158
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1159
    load_reg( R_EDX, 0 );
nkeynes@586
  1160
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1162
:}
nkeynes@359
  1163
MOV.B @Rm, Rn {:  
nkeynes@671
  1164
    COUNT_INST(I_MOVB);
nkeynes@586
  1165
    load_reg( R_EAX, Rm );
nkeynes@586
  1166
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1167
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1168
    store_reg( R_EAX, Rn );
nkeynes@417
  1169
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1170
:}
nkeynes@359
  1171
MOV.B @Rm+, Rn {:  
nkeynes@671
  1172
    COUNT_INST(I_MOVB);
nkeynes@586
  1173
    load_reg( R_EAX, Rm );
nkeynes@586
  1174
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1175
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1176
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1177
    store_reg( R_EAX, Rn );
nkeynes@417
  1178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1179
:}
nkeynes@359
  1180
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1181
    COUNT_INST(I_MOVB);
nkeynes@359
  1182
    load_reg( R_EAX, 0 );
nkeynes@359
  1183
    load_reg( R_ECX, Rm );
nkeynes@586
  1184
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1185
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1186
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1187
    store_reg( R_EAX, Rn );
nkeynes@417
  1188
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1189
:}
nkeynes@359
  1190
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1191
    COUNT_INST(I_MOVB);
nkeynes@586
  1192
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1193
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1194
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1195
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1196
    store_reg( R_EAX, 0 );
nkeynes@417
  1197
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1198
:}
nkeynes@359
  1199
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1200
    COUNT_INST(I_MOVB);
nkeynes@586
  1201
    load_reg( R_EAX, Rm );
nkeynes@586
  1202
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1203
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1204
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1205
    store_reg( R_EAX, 0 );
nkeynes@417
  1206
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1207
:}
nkeynes@374
  1208
MOV.L Rm, @Rn {:
nkeynes@671
  1209
    COUNT_INST(I_MOVL);
nkeynes@586
  1210
    load_reg( R_EAX, Rn );
nkeynes@586
  1211
    check_walign32(R_EAX);
nkeynes@586
  1212
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1213
    load_reg( R_EDX, Rm );
nkeynes@586
  1214
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1216
:}
nkeynes@361
  1217
MOV.L Rm, @-Rn {:  
nkeynes@671
  1218
    COUNT_INST(I_MOVL);
nkeynes@586
  1219
    load_reg( R_EAX, Rn );
nkeynes@586
  1220
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1221
    check_walign32( R_EAX );
nkeynes@586
  1222
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1223
    load_reg( R_EDX, Rm );
nkeynes@586
  1224
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1225
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1226
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1227
:}
nkeynes@361
  1228
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1229
    COUNT_INST(I_MOVL);
nkeynes@361
  1230
    load_reg( R_EAX, 0 );
nkeynes@361
  1231
    load_reg( R_ECX, Rn );
nkeynes@586
  1232
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1233
    check_walign32( R_EAX );
nkeynes@586
  1234
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1235
    load_reg( R_EDX, Rm );
nkeynes@586
  1236
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1237
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1238
:}
nkeynes@361
  1239
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1240
    COUNT_INST(I_MOVL);
nkeynes@586
  1241
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1242
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1243
    check_walign32( R_EAX );
nkeynes@586
  1244
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1245
    load_reg( R_EDX, 0 );
nkeynes@586
  1246
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1248
:}
nkeynes@361
  1249
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1250
    COUNT_INST(I_MOVL);
nkeynes@586
  1251
    load_reg( R_EAX, Rn );
nkeynes@586
  1252
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1253
    check_walign32( R_EAX );
nkeynes@586
  1254
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1255
    load_reg( R_EDX, Rm );
nkeynes@586
  1256
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1257
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1258
:}
nkeynes@361
  1259
MOV.L @Rm, Rn {:  
nkeynes@671
  1260
    COUNT_INST(I_MOVL);
nkeynes@586
  1261
    load_reg( R_EAX, Rm );
nkeynes@586
  1262
    check_ralign32( R_EAX );
nkeynes@586
  1263
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1264
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1265
    store_reg( R_EAX, Rn );
nkeynes@417
  1266
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1267
:}
nkeynes@361
  1268
MOV.L @Rm+, Rn {:  
nkeynes@671
  1269
    COUNT_INST(I_MOVL);
nkeynes@361
  1270
    load_reg( R_EAX, Rm );
nkeynes@382
  1271
    check_ralign32( R_EAX );
nkeynes@586
  1272
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1273
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1274
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1275
    store_reg( R_EAX, Rn );
nkeynes@417
  1276
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1277
:}
nkeynes@361
  1278
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1279
    COUNT_INST(I_MOVL);
nkeynes@361
  1280
    load_reg( R_EAX, 0 );
nkeynes@361
  1281
    load_reg( R_ECX, Rm );
nkeynes@586
  1282
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1283
    check_ralign32( R_EAX );
nkeynes@586
  1284
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1285
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1286
    store_reg( R_EAX, Rn );
nkeynes@417
  1287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1288
:}
nkeynes@361
  1289
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1290
    COUNT_INST(I_MOVL);
nkeynes@586
  1291
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1292
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1293
    check_ralign32( R_EAX );
nkeynes@586
  1294
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1295
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1296
    store_reg( R_EAX, 0 );
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1298
:}
nkeynes@361
  1299
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1300
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1301
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1302
	SLOTILLEGAL();
nkeynes@374
  1303
    } else {
nkeynes@388
  1304
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1305
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1306
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1307
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1308
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1309
nkeynes@586
  1310
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1311
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1312
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1313
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1314
	    // behaviour though.
nkeynes@586
  1315
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1316
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1317
	} else {
nkeynes@586
  1318
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1319
	    // different virtual address than the translation was done with,
nkeynes@586
  1320
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1321
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1322
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1323
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1324
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1325
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1326
	}
nkeynes@382
  1327
	store_reg( R_EAX, Rn );
nkeynes@374
  1328
    }
nkeynes@361
  1329
:}
nkeynes@361
  1330
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1331
    COUNT_INST(I_MOVL);
nkeynes@586
  1332
    load_reg( R_EAX, Rm );
nkeynes@586
  1333
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1334
    check_ralign32( R_EAX );
nkeynes@586
  1335
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1336
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1337
    store_reg( R_EAX, Rn );
nkeynes@417
  1338
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1339
:}
nkeynes@361
  1340
MOV.W Rm, @Rn {:  
nkeynes@671
  1341
    COUNT_INST(I_MOVW);
nkeynes@586
  1342
    load_reg( R_EAX, Rn );
nkeynes@586
  1343
    check_walign16( R_EAX );
nkeynes@586
  1344
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1345
    load_reg( R_EDX, Rm );
nkeynes@586
  1346
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1348
:}
nkeynes@361
  1349
MOV.W Rm, @-Rn {:  
nkeynes@671
  1350
    COUNT_INST(I_MOVW);
nkeynes@586
  1351
    load_reg( R_EAX, Rn );
nkeynes@586
  1352
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1353
    check_walign16( R_EAX );
nkeynes@586
  1354
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1355
    load_reg( R_EDX, Rm );
nkeynes@586
  1356
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1357
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1359
:}
nkeynes@361
  1360
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1361
    COUNT_INST(I_MOVW);
nkeynes@361
  1362
    load_reg( R_EAX, 0 );
nkeynes@361
  1363
    load_reg( R_ECX, Rn );
nkeynes@586
  1364
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1365
    check_walign16( R_EAX );
nkeynes@586
  1366
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1367
    load_reg( R_EDX, Rm );
nkeynes@586
  1368
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1370
:}
nkeynes@361
  1371
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1372
    COUNT_INST(I_MOVW);
nkeynes@586
  1373
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1374
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1375
    check_walign16( R_EAX );
nkeynes@586
  1376
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1377
    load_reg( R_EDX, 0 );
nkeynes@586
  1378
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1380
:}
nkeynes@361
  1381
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1382
    COUNT_INST(I_MOVW);
nkeynes@586
  1383
    load_reg( R_EAX, Rn );
nkeynes@586
  1384
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1385
    check_walign16( R_EAX );
nkeynes@586
  1386
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1387
    load_reg( R_EDX, 0 );
nkeynes@586
  1388
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1390
:}
nkeynes@361
  1391
MOV.W @Rm, Rn {:  
nkeynes@671
  1392
    COUNT_INST(I_MOVW);
nkeynes@586
  1393
    load_reg( R_EAX, Rm );
nkeynes@586
  1394
    check_ralign16( R_EAX );
nkeynes@586
  1395
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1396
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1397
    store_reg( R_EAX, Rn );
nkeynes@417
  1398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1399
:}
nkeynes@361
  1400
MOV.W @Rm+, Rn {:  
nkeynes@671
  1401
    COUNT_INST(I_MOVW);
nkeynes@361
  1402
    load_reg( R_EAX, Rm );
nkeynes@374
  1403
    check_ralign16( R_EAX );
nkeynes@586
  1404
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1405
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1406
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1407
    store_reg( R_EAX, Rn );
nkeynes@417
  1408
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1409
:}
nkeynes@361
  1410
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1411
    COUNT_INST(I_MOVW);
nkeynes@361
  1412
    load_reg( R_EAX, 0 );
nkeynes@361
  1413
    load_reg( R_ECX, Rm );
nkeynes@586
  1414
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1415
    check_ralign16( R_EAX );
nkeynes@586
  1416
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1417
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1418
    store_reg( R_EAX, Rn );
nkeynes@417
  1419
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1420
:}
nkeynes@361
  1421
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1422
    COUNT_INST(I_MOVW);
nkeynes@586
  1423
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1424
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1425
    check_ralign16( R_EAX );
nkeynes@586
  1426
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1427
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1428
    store_reg( R_EAX, 0 );
nkeynes@417
  1429
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1430
:}
nkeynes@361
  1431
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1432
    COUNT_INST(I_MOVW);
nkeynes@374
  1433
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1434
	SLOTILLEGAL();
nkeynes@374
  1435
    } else {
nkeynes@586
  1436
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1437
	uint32_t target = pc + disp + 4;
nkeynes@586
  1438
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1439
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1440
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1441
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1442
	} else {
nkeynes@586
  1443
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1444
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1445
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1446
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1447
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1448
	}
nkeynes@374
  1449
	store_reg( R_EAX, Rn );
nkeynes@374
  1450
    }
nkeynes@361
  1451
:}
nkeynes@361
  1452
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1453
    COUNT_INST(I_MOVW);
nkeynes@586
  1454
    load_reg( R_EAX, Rm );
nkeynes@586
  1455
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1456
    check_ralign16( R_EAX );
nkeynes@586
  1457
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1458
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1459
    store_reg( R_EAX, 0 );
nkeynes@417
  1460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1461
:}
nkeynes@361
  1462
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1463
    COUNT_INST(I_MOVA);
nkeynes@374
  1464
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1465
	SLOTILLEGAL();
nkeynes@374
  1466
    } else {
nkeynes@586
  1467
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1468
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1469
	store_reg( R_ECX, 0 );
nkeynes@586
  1470
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1471
    }
nkeynes@361
  1472
:}
nkeynes@361
  1473
MOVCA.L R0, @Rn {:  
nkeynes@671
  1474
    COUNT_INST(I_MOVCA);
nkeynes@586
  1475
    load_reg( R_EAX, Rn );
nkeynes@586
  1476
    check_walign32( R_EAX );
nkeynes@586
  1477
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1478
    load_reg( R_EDX, 0 );
nkeynes@586
  1479
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1481
:}
nkeynes@359
  1482
nkeynes@359
  1483
/* Control transfer instructions */
nkeynes@374
  1484
BF disp {:
nkeynes@671
  1485
    COUNT_INST(I_BF);
nkeynes@374
  1486
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1487
	SLOTILLEGAL();
nkeynes@374
  1488
    } else {
nkeynes@586
  1489
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1490
	JT_rel8( nottaken );
nkeynes@586
  1491
	exit_block_rel(target, pc+2 );
nkeynes@380
  1492
	JMP_TARGET(nottaken);
nkeynes@408
  1493
	return 2;
nkeynes@374
  1494
    }
nkeynes@374
  1495
:}
nkeynes@374
  1496
BF/S disp {:
nkeynes@671
  1497
    COUNT_INST(I_BFS);
nkeynes@374
  1498
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1499
	SLOTILLEGAL();
nkeynes@374
  1500
    } else {
nkeynes@590
  1501
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1502
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1503
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1504
	    JT_rel8(nottaken);
nkeynes@601
  1505
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1506
	    JMP_TARGET(nottaken);
nkeynes@601
  1507
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1508
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1509
	    exit_block_emu(pc+2);
nkeynes@601
  1510
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1511
	    return 2;
nkeynes@601
  1512
	} else {
nkeynes@601
  1513
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1514
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1515
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1516
	    }
nkeynes@601
  1517
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1518
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1519
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1520
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1521
	    
nkeynes@601
  1522
	    // not taken
nkeynes@601
  1523
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1524
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1525
	    return 4;
nkeynes@417
  1526
	}
nkeynes@374
  1527
    }
nkeynes@374
  1528
:}
nkeynes@374
  1529
BRA disp {:  
nkeynes@671
  1530
    COUNT_INST(I_BRA);
nkeynes@374
  1531
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1532
	SLOTILLEGAL();
nkeynes@374
  1533
    } else {
nkeynes@590
  1534
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1535
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1536
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1537
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1538
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1539
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1540
	    exit_block_emu(pc+2);
nkeynes@601
  1541
	    return 2;
nkeynes@601
  1542
	} else {
nkeynes@601
  1543
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1544
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1545
	    return 4;
nkeynes@601
  1546
	}
nkeynes@374
  1547
    }
nkeynes@374
  1548
:}
nkeynes@374
  1549
BRAF Rn {:  
nkeynes@671
  1550
    COUNT_INST(I_BRAF);
nkeynes@374
  1551
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1552
	SLOTILLEGAL();
nkeynes@374
  1553
    } else {
nkeynes@590
  1554
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1555
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1556
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1557
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1558
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1559
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1560
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1561
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1562
	    exit_block_emu(pc+2);
nkeynes@601
  1563
	    return 2;
nkeynes@601
  1564
	} else {
nkeynes@601
  1565
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1566
	    exit_block_newpcset(pc+2);
nkeynes@601
  1567
	    return 4;
nkeynes@601
  1568
	}
nkeynes@374
  1569
    }
nkeynes@374
  1570
:}
nkeynes@374
  1571
BSR disp {:  
nkeynes@671
  1572
    COUNT_INST(I_BSR);
nkeynes@374
  1573
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1574
	SLOTILLEGAL();
nkeynes@374
  1575
    } else {
nkeynes@590
  1576
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1577
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1578
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1579
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1580
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1581
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1582
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1583
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1584
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1585
	    exit_block_emu(pc+2);
nkeynes@601
  1586
	    return 2;
nkeynes@601
  1587
	} else {
nkeynes@601
  1588
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1589
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1590
	    return 4;
nkeynes@601
  1591
	}
nkeynes@374
  1592
    }
nkeynes@374
  1593
:}
nkeynes@374
  1594
BSRF Rn {:  
nkeynes@671
  1595
    COUNT_INST(I_BSRF);
nkeynes@374
  1596
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1597
	SLOTILLEGAL();
nkeynes@374
  1598
    } else {
nkeynes@590
  1599
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1600
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1601
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1602
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1603
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1604
nkeynes@601
  1605
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1606
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1607
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1608
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1609
	    exit_block_emu(pc+2);
nkeynes@601
  1610
	    return 2;
nkeynes@601
  1611
	} else {
nkeynes@601
  1612
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1613
	    exit_block_newpcset(pc+2);
nkeynes@601
  1614
	    return 4;
nkeynes@601
  1615
	}
nkeynes@374
  1616
    }
nkeynes@374
  1617
:}
nkeynes@374
  1618
BT disp {:
nkeynes@671
  1619
    COUNT_INST(I_BT);
nkeynes@374
  1620
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1621
	SLOTILLEGAL();
nkeynes@374
  1622
    } else {
nkeynes@586
  1623
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1624
	JF_rel8( nottaken );
nkeynes@586
  1625
	exit_block_rel(target, pc+2 );
nkeynes@380
  1626
	JMP_TARGET(nottaken);
nkeynes@408
  1627
	return 2;
nkeynes@374
  1628
    }
nkeynes@374
  1629
:}
nkeynes@374
  1630
BT/S disp {:
nkeynes@671
  1631
    COUNT_INST(I_BTS);
nkeynes@374
  1632
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1633
	SLOTILLEGAL();
nkeynes@374
  1634
    } else {
nkeynes@590
  1635
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1636
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1637
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1638
	    JF_rel8(nottaken);
nkeynes@601
  1639
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1640
	    JMP_TARGET(nottaken);
nkeynes@601
  1641
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1642
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1643
	    exit_block_emu(pc+2);
nkeynes@601
  1644
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1645
	    return 2;
nkeynes@601
  1646
	} else {
nkeynes@601
  1647
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1648
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1649
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1650
	    }
nkeynes@601
  1651
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1652
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1653
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1654
	    // not taken
nkeynes@601
  1655
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1656
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1657
	    return 4;
nkeynes@417
  1658
	}
nkeynes@374
  1659
    }
nkeynes@374
  1660
:}
nkeynes@374
  1661
JMP @Rn {:  
nkeynes@671
  1662
    COUNT_INST(I_JMP);
nkeynes@374
  1663
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1664
	SLOTILLEGAL();
nkeynes@374
  1665
    } else {
nkeynes@408
  1666
	load_reg( R_ECX, Rn );
nkeynes@590
  1667
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1668
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1669
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1670
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1671
	    exit_block_emu(pc+2);
nkeynes@601
  1672
	    return 2;
nkeynes@601
  1673
	} else {
nkeynes@601
  1674
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1675
	    exit_block_newpcset(pc+2);
nkeynes@601
  1676
	    return 4;
nkeynes@601
  1677
	}
nkeynes@374
  1678
    }
nkeynes@374
  1679
:}
nkeynes@374
  1680
JSR @Rn {:  
nkeynes@671
  1681
    COUNT_INST(I_JSR);
nkeynes@374
  1682
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1683
	SLOTILLEGAL();
nkeynes@374
  1684
    } else {
nkeynes@590
  1685
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1686
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1687
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1688
	load_reg( R_ECX, Rn );
nkeynes@590
  1689
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1690
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1691
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1692
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1693
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1694
	    exit_block_emu(pc+2);
nkeynes@601
  1695
	    return 2;
nkeynes@601
  1696
	} else {
nkeynes@601
  1697
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1698
	    exit_block_newpcset(pc+2);
nkeynes@601
  1699
	    return 4;
nkeynes@601
  1700
	}
nkeynes@374
  1701
    }
nkeynes@374
  1702
:}
nkeynes@374
  1703
RTE {:  
nkeynes@671
  1704
    COUNT_INST(I_RTE);
nkeynes@374
  1705
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1706
	SLOTILLEGAL();
nkeynes@374
  1707
    } else {
nkeynes@408
  1708
	check_priv();
nkeynes@408
  1709
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1710
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1711
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1712
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1713
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1714
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1715
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1716
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1717
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1718
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1719
	    exit_block_emu(pc+2);
nkeynes@601
  1720
	    return 2;
nkeynes@601
  1721
	} else {
nkeynes@601
  1722
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1723
	    exit_block_newpcset(pc+2);
nkeynes@601
  1724
	    return 4;
nkeynes@601
  1725
	}
nkeynes@374
  1726
    }
nkeynes@374
  1727
:}
nkeynes@374
  1728
RTS {:  
nkeynes@671
  1729
    COUNT_INST(I_RTS);
nkeynes@374
  1730
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1731
	SLOTILLEGAL();
nkeynes@374
  1732
    } else {
nkeynes@408
  1733
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1734
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1735
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1736
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1737
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1738
	    exit_block_emu(pc+2);
nkeynes@601
  1739
	    return 2;
nkeynes@601
  1740
	} else {
nkeynes@601
  1741
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1742
	    exit_block_newpcset(pc+2);
nkeynes@601
  1743
	    return 4;
nkeynes@601
  1744
	}
nkeynes@374
  1745
    }
nkeynes@374
  1746
:}
nkeynes@374
  1747
TRAPA #imm {:  
nkeynes@671
  1748
    COUNT_INST(I_TRAPA);
nkeynes@374
  1749
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1750
	SLOTILLEGAL();
nkeynes@374
  1751
    } else {
nkeynes@590
  1752
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1753
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1754
	load_imm32( R_EAX, imm );
nkeynes@527
  1755
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1756
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1757
	exit_block_pcset(pc);
nkeynes@409
  1758
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1759
	return 2;
nkeynes@374
  1760
    }
nkeynes@374
  1761
:}
nkeynes@374
  1762
UNDEF {:  
nkeynes@671
  1763
    COUNT_INST(I_UNDEF);
nkeynes@374
  1764
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1765
	SLOTILLEGAL();
nkeynes@374
  1766
    } else {
nkeynes@586
  1767
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1768
	return 2;
nkeynes@374
  1769
    }
nkeynes@368
  1770
:}
nkeynes@374
  1771
nkeynes@374
  1772
CLRMAC {:  
nkeynes@671
  1773
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1774
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1775
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1776
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1777
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1778
:}
nkeynes@374
  1779
CLRS {:
nkeynes@671
  1780
    COUNT_INST(I_CLRS);
nkeynes@374
  1781
    CLC();
nkeynes@374
  1782
    SETC_sh4r(R_S);
nkeynes@417
  1783
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1784
:}
nkeynes@374
  1785
CLRT {:  
nkeynes@671
  1786
    COUNT_INST(I_CLRT);
nkeynes@374
  1787
    CLC();
nkeynes@374
  1788
    SETC_t();
nkeynes@417
  1789
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1790
:}
nkeynes@374
  1791
SETS {:  
nkeynes@671
  1792
    COUNT_INST(I_SETS);
nkeynes@374
  1793
    STC();
nkeynes@374
  1794
    SETC_sh4r(R_S);
nkeynes@417
  1795
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1796
:}
nkeynes@374
  1797
SETT {:  
nkeynes@671
  1798
    COUNT_INST(I_SETT);
nkeynes@374
  1799
    STC();
nkeynes@374
  1800
    SETC_t();
nkeynes@417
  1801
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1802
:}
nkeynes@359
  1803
nkeynes@375
  1804
/* Floating point moves */
nkeynes@375
  1805
FMOV FRm, FRn {:  
nkeynes@671
  1806
    COUNT_INST(I_FMOV1);
nkeynes@377
  1807
    check_fpuen();
nkeynes@375
  1808
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1809
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@669
  1810
    JNE_rel8(doublesize);
nkeynes@673
  1811
    load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@669
  1812
    store_fr( R_EAX, FRn );
nkeynes@669
  1813
    JMP_rel8(end);
nkeynes@669
  1814
    JMP_TARGET(doublesize);
nkeynes@669
  1815
    load_dr0( R_EAX, FRm );
nkeynes@669
  1816
    load_dr1( R_ECX, FRm );
nkeynes@669
  1817
    store_dr0( R_EAX, FRn );
nkeynes@669
  1818
    store_dr1( R_ECX, FRn );
nkeynes@669
  1819
    JMP_TARGET(end);
nkeynes@417
  1820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1821
:}
nkeynes@416
  1822
FMOV FRm, @Rn {: 
nkeynes@671
  1823
    COUNT_INST(I_FMOV2);
nkeynes@586
  1824
    check_fpuen();
nkeynes@586
  1825
    load_reg( R_EAX, Rn );
nkeynes@416
  1826
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1827
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1828
    JNE_rel8(doublesize);
nkeynes@669
  1829
nkeynes@732
  1830
    check_walign32( R_EAX );
nkeynes@732
  1831
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1832
    load_fr( R_ECX, FRm );
nkeynes@586
  1833
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1834
    JMP_rel8(end);
nkeynes@669
  1835
nkeynes@669
  1836
    JMP_TARGET(doublesize);
nkeynes@732
  1837
    check_walign64( R_EAX );
nkeynes@732
  1838
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1839
    load_dr0( R_ECX, FRm );
nkeynes@669
  1840
    load_dr1( R_EDX, FRm );
nkeynes@669
  1841
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1842
    JMP_TARGET(end);
nkeynes@417
  1843
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1844
:}
nkeynes@375
  1845
FMOV @Rm, FRn {:  
nkeynes@671
  1846
    COUNT_INST(I_FMOV5);
nkeynes@586
  1847
    check_fpuen();
nkeynes@586
  1848
    load_reg( R_EAX, Rm );
nkeynes@416
  1849
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1850
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1851
    JNE_rel8(doublesize);
nkeynes@669
  1852
nkeynes@732
  1853
    check_ralign32( R_EAX );
nkeynes@732
  1854
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1855
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1856
    store_fr( R_EAX, FRn );
nkeynes@669
  1857
    JMP_rel8(end);
nkeynes@669
  1858
nkeynes@669
  1859
    JMP_TARGET(doublesize);
nkeynes@732
  1860
    check_ralign64( R_EAX );
nkeynes@732
  1861
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1862
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1863
    store_dr0( R_ECX, FRn );
nkeynes@669
  1864
    store_dr1( R_EAX, FRn );
nkeynes@669
  1865
    JMP_TARGET(end);
nkeynes@417
  1866
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1867
:}
nkeynes@377
  1868
FMOV FRm, @-Rn {:  
nkeynes@671
  1869
    COUNT_INST(I_FMOV3);
nkeynes@586
  1870
    check_fpuen();
nkeynes@586
  1871
    load_reg( R_EAX, Rn );
nkeynes@416
  1872
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1873
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1874
    JNE_rel8(doublesize);
nkeynes@669
  1875
nkeynes@732
  1876
    check_walign32( R_EAX );
nkeynes@586
  1877
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1878
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1879
    load_fr( R_ECX, FRm );
nkeynes@586
  1880
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@669
  1881
    MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@669
  1882
    JMP_rel8(end);
nkeynes@669
  1883
nkeynes@669
  1884
    JMP_TARGET(doublesize);
nkeynes@732
  1885
    check_walign64( R_EAX );
nkeynes@669
  1886
    ADD_imm8s_r32(-8,R_EAX);
nkeynes@669
  1887
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1888
    load_dr0( R_ECX, FRm );
nkeynes@669
  1889
    load_dr1( R_EDX, FRm );
nkeynes@669
  1890
    ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@669
  1891
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1892
    JMP_TARGET(end);
nkeynes@669
  1893
nkeynes@417
  1894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1895
:}
nkeynes@416
  1896
FMOV @Rm+, FRn {:
nkeynes@671
  1897
    COUNT_INST(I_FMOV6);
nkeynes@586
  1898
    check_fpuen();
nkeynes@586
  1899
    load_reg( R_EAX, Rm );
nkeynes@416
  1900
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1901
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1902
    JNE_rel8(doublesize);
nkeynes@669
  1903
nkeynes@732
  1904
    check_ralign32( R_EAX );
nkeynes@732
  1905
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1906
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1907
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1908
    store_fr( R_EAX, FRn );
nkeynes@669
  1909
    JMP_rel8(end);
nkeynes@669
  1910
nkeynes@669
  1911
    JMP_TARGET(doublesize);
nkeynes@732
  1912
    check_ralign64( R_EAX );
nkeynes@732
  1913
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1914
    ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@669
  1915
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1916
    store_dr0( R_ECX, FRn );
nkeynes@669
  1917
    store_dr1( R_EAX, FRn );
nkeynes@669
  1918
    JMP_TARGET(end);
nkeynes@669
  1919
nkeynes@417
  1920
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1921
:}
nkeynes@377
  1922
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1923
    COUNT_INST(I_FMOV4);
nkeynes@586
  1924
    check_fpuen();
nkeynes@586
  1925
    load_reg( R_EAX, Rn );
nkeynes@586
  1926
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1927
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1928
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1929
    JNE_rel8(doublesize);
nkeynes@669
  1930
nkeynes@732
  1931
    check_walign32( R_EAX );
nkeynes@732
  1932
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1933
    load_fr( R_ECX, FRm );
nkeynes@586
  1934
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1935
    JMP_rel8(end);
nkeynes@669
  1936
nkeynes@669
  1937
    JMP_TARGET(doublesize);
nkeynes@732
  1938
    check_walign64( R_EAX );
nkeynes@732
  1939
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1940
    load_dr0( R_ECX, FRm );
nkeynes@669
  1941
    load_dr1( R_EDX, FRm );
nkeynes@669
  1942
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1943
    JMP_TARGET(end);
nkeynes@669
  1944
nkeynes@417
  1945
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1946
:}
nkeynes@377
  1947
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1948
    COUNT_INST(I_FMOV7);
nkeynes@586
  1949
    check_fpuen();
nkeynes@586
  1950
    load_reg( R_EAX, Rm );
nkeynes@586
  1951
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1952
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1953
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1954
    JNE_rel8(doublesize);
nkeynes@669
  1955
nkeynes@732
  1956
    check_ralign32( R_EAX );
nkeynes@732
  1957
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1958
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1959
    store_fr( R_EAX, FRn );
nkeynes@669
  1960
    JMP_rel8(end);
nkeynes@669
  1961
nkeynes@669
  1962
    JMP_TARGET(doublesize);
nkeynes@732
  1963
    check_ralign64( R_EAX );
nkeynes@732
  1964
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1965
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1966
    store_dr0( R_ECX, FRn );
nkeynes@669
  1967
    store_dr1( R_EAX, FRn );
nkeynes@669
  1968
    JMP_TARGET(end);
nkeynes@669
  1969
nkeynes@417
  1970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1971
:}
nkeynes@377
  1972
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1973
    COUNT_INST(I_FLDI0);
nkeynes@377
  1974
    check_fpuen();
nkeynes@377
  1975
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1976
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1977
    JNE_rel8(end);
nkeynes@377
  1978
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  1979
    store_fr( R_EAX, FRn );
nkeynes@380
  1980
    JMP_TARGET(end);
nkeynes@417
  1981
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1982
:}
nkeynes@377
  1983
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1984
    COUNT_INST(I_FLDI1);
nkeynes@377
  1985
    check_fpuen();
nkeynes@377
  1986
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1987
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1988
    JNE_rel8(end);
nkeynes@377
  1989
    load_imm32(R_EAX, 0x3F800000);
nkeynes@669
  1990
    store_fr( R_EAX, FRn );
nkeynes@380
  1991
    JMP_TARGET(end);
nkeynes@417
  1992
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1993
:}
nkeynes@377
  1994
nkeynes@377
  1995
FLOAT FPUL, FRn {:  
nkeynes@671
  1996
    COUNT_INST(I_FLOAT);
nkeynes@377
  1997
    check_fpuen();
nkeynes@377
  1998
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1999
    FILD_sh4r(R_FPUL);
nkeynes@377
  2000
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2001
    JNE_rel8(doubleprec);
nkeynes@669
  2002
    pop_fr( FRn );
nkeynes@669
  2003
    JMP_rel8(end);
nkeynes@380
  2004
    JMP_TARGET(doubleprec);
nkeynes@669
  2005
    pop_dr( FRn );
nkeynes@380
  2006
    JMP_TARGET(end);
nkeynes@417
  2007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2008
:}
nkeynes@377
  2009
FTRC FRm, FPUL {:  
nkeynes@671
  2010
    COUNT_INST(I_FTRC);
nkeynes@377
  2011
    check_fpuen();
nkeynes@388
  2012
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2013
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2014
    JNE_rel8(doubleprec);
nkeynes@669
  2015
    push_fr( FRm );
nkeynes@669
  2016
    JMP_rel8(doop);
nkeynes@388
  2017
    JMP_TARGET(doubleprec);
nkeynes@669
  2018
    push_dr( FRm );
nkeynes@388
  2019
    JMP_TARGET( doop );
nkeynes@388
  2020
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  2021
    FILD_r32ind( R_ECX );
nkeynes@388
  2022
    FCOMIP_st(1);
nkeynes@669
  2023
    JNA_rel8( sat );
nkeynes@388
  2024
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  2025
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2026
    FCOMIP_st(1);                   // 2
nkeynes@669
  2027
    JAE_rel8( sat2 );            // 2
nkeynes@394
  2028
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  2029
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  2030
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  2031
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2032
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2033
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2034
    JMP_rel8(end);             // 2
nkeynes@388
  2035
nkeynes@388
  2036
    JMP_TARGET(sat);
nkeynes@388
  2037
    JMP_TARGET(sat2);
nkeynes@388
  2038
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2039
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2040
    FPOP_st();
nkeynes@388
  2041
    JMP_TARGET(end);
nkeynes@417
  2042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2043
:}
nkeynes@377
  2044
FLDS FRm, FPUL {:  
nkeynes@671
  2045
    COUNT_INST(I_FLDS);
nkeynes@377
  2046
    check_fpuen();
nkeynes@669
  2047
    load_fr( R_EAX, FRm );
nkeynes@377
  2048
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2049
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2050
:}
nkeynes@377
  2051
FSTS FPUL, FRn {:  
nkeynes@671
  2052
    COUNT_INST(I_FSTS);
nkeynes@377
  2053
    check_fpuen();
nkeynes@377
  2054
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2055
    store_fr( R_EAX, FRn );
nkeynes@417
  2056
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2057
:}
nkeynes@377
  2058
FCNVDS FRm, FPUL {:  
nkeynes@671
  2059
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2060
    check_fpuen();
nkeynes@377
  2061
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2062
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2063
    JE_rel8(end); // only when PR=1
nkeynes@669
  2064
    push_dr( FRm );
nkeynes@377
  2065
    pop_fpul();
nkeynes@380
  2066
    JMP_TARGET(end);
nkeynes@417
  2067
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2068
:}
nkeynes@377
  2069
FCNVSD FPUL, FRn {:  
nkeynes@671
  2070
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2071
    check_fpuen();
nkeynes@377
  2072
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2073
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2074
    JE_rel8(end); // only when PR=1
nkeynes@377
  2075
    push_fpul();
nkeynes@669
  2076
    pop_dr( FRn );
nkeynes@380
  2077
    JMP_TARGET(end);
nkeynes@417
  2078
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2079
:}
nkeynes@375
  2080
nkeynes@359
  2081
/* Floating point instructions */
nkeynes@374
  2082
FABS FRn {:  
nkeynes@671
  2083
    COUNT_INST(I_FABS);
nkeynes@377
  2084
    check_fpuen();
nkeynes@374
  2085
    load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  2086
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2087
    JNE_rel8(doubleprec);
nkeynes@669
  2088
    push_fr(FRn); // 6
nkeynes@374
  2089
    FABS_st0(); // 2
nkeynes@669
  2090
    pop_fr(FRn); //6
nkeynes@669
  2091
    JMP_rel8(end); // 2
nkeynes@380
  2092
    JMP_TARGET(doubleprec);
nkeynes@669
  2093
    push_dr(FRn);
nkeynes@374
  2094
    FABS_st0();
nkeynes@669
  2095
    pop_dr(FRn);
nkeynes@380
  2096
    JMP_TARGET(end);
nkeynes@417
  2097
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2098
:}
nkeynes@377
  2099
FADD FRm, FRn {:  
nkeynes@671
  2100
    COUNT_INST(I_FADD);
nkeynes@377
  2101
    check_fpuen();
nkeynes@375
  2102
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2103
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2104
    JNE_rel8(doubleprec);
nkeynes@669
  2105
    push_fr(FRm);
nkeynes@669
  2106
    push_fr(FRn);
nkeynes@377
  2107
    FADDP_st(1);
nkeynes@669
  2108
    pop_fr(FRn);
nkeynes@669
  2109
    JMP_rel8(end);
nkeynes@380
  2110
    JMP_TARGET(doubleprec);
nkeynes@669
  2111
    push_dr(FRm);
nkeynes@669
  2112
    push_dr(FRn);
nkeynes@377
  2113
    FADDP_st(1);
nkeynes@669
  2114
    pop_dr(FRn);
nkeynes@380
  2115
    JMP_TARGET(end);
nkeynes@417
  2116
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2117
:}
nkeynes@377
  2118
FDIV FRm, FRn {:  
nkeynes@671
  2119
    COUNT_INST(I_FDIV);
nkeynes@377
  2120
    check_fpuen();
nkeynes@375
  2121
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2122
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2123
    JNE_rel8(doubleprec);
nkeynes@669
  2124
    push_fr(FRn);
nkeynes@669
  2125
    push_fr(FRm);
nkeynes@377
  2126
    FDIVP_st(1);
nkeynes@669
  2127
    pop_fr(FRn);
nkeynes@669
  2128
    JMP_rel8(end);
nkeynes@380
  2129
    JMP_TARGET(doubleprec);
nkeynes@669
  2130
    push_dr(FRn);
nkeynes@669
  2131
    push_dr(FRm);
nkeynes@377
  2132
    FDIVP_st(1);
nkeynes@669
  2133
    pop_dr(FRn);
nkeynes@380
  2134
    JMP_TARGET(end);
nkeynes@417
  2135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2136
:}
nkeynes@375
  2137
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2138
    COUNT_INST(I_FMAC);
nkeynes@377
  2139
    check_fpuen();
nkeynes@375
  2140
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2141
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2142
    JNE_rel8(doubleprec);
nkeynes@669
  2143
    push_fr( 0 );
nkeynes@669
  2144
    push_fr( FRm );
nkeynes@375
  2145
    FMULP_st(1);
nkeynes@669
  2146
    push_fr( FRn );
nkeynes@375
  2147
    FADDP_st(1);
nkeynes@669
  2148
    pop_fr( FRn );
nkeynes@669
  2149
    JMP_rel8(end);
nkeynes@380
  2150
    JMP_TARGET(doubleprec);
nkeynes@669
  2151
    push_dr( 0 );
nkeynes@669
  2152
    push_dr( FRm );
nkeynes@375
  2153
    FMULP_st(1);
nkeynes@669
  2154
    push_dr( FRn );
nkeynes@375
  2155
    FADDP_st(1);
nkeynes@669
  2156
    pop_dr( FRn );
nkeynes@380
  2157
    JMP_TARGET(end);
nkeynes@417
  2158
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2159
:}
nkeynes@375
  2160
nkeynes@377
  2161
FMUL FRm, FRn {:  
nkeynes@671
  2162
    COUNT_INST(I_FMUL);
nkeynes@377
  2163
    check_fpuen();
nkeynes@377
  2164
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2165
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2166
    JNE_rel8(doubleprec);
nkeynes@669
  2167
    push_fr(FRm);
nkeynes@669
  2168
    push_fr(FRn);
nkeynes@377
  2169
    FMULP_st(1);
nkeynes@669
  2170
    pop_fr(FRn);
nkeynes@669
  2171
    JMP_rel8(end);
nkeynes@380
  2172
    JMP_TARGET(doubleprec);
nkeynes@669
  2173
    push_dr(FRm);
nkeynes@669
  2174
    push_dr(FRn);
nkeynes@377
  2175
    FMULP_st(1);
nkeynes@669
  2176
    pop_dr(FRn);
nkeynes@380
  2177
    JMP_TARGET(end);
nkeynes@417
  2178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2179
:}
nkeynes@377
  2180
FNEG FRn {:  
nkeynes@671
  2181
    COUNT_INST(I_FNEG);
nkeynes@377
  2182
    check_fpuen();
nkeynes@377
  2183
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2184
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2185
    JNE_rel8(doubleprec);
nkeynes@669
  2186
    push_fr(FRn);
nkeynes@377
  2187
    FCHS_st0();
nkeynes@669
  2188
    pop_fr(FRn);
nkeynes@669
  2189
    JMP_rel8(end);
nkeynes@380
  2190
    JMP_TARGET(doubleprec);
nkeynes@669
  2191
    push_dr(FRn);
nkeynes@377
  2192
    FCHS_st0();
nkeynes@669
  2193
    pop_dr(FRn);
nkeynes@380
  2194
    JMP_TARGET(end);
nkeynes@417
  2195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2196
:}
nkeynes@377
  2197
FSRRA FRn {:  
nkeynes@671
  2198
    COUNT_INST(I_FSRRA);
nkeynes@377
  2199
    check_fpuen();
nkeynes@377
  2200
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2201
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2202
    JNE_rel8(end); // PR=0 only
nkeynes@377
  2203
    FLD1_st0();
nkeynes@669
  2204
    push_fr(FRn);
nkeynes@377
  2205
    FSQRT_st0();
nkeynes@377
  2206
    FDIVP_st(1);
nkeynes@669
  2207
    pop_fr(FRn);
nkeynes@380
  2208
    JMP_TARGET(end);
nkeynes@417
  2209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2210
:}
nkeynes@377
  2211
FSQRT FRn {:  
nkeynes@671
  2212
    COUNT_INST(I_FSQRT);
nkeynes@377
  2213
    check_fpuen();
nkeynes@377
  2214
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2215
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2216
    JNE_rel8(doubleprec);
nkeynes@669
  2217
    push_fr(FRn);
nkeynes@377
  2218
    FSQRT_st0();
nkeynes@669
  2219
    pop_fr(FRn);
nkeynes@669
  2220
    JMP_rel8(end);
nkeynes@380
  2221
    JMP_TARGET(doubleprec);
nkeynes@669
  2222
    push_dr(FRn);
nkeynes@377
  2223
    FSQRT_st0();
nkeynes@669
  2224
    pop_dr(FRn);
nkeynes@380
  2225
    JMP_TARGET(end);
nkeynes@417
  2226
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2227
:}
nkeynes@377
  2228
FSUB FRm, FRn {:  
nkeynes@671
  2229
    COUNT_INST(I_FSUB);
nkeynes@377
  2230
    check_fpuen();
nkeynes@377
  2231
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2232
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2233
    JNE_rel8(doubleprec);
nkeynes@669
  2234
    push_fr(FRn);
nkeynes@669
  2235
    push_fr(FRm);
nkeynes@388
  2236
    FSUBP_st(1);
nkeynes@669
  2237
    pop_fr(FRn);
nkeynes@669
  2238
    JMP_rel8(end);
nkeynes@380
  2239
    JMP_TARGET(doubleprec);
nkeynes@669
  2240
    push_dr(FRn);
nkeynes@669
  2241
    push_dr(FRm);
nkeynes@388
  2242
    FSUBP_st(1);
nkeynes@669
  2243
    pop_dr(FRn);
nkeynes@380
  2244
    JMP_TARGET(end);
nkeynes@417
  2245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2246
:}
nkeynes@377
  2247
nkeynes@377
  2248
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2249
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2250
    check_fpuen();
nkeynes@377
  2251
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2252
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2253
    JNE_rel8(doubleprec);
nkeynes@669
  2254
    push_fr(FRm);
nkeynes@669
  2255
    push_fr(FRn);
nkeynes@669
  2256
    JMP_rel8(end);
nkeynes@380
  2257
    JMP_TARGET(doubleprec);
nkeynes@669
  2258
    push_dr(FRm);
nkeynes@669
  2259
    push_dr(FRn);
nkeynes@382
  2260
    JMP_TARGET(end);
nkeynes@377
  2261
    FCOMIP_st(1);
nkeynes@377
  2262
    SETE_t();
nkeynes@377
  2263
    FPOP_st();
nkeynes@417
  2264
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2265
:}
nkeynes@377
  2266
FCMP/GT FRm, FRn {:  
nkeynes@671
  2267
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2268
    check_fpuen();
nkeynes@377
  2269
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2270
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2271
    JNE_rel8(doubleprec);
nkeynes@669
  2272
    push_fr(FRm);
nkeynes@669
  2273
    push_fr(FRn);
nkeynes@669
  2274
    JMP_rel8(end);
nkeynes@380
  2275
    JMP_TARGET(doubleprec);
nkeynes@669
  2276
    push_dr(FRm);
nkeynes@669
  2277
    push_dr(FRn);
nkeynes@380
  2278
    JMP_TARGET(end);
nkeynes@377
  2279
    FCOMIP_st(1);
nkeynes@377
  2280
    SETA_t();
nkeynes@377
  2281
    FPOP_st();
nkeynes@417
  2282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2283
:}
nkeynes@377
  2284
nkeynes@377
  2285
FSCA FPUL, FRn {:  
nkeynes@671
  2286
    COUNT_INST(I_FSCA);
nkeynes@377
  2287
    check_fpuen();
nkeynes@388
  2288
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2289
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2290
    JNE_rel8(doubleprec );
nkeynes@669
  2291
    LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@388
  2292
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2293
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2294
    JMP_TARGET(doubleprec);
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2296
:}
nkeynes@377
  2297
FIPR FVm, FVn {:  
nkeynes@671
  2298
    COUNT_INST(I_FIPR);
nkeynes@377
  2299
    check_fpuen();
nkeynes@388
  2300
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2301
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2302
    JNE_rel8( doubleprec);
nkeynes@388
  2303
    
nkeynes@669
  2304
    push_fr( FVm<<2 );
nkeynes@669
  2305
    push_fr( FVn<<2 );
nkeynes@388
  2306
    FMULP_st(1);
nkeynes@669
  2307
    push_fr( (FVm<<2)+1);
nkeynes@669
  2308
    push_fr( (FVn<<2)+1);
nkeynes@388
  2309
    FMULP_st(1);
nkeynes@388
  2310
    FADDP_st(1);
nkeynes@669
  2311
    push_fr( (FVm<<2)+2);
nkeynes@669
  2312
    push_fr( (FVn<<2)+2);
nkeynes@388
  2313
    FMULP_st(1);
nkeynes@388
  2314
    FADDP_st(1);
nkeynes@669
  2315
    push_fr( (FVm<<2)+3);
nkeynes@669
  2316
    push_fr( (FVn<<2)+3);
nkeynes@388
  2317
    FMULP_st(1);
nkeynes@388
  2318
    FADDP_st(1);
nkeynes@669
  2319
    pop_fr( (FVn<<2)+3);
nkeynes@388
  2320
    JMP_TARGET(doubleprec);
nkeynes@417
  2321
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2322
:}
nkeynes@377
  2323
FTRV XMTRX, FVn {:  
nkeynes@671
  2324
    COUNT_INST(I_FTRV);
nkeynes@377
  2325
    check_fpuen();
nkeynes@388
  2326
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2327
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2328
    JNE_rel8( doubleprec );
nkeynes@669
  2329
    LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
nkeynes@669
  2330
    call_func1( sh4_ftrv, R_EDX );  // 12
nkeynes@388
  2331
    JMP_TARGET(doubleprec);
nkeynes@417
  2332
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2333
:}
nkeynes@377
  2334
nkeynes@377
  2335
FRCHG {:  
nkeynes@671
  2336
    COUNT_INST(I_FRCHG);
nkeynes@377
  2337
    check_fpuen();
nkeynes@377
  2338
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2339
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2340
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2341
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2343
:}
nkeynes@377
  2344
FSCHG {:  
nkeynes@671
  2345
    COUNT_INST(I_FSCHG);
nkeynes@377
  2346
    check_fpuen();
nkeynes@377
  2347
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2348
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2349
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2351
:}
nkeynes@359
  2352
nkeynes@359
  2353
/* Processor control instructions */
nkeynes@368
  2354
LDC Rm, SR {:
nkeynes@671
  2355
    COUNT_INST(I_LDCSR);
nkeynes@386
  2356
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2357
	SLOTILLEGAL();
nkeynes@386
  2358
    } else {
nkeynes@386
  2359
	check_priv();
nkeynes@386
  2360
	load_reg( R_EAX, Rm );
nkeynes@386
  2361
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2362
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2363
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2364
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2365
    }
nkeynes@368
  2366
:}
nkeynes@359
  2367
LDC Rm, GBR {: 
nkeynes@671
  2368
    COUNT_INST(I_LDC);
nkeynes@359
  2369
    load_reg( R_EAX, Rm );
nkeynes@359
  2370
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2371
:}
nkeynes@359
  2372
LDC Rm, VBR {:  
nkeynes@671
  2373
    COUNT_INST(I_LDC);
nkeynes@386
  2374
    check_priv();
nkeynes@359
  2375
    load_reg( R_EAX, Rm );
nkeynes@359
  2376
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2377
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2378
:}
nkeynes@359
  2379
LDC Rm, SSR {:  
nkeynes@671
  2380
    COUNT_INST(I_LDC);
nkeynes@386
  2381
    check_priv();
nkeynes@359
  2382
    load_reg( R_EAX, Rm );
nkeynes@359
  2383
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2385
:}
nkeynes@359
  2386
LDC Rm, SGR {:  
nkeynes@671
  2387
    COUNT_INST(I_LDC);
nkeynes@386
  2388
    check_priv();
nkeynes@359
  2389
    load_reg( R_EAX, Rm );
nkeynes@359
  2390
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2392
:}
nkeynes@359
  2393
LDC Rm, SPC {:  
nkeynes@671
  2394
    COUNT_INST(I_LDC);
nkeynes@386
  2395
    check_priv();
nkeynes@359
  2396
    load_reg( R_EAX, Rm );
nkeynes@359
  2397
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2399
:}
nkeynes@359
  2400
LDC Rm, DBR {:  
nkeynes@671
  2401
    COUNT_INST(I_LDC);
nkeynes@386
  2402
    check_priv();
nkeynes@359
  2403
    load_reg( R_EAX, Rm );
nkeynes@359
  2404
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2406
:}
nkeynes@374
  2407
LDC Rm, Rn_BANK {:  
nkeynes@671
  2408
    COUNT_INST(I_LDC);
nkeynes@386
  2409
    check_priv();
nkeynes@374
  2410
    load_reg( R_EAX, Rm );
nkeynes@374
  2411
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2413
:}
nkeynes@359
  2414
LDC.L @Rm+, GBR {:  
nkeynes@671
  2415
    COUNT_INST(I_LDCM);
nkeynes@359
  2416
    load_reg( R_EAX, Rm );
nkeynes@395
  2417
    check_ralign32( R_EAX );
nkeynes@586
  2418
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2419
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2420
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2421
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2423
:}
nkeynes@368
  2424
LDC.L @Rm+, SR {:
nkeynes@671
  2425
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2426
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2427
	SLOTILLEGAL();
nkeynes@386
  2428
    } else {
nkeynes@586
  2429
	check_priv();
nkeynes@386
  2430
	load_reg( R_EAX, Rm );
nkeynes@395
  2431
	check_ralign32( R_EAX );
nkeynes@586
  2432
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2433
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2434
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2435
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2436
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2437
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2438
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2439
    }
nkeynes@359
  2440
:}
nkeynes@359
  2441
LDC.L @Rm+, VBR {:  
nkeynes@671
  2442
    COUNT_INST(I_LDCM);
nkeynes@586
  2443
    check_priv();
nkeynes@359
  2444
    load_reg( R_EAX, Rm );
nkeynes@395
  2445
    check_ralign32( R_EAX );
nkeynes@586
  2446
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2447
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2448
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2449
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2451
:}
nkeynes@359
  2452
LDC.L @Rm+, SSR {:
nkeynes@671
  2453
    COUNT_INST(I_LDCM);
nkeynes@586
  2454
    check_priv();
nkeynes@359
  2455
    load_reg( R_EAX, Rm );
nkeynes@416
  2456
    check_ralign32( R_EAX );
nkeynes@586
  2457
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2458
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2459
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2460
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2462
:}
nkeynes@359
  2463
LDC.L @Rm+, SGR {:  
nkeynes@671
  2464
    COUNT_INST(I_LDCM);
nkeynes@586
  2465
    check_priv();
nkeynes@359
  2466
    load_reg( R_EAX, Rm );
nkeynes@395
  2467
    check_ralign32( R_EAX );
nkeynes@586
  2468
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2469
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2470
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2471
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2473
:}
nkeynes@359
  2474
LDC.L @Rm+, SPC {:  
nkeynes@671
  2475
    COUNT_INST(I_LDCM);
nkeynes@586
  2476
    check_priv();
nkeynes@359
  2477
    load_reg( R_EAX, Rm );
nkeynes@395
  2478
    check_ralign32( R_EAX );
nkeynes@586
  2479
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2480
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2481
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2482
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2483
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2484
:}
nkeynes@359
  2485
LDC.L @Rm+, DBR {:  
nkeynes@671
  2486
    COUNT_INST(I_LDCM);
nkeynes@586
  2487
    check_priv();
nkeynes@359
  2488
    load_reg( R_EAX, Rm );
nkeynes@395
  2489
    check_ralign32( R_EAX );
nkeynes@586
  2490
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2491
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2492
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2493
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2494
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2495
:}
nkeynes@359
  2496
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2497
    COUNT_INST(I_LDCM);
nkeynes@586
  2498
    check_priv();
nkeynes@374
  2499
    load_reg( R_EAX, Rm );
nkeynes@395
  2500
    check_ralign32( R_EAX );
nkeynes@586
  2501
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2502
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2503
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2504
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2505
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2506
:}
nkeynes@626
  2507
LDS Rm, FPSCR {:
nkeynes@673
  2508
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2509
    check_fpuen();
nkeynes@359
  2510
    load_reg( R_EAX, Rm );
nkeynes@669
  2511
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2512
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2513
:}
nkeynes@359
  2514
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2515
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2516
    check_fpuen();
nkeynes@359
  2517
    load_reg( R_EAX, Rm );
nkeynes@395
  2518
    check_ralign32( R_EAX );
nkeynes@586
  2519
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2520
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2521
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2522
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2523
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2524
:}
nkeynes@359
  2525
LDS Rm, FPUL {:  
nkeynes@671
  2526
    COUNT_INST(I_LDS);
nkeynes@626
  2527
    check_fpuen();
nkeynes@359
  2528
    load_reg( R_EAX, Rm );
nkeynes@359
  2529
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2530
:}
nkeynes@359
  2531
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2532
    COUNT_INST(I_LDSM);
nkeynes@626
  2533
    check_fpuen();
nkeynes@359
  2534
    load_reg( R_EAX, Rm );
nkeynes@395
  2535
    check_ralign32( R_EAX );
nkeynes@586
  2536
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2537
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2538
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2539
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2540
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2541
:}
nkeynes@359
  2542
LDS Rm, MACH {: 
nkeynes@671
  2543
    COUNT_INST(I_LDS);
nkeynes@359
  2544
    load_reg( R_EAX, Rm );
nkeynes@359
  2545
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2546
:}
nkeynes@359
  2547
LDS.L @Rm+, MACH {:  
nkeynes@671
  2548
    COUNT_INST(I_LDSM);
nkeynes@359
  2549
    load_reg( R_EAX, Rm );
nkeynes@395
  2550
    check_ralign32( R_EAX );
nkeynes@586
  2551
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2552
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2553
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2554
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2556
:}
nkeynes@359
  2557
LDS Rm, MACL {:  
nkeynes@671
  2558
    COUNT_INST(I_LDS);
nkeynes@359
  2559
    load_reg( R_EAX, Rm );
nkeynes@359
  2560
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2561
:}
nkeynes@359
  2562
LDS.L @Rm+, MACL {:  
nkeynes@671
  2563
    COUNT_INST(I_LDSM);
nkeynes@359
  2564
    load_reg( R_EAX, Rm );
nkeynes@395
  2565
    check_ralign32( R_EAX );
nkeynes@586
  2566
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2567
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2568
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2569
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2570
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2571
:}
nkeynes@359
  2572
LDS Rm, PR {:  
nkeynes@671
  2573
    COUNT_INST(I_LDS);
nkeynes@359
  2574
    load_reg( R_EAX, Rm );
nkeynes@359
  2575
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2576
:}
nkeynes@359
  2577
LDS.L @Rm+, PR {:  
nkeynes@671
  2578
    COUNT_INST(I_LDSM);
nkeynes@359
  2579
    load_reg( R_EAX, Rm );
nkeynes@395
  2580
    check_ralign32( R_EAX );
nkeynes@586
  2581
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2582
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2583
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2584
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2585
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2586
:}
nkeynes@550
  2587
LDTLB {:  
nkeynes@671
  2588
    COUNT_INST(I_LDTLB);
nkeynes@553
  2589
    call_func0( MMU_ldtlb );
nkeynes@550
  2590
:}
nkeynes@671
  2591
OCBI @Rn {:
nkeynes@671
  2592
    COUNT_INST(I_OCBI);
nkeynes@671
  2593
:}
nkeynes@671
  2594
OCBP @Rn {:
nkeynes@671
  2595
    COUNT_INST(I_OCBP);
nkeynes@671
  2596
:}
nkeynes@671
  2597
OCBWB @Rn {:
nkeynes@671
  2598
    COUNT_INST(I_OCBWB);
nkeynes@671
  2599
:}
nkeynes@374
  2600
PREF @Rn {:
nkeynes@671
  2601
    COUNT_INST(I_PREF);
nkeynes@374
  2602
    load_reg( R_EAX, Rn );
nkeynes@532
  2603
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2604
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2605
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2606
    JNE_rel8(end);
nkeynes@532
  2607
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2608
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2609
    JE_exc(-1);
nkeynes@380
  2610
    JMP_TARGET(end);
nkeynes@417
  2611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2612
:}
nkeynes@388
  2613
SLEEP {: 
nkeynes@671
  2614
    COUNT_INST(I_SLEEP);
nkeynes@388
  2615
    check_priv();
nkeynes@388
  2616
    call_func0( sh4_sleep );
nkeynes@417
  2617
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2618
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2619
    return 2;
nkeynes@388
  2620
:}
nkeynes@386
  2621
STC SR, Rn {:
nkeynes@671
  2622
    COUNT_INST(I_STCSR);
nkeynes@386
  2623
    check_priv();
nkeynes@386
  2624
    call_func0(sh4_read_sr);
nkeynes@386
  2625
    store_reg( R_EAX, Rn );
nkeynes@417
  2626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2627
:}
nkeynes@359
  2628
STC GBR, Rn {:  
nkeynes@671
  2629
    COUNT_INST(I_STC);
nkeynes@359
  2630
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2631
    store_reg( R_EAX, Rn );
nkeynes@359
  2632
:}
nkeynes@359
  2633
STC VBR, Rn {:  
nkeynes@671
  2634
    COUNT_INST(I_STC);
nkeynes@386
  2635
    check_priv();
nkeynes@359
  2636
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2637
    store_reg( R_EAX, Rn );
nkeynes@417
  2638
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2639
:}
nkeynes@359
  2640
STC SSR, Rn {:  
nkeynes@671
  2641
    COUNT_INST(I_STC);
nkeynes@386
  2642
    check_priv();
nkeynes@359
  2643
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2644
    store_reg( R_EAX, Rn );
nkeynes@417
  2645
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2646
:}
nkeynes@359
  2647
STC SPC, Rn {:  
nkeynes@671
  2648
    COUNT_INST(I_STC);
nkeynes@386
  2649
    check_priv();
nkeynes@359
  2650
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2651
    store_reg( R_EAX, Rn );
nkeynes@417
  2652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2653
:}
nkeynes@359
  2654
STC SGR, Rn {:  
nkeynes@671
  2655
    COUNT_INST(I_STC);
nkeynes@386
  2656
    check_priv();
nkeynes@359
  2657
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2658
    store_reg( R_EAX, Rn );
nkeynes@417
  2659
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2660
:}
nkeynes@359
  2661
STC DBR, Rn {:  
nkeynes@671
  2662
    COUNT_INST(I_STC);
nkeynes@386
  2663
    check_priv();
nkeynes@359
  2664
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2665
    store_reg( R_EAX, Rn );
nkeynes@417
  2666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2667
:}
nkeynes@374
  2668
STC Rm_BANK, Rn {:
nkeynes@671
  2669
    COUNT_INST(I_STC);
nkeynes@386
  2670
    check_priv();
nkeynes@374
  2671
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2672
    store_reg( R_EAX, Rn );
nkeynes@417
  2673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2674
:}
nkeynes@374
  2675
STC.L SR, @-Rn {:
nkeynes@671
  2676
    COUNT_INST(I_STCSRM);
nkeynes@586
  2677
    check_priv();
nkeynes@586
  2678
    load_reg( R_EAX, Rn );
nkeynes@586
  2679
    check_walign32( R_EAX );
nkeynes@586
  2680
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2681
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2682
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2683
    call_func0( sh4_read_sr );
nkeynes@586
  2684
    POP_realigned_r32( R_ECX );
nkeynes@586
  2685
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2686
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2687
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2688
:}
nkeynes@359
  2689
STC.L VBR, @-Rn {:  
nkeynes@671
  2690
    COUNT_INST(I_STCM);
nkeynes@586
  2691
    check_priv();
nkeynes@586
  2692
    load_reg( R_EAX, Rn );
nkeynes@586
  2693
    check_walign32( R_EAX );
nkeynes@586
  2694
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2695
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2696
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2697
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2698
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2699
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2700
:}
nkeynes@359
  2701
STC.L SSR, @-Rn {:  
nkeynes@671
  2702
    COUNT_INST(I_STCM);
nkeynes@586
  2703
    check_priv();
nkeynes@586
  2704
    load_reg( R_EAX, Rn );
nkeynes@586
  2705
    check_walign32( R_EAX );
nkeynes@586
  2706
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2707
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2708
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2709
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2710
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2711
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2712
:}
nkeynes@416
  2713
STC.L SPC, @-Rn {:
nkeynes@671
  2714
    COUNT_INST(I_STCM);
nkeynes@586
  2715
    check_priv();
nkeynes@586
  2716
    load_reg( R_EAX, Rn );
nkeynes@586
  2717
    check_walign32( R_EAX );
nkeynes@586
  2718
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2719
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2720
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2721
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2722
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2723
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2724
:}
nkeynes@359
  2725
STC.L SGR, @-Rn {:  
nkeynes@671
  2726
    COUNT_INST(I_STCM);
nkeynes@586
  2727
    check_priv();
nkeynes@586
  2728
    load_reg( R_EAX, Rn );
nkeynes@586
  2729
    check_walign32( R_EAX );
nkeynes@586
  2730
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2731
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2732
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2733
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2734
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2736
:}
nkeynes@359
  2737
STC.L DBR, @-Rn {:  
nkeynes@671
  2738
    COUNT_INST(I_STCM);
nkeynes@586
  2739
    check_priv();
nkeynes@586
  2740
    load_reg( R_EAX, Rn );
nkeynes@586
  2741
    check_walign32( R_EAX );
nkeynes@586
  2742
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2743
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2744
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2745
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2746
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2747
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2748
:}
nkeynes@374
  2749
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2750
    COUNT_INST(I_STCM);
nkeynes@586
  2751
    check_priv();
nkeynes@586
  2752
    load_reg( R_EAX, Rn );
nkeynes@586
  2753
    check_walign32( R_EAX );
nkeynes@586
  2754
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2755
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2756
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2757
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2758
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2759
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2760
:}
nkeynes@359
  2761
STC.L GBR, @-Rn {:  
nkeynes@671
  2762
    COUNT_INST(I_STCM);
nkeynes@586
  2763