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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 951:63483914846f
prev948:545c85cc56f1
next952:18e579840923
author nkeynes
date Wed Jan 07 05:45:15 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Tidy up exceptions+resets
Implement manual reset on general exception when SR.BL == 1
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * SH4 MMU implementation based on address space page maps. This module
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 * is responsible for all address decoding functions. 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include <assert.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "mmu.h"
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#define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
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/* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
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#define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
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/* Primary address space (used directly by SH4 cores) */
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mem_region_fn_t *sh4_address_space;
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mem_region_fn_t *sh4_user_address_space;
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/* Accessed from the UTLB accessor methods */
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uint32_t mmu_urc;
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uint32_t mmu_urb;
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/* Module globals */
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static struct utlb_default_regions *mmu_user_storequeue_regions;
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/* Structures for 1K page handling */
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static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_index;
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/* Function prototypes */
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static void mmu_invalidate_tlb();
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static void mmu_utlb_register_all();
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static void mmu_utlb_remove_entry(int);
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static void mmu_utlb_insert_entry(int);
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static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_set_tlb_enabled( int tlb_on );
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static void mmu_set_tlb_asid( uint32_t asid );
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static void mmu_set_storequeue_protected( int protected, int tlb_on );
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static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
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static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
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static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
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static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
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static void mmu_utlb_1k_init();
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static struct utlb_1k_entry *mmu_utlb_1k_alloc();
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static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
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static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
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static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
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static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
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static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
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static uint32_t get_tlb_size_mask( uint32_t flags );
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static uint32_t get_tlb_size_pages( uint32_t flags );
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#define DEFAULT_REGIONS 0
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#define DEFAULT_STOREQUEUE_REGIONS 1
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#define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
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static struct utlb_default_regions mmu_default_regions[3] = {
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        { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
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        { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
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        { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
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#define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
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/*********************** Module public functions ****************************/
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/**
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 * Allocate memory for the address space maps, and initialize them according
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 * to the default (reset) values. (TLB is disabled by default)
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 */
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void MMU_init()
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{
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    sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
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    mmu_set_tlb_enabled(0);
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    mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
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    mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
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    /* Setup P4 tlb/cache access regions */
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    mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
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    mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
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    mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
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    mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
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    mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
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    mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
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    mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
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    mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
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    mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
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    mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
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    mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
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    /* Setup P4 control region */
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    mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
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    mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
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    mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
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    mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
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    mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
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    mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
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    mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
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    mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
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    mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
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    mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
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    mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
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    mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
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    mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
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    register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
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    mmu_utlb_1k_init();
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    /* Ensure the code regions are executable */
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    mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
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    mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
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    mmu_set_tlb_enabled(mmucr&MMUCR_AT);
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    mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
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    return 0;
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}
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_urc %= mmu_urb;
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    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
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        mmu_utlb_remove_entry( mmu_urc );
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_tlb_size_mask(mmu_utlb[mmu_urc].flags);
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    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
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        mmu_utlb_insert_entry( mmu_urc );
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}
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MMIO_REGION_READ_FN( MMU, reg )
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{
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    reg &= 0xFFF;
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    switch( reg ) {
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    case MMUCR:
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        mmu_urc %= mmu_urb;
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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MMIO_REGION_WRITE_FN( MMU, reg, val )
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{
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    uint32_t tmp;
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    reg &= 0xFFF;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_set_tlb_asid( val&0xFF );
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case TRA:
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        val &= 0x000003FC;
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        break;
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    case EXPEVT:
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    case INTEVT:
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        val &= 0x00000FFF;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        if( mmu_urb == 0 ) {
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            mmu_urb = 0x40;
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        }
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & (MMUCR_SQMD) ) {
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            mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
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        }
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        if( (val ^ tmp) & (MMUCR_AT) ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            mmu_set_tlb_enabled( val & MMUCR_AT );
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
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            xlat_flush_cache(); // If we're not running, flush the cache anyway
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        }
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        break;
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    case CCR:
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        CCN_set_cache_control( val );
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        val &= 0x81A7;
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        break;
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    case MMUUNK1:
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        /* Note that if the high bit is set, this appears to reset the machine.
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         * Not emulating this behaviour yet until we know why...
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         */
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        val &= 0x00010007;
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        break;
nkeynes@939
   288
    case QACR0:
nkeynes@939
   289
    case QACR1:
nkeynes@939
   290
        val &= 0x0000001C;
nkeynes@939
   291
        break;
nkeynes@939
   292
    case PMCR1:
nkeynes@939
   293
        PMM_write_control(0, val);
nkeynes@939
   294
        val &= 0x0000C13F;
nkeynes@939
   295
        break;
nkeynes@939
   296
    case PMCR2:
nkeynes@939
   297
        PMM_write_control(1, val);
nkeynes@939
   298
        val &= 0x0000C13F;
nkeynes@939
   299
        break;
nkeynes@939
   300
    default:
nkeynes@939
   301
        break;
nkeynes@939
   302
    }
nkeynes@939
   303
    MMIO_WRITE( MMU, reg, val );
nkeynes@939
   304
}
nkeynes@939
   305
nkeynes@939
   306
/********************** 1K Page handling ***********************/
nkeynes@939
   307
/* Since we use 4K pages as our native page size, 1K pages need a bit of extra
nkeynes@939
   308
 * effort to manage - we justify this on the basis that most programs won't
nkeynes@939
   309
 * actually use 1K pages, so we may as well optimize for the common case.
nkeynes@939
   310
 * 
nkeynes@939
   311
 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
nkeynes@939
   312
 * redirects requests to the 'real' page entry. These are allocated on an
nkeynes@939
   313
 * as-needed basis, and returned to the pool when all subpages are empty.
nkeynes@939
   314
 */ 
nkeynes@939
   315
static void mmu_utlb_1k_init()
nkeynes@939
   316
{
nkeynes@939
   317
    int i;
nkeynes@939
   318
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   319
        mmu_utlb_1k_free_list[i] = i;
nkeynes@939
   320
        mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
nkeynes@939
   321
    }
nkeynes@939
   322
    mmu_utlb_1k_free_index = 0;
nkeynes@939
   323
}
nkeynes@939
   324
nkeynes@939
   325
static struct utlb_1k_entry *mmu_utlb_1k_alloc()
nkeynes@939
   326
{
nkeynes@939
   327
    assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
nkeynes@939
   328
    struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_index++];
nkeynes@939
   329
    return entry;
nkeynes@939
   330
}    
nkeynes@939
   331
nkeynes@939
   332
static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
nkeynes@939
   333
{
nkeynes@939
   334
    unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
nkeynes@939
   335
    assert( entryNo < UTLB_ENTRY_COUNT );
nkeynes@939
   336
    assert( mmu_utlb_1k_free_index > 0 );
nkeynes@939
   337
    mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
nkeynes@939
   338
}
nkeynes@939
   339
nkeynes@939
   340
nkeynes@939
   341
/********************** Address space maintenance *************************/
nkeynes@939
   342
nkeynes@939
   343
/**
nkeynes@939
   344
 * MMU accessor functions just increment URC - fixup here if necessary
nkeynes@939
   345
 */
nkeynes@939
   346
static inline void mmu_urc_fixup()
nkeynes@939
   347
{
nkeynes@939
   348
   mmu_urc %= mmu_urb; 
nkeynes@939
   349
}
nkeynes@939
   350
nkeynes@939
   351
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   352
{
nkeynes@939
   353
    int count = (end - start) >> 12;
nkeynes@939
   354
    mem_region_fn_t *ptr = &sh4_address_space[start>>12];
nkeynes@939
   355
    while( count-- > 0 ) {
nkeynes@939
   356
        *ptr++ = fn;
nkeynes@939
   357
    }
nkeynes@939
   358
}
nkeynes@939
   359
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   360
{
nkeynes@939
   361
    int count = (end - start) >> 12;
nkeynes@939
   362
    mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
nkeynes@939
   363
    while( count-- > 0 ) {
nkeynes@939
   364
        *ptr++ = fn;
nkeynes@939
   365
    }
nkeynes@939
   366
}
nkeynes@939
   367
nkeynes@939
   368
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
nkeynes@939
   369
{
nkeynes@939
   370
    int i;
nkeynes@939
   371
    if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
nkeynes@939
   372
        /* TLB on */
nkeynes@939
   373
        sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
nkeynes@939
   374
        sh4_address_space[(page|0xA0000000)>>12] = fn;
nkeynes@939
   375
        /* Scan UTLB and update any direct-referencing entries */
nkeynes@939
   376
    } else {
nkeynes@939
   377
        /* Direct map to U0, P0, P1, P2, P3 */
nkeynes@939
   378
        for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
nkeynes@939
   379
            sh4_address_space[(page|i)>>12] = fn;
nkeynes@939
   380
        }
nkeynes@939
   381
        for( i=0; i < 0x80000000; i+= 0x20000000 ) {
nkeynes@939
   382
            sh4_user_address_space[(page|i)>>12] = fn;
nkeynes@939
   383
        }
nkeynes@939
   384
    }
nkeynes@939
   385
}
nkeynes@939
   386
nkeynes@939
   387
static void mmu_set_tlb_enabled( int tlb_on )
nkeynes@939
   388
{
nkeynes@939
   389
    mem_region_fn_t *ptr, *uptr;
nkeynes@939
   390
    int i;
nkeynes@939
   391
    
nkeynes@946
   392
    /* Reset the storequeue area */
nkeynes@946
   393
nkeynes@939
   394
    if( tlb_on ) {
nkeynes@939
   395
        mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@939
   396
        mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
nkeynes@939
   397
        mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@946
   398
        
nkeynes@946
   399
        /* Default SQ prefetch goes to TLB miss (?) */
nkeynes@946
   400
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
nkeynes@946
   401
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@939
   402
        mmu_utlb_register_all();
nkeynes@939
   403
    } else {
nkeynes@939
   404
        for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   405
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   406
        }
nkeynes@939
   407
        for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   408
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   409
        }
nkeynes@946
   410
nkeynes@946
   411
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   412
        if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   413
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
nkeynes@946
   414
        } else {
nkeynes@946
   415
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   416
        }
nkeynes@939
   417
    }
nkeynes@946
   418
    
nkeynes@939
   419
}
nkeynes@939
   420
nkeynes@946
   421
/**
nkeynes@946
   422
 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
nkeynes@946
   423
 * anything expects to do this frequently.
nkeynes@946
   424
 */
nkeynes@946
   425
static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
nkeynes@939
   426
{
nkeynes@946
   427
    mem_region_fn_t nontlb_region;
nkeynes@946
   428
    int i;
nkeynes@946
   429
nkeynes@939
   430
    if( protected ) {
nkeynes@946
   431
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
nkeynes@946
   432
        nontlb_region = &p4_region_storequeue_sqmd;
nkeynes@939
   433
    } else {
nkeynes@946
   434
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   435
        nontlb_region = &p4_region_storequeue; 
nkeynes@939
   436
    }
nkeynes@946
   437
nkeynes@946
   438
    if( tlb_on ) {
nkeynes@946
   439
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@946
   440
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@946
   441
            if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   442
                mmu_utlb_insert_entry(i);
nkeynes@946
   443
            }
nkeynes@946
   444
        }
nkeynes@946
   445
    } else {
nkeynes@946
   446
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
nkeynes@946
   447
    }
nkeynes@946
   448
    
nkeynes@939
   449
}
nkeynes@939
   450
nkeynes@939
   451
static void mmu_set_tlb_asid( uint32_t asid )
nkeynes@939
   452
{
nkeynes@939
   453
    /* Scan for pages that need to be remapped */
nkeynes@939
   454
    int i;
nkeynes@939
   455
    if( IS_SV_ENABLED() ) {
nkeynes@939
   456
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   457
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   458
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   459
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   460
                        if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   461
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   462
                            mmu_utlb_remap_pages( FALSE, TRUE, i );
nkeynes@939
   463
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   464
                        mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   465
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   466
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   467
                    }
nkeynes@939
   468
                }
nkeynes@939
   469
            }
nkeynes@939
   470
        }
nkeynes@939
   471
    } else {
nkeynes@939
   472
        // Remap both Priv+user pages
nkeynes@939
   473
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   474
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   475
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   476
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   477
                        if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   478
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   479
                            mmu_utlb_remap_pages( TRUE, TRUE, i );
nkeynes@939
   480
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   481
                        mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   482
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   483
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   484
                    }
nkeynes@939
   485
                }
nkeynes@939
   486
            }
nkeynes@939
   487
        }
nkeynes@939
   488
    }
nkeynes@939
   489
    
nkeynes@939
   490
    mmu_asid = asid;
nkeynes@939
   491
}
nkeynes@939
   492
nkeynes@939
   493
static uint32_t get_tlb_size_mask( uint32_t flags )
nkeynes@939
   494
{
nkeynes@939
   495
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   496
    case TLB_SIZE_1K: return MASK_1K;
nkeynes@939
   497
    case TLB_SIZE_4K: return MASK_4K;
nkeynes@939
   498
    case TLB_SIZE_64K: return MASK_64K;
nkeynes@939
   499
    case TLB_SIZE_1M: return MASK_1M;
nkeynes@939
   500
    default: return 0; /* Unreachable */
nkeynes@939
   501
    }
nkeynes@939
   502
}
nkeynes@939
   503
static uint32_t get_tlb_size_pages( uint32_t flags )
nkeynes@939
   504
{
nkeynes@939
   505
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   506
    case TLB_SIZE_1K: return 0;
nkeynes@939
   507
    case TLB_SIZE_4K: return 1;
nkeynes@939
   508
    case TLB_SIZE_64K: return 16;
nkeynes@939
   509
    case TLB_SIZE_1M: return 256;
nkeynes@939
   510
    default: return 0; /* Unreachable */
nkeynes@939
   511
    }
nkeynes@939
   512
}
nkeynes@939
   513
nkeynes@939
   514
/**
nkeynes@939
   515
 * Add a new TLB entry mapping to the address space table. If any of the pages
nkeynes@939
   516
 * are already mapped, they are mapped to the TLB multi-hit page instead.
nkeynes@939
   517
 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
nkeynes@939
   518
 */ 
nkeynes@939
   519
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
nkeynes@939
   520
{
nkeynes@939
   521
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   522
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   523
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   524
    struct utlb_default_regions *userdefs = privdefs;    
nkeynes@946
   525
    
nkeynes@939
   526
    gboolean mapping_ok = TRUE;
nkeynes@939
   527
    int i;
nkeynes@939
   528
    
nkeynes@939
   529
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   530
        /* Storequeue mapping */
nkeynes@946
   531
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   532
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   533
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   534
        user_page = NULL; /* No user access to P3 region */
nkeynes@939
   535
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   536
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   537
    }
nkeynes@939
   538
nkeynes@939
   539
    if( npages == 0 ) {
nkeynes@939
   540
        struct utlb_1k_entry *ent;
nkeynes@939
   541
        int i, idx = (start_addr >> 10) & 0x03;
nkeynes@939
   542
        if( IS_1K_PAGE_ENTRY(*ptr) ) {
nkeynes@939
   543
            ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   544
        } else {
nkeynes@939
   545
            ent = mmu_utlb_1k_alloc();
nkeynes@939
   546
            /* New 1K struct - init to previous contents of region */
nkeynes@939
   547
            for( i=0; i<4; i++ ) {
nkeynes@939
   548
                ent->subpages[i] = *ptr;
nkeynes@939
   549
                ent->user_subpages[i] = *uptr;
nkeynes@939
   550
            }
nkeynes@939
   551
            *ptr = &ent->fn;
nkeynes@939
   552
            *uptr = &ent->user_fn;
nkeynes@939
   553
        }
nkeynes@939
   554
        
nkeynes@939
   555
        if( priv_page != NULL ) {
nkeynes@946
   556
            if( ent->subpages[idx] == privdefs->tlb_miss ) {
nkeynes@939
   557
                ent->subpages[idx] = priv_page;
nkeynes@939
   558
            } else {
nkeynes@939
   559
                mapping_ok = FALSE;
nkeynes@946
   560
                ent->subpages[idx] = privdefs->tlb_multihit;
nkeynes@939
   561
            }
nkeynes@939
   562
        }
nkeynes@939
   563
        if( user_page != NULL ) {
nkeynes@946
   564
            if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
nkeynes@939
   565
                ent->user_subpages[idx] = user_page;
nkeynes@939
   566
            } else {
nkeynes@939
   567
                mapping_ok = FALSE;
nkeynes@946
   568
                ent->user_subpages[idx] = userdefs->tlb_multihit;
nkeynes@939
   569
            }
nkeynes@939
   570
        }
nkeynes@939
   571
        
nkeynes@939
   572
    } else {
nkeynes@943
   573
        if( priv_page != NULL ) {
nkeynes@946
   574
            /* Privileged mapping only */
nkeynes@946
   575
            for( i=0; i<npages; i++ ) {
nkeynes@946
   576
                if( *ptr == privdefs->tlb_miss ) {
nkeynes@946
   577
                    *ptr++ = priv_page;
nkeynes@946
   578
                } else {
nkeynes@946
   579
                    mapping_ok = FALSE;
nkeynes@946
   580
                    *ptr++ = privdefs->tlb_multihit;
nkeynes@939
   581
                }
nkeynes@939
   582
            }
nkeynes@946
   583
        }
nkeynes@946
   584
        if( user_page != NULL ) {
nkeynes@943
   585
            /* User mapping only (eg ASID change remap w/ SV=1) */
nkeynes@939
   586
            for( i=0; i<npages; i++ ) {
nkeynes@946
   587
                if( *uptr == userdefs->tlb_miss ) {
nkeynes@939
   588
                    *uptr++ = user_page;
nkeynes@939
   589
                } else {
nkeynes@939
   590
                    mapping_ok = FALSE;
nkeynes@946
   591
                    *uptr++ = userdefs->tlb_multihit;
nkeynes@939
   592
                }
nkeynes@939
   593
            }        
nkeynes@939
   594
        }
nkeynes@939
   595
    }
nkeynes@946
   596
nkeynes@939
   597
    return mapping_ok;
nkeynes@939
   598
}
nkeynes@939
   599
nkeynes@939
   600
/**
nkeynes@943
   601
 * Remap any pages within the region covered by entryNo, but not including 
nkeynes@943
   602
 * entryNo itself. This is used to reestablish pages that were previously
nkeynes@943
   603
 * covered by a multi-hit exception region when one of the pages is removed.
nkeynes@943
   604
 */
nkeynes@943
   605
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
nkeynes@943
   606
{
nkeynes@943
   607
    int mask = mmu_utlb[entryNo].mask;
nkeynes@943
   608
    uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
nkeynes@943
   609
    int i;
nkeynes@943
   610
    
nkeynes@943
   611
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@943
   612
        if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
nkeynes@943
   613
            /* Overlapping region */
nkeynes@943
   614
            mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
nkeynes@943
   615
            mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
nkeynes@943
   616
            uint32_t start_addr;
nkeynes@943
   617
            int npages;
nkeynes@943
   618
nkeynes@943
   619
            if( mmu_utlb[i].mask >= mask ) {
nkeynes@943
   620
                /* entry is no larger than the area we're replacing - map completely */
nkeynes@943
   621
                start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
nkeynes@943
   622
                npages = get_tlb_size_pages( mmu_utlb[i].flags );
nkeynes@943
   623
            } else {
nkeynes@943
   624
                /* Otherwise map subset - region covered by removed page */
nkeynes@943
   625
                start_addr = remap_addr;
nkeynes@943
   626
                npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
nkeynes@943
   627
            }
nkeynes@943
   628
nkeynes@943
   629
            if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
nkeynes@943
   630
                mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
nkeynes@943
   631
            } else if( IS_SV_ENABLED() ) {
nkeynes@943
   632
                mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
nkeynes@943
   633
            }
nkeynes@943
   634
nkeynes@943
   635
        }
nkeynes@943
   636
    }
nkeynes@943
   637
}
nkeynes@943
   638
nkeynes@943
   639
/**
nkeynes@939
   640
 * Remove a previous TLB mapping (replacing them with the TLB miss region).
nkeynes@939
   641
 * @return FALSE if any pages were previously mapped to the TLB multihit page, 
nkeynes@939
   642
 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
nkeynes@939
   643
 */
nkeynes@943
   644
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
nkeynes@939
   645
{
nkeynes@939
   646
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   647
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   648
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   649
    struct utlb_default_regions *userdefs = privdefs;
nkeynes@946
   650
nkeynes@939
   651
    gboolean unmapping_ok = TRUE;
nkeynes@939
   652
    int i;
nkeynes@939
   653
    
nkeynes@939
   654
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   655
        /* Storequeue mapping */
nkeynes@946
   656
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   657
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   658
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   659
        unmap_user = FALSE;
nkeynes@939
   660
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   661
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   662
    }
nkeynes@939
   663
nkeynes@939
   664
    if( npages == 0 ) { // 1K page
nkeynes@939
   665
        assert( IS_1K_PAGE_ENTRY( *ptr ) );
nkeynes@939
   666
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   667
        int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
nkeynes@946
   668
        if( ent->subpages[idx] == privdefs->tlb_multihit ) {
nkeynes@939
   669
            unmapping_ok = FALSE;
nkeynes@939
   670
        }
nkeynes@943
   671
        if( unmap_priv )
nkeynes@946
   672
            ent->subpages[idx] = privdefs->tlb_miss;
nkeynes@943
   673
        if( unmap_user )
nkeynes@946
   674
            ent->user_subpages[idx] = userdefs->tlb_miss;
nkeynes@939
   675
nkeynes@939
   676
        /* If all 4 subpages have the same content, merge them together and
nkeynes@939
   677
         * release the 1K entry
nkeynes@939
   678
         */
nkeynes@939
   679
        mem_region_fn_t priv_page = ent->subpages[0];
nkeynes@939
   680
        mem_region_fn_t user_page = ent->user_subpages[0];
nkeynes@939
   681
        for( i=1; i<4; i++ ) {
nkeynes@939
   682
            if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
nkeynes@939
   683
                mergeable = 0;
nkeynes@939
   684
                break;
nkeynes@939
   685
            }
nkeynes@939
   686
        }
nkeynes@939
   687
        if( mergeable ) {
nkeynes@939
   688
            mmu_utlb_1k_free(ent);
nkeynes@939
   689
            *ptr = priv_page;
nkeynes@939
   690
            *uptr = user_page;
nkeynes@939
   691
        }
nkeynes@939
   692
    } else {
nkeynes@943
   693
        if( unmap_priv ) {
nkeynes@946
   694
            /* Privileged (un)mapping */
nkeynes@939
   695
            for( i=0; i<npages; i++ ) {
nkeynes@946
   696
                if( *ptr == privdefs->tlb_multihit ) {
nkeynes@939
   697
                    unmapping_ok = FALSE;
nkeynes@939
   698
                }
nkeynes@946
   699
                *ptr++ = privdefs->tlb_miss;
nkeynes@946
   700
            }
nkeynes@946
   701
        }
nkeynes@946
   702
        if( unmap_user ) {
nkeynes@946
   703
            /* User (un)mapping */
nkeynes@946
   704
            for( i=0; i<npages; i++ ) {
nkeynes@946
   705
                if( *uptr == userdefs->tlb_multihit ) {
nkeynes@946
   706
                    unmapping_ok = FALSE;
nkeynes@946
   707
                }
nkeynes@946
   708
                *uptr++ = userdefs->tlb_miss;
nkeynes@943
   709
            }            
nkeynes@939
   710
        }
nkeynes@939
   711
    }
nkeynes@943
   712
    
nkeynes@939
   713
    return unmapping_ok;
nkeynes@939
   714
}
nkeynes@939
   715
nkeynes@939
   716
static void mmu_utlb_insert_entry( int entry )
nkeynes@939
   717
{
nkeynes@939
   718
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   719
    mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
nkeynes@939
   720
    mem_region_fn_t upage;
nkeynes@939
   721
    sh4addr_t start_addr = ent->vpn & ent->mask;
nkeynes@939
   722
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   723
nkeynes@946
   724
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   725
        /* Store queue mappings are a bit different - normal access is fixed to
nkeynes@946
   726
         * the store queue register block, and we only map prefetches through
nkeynes@946
   727
         * the TLB 
nkeynes@946
   728
         */
nkeynes@946
   729
        mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
nkeynes@946
   730
nkeynes@946
   731
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   732
            upage = mmu_user_storequeue_regions->tlb_prot;
nkeynes@946
   733
        } else if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   734
            upage = &p4_region_storequeue_sqmd;
nkeynes@946
   735
        } else {
nkeynes@946
   736
            upage = page;
nkeynes@946
   737
        }
nkeynes@946
   738
nkeynes@946
   739
    }  else {
nkeynes@946
   740
nkeynes@946
   741
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   742
            upage = &mem_region_tlb_protected;
nkeynes@946
   743
        } else {        
nkeynes@946
   744
            upage = page;
nkeynes@946
   745
        }
nkeynes@946
   746
nkeynes@946
   747
        if( (ent->flags & TLB_WRITABLE) == 0 ) {
nkeynes@946
   748
            page->write_long = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   749
            page->write_word = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   750
            page->write_byte = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   751
            page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
nkeynes@946
   752
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   753
        } else if( (ent->flags & TLB_DIRTY) == 0 ) {
nkeynes@946
   754
            page->write_long = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   755
            page->write_word = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   756
            page->write_byte = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   757
            page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
nkeynes@946
   758
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   759
        } else {
nkeynes@946
   760
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
nkeynes@946
   761
        }
nkeynes@939
   762
    }
nkeynes@946
   763
    
nkeynes@939
   764
    mmu_utlb_pages[entry].user_fn = upage;
nkeynes@939
   765
nkeynes@939
   766
    /* Is page visible? */
nkeynes@939
   767
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
nkeynes@939
   768
        mmu_utlb_map_pages( page, upage, start_addr, npages );
nkeynes@939
   769
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   770
        mmu_utlb_map_pages( page, NULL, start_addr, npages );
nkeynes@939
   771
    }
nkeynes@939
   772
}
nkeynes@939
   773
nkeynes@939
   774
static void mmu_utlb_remove_entry( int entry )
nkeynes@939
   775
{
nkeynes@939
   776
    int i, j;
nkeynes@939
   777
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   778
    sh4addr_t start_addr = ent->vpn&ent->mask;
nkeynes@939
   779
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   780
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@939
   781
    gboolean unmap_user;
nkeynes@939
   782
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   783
    
nkeynes@939
   784
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
nkeynes@939
   785
        unmap_user = TRUE;
nkeynes@939
   786
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   787
        unmap_user = FALSE;
nkeynes@939
   788
    } else {
nkeynes@939
   789
        return; // Not mapped
nkeynes@939
   790
    }
nkeynes@939
   791
    
nkeynes@943
   792
    gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
nkeynes@939
   793
    
nkeynes@939
   794
    if( !clean_unmap ) {
nkeynes@943
   795
        mmu_utlb_remap_pages( TRUE, unmap_user, entry );
nkeynes@939
   796
    }
nkeynes@939
   797
}
nkeynes@939
   798
nkeynes@939
   799
static void mmu_utlb_register_all()
nkeynes@939
   800
{
nkeynes@939
   801
    int i;
nkeynes@939
   802
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   803
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@939
   804
            mmu_utlb_insert_entry( i );
nkeynes@939
   805
    }
nkeynes@939
   806
}
nkeynes@939
   807
nkeynes@550
   808
static void mmu_invalidate_tlb()
nkeynes@550
   809
{
nkeynes@550
   810
    int i;
nkeynes@550
   811
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   812
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   813
    }
nkeynes@939
   814
    if( IS_TLB_ENABLED() ) {
nkeynes@939
   815
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   816
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   817
                mmu_utlb_remove_entry( i );
nkeynes@939
   818
            }
nkeynes@939
   819
        }
nkeynes@939
   820
    }
nkeynes@550
   821
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   822
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   823
    }
nkeynes@550
   824
}
nkeynes@550
   825
nkeynes@586
   826
/******************************************************************************/
nkeynes@586
   827
/*                        MMU TLB address translation                         */
nkeynes@586
   828
/******************************************************************************/
nkeynes@586
   829
nkeynes@586
   830
/**
nkeynes@939
   831
 * Translate a 32-bit address into a UTLB entry number. Does not check for
nkeynes@939
   832
 * page protection etc.
nkeynes@939
   833
 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
nkeynes@586
   834
 */
nkeynes@939
   835
int mmu_utlb_entry_for_vpn( uint32_t vpn )
nkeynes@939
   836
{
nkeynes@939
   837
    mem_region_fn_t fn = sh4_address_space[vpn>>12];
nkeynes@939
   838
    if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@939
   839
        return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@939
   840
    } else if( fn == &mem_region_tlb_multihit ) {
nkeynes@939
   841
        return -2;
nkeynes@939
   842
    } else {
nkeynes@939
   843
        return -1;
nkeynes@939
   844
    }
nkeynes@939
   845
}
nkeynes@939
   846
nkeynes@586
   847
nkeynes@586
   848
/**
nkeynes@586
   849
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   850
 * Possible utcomes are:
nkeynes@586
   851
 *   0..63 Single match - good, return entry found
nkeynes@586
   852
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   853
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   854
 * @param vpn virtual address to resolve
nkeynes@586
   855
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   856
 */
nkeynes@586
   857
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   858
{
nkeynes@586
   859
    int result = -1;
nkeynes@586
   860
    unsigned int i;
nkeynes@586
   861
nkeynes@586
   862
    mmu_urc++;
nkeynes@586
   863
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   864
        mmu_urc = 0;
nkeynes@586
   865
    }
nkeynes@586
   866
nkeynes@586
   867
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   868
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   869
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   870
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   871
            if( result != -1 ) {
nkeynes@736
   872
                return -2;
nkeynes@736
   873
            }
nkeynes@736
   874
            result = i;
nkeynes@736
   875
        }
nkeynes@586
   876
    }
nkeynes@586
   877
    return result;
nkeynes@586
   878
}
nkeynes@586
   879
nkeynes@586
   880
/**
nkeynes@586
   881
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   882
 * Possible utcomes are:
nkeynes@586
   883
 *   0..63 Single match - good, return entry found
nkeynes@586
   884
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   885
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   886
 * @param vpn virtual address to resolve
nkeynes@586
   887
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   888
 */
nkeynes@586
   889
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   890
{
nkeynes@586
   891
    int result = -1;
nkeynes@586
   892
    unsigned int i;
nkeynes@586
   893
nkeynes@586
   894
    mmu_urc++;
nkeynes@586
   895
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   896
        mmu_urc = 0;
nkeynes@586
   897
    }
nkeynes@586
   898
nkeynes@586
   899
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   900
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   901
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   902
            if( result != -1 ) {
nkeynes@736
   903
                return -2;
nkeynes@736
   904
            }
nkeynes@736
   905
            result = i;
nkeynes@736
   906
        }
nkeynes@586
   907
    }
nkeynes@586
   908
nkeynes@586
   909
    return result;
nkeynes@586
   910
}
nkeynes@586
   911
nkeynes@586
   912
/**
nkeynes@586
   913
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   914
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   915
 */
nkeynes@586
   916
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   917
{
nkeynes@586
   918
    int replace;
nkeynes@586
   919
    /* Determine entry to replace based on lrui */
nkeynes@586
   920
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   921
        replace = 0;
nkeynes@736
   922
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   923
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   924
        replace = 1;
nkeynes@736
   925
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   926
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   927
        replace = 2;
nkeynes@736
   928
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   929
    } else { // Note - gets invalid entries too
nkeynes@736
   930
        replace = 3;
nkeynes@736
   931
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   932
    }
nkeynes@586
   933
nkeynes@586
   934
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   935
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   936
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   937
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   938
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   939
    return replace;
nkeynes@586
   940
}
nkeynes@586
   941
nkeynes@586
   942
/**
nkeynes@586
   943
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   944
 * Possible utcomes are:
nkeynes@586
   945
 *   0..63 Single match - good, return entry found
nkeynes@586
   946
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   947
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   948
 * @param vpn virtual address to resolve
nkeynes@586
   949
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   950
 */
nkeynes@586
   951
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   952
{
nkeynes@586
   953
    int result = -1;
nkeynes@586
   954
    unsigned int i;
nkeynes@586
   955
nkeynes@586
   956
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   957
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   958
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   959
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   960
            if( result != -1 ) {
nkeynes@736
   961
                return -2;
nkeynes@736
   962
            }
nkeynes@736
   963
            result = i;
nkeynes@736
   964
        }
nkeynes@586
   965
    }
nkeynes@586
   966
nkeynes@586
   967
    if( result == -1 ) {
nkeynes@939
   968
        int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
nkeynes@736
   969
        if( utlbEntry < 0 ) {
nkeynes@736
   970
            return utlbEntry;
nkeynes@736
   971
        } else {
nkeynes@736
   972
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   973
        }
nkeynes@586
   974
    }
nkeynes@586
   975
nkeynes@586
   976
    switch( result ) {
nkeynes@586
   977
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   978
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   979
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   980
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   981
    }
nkeynes@736
   982
nkeynes@586
   983
    return result;
nkeynes@586
   984
}
nkeynes@586
   985
nkeynes@586
   986
/**
nkeynes@586
   987
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   988
 * Possible utcomes are:
nkeynes@586
   989
 *   0..63 Single match - good, return entry found
nkeynes@586
   990
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   991
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   992
 * @param vpn virtual address to resolve
nkeynes@586
   993
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   994
 */
nkeynes@586
   995
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   996
{
nkeynes@586
   997
    int result = -1;
nkeynes@586
   998
    unsigned int i;
nkeynes@586
   999
nkeynes@586
  1000
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
  1001
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
  1002
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
  1003
            if( result != -1 ) {
nkeynes@736
  1004
                return -2;
nkeynes@736
  1005
            }
nkeynes@736
  1006
            result = i;
nkeynes@736
  1007
        }
nkeynes@586
  1008
    }
nkeynes@586
  1009
nkeynes@586
  1010
    if( result == -1 ) {
nkeynes@736
  1011
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
  1012
        if( utlbEntry < 0 ) {
nkeynes@736
  1013
            return utlbEntry;
nkeynes@736
  1014
        } else {
nkeynes@736
  1015
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1016
        }
nkeynes@586
  1017
    }
nkeynes@586
  1018
nkeynes@586
  1019
    switch( result ) {
nkeynes@586
  1020
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1021
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1022
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1023
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1024
    }
nkeynes@736
  1025
nkeynes@586
  1026
    return result;
nkeynes@586
  1027
}
nkeynes@927
  1028
nkeynes@586
  1029
/**
nkeynes@586
  1030
 * Update the icache for an untranslated address
nkeynes@586
  1031
 */
nkeynes@905
  1032
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
  1033
{
nkeynes@586
  1034
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
  1035
        /* Main ram */
nkeynes@736
  1036
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
  1037
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
  1038
        sh4_icache.mask = 0xFF000000;
nkeynes@934
  1039
        sh4_icache.page = dc_main_ram;
nkeynes@586
  1040
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
  1041
        /* BIOS ROM */
nkeynes@736
  1042
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
  1043
        sh4_icache.page_ppa = 0;
nkeynes@736
  1044
        sh4_icache.mask = 0xFFE00000;
nkeynes@934
  1045
        sh4_icache.page = dc_boot_rom;
nkeynes@586
  1046
    } else {
nkeynes@736
  1047
        /* not supported */
nkeynes@736
  1048
        sh4_icache.page_vma = -1;
nkeynes@586
  1049
    }
nkeynes@586
  1050
}
nkeynes@586
  1051
nkeynes@586
  1052
/**
nkeynes@586
  1053
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
  1054
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
  1055
 * will be invalidated instead.
nkeynes@586
  1056
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
  1057
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
  1058
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
  1059
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
  1060
 * the icache.
nkeynes@586
  1061
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
  1062
 * if an exception was raised.
nkeynes@586
  1063
 */
nkeynes@905
  1064
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
  1065
{
nkeynes@586
  1066
    int entryNo;
nkeynes@586
  1067
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
  1068
        if( addr & 0x80000000 ) {
nkeynes@736
  1069
            if( addr < 0xC0000000 ) {
nkeynes@736
  1070
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1071
                mmu_update_icache_phys(addr);
nkeynes@736
  1072
                return TRUE;
nkeynes@736
  1073
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@939
  1074
                RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1075
                return FALSE;
nkeynes@736
  1076
            }
nkeynes@736
  1077
        }
nkeynes@586
  1078
nkeynes@736
  1079
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1080
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1081
            mmu_update_icache_phys(addr);
nkeynes@736
  1082
            return TRUE;
nkeynes@736
  1083
        }
nkeynes@736
  1084
nkeynes@826
  1085
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1086
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1087
        else
nkeynes@807
  1088
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1089
    } else {
nkeynes@736
  1090
        if( addr & 0x80000000 ) {
nkeynes@939
  1091
            RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1092
            return FALSE;
nkeynes@736
  1093
        }
nkeynes@586
  1094
nkeynes@736
  1095
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1096
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1097
            mmu_update_icache_phys(addr);
nkeynes@736
  1098
            return TRUE;
nkeynes@736
  1099
        }
nkeynes@736
  1100
nkeynes@807
  1101
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1102
nkeynes@736
  1103
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@939
  1104
            RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@736
  1105
            return FALSE;
nkeynes@736
  1106
        }
nkeynes@586
  1107
    }
nkeynes@586
  1108
nkeynes@586
  1109
    switch(entryNo) {
nkeynes@586
  1110
    case -1:
nkeynes@939
  1111
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@736
  1112
    return FALSE;
nkeynes@586
  1113
    case -2:
nkeynes@939
  1114
    RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@736
  1115
    return FALSE;
nkeynes@586
  1116
    default:
nkeynes@736
  1117
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1118
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1119
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1120
            sh4_icache.page_vma = -1;
nkeynes@736
  1121
        } else {
nkeynes@736
  1122
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1123
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1124
        }
nkeynes@736
  1125
        return TRUE;
nkeynes@586
  1126
    }
nkeynes@586
  1127
}
nkeynes@586
  1128
nkeynes@597
  1129
/**
nkeynes@826
  1130
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1131
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1132
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1133
 * on translation failure.
nkeynes@597
  1134
 */
nkeynes@905
  1135
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1136
{
nkeynes@597
  1137
    if( vma & 0x80000000 ) {
nkeynes@736
  1138
        if( vma < 0xC0000000 ) {
nkeynes@736
  1139
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1140
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1141
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1142
            /* Not translatable */
nkeynes@736
  1143
            return MMU_VMA_ERROR;
nkeynes@736
  1144
        }
nkeynes@597
  1145
    }
nkeynes@597
  1146
nkeynes@597
  1147
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1148
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1149
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1150
    }
nkeynes@736
  1151
nkeynes@597
  1152
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1153
    if( entryNo == -2 ) {
nkeynes@736
  1154
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1155
    }
nkeynes@597
  1156
    if( entryNo < 0 ) {
nkeynes@736
  1157
        return MMU_VMA_ERROR;
nkeynes@597
  1158
    } else {
nkeynes@826
  1159
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1160
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1161
    }
nkeynes@597
  1162
}
nkeynes@597
  1163
nkeynes@939
  1164
/********************** TLB Direct-Access Regions ***************************/
nkeynes@939
  1165
#ifdef HAVE_FRAME_ADDRESS
nkeynes@939
  1166
#define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
nkeynes@939
  1167
#else
nkeynes@939
  1168
#define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
nkeynes@939
  1169
#endif
nkeynes@939
  1170
nkeynes@939
  1171
nkeynes@939
  1172
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@939
  1173
nkeynes@939
  1174
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@939
  1175
{
nkeynes@939
  1176
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1177
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@939
  1178
}
nkeynes@939
  1179
nkeynes@939
  1180
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1181
{
nkeynes@939
  1182
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1183
    ent->vpn = val & 0xFFFFFC00;
nkeynes@939
  1184
    ent->asid = val & 0x000000FF;
nkeynes@939
  1185
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@939
  1186
}
nkeynes@939
  1187
nkeynes@939
  1188
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@939
  1189
{
nkeynes@939
  1190
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1191
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@939
  1192
}
nkeynes@939
  1193
nkeynes@939
  1194
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1195
{
nkeynes@939
  1196
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1197
    ent->ppn = val & 0x1FFFFC00;
nkeynes@939
  1198
    ent->flags = val & 0x00001DA;
nkeynes@939
  1199
    ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1200
    if( ent->ppn >= 0x1C000000 )
nkeynes@939
  1201
        ent->ppn |= 0xE0000000;
nkeynes@939
  1202
}
nkeynes@939
  1203
nkeynes@939
  1204
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@939
  1205
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@939
  1206
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@939
  1207
nkeynes@939
  1208
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@939
  1209
{
nkeynes@939
  1210
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1211
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@939
  1212
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@939
  1213
}
nkeynes@939
  1214
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@939
  1215
{
nkeynes@939
  1216
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1217
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1218
        return ent->pcmcia;
nkeynes@939
  1219
    } else {
nkeynes@939
  1220
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@939
  1221
    }
nkeynes@939
  1222
}
nkeynes@939
  1223
nkeynes@939
  1224
/**
nkeynes@939
  1225
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@939
  1226
 * lookup but ignores the valid bit.
nkeynes@939
  1227
 */
nkeynes@939
  1228
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1229
{
nkeynes@939
  1230
    int result = -1;
nkeynes@939
  1231
    unsigned int i;
nkeynes@939
  1232
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1233
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@939
  1234
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@939
  1235
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@939
  1236
            if( result != -1 ) {
nkeynes@939
  1237
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@939
  1238
                return -2;
nkeynes@939
  1239
            }
nkeynes@939
  1240
            result = i;
nkeynes@939
  1241
        }
nkeynes@939
  1242
    }
nkeynes@939
  1243
    return result;
nkeynes@939
  1244
}
nkeynes@939
  1245
nkeynes@939
  1246
/**
nkeynes@939
  1247
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@939
  1248
 * lookup but ignores the valid bit.
nkeynes@939
  1249
 */
nkeynes@939
  1250
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1251
{
nkeynes@939
  1252
    int result = -1;
nkeynes@939
  1253
    unsigned int i;
nkeynes@939
  1254
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1255
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@939
  1256
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@939
  1257
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@939
  1258
            if( result != -1 ) {
nkeynes@939
  1259
                return -2;
nkeynes@939
  1260
            }
nkeynes@939
  1261
            result = i;
nkeynes@939
  1262
        }
nkeynes@939
  1263
    }
nkeynes@939
  1264
    return result;
nkeynes@939
  1265
}
nkeynes@939
  1266
nkeynes@939
  1267
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1268
{
nkeynes@939
  1269
    if( UTLB_ASSOC(addr) ) {
nkeynes@939
  1270
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1271
        if( utlb >= 0 ) {
nkeynes@939
  1272
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@939
  1273
            uint32_t old_flags = ent->flags;
nkeynes@939
  1274
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@939
  1275
            ent->flags |= (val & TLB_VALID);
nkeynes@939
  1276
            ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1277
            if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
nkeynes@939
  1278
                if( old_flags & TLB_VALID )
nkeynes@939
  1279
                    mmu_utlb_remove_entry( utlb );
nkeynes@939
  1280
                if( ent->flags & TLB_VALID )
nkeynes@939
  1281
                    mmu_utlb_insert_entry( utlb );
nkeynes@939
  1282
            }
nkeynes@939
  1283
        }
nkeynes@939
  1284
nkeynes@939
  1285
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1286
        if( itlb >= 0 ) {
nkeynes@939
  1287
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@939
  1288
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@939
  1289
        }
nkeynes@939
  1290
nkeynes@939
  1291
        if( itlb == -2 || utlb == -2 ) {
nkeynes@939
  1292
            RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@939
  1293
            EXCEPTION_EXIT();
nkeynes@939
  1294
            return;
nkeynes@939
  1295
        }
nkeynes@939
  1296
    } else {
nkeynes@939
  1297
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1298
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1299
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1300
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@939
  1301
        ent->asid = (val & 0xFF);
nkeynes@939
  1302
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@939
  1303
        ent->flags |= (val & TLB_VALID);
nkeynes@939
  1304
        ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1305
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1306
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1307
    }
nkeynes@939
  1308
}
nkeynes@939
  1309
nkeynes@939
  1310
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1311
{
nkeynes@939
  1312
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1313
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1314
        ent->pcmcia = val & 0x0000000F;
nkeynes@939
  1315
    } else {
nkeynes@939
  1316
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1317
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1318
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@939
  1319
        ent->flags = (val & 0x000001FF);
nkeynes@939
  1320
        ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1321
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1322
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1323
    }
nkeynes@939
  1324
}
nkeynes@939
  1325
nkeynes@939
  1326
struct mem_region_fn p4_region_itlb_addr = {
nkeynes@939
  1327
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1328
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1329
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@946
  1330
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1331
        unmapped_prefetch };
nkeynes@939
  1332
struct mem_region_fn p4_region_itlb_data = {
nkeynes@939
  1333
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1334
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1335
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@946
  1336
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1337
        unmapped_prefetch };
nkeynes@939
  1338
struct mem_region_fn p4_region_utlb_addr = {
nkeynes@939
  1339
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1340
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1341
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@946
  1342
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1343
        unmapped_prefetch };
nkeynes@939
  1344
struct mem_region_fn p4_region_utlb_data = {
nkeynes@939
  1345
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1346
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1347
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@946
  1348
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1349
        unmapped_prefetch };
nkeynes@939
  1350
nkeynes@939
  1351
/********************** Error regions **************************/
nkeynes@939
  1352
nkeynes@939
  1353
static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
nkeynes@939
  1354
{
nkeynes@939
  1355
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1356
    EXCEPTION_EXIT();
nkeynes@939
  1357
}
nkeynes@939
  1358
nkeynes@939
  1359
static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
nkeynes@939
  1360
{
nkeynes@939
  1361
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1362
    EXCEPTION_EXIT();
nkeynes@939
  1363
}
nkeynes@939
  1364
nkeynes@939
  1365
static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1366
{
nkeynes@939
  1367
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@939
  1368
    EXCEPTION_EXIT();
nkeynes@939
  1369
}
nkeynes@939
  1370
nkeynes@939
  1371
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
nkeynes@939
  1372
{
nkeynes@939
  1373
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1374
    EXCEPTION_EXIT();
nkeynes@939
  1375
}
nkeynes@939
  1376
nkeynes@939
  1377
static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1378
{
nkeynes@939
  1379
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1380
    EXCEPTION_EXIT();
nkeynes@939
  1381
}
nkeynes@939
  1382
nkeynes@939
  1383
static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1384
{
nkeynes@939
  1385
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@939
  1386
    EXCEPTION_EXIT();
nkeynes@939
  1387
}    
nkeynes@939
  1388
nkeynes@939
  1389
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
nkeynes@939
  1390
{
nkeynes@939
  1391
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1392
    EXCEPTION_EXIT();
nkeynes@939
  1393
}
nkeynes@939
  1394
nkeynes@939
  1395
static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1396
{
nkeynes@939
  1397
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1398
    EXCEPTION_EXIT();
nkeynes@939
  1399
}
nkeynes@939
  1400
nkeynes@939
  1401
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1402
{
nkeynes@939
  1403
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@939
  1404
    EXCEPTION_EXIT();
nkeynes@939
  1405
}
nkeynes@939
  1406
nkeynes@939
  1407
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1408
{
nkeynes@939
  1409
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@939
  1410
    EXCEPTION_EXIT();
nkeynes@939
  1411
}
nkeynes@939
  1412
    
nkeynes@939
  1413
static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
nkeynes@939
  1414
{
nkeynes@951
  1415
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1416
    EXCEPTION_EXIT();
nkeynes@939
  1417
}
nkeynes@939
  1418
nkeynes@939
  1419
static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1420
{
nkeynes@951
  1421
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1422
    EXCEPTION_EXIT();
nkeynes@939
  1423
}
nkeynes@939
  1424
static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1425
{
nkeynes@951
  1426
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1427
    EXCEPTION_EXIT();
nkeynes@939
  1428
}
nkeynes@939
  1429
nkeynes@939
  1430
/**
nkeynes@939
  1431
 * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
nkeynes@939
  1432
 */
nkeynes@939
  1433
struct mem_region_fn mem_region_address_error = {
nkeynes@939
  1434
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1435
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1436
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1437
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1438
        unmapped_prefetch };
nkeynes@939
  1439
nkeynes@939
  1440
struct mem_region_fn mem_region_tlb_miss = {
nkeynes@939
  1441
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1442
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1443
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@946
  1444
        (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
nkeynes@946
  1445
        unmapped_prefetch };
nkeynes@939
  1446
nkeynes@946
  1447
struct mem_region_fn mem_region_tlb_protected = {
nkeynes@939
  1448
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1449
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1450
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@946
  1451
        (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
nkeynes@946
  1452
        unmapped_prefetch };
nkeynes@939
  1453
nkeynes@939
  1454
struct mem_region_fn mem_region_tlb_multihit = {
nkeynes@939
  1455
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1456
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1457
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@946
  1458
        (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
nkeynes@946
  1459
        (mem_prefetch_fn_t)tlb_multi_hit_read };
nkeynes@939
  1460
        
nkeynes@946
  1461
nkeynes@946
  1462
/* Store-queue regions */
nkeynes@946
  1463
/* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
nkeynes@946
  1464
 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
nkeynes@946
  1465
 * some cases), in contrast to the ordinary fields above.
nkeynes@946
  1466
 * 
nkeynes@946
  1467
 * There is probably a simpler way to do this.
nkeynes@946
  1468
 */
nkeynes@946
  1469
nkeynes@946
  1470
struct mem_region_fn p4_region_storequeue = { 
nkeynes@946
  1471
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1472
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1473
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1474
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1475
        ccn_storequeue_prefetch }; 
nkeynes@946
  1476
nkeynes@946
  1477
struct mem_region_fn p4_region_storequeue_miss = { 
nkeynes@946
  1478
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1479
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1480
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1481
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1482
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1483
nkeynes@946
  1484
struct mem_region_fn p4_region_storequeue_multihit = { 
nkeynes@946
  1485
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1486
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1487
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1488
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1489
        (mem_prefetch_fn_t)tlb_multi_hit_read }; 
nkeynes@946
  1490
nkeynes@946
  1491
struct mem_region_fn p4_region_storequeue_protected = {
nkeynes@946
  1492
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1493
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1494
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1495
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1496
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1497
nkeynes@946
  1498
struct mem_region_fn p4_region_storequeue_sqmd = {
nkeynes@946
  1499
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1500
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1501
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1502
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1503
        (mem_prefetch_fn_t)address_error_read };        
nkeynes@939
  1504
        
nkeynes@946
  1505
struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
nkeynes@946
  1506
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1507
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1508
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1509
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1510
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1511
nkeynes@946
  1512
struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
nkeynes@946
  1513
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1514
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1515
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1516
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1517
        (mem_prefetch_fn_t)tlb_multi_hit_read };        
nkeynes@946
  1518
        
nkeynes@946
  1519
struct mem_region_fn p4_region_storequeue_sqmd_protected = {
nkeynes@946
  1520
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1521
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1522
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1523
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1524
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1525
.