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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 397:640324505325
prev395:c473acbde186
next401:f79327f39818
author nkeynes
date Wed Sep 19 11:30:30 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix SHLL/SHLR/SHAL/SHAR flag setting
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.14 2007-09-19 11:30:30 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    int exit_code;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void signsat48( void )
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{
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    if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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	sh4r.mac = 0xFFFF800000000000LL;
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    else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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	sh4r.mac = 0x00007FFFFFFFFFFFLL;
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}
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void sh4_fsca( uint32_t anglei, float *fr )
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{
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    float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
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    *fr++ = cosf(angle);
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    *fr = sinf(angle);
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}
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void sh4_sleep()
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{
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    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
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	sh4r.sh4_state = SH4_STATE_STANDBY;
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    } else {
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	sh4r.sh4_state = SH4_STATE_SLEEP;
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    }
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}
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/**
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 * Compute the matrix tranform of fv given the matrix xf.
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 * Both fv and xf are word-swapped as per the sh4r.fr banks
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 */
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void sh4_ftrv( float *target, float *xf )
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{
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    float fv[4] = { target[1], target[0], target[3], target[2] };
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    target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
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	xf[9]*fv[2] + xf[13]*fv[3];
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    target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
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	xf[8]*fv[2] + xf[12]*fv[3];
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    target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
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	xf[11]*fv[2] + xf[15]*fv[3];
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    target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
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	xf[10]*fv[2] + xf[14]*fv[3];
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}
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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   353
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   354
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   355
	load_spreg( R_EAX, R_SR );
nkeynes@368
   356
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   357
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   358
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   359
	} else {
nkeynes@368
   360
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   361
	}
nkeynes@368
   362
    }
nkeynes@368
   363
}
nkeynes@368
   364
nkeynes@368
   365
static void check_ralign16( int x86reg )
nkeynes@368
   366
{
nkeynes@368
   367
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   368
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   369
}
nkeynes@368
   370
nkeynes@368
   371
static void check_walign16( int x86reg )
nkeynes@368
   372
{
nkeynes@368
   373
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   374
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   375
}
nkeynes@368
   376
nkeynes@368
   377
static void check_ralign32( int x86reg )
nkeynes@368
   378
{
nkeynes@368
   379
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   380
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   381
}
nkeynes@368
   382
static void check_walign32( int x86reg )
nkeynes@368
   383
{
nkeynes@368
   384
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   385
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   386
}
nkeynes@368
   387
nkeynes@361
   388
#define UNDEF()
nkeynes@361
   389
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   390
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   391
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   392
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   393
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   394
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   395
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   396
nkeynes@386
   397
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   398
nkeynes@368
   399
nkeynes@359
   400
nkeynes@359
   401
/**
nkeynes@359
   402
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   403
 * SI/DI as required
nkeynes@359
   404
 */
nkeynes@368
   405
void sh4_translate_begin_block() 
nkeynes@368
   406
{
nkeynes@368
   407
    PUSH_r32(R_EBP);
nkeynes@359
   408
    /* mov &sh4r, ebp */
nkeynes@359
   409
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   410
    PUSH_r32(R_EDI);
nkeynes@368
   411
    PUSH_r32(R_ESI);
nkeynes@380
   412
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   413
    
nkeynes@368
   414
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   415
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   416
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   417
    sh4_x86.backpatch_posn = 0;
nkeynes@388
   418
    sh4_x86.exit_code = 1;
nkeynes@368
   419
}
nkeynes@359
   420
nkeynes@368
   421
/**
nkeynes@368
   422
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   423
 */
nkeynes@374
   424
void exit_block( )
nkeynes@368
   425
{
nkeynes@374
   426
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   427
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   428
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   429
    MUL_r32( R_ESI );
nkeynes@368
   430
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   431
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   432
    load_imm32( R_EAX, sh4_x86.exit_code );
nkeynes@374
   433
    POP_r32(R_ESI);
nkeynes@374
   434
    POP_r32(R_EDI);
nkeynes@374
   435
    POP_r32(R_EBP);
nkeynes@368
   436
    RET();
nkeynes@359
   437
}
nkeynes@359
   438
nkeynes@359
   439
/**
nkeynes@359
   440
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   441
 */
nkeynes@359
   442
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   443
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   444
    // Normal termination - save PC, cycle count
nkeynes@374
   445
    exit_block( );
nkeynes@359
   446
nkeynes@388
   447
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   448
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   449
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   450
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   451
	JMP_rel8( 33, target1 );
nkeynes@388
   452
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   453
	JMP_rel8( 26, target2 );
nkeynes@388
   454
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   455
	JMP_rel8( 19, target3 );
nkeynes@388
   456
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   457
	JMP_rel8( 12, target4 );
nkeynes@388
   458
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   459
	JMP_rel8( 5, target5 );
nkeynes@388
   460
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   461
	// target
nkeynes@388
   462
	JMP_TARGET(target1);
nkeynes@388
   463
	JMP_TARGET(target2);
nkeynes@388
   464
	JMP_TARGET(target3);
nkeynes@388
   465
	JMP_TARGET(target4);
nkeynes@388
   466
	JMP_TARGET(target5);
nkeynes@388
   467
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   468
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   469
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   470
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   471
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388
   472
	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   473
	MUL_r32( R_ESI );
nkeynes@388
   474
	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388
   475
	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   476
	
nkeynes@388
   477
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   478
	CALL_r32( R_EAX ); // 2
nkeynes@388
   479
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@388
   480
	POP_r32(R_ESI);
nkeynes@388
   481
	POP_r32(R_EDI);
nkeynes@388
   482
	POP_r32(R_EBP);
nkeynes@388
   483
	RET();
nkeynes@368
   484
nkeynes@388
   485
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   486
    }
nkeynes@368
   487
nkeynes@359
   488
}
nkeynes@359
   489
nkeynes@388
   490
nkeynes@388
   491
extern uint16_t *sh4_icache;
nkeynes@388
   492
extern uint32_t sh4_icache_addr;
nkeynes@388
   493
nkeynes@359
   494
/**
nkeynes@359
   495
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   496
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   497
 * 
nkeynes@359
   498
 *
nkeynes@359
   499
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   500
 * (eg a branch or 
nkeynes@359
   501
 */
nkeynes@359
   502
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   503
{
nkeynes@388
   504
    uint32_t ir;
nkeynes@388
   505
    /* Read instruction */
nkeynes@388
   506
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   507
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   508
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   509
    } else {
nkeynes@388
   510
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   511
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   512
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   513
	     * region, fallback on the full-blown memory read
nkeynes@388
   514
	     */
nkeynes@388
   515
	    sh4_icache = NULL;
nkeynes@388
   516
	    ir = sh4_read_word(pc);
nkeynes@388
   517
	} else {
nkeynes@388
   518
	    sh4_icache_addr = pageaddr;
nkeynes@388
   519
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   520
	}
nkeynes@388
   521
    }
nkeynes@388
   522
nkeynes@359
   523
%%
nkeynes@359
   524
/* ALU operations */
nkeynes@359
   525
ADD Rm, Rn {:
nkeynes@359
   526
    load_reg( R_EAX, Rm );
nkeynes@359
   527
    load_reg( R_ECX, Rn );
nkeynes@359
   528
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   529
    store_reg( R_ECX, Rn );
nkeynes@359
   530
:}
nkeynes@359
   531
ADD #imm, Rn {:  
nkeynes@359
   532
    load_reg( R_EAX, Rn );
nkeynes@359
   533
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   534
    store_reg( R_EAX, Rn );
nkeynes@359
   535
:}
nkeynes@359
   536
ADDC Rm, Rn {:
nkeynes@359
   537
    load_reg( R_EAX, Rm );
nkeynes@359
   538
    load_reg( R_ECX, Rn );
nkeynes@359
   539
    LDC_t();
nkeynes@359
   540
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   541
    store_reg( R_ECX, Rn );
nkeynes@359
   542
    SETC_t();
nkeynes@359
   543
:}
nkeynes@359
   544
ADDV Rm, Rn {:
nkeynes@359
   545
    load_reg( R_EAX, Rm );
nkeynes@359
   546
    load_reg( R_ECX, Rn );
nkeynes@359
   547
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   548
    store_reg( R_ECX, Rn );
nkeynes@359
   549
    SETO_t();
nkeynes@359
   550
:}
nkeynes@359
   551
AND Rm, Rn {:
nkeynes@359
   552
    load_reg( R_EAX, Rm );
nkeynes@359
   553
    load_reg( R_ECX, Rn );
nkeynes@359
   554
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   555
    store_reg( R_ECX, Rn );
nkeynes@359
   556
:}
nkeynes@359
   557
AND #imm, R0 {:  
nkeynes@359
   558
    load_reg( R_EAX, 0 );
nkeynes@359
   559
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   560
    store_reg( R_EAX, 0 );
nkeynes@359
   561
:}
nkeynes@359
   562
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   563
    load_reg( R_EAX, 0 );
nkeynes@359
   564
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   565
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   566
    PUSH_r32(R_ECX);
nkeynes@386
   567
    call_func0(sh4_read_byte);
nkeynes@386
   568
    POP_r32(R_ECX);
nkeynes@386
   569
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   570
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   571
:}
nkeynes@359
   572
CMP/EQ Rm, Rn {:  
nkeynes@359
   573
    load_reg( R_EAX, Rm );
nkeynes@359
   574
    load_reg( R_ECX, Rn );
nkeynes@359
   575
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   576
    SETE_t();
nkeynes@359
   577
:}
nkeynes@359
   578
CMP/EQ #imm, R0 {:  
nkeynes@359
   579
    load_reg( R_EAX, 0 );
nkeynes@359
   580
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   581
    SETE_t();
nkeynes@359
   582
:}
nkeynes@359
   583
CMP/GE Rm, Rn {:  
nkeynes@359
   584
    load_reg( R_EAX, Rm );
nkeynes@359
   585
    load_reg( R_ECX, Rn );
nkeynes@359
   586
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   587
    SETGE_t();
nkeynes@359
   588
:}
nkeynes@359
   589
CMP/GT Rm, Rn {: 
nkeynes@359
   590
    load_reg( R_EAX, Rm );
nkeynes@359
   591
    load_reg( R_ECX, Rn );
nkeynes@359
   592
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   593
    SETG_t();
nkeynes@359
   594
:}
nkeynes@359
   595
CMP/HI Rm, Rn {:  
nkeynes@359
   596
    load_reg( R_EAX, Rm );
nkeynes@359
   597
    load_reg( R_ECX, Rn );
nkeynes@359
   598
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   599
    SETA_t();
nkeynes@359
   600
:}
nkeynes@359
   601
CMP/HS Rm, Rn {: 
nkeynes@359
   602
    load_reg( R_EAX, Rm );
nkeynes@359
   603
    load_reg( R_ECX, Rn );
nkeynes@359
   604
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   605
    SETAE_t();
nkeynes@359
   606
 :}
nkeynes@359
   607
CMP/PL Rn {: 
nkeynes@359
   608
    load_reg( R_EAX, Rn );
nkeynes@359
   609
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   610
    SETG_t();
nkeynes@359
   611
:}
nkeynes@359
   612
CMP/PZ Rn {:  
nkeynes@359
   613
    load_reg( R_EAX, Rn );
nkeynes@359
   614
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   615
    SETGE_t();
nkeynes@359
   616
:}
nkeynes@361
   617
CMP/STR Rm, Rn {:  
nkeynes@368
   618
    load_reg( R_EAX, Rm );
nkeynes@368
   619
    load_reg( R_ECX, Rn );
nkeynes@368
   620
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   621
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   622
    JE_rel8(13, target1);
nkeynes@368
   623
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   624
    JE_rel8(9, target2);
nkeynes@368
   625
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   626
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   627
    JE_rel8(2, target3);
nkeynes@368
   628
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   629
    JMP_TARGET(target1);
nkeynes@380
   630
    JMP_TARGET(target2);
nkeynes@380
   631
    JMP_TARGET(target3);
nkeynes@368
   632
    SETE_t();
nkeynes@361
   633
:}
nkeynes@361
   634
DIV0S Rm, Rn {:
nkeynes@361
   635
    load_reg( R_EAX, Rm );
nkeynes@386
   636
    load_reg( R_ECX, Rn );
nkeynes@361
   637
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   638
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   639
    store_spreg( R_EAX, R_M );
nkeynes@361
   640
    store_spreg( R_ECX, R_Q );
nkeynes@361
   641
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   642
    SETNE_t();
nkeynes@361
   643
:}
nkeynes@361
   644
DIV0U {:  
nkeynes@361
   645
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   646
    store_spreg( R_EAX, R_Q );
nkeynes@361
   647
    store_spreg( R_EAX, R_M );
nkeynes@361
   648
    store_spreg( R_EAX, R_T );
nkeynes@361
   649
:}
nkeynes@386
   650
DIV1 Rm, Rn {:
nkeynes@386
   651
    load_spreg( R_ECX, R_M );
nkeynes@386
   652
    load_reg( R_EAX, Rn );
nkeynes@374
   653
    LDC_t();
nkeynes@386
   654
    RCL1_r32( R_EAX );
nkeynes@386
   655
    SETC_r8( R_DL ); // Q'
nkeynes@386
   656
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   657
    JE_rel8(5, mqequal);
nkeynes@386
   658
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   659
    JMP_rel8(3, end);
nkeynes@380
   660
    JMP_TARGET(mqequal);
nkeynes@386
   661
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   662
    JMP_TARGET(end);
nkeynes@386
   663
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   664
    SETC_r8(R_AL); // tmp1
nkeynes@386
   665
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   666
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   667
    store_spreg( R_ECX, R_Q );
nkeynes@386
   668
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   669
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   670
    store_spreg( R_EAX, R_T );
nkeynes@374
   671
:}
nkeynes@361
   672
DMULS.L Rm, Rn {:  
nkeynes@361
   673
    load_reg( R_EAX, Rm );
nkeynes@361
   674
    load_reg( R_ECX, Rn );
nkeynes@361
   675
    IMUL_r32(R_ECX);
nkeynes@361
   676
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   677
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   678
:}
nkeynes@361
   679
DMULU.L Rm, Rn {:  
nkeynes@361
   680
    load_reg( R_EAX, Rm );
nkeynes@361
   681
    load_reg( R_ECX, Rn );
nkeynes@361
   682
    MUL_r32(R_ECX);
nkeynes@361
   683
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   684
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   685
:}
nkeynes@359
   686
DT Rn {:  
nkeynes@359
   687
    load_reg( R_EAX, Rn );
nkeynes@382
   688
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   689
    store_reg( R_EAX, Rn );
nkeynes@359
   690
    SETE_t();
nkeynes@359
   691
:}
nkeynes@359
   692
EXTS.B Rm, Rn {:  
nkeynes@359
   693
    load_reg( R_EAX, Rm );
nkeynes@359
   694
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   695
    store_reg( R_EAX, Rn );
nkeynes@359
   696
:}
nkeynes@361
   697
EXTS.W Rm, Rn {:  
nkeynes@361
   698
    load_reg( R_EAX, Rm );
nkeynes@361
   699
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   700
    store_reg( R_EAX, Rn );
nkeynes@361
   701
:}
nkeynes@361
   702
EXTU.B Rm, Rn {:  
nkeynes@361
   703
    load_reg( R_EAX, Rm );
nkeynes@361
   704
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   705
    store_reg( R_EAX, Rn );
nkeynes@361
   706
:}
nkeynes@361
   707
EXTU.W Rm, Rn {:  
nkeynes@361
   708
    load_reg( R_EAX, Rm );
nkeynes@361
   709
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   710
    store_reg( R_EAX, Rn );
nkeynes@361
   711
:}
nkeynes@386
   712
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   713
    load_reg( R_ECX, Rm );
nkeynes@386
   714
    check_ralign32( R_ECX );
nkeynes@386
   715
    load_reg( R_ECX, Rn );
nkeynes@386
   716
    check_ralign32( R_ECX );
nkeynes@386
   717
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   718
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   719
    PUSH_r32( R_EAX );
nkeynes@386
   720
    load_reg( R_ECX, Rm );
nkeynes@386
   721
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   722
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   723
    POP_r32( R_ECX );
nkeynes@386
   724
    IMUL_r32( R_ECX );
nkeynes@386
   725
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   726
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   727
nkeynes@386
   728
    load_spreg( R_ECX, R_S );
nkeynes@386
   729
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   730
    JE_rel8( 7, nosat );
nkeynes@386
   731
    call_func0( signsat48 );
nkeynes@386
   732
    JMP_TARGET( nosat );
nkeynes@386
   733
:}
nkeynes@386
   734
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   735
    load_reg( R_ECX, Rm );
nkeynes@386
   736
    check_ralign16( R_ECX );
nkeynes@386
   737
    load_reg( R_ECX, Rn );
nkeynes@386
   738
    check_ralign16( R_ECX );
nkeynes@386
   739
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   740
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   741
    PUSH_r32( R_EAX );
nkeynes@386
   742
    load_reg( R_ECX, Rm );
nkeynes@386
   743
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   744
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   745
    POP_r32( R_ECX );
nkeynes@386
   746
    IMUL_r32( R_ECX );
nkeynes@386
   747
nkeynes@386
   748
    load_spreg( R_ECX, R_S );
nkeynes@386
   749
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   750
    JE_rel8( 47, nosat );
nkeynes@386
   751
nkeynes@386
   752
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   753
    JNO_rel8( 51, end );            // 2
nkeynes@386
   754
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   755
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   756
    JS_rel8( 13, positive );        // 2
nkeynes@386
   757
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   758
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   759
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   760
nkeynes@386
   761
    JMP_TARGET(positive);
nkeynes@386
   762
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   763
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   764
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   765
nkeynes@386
   766
    JMP_TARGET(nosat);
nkeynes@386
   767
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   768
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   769
    JMP_TARGET(end);
nkeynes@386
   770
    JMP_TARGET(end2);
nkeynes@386
   771
    JMP_TARGET(end3);
nkeynes@386
   772
:}
nkeynes@359
   773
MOVT Rn {:  
nkeynes@359
   774
    load_spreg( R_EAX, R_T );
nkeynes@359
   775
    store_reg( R_EAX, Rn );
nkeynes@359
   776
:}
nkeynes@361
   777
MUL.L Rm, Rn {:  
nkeynes@361
   778
    load_reg( R_EAX, Rm );
nkeynes@361
   779
    load_reg( R_ECX, Rn );
nkeynes@361
   780
    MUL_r32( R_ECX );
nkeynes@361
   781
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   782
:}
nkeynes@374
   783
MULS.W Rm, Rn {:
nkeynes@374
   784
    load_reg16s( R_EAX, Rm );
nkeynes@374
   785
    load_reg16s( R_ECX, Rn );
nkeynes@374
   786
    MUL_r32( R_ECX );
nkeynes@374
   787
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   788
:}
nkeynes@374
   789
MULU.W Rm, Rn {:  
nkeynes@374
   790
    load_reg16u( R_EAX, Rm );
nkeynes@374
   791
    load_reg16u( R_ECX, Rn );
nkeynes@374
   792
    MUL_r32( R_ECX );
nkeynes@374
   793
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   794
:}
nkeynes@359
   795
NEG Rm, Rn {:
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    NEG_r32( R_EAX );
nkeynes@359
   798
    store_reg( R_EAX, Rn );
nkeynes@359
   799
:}
nkeynes@359
   800
NEGC Rm, Rn {:  
nkeynes@359
   801
    load_reg( R_EAX, Rm );
nkeynes@359
   802
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   803
    LDC_t();
nkeynes@359
   804
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   805
    store_reg( R_ECX, Rn );
nkeynes@359
   806
    SETC_t();
nkeynes@359
   807
:}
nkeynes@359
   808
NOT Rm, Rn {:  
nkeynes@359
   809
    load_reg( R_EAX, Rm );
nkeynes@359
   810
    NOT_r32( R_EAX );
nkeynes@359
   811
    store_reg( R_EAX, Rn );
nkeynes@359
   812
:}
nkeynes@359
   813
OR Rm, Rn {:  
nkeynes@359
   814
    load_reg( R_EAX, Rm );
nkeynes@359
   815
    load_reg( R_ECX, Rn );
nkeynes@359
   816
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   817
    store_reg( R_ECX, Rn );
nkeynes@359
   818
:}
nkeynes@359
   819
OR #imm, R0 {:
nkeynes@359
   820
    load_reg( R_EAX, 0 );
nkeynes@359
   821
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   822
    store_reg( R_EAX, 0 );
nkeynes@359
   823
:}
nkeynes@374
   824
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   825
    load_reg( R_EAX, 0 );
nkeynes@374
   826
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   827
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   828
    PUSH_r32(R_ECX);
nkeynes@386
   829
    call_func0(sh4_read_byte);
nkeynes@386
   830
    POP_r32(R_ECX);
nkeynes@386
   831
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   832
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   833
:}
nkeynes@359
   834
ROTCL Rn {:
nkeynes@359
   835
    load_reg( R_EAX, Rn );
nkeynes@359
   836
    LDC_t();
nkeynes@359
   837
    RCL1_r32( R_EAX );
nkeynes@359
   838
    store_reg( R_EAX, Rn );
nkeynes@359
   839
    SETC_t();
nkeynes@359
   840
:}
nkeynes@359
   841
ROTCR Rn {:  
nkeynes@359
   842
    load_reg( R_EAX, Rn );
nkeynes@359
   843
    LDC_t();
nkeynes@359
   844
    RCR1_r32( R_EAX );
nkeynes@359
   845
    store_reg( R_EAX, Rn );
nkeynes@359
   846
    SETC_t();
nkeynes@359
   847
:}
nkeynes@359
   848
ROTL Rn {:  
nkeynes@359
   849
    load_reg( R_EAX, Rn );
nkeynes@359
   850
    ROL1_r32( R_EAX );
nkeynes@359
   851
    store_reg( R_EAX, Rn );
nkeynes@359
   852
    SETC_t();
nkeynes@359
   853
:}
nkeynes@359
   854
ROTR Rn {:  
nkeynes@359
   855
    load_reg( R_EAX, Rn );
nkeynes@359
   856
    ROR1_r32( R_EAX );
nkeynes@359
   857
    store_reg( R_EAX, Rn );
nkeynes@359
   858
    SETC_t();
nkeynes@359
   859
:}
nkeynes@359
   860
SHAD Rm, Rn {:
nkeynes@359
   861
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   862
    load_reg( R_EAX, Rn );
nkeynes@361
   863
    load_reg( R_ECX, Rm );
nkeynes@361
   864
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   865
    JGE_rel8(16, doshl);
nkeynes@361
   866
                    
nkeynes@361
   867
    NEG_r32( R_ECX );      // 2
nkeynes@361
   868
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   869
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   870
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   871
    JMP_rel8(10, end);          // 2
nkeynes@386
   872
nkeynes@386
   873
    JMP_TARGET(emptysar);
nkeynes@386
   874
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   875
    JMP_rel8(5, end2);
nkeynes@382
   876
nkeynes@380
   877
    JMP_TARGET(doshl);
nkeynes@361
   878
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   879
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   880
    JMP_TARGET(end);
nkeynes@386
   881
    JMP_TARGET(end2);
nkeynes@361
   882
    store_reg( R_EAX, Rn );
nkeynes@359
   883
:}
nkeynes@359
   884
SHLD Rm, Rn {:  
nkeynes@368
   885
    load_reg( R_EAX, Rn );
nkeynes@368
   886
    load_reg( R_ECX, Rm );
nkeynes@382
   887
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   888
    JGE_rel8(15, doshl);
nkeynes@368
   889
nkeynes@382
   890
    NEG_r32( R_ECX );      // 2
nkeynes@382
   891
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   892
    JE_rel8( 4, emptyshr );
nkeynes@382
   893
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   894
    JMP_rel8(9, end);          // 2
nkeynes@386
   895
nkeynes@386
   896
    JMP_TARGET(emptyshr);
nkeynes@386
   897
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   898
    JMP_rel8(5, end2);
nkeynes@382
   899
nkeynes@382
   900
    JMP_TARGET(doshl);
nkeynes@382
   901
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   902
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   903
    JMP_TARGET(end);
nkeynes@386
   904
    JMP_TARGET(end2);
nkeynes@368
   905
    store_reg( R_EAX, Rn );
nkeynes@359
   906
:}
nkeynes@359
   907
SHAL Rn {: 
nkeynes@359
   908
    load_reg( R_EAX, Rn );
nkeynes@359
   909
    SHL1_r32( R_EAX );
nkeynes@397
   910
    SETC_t();
nkeynes@359
   911
    store_reg( R_EAX, Rn );
nkeynes@359
   912
:}
nkeynes@359
   913
SHAR Rn {:  
nkeynes@359
   914
    load_reg( R_EAX, Rn );
nkeynes@359
   915
    SAR1_r32( R_EAX );
nkeynes@397
   916
    SETC_t();
nkeynes@359
   917
    store_reg( R_EAX, Rn );
nkeynes@359
   918
:}
nkeynes@359
   919
SHLL Rn {:  
nkeynes@359
   920
    load_reg( R_EAX, Rn );
nkeynes@359
   921
    SHL1_r32( R_EAX );
nkeynes@397
   922
    SETC_t();
nkeynes@359
   923
    store_reg( R_EAX, Rn );
nkeynes@359
   924
:}
nkeynes@359
   925
SHLL2 Rn {:
nkeynes@359
   926
    load_reg( R_EAX, Rn );
nkeynes@359
   927
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   928
    store_reg( R_EAX, Rn );
nkeynes@359
   929
:}
nkeynes@359
   930
SHLL8 Rn {:  
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@359
   934
:}
nkeynes@359
   935
SHLL16 Rn {:  
nkeynes@359
   936
    load_reg( R_EAX, Rn );
nkeynes@359
   937
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   938
    store_reg( R_EAX, Rn );
nkeynes@359
   939
:}
nkeynes@359
   940
SHLR Rn {:  
nkeynes@359
   941
    load_reg( R_EAX, Rn );
nkeynes@359
   942
    SHR1_r32( R_EAX );
nkeynes@397
   943
    SETC_t();
nkeynes@359
   944
    store_reg( R_EAX, Rn );
nkeynes@359
   945
:}
nkeynes@359
   946
SHLR2 Rn {:  
nkeynes@359
   947
    load_reg( R_EAX, Rn );
nkeynes@359
   948
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   949
    store_reg( R_EAX, Rn );
nkeynes@359
   950
:}
nkeynes@359
   951
SHLR8 Rn {:  
nkeynes@359
   952
    load_reg( R_EAX, Rn );
nkeynes@359
   953
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@359
   955
:}
nkeynes@359
   956
SHLR16 Rn {:  
nkeynes@359
   957
    load_reg( R_EAX, Rn );
nkeynes@359
   958
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   959
    store_reg( R_EAX, Rn );
nkeynes@359
   960
:}
nkeynes@359
   961
SUB Rm, Rn {:  
nkeynes@359
   962
    load_reg( R_EAX, Rm );
nkeynes@359
   963
    load_reg( R_ECX, Rn );
nkeynes@359
   964
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   965
    store_reg( R_ECX, Rn );
nkeynes@359
   966
:}
nkeynes@359
   967
SUBC Rm, Rn {:  
nkeynes@359
   968
    load_reg( R_EAX, Rm );
nkeynes@359
   969
    load_reg( R_ECX, Rn );
nkeynes@359
   970
    LDC_t();
nkeynes@359
   971
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   972
    store_reg( R_ECX, Rn );
nkeynes@394
   973
    SETC_t();
nkeynes@359
   974
:}
nkeynes@359
   975
SUBV Rm, Rn {:  
nkeynes@359
   976
    load_reg( R_EAX, Rm );
nkeynes@359
   977
    load_reg( R_ECX, Rn );
nkeynes@359
   978
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   979
    store_reg( R_ECX, Rn );
nkeynes@359
   980
    SETO_t();
nkeynes@359
   981
:}
nkeynes@359
   982
SWAP.B Rm, Rn {:  
nkeynes@359
   983
    load_reg( R_EAX, Rm );
nkeynes@359
   984
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   985
    store_reg( R_EAX, Rn );
nkeynes@359
   986
:}
nkeynes@359
   987
SWAP.W Rm, Rn {:  
nkeynes@359
   988
    load_reg( R_EAX, Rm );
nkeynes@359
   989
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   990
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   991
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   992
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   993
    store_reg( R_ECX, Rn );
nkeynes@359
   994
:}
nkeynes@361
   995
TAS.B @Rn {:  
nkeynes@361
   996
    load_reg( R_ECX, Rn );
nkeynes@361
   997
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   998
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   999
    SETE_t();
nkeynes@361
  1000
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1001
    load_reg( R_ECX, Rn );
nkeynes@361
  1002
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
  1003
:}
nkeynes@361
  1004
TST Rm, Rn {:  
nkeynes@361
  1005
    load_reg( R_EAX, Rm );
nkeynes@361
  1006
    load_reg( R_ECX, Rn );
nkeynes@361
  1007
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1008
    SETE_t();
nkeynes@361
  1009
:}
nkeynes@368
  1010
TST #imm, R0 {:  
nkeynes@368
  1011
    load_reg( R_EAX, 0 );
nkeynes@368
  1012
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1013
    SETE_t();
nkeynes@368
  1014
:}
nkeynes@368
  1015
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1016
    load_reg( R_EAX, 0);
nkeynes@368
  1017
    load_reg( R_ECX, R_GBR);
nkeynes@368
  1018
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1019
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  1020
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1021
    SETE_t();
nkeynes@368
  1022
:}
nkeynes@359
  1023
XOR Rm, Rn {:  
nkeynes@359
  1024
    load_reg( R_EAX, Rm );
nkeynes@359
  1025
    load_reg( R_ECX, Rn );
nkeynes@359
  1026
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1027
    store_reg( R_ECX, Rn );
nkeynes@359
  1028
:}
nkeynes@359
  1029
XOR #imm, R0 {:  
nkeynes@359
  1030
    load_reg( R_EAX, 0 );
nkeynes@359
  1031
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1032
    store_reg( R_EAX, 0 );
nkeynes@359
  1033
:}
nkeynes@359
  1034
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1035
    load_reg( R_EAX, 0 );
nkeynes@359
  1036
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1037
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1038
    PUSH_r32(R_ECX);
nkeynes@386
  1039
    call_func0(sh4_read_byte);
nkeynes@386
  1040
    POP_r32(R_ECX);
nkeynes@359
  1041
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1042
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1043
:}
nkeynes@361
  1044
XTRCT Rm, Rn {:
nkeynes@361
  1045
    load_reg( R_EAX, Rm );
nkeynes@394
  1046
    load_reg( R_ECX, Rn );
nkeynes@394
  1047
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1048
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1049
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1050
    store_reg( R_ECX, Rn );
nkeynes@359
  1051
:}
nkeynes@359
  1052
nkeynes@359
  1053
/* Data move instructions */
nkeynes@359
  1054
MOV Rm, Rn {:  
nkeynes@359
  1055
    load_reg( R_EAX, Rm );
nkeynes@359
  1056
    store_reg( R_EAX, Rn );
nkeynes@359
  1057
:}
nkeynes@359
  1058
MOV #imm, Rn {:  
nkeynes@359
  1059
    load_imm32( R_EAX, imm );
nkeynes@359
  1060
    store_reg( R_EAX, Rn );
nkeynes@359
  1061
:}
nkeynes@359
  1062
MOV.B Rm, @Rn {:  
nkeynes@359
  1063
    load_reg( R_EAX, Rm );
nkeynes@359
  1064
    load_reg( R_ECX, Rn );
nkeynes@359
  1065
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1066
:}
nkeynes@359
  1067
MOV.B Rm, @-Rn {:  
nkeynes@359
  1068
    load_reg( R_EAX, Rm );
nkeynes@359
  1069
    load_reg( R_ECX, Rn );
nkeynes@382
  1070
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1071
    store_reg( R_ECX, Rn );
nkeynes@359
  1072
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1073
:}
nkeynes@359
  1074
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1075
    load_reg( R_EAX, 0 );
nkeynes@359
  1076
    load_reg( R_ECX, Rn );
nkeynes@359
  1077
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1078
    load_reg( R_EAX, Rm );
nkeynes@359
  1079
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1080
:}
nkeynes@359
  1081
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1082
    load_reg( R_EAX, 0 );
nkeynes@359
  1083
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1084
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1085
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1086
:}
nkeynes@359
  1087
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1088
    load_reg( R_EAX, 0 );
nkeynes@359
  1089
    load_reg( R_ECX, Rn );
nkeynes@359
  1090
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1091
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1092
:}
nkeynes@359
  1093
MOV.B @Rm, Rn {:  
nkeynes@359
  1094
    load_reg( R_ECX, Rm );
nkeynes@359
  1095
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1096
    store_reg( R_EAX, Rn );
nkeynes@359
  1097
:}
nkeynes@359
  1098
MOV.B @Rm+, Rn {:  
nkeynes@359
  1099
    load_reg( R_ECX, Rm );
nkeynes@359
  1100
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1101
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1102
    store_reg( R_EAX, Rm );
nkeynes@359
  1103
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1104
    store_reg( R_EAX, Rn );
nkeynes@359
  1105
:}
nkeynes@359
  1106
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1107
    load_reg( R_EAX, 0 );
nkeynes@359
  1108
    load_reg( R_ECX, Rm );
nkeynes@359
  1109
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1110
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1111
    store_reg( R_EAX, Rn );
nkeynes@359
  1112
:}
nkeynes@359
  1113
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1114
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1115
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1116
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1117
    store_reg( R_EAX, 0 );
nkeynes@359
  1118
:}
nkeynes@359
  1119
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1120
    load_reg( R_ECX, Rm );
nkeynes@359
  1121
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1122
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1123
    store_reg( R_EAX, 0 );
nkeynes@359
  1124
:}
nkeynes@374
  1125
MOV.L Rm, @Rn {:
nkeynes@361
  1126
    load_reg( R_EAX, Rm );
nkeynes@361
  1127
    load_reg( R_ECX, Rn );
nkeynes@374
  1128
    check_walign32(R_ECX);
nkeynes@361
  1129
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1130
:}
nkeynes@361
  1131
MOV.L Rm, @-Rn {:  
nkeynes@361
  1132
    load_reg( R_EAX, Rm );
nkeynes@361
  1133
    load_reg( R_ECX, Rn );
nkeynes@374
  1134
    check_walign32( R_ECX );
nkeynes@361
  1135
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1136
    store_reg( R_ECX, Rn );
nkeynes@361
  1137
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1138
:}
nkeynes@361
  1139
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1140
    load_reg( R_EAX, 0 );
nkeynes@361
  1141
    load_reg( R_ECX, Rn );
nkeynes@361
  1142
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1143
    check_walign32( R_ECX );
nkeynes@361
  1144
    load_reg( R_EAX, Rm );
nkeynes@361
  1145
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1146
:}
nkeynes@361
  1147
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1148
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1149
    load_reg( R_EAX, 0 );
nkeynes@361
  1150
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1151
    check_walign32( R_ECX );
nkeynes@361
  1152
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1153
:}
nkeynes@361
  1154
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1155
    load_reg( R_ECX, Rn );
nkeynes@361
  1156
    load_reg( R_EAX, Rm );
nkeynes@361
  1157
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1158
    check_walign32( R_ECX );
nkeynes@361
  1159
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1160
:}
nkeynes@361
  1161
MOV.L @Rm, Rn {:  
nkeynes@361
  1162
    load_reg( R_ECX, Rm );
nkeynes@374
  1163
    check_ralign32( R_ECX );
nkeynes@361
  1164
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1165
    store_reg( R_EAX, Rn );
nkeynes@361
  1166
:}
nkeynes@361
  1167
MOV.L @Rm+, Rn {:  
nkeynes@361
  1168
    load_reg( R_EAX, Rm );
nkeynes@382
  1169
    check_ralign32( R_EAX );
nkeynes@361
  1170
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1171
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1172
    store_reg( R_EAX, Rm );
nkeynes@361
  1173
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1174
    store_reg( R_EAX, Rn );
nkeynes@361
  1175
:}
nkeynes@361
  1176
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1177
    load_reg( R_EAX, 0 );
nkeynes@361
  1178
    load_reg( R_ECX, Rm );
nkeynes@361
  1179
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1180
    check_ralign32( R_ECX );
nkeynes@361
  1181
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1182
    store_reg( R_EAX, Rn );
nkeynes@361
  1183
:}
nkeynes@361
  1184
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1185
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1186
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1187
    check_ralign32( R_ECX );
nkeynes@361
  1188
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1189
    store_reg( R_EAX, 0 );
nkeynes@361
  1190
:}
nkeynes@361
  1191
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1192
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1193
	SLOTILLEGAL();
nkeynes@374
  1194
    } else {
nkeynes@388
  1195
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  1196
	char *ptr = mem_get_region(target);
nkeynes@388
  1197
	if( ptr != NULL ) {
nkeynes@388
  1198
	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  1199
	} else {
nkeynes@388
  1200
	    load_imm32( R_ECX, target );
nkeynes@388
  1201
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1202
	}
nkeynes@382
  1203
	store_reg( R_EAX, Rn );
nkeynes@374
  1204
    }
nkeynes@361
  1205
:}
nkeynes@361
  1206
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1207
    load_reg( R_ECX, Rm );
nkeynes@361
  1208
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1209
    check_ralign32( R_ECX );
nkeynes@361
  1210
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1211
    store_reg( R_EAX, Rn );
nkeynes@361
  1212
:}
nkeynes@361
  1213
MOV.W Rm, @Rn {:  
nkeynes@361
  1214
    load_reg( R_ECX, Rn );
nkeynes@374
  1215
    check_walign16( R_ECX );
nkeynes@382
  1216
    load_reg( R_EAX, Rm );
nkeynes@382
  1217
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1218
:}
nkeynes@361
  1219
MOV.W Rm, @-Rn {:  
nkeynes@361
  1220
    load_reg( R_ECX, Rn );
nkeynes@374
  1221
    check_walign16( R_ECX );
nkeynes@361
  1222
    load_reg( R_EAX, Rm );
nkeynes@361
  1223
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1224
    store_reg( R_ECX, Rn );
nkeynes@361
  1225
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1226
:}
nkeynes@361
  1227
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1228
    load_reg( R_EAX, 0 );
nkeynes@361
  1229
    load_reg( R_ECX, Rn );
nkeynes@361
  1230
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1231
    check_walign16( R_ECX );
nkeynes@361
  1232
    load_reg( R_EAX, Rm );
nkeynes@361
  1233
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1234
:}
nkeynes@361
  1235
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1236
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1237
    load_reg( R_EAX, 0 );
nkeynes@361
  1238
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1239
    check_walign16( R_ECX );
nkeynes@361
  1240
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1241
:}
nkeynes@361
  1242
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1243
    load_reg( R_ECX, Rn );
nkeynes@361
  1244
    load_reg( R_EAX, 0 );
nkeynes@361
  1245
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1246
    check_walign16( R_ECX );
nkeynes@361
  1247
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1248
:}
nkeynes@361
  1249
MOV.W @Rm, Rn {:  
nkeynes@361
  1250
    load_reg( R_ECX, Rm );
nkeynes@374
  1251
    check_ralign16( R_ECX );
nkeynes@361
  1252
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1253
    store_reg( R_EAX, Rn );
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.W @Rm+, Rn {:  
nkeynes@361
  1256
    load_reg( R_EAX, Rm );
nkeynes@374
  1257
    check_ralign16( R_EAX );
nkeynes@361
  1258
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1259
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1260
    store_reg( R_EAX, Rm );
nkeynes@361
  1261
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1262
    store_reg( R_EAX, Rn );
nkeynes@361
  1263
:}
nkeynes@361
  1264
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1265
    load_reg( R_EAX, 0 );
nkeynes@361
  1266
    load_reg( R_ECX, Rm );
nkeynes@361
  1267
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1268
    check_ralign16( R_ECX );
nkeynes@361
  1269
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1270
    store_reg( R_EAX, Rn );
nkeynes@361
  1271
:}
nkeynes@361
  1272
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1273
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1274
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1275
    check_ralign16( R_ECX );
nkeynes@361
  1276
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1277
    store_reg( R_EAX, 0 );
nkeynes@361
  1278
:}
nkeynes@361
  1279
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1280
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1281
	SLOTILLEGAL();
nkeynes@374
  1282
    } else {
nkeynes@374
  1283
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1284
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1285
	store_reg( R_EAX, Rn );
nkeynes@374
  1286
    }
nkeynes@361
  1287
:}
nkeynes@361
  1288
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1289
    load_reg( R_ECX, Rm );
nkeynes@361
  1290
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1291
    check_ralign16( R_ECX );
nkeynes@361
  1292
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1293
    store_reg( R_EAX, 0 );
nkeynes@361
  1294
:}
nkeynes@361
  1295
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1296
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1297
	SLOTILLEGAL();
nkeynes@374
  1298
    } else {
nkeynes@374
  1299
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1300
	store_reg( R_ECX, 0 );
nkeynes@374
  1301
    }
nkeynes@361
  1302
:}
nkeynes@361
  1303
MOVCA.L R0, @Rn {:  
nkeynes@361
  1304
    load_reg( R_EAX, 0 );
nkeynes@361
  1305
    load_reg( R_ECX, Rn );
nkeynes@374
  1306
    check_walign32( R_ECX );
nkeynes@361
  1307
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1308
:}
nkeynes@359
  1309
nkeynes@359
  1310
/* Control transfer instructions */
nkeynes@374
  1311
BF disp {:
nkeynes@374
  1312
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1313
	SLOTILLEGAL();
nkeynes@374
  1314
    } else {
nkeynes@374
  1315
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1316
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1317
	JNE_rel8( 5, nottaken );
nkeynes@374
  1318
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1319
	JMP_TARGET(nottaken);
nkeynes@374
  1320
	INC_r32(R_ESI);
nkeynes@374
  1321
	return 1;
nkeynes@374
  1322
    }
nkeynes@374
  1323
:}
nkeynes@374
  1324
BF/S disp {:
nkeynes@374
  1325
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1326
	SLOTILLEGAL();
nkeynes@374
  1327
    } else {
nkeynes@386
  1328
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1329
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1330
	JNE_rel8( 5, nottaken );
nkeynes@374
  1331
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1332
	JMP_TARGET(nottaken);
nkeynes@374
  1333
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1334
	return 0;
nkeynes@374
  1335
    }
nkeynes@374
  1336
:}
nkeynes@374
  1337
BRA disp {:  
nkeynes@374
  1338
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1339
	SLOTILLEGAL();
nkeynes@374
  1340
    } else {
nkeynes@374
  1341
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1342
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1343
	return 0;
nkeynes@374
  1344
    }
nkeynes@374
  1345
:}
nkeynes@374
  1346
BRAF Rn {:  
nkeynes@374
  1347
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1348
	SLOTILLEGAL();
nkeynes@374
  1349
    } else {
nkeynes@374
  1350
	load_reg( R_EDI, Rn );
nkeynes@382
  1351
	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
  1352
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1353
	return 0;
nkeynes@374
  1354
    }
nkeynes@374
  1355
:}
nkeynes@374
  1356
BSR disp {:  
nkeynes@374
  1357
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1358
	SLOTILLEGAL();
nkeynes@374
  1359
    } else {
nkeynes@374
  1360
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1361
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1362
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1363
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1364
	return 0;
nkeynes@374
  1365
    }
nkeynes@374
  1366
:}
nkeynes@374
  1367
BSRF Rn {:  
nkeynes@374
  1368
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1369
	SLOTILLEGAL();
nkeynes@374
  1370
    } else {
nkeynes@374
  1371
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1372
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1373
	load_reg( R_EDI, Rn );
nkeynes@374
  1374
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1375
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1376
	return 0;
nkeynes@374
  1377
    }
nkeynes@374
  1378
:}
nkeynes@374
  1379
BT disp {:
nkeynes@374
  1380
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1381
	SLOTILLEGAL();
nkeynes@374
  1382
    } else {
nkeynes@374
  1383
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1384
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1385
	JE_rel8( 5, nottaken );
nkeynes@374
  1386
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1387
	JMP_TARGET(nottaken);
nkeynes@374
  1388
	INC_r32(R_ESI);
nkeynes@374
  1389
	return 1;
nkeynes@374
  1390
    }
nkeynes@374
  1391
:}
nkeynes@374
  1392
BT/S disp {:
nkeynes@374
  1393
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1394
	SLOTILLEGAL();
nkeynes@374
  1395
    } else {
nkeynes@386
  1396
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1397
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1398
	JE_rel8( 5, nottaken );
nkeynes@374
  1399
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1400
	JMP_TARGET(nottaken);
nkeynes@374
  1401
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1402
	return 0;
nkeynes@374
  1403
    }
nkeynes@374
  1404
:}
nkeynes@374
  1405
JMP @Rn {:  
nkeynes@374
  1406
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1407
	SLOTILLEGAL();
nkeynes@374
  1408
    } else {
nkeynes@374
  1409
	load_reg( R_EDI, Rn );
nkeynes@374
  1410
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1411
	return 0;
nkeynes@374
  1412
    }
nkeynes@374
  1413
:}
nkeynes@374
  1414
JSR @Rn {:  
nkeynes@374
  1415
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1416
	SLOTILLEGAL();
nkeynes@374
  1417
    } else {
nkeynes@374
  1418
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1419
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1420
	load_reg( R_EDI, Rn );
nkeynes@374
  1421
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1422
	return 0;
nkeynes@374
  1423
    }
nkeynes@374
  1424
:}
nkeynes@374
  1425
RTE {:  
nkeynes@374
  1426
    check_priv();
nkeynes@374
  1427
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1428
	SLOTILLEGAL();
nkeynes@374
  1429
    } else {
nkeynes@386
  1430
	load_spreg( R_EDI, R_SPC );
nkeynes@374
  1431
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1432
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1433
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1434
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1435
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1436
	return 0;
nkeynes@374
  1437
    }
nkeynes@374
  1438
:}
nkeynes@374
  1439
RTS {:  
nkeynes@374
  1440
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1441
	SLOTILLEGAL();
nkeynes@374
  1442
    } else {
nkeynes@374
  1443
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1444
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1445
	return 0;
nkeynes@374
  1446
    }
nkeynes@374
  1447
:}
nkeynes@374
  1448
TRAPA #imm {:  
nkeynes@374
  1449
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1450
	SLOTILLEGAL();
nkeynes@374
  1451
    } else {
nkeynes@388
  1452
	PUSH_imm32( imm );
nkeynes@388
  1453
	call_func0( sh4_raise_trap );
nkeynes@388
  1454
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  1455
    }
nkeynes@374
  1456
:}
nkeynes@374
  1457
UNDEF {:  
nkeynes@374
  1458
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1459
	SLOTILLEGAL();
nkeynes@374
  1460
    } else {
nkeynes@386
  1461
	JMP_exit(EXIT_ILLEGAL);
nkeynes@382
  1462
	return 1;
nkeynes@374
  1463
    }
nkeynes@368
  1464
:}
nkeynes@374
  1465
nkeynes@374
  1466
CLRMAC {:  
nkeynes@374
  1467
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1468
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1469
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1470
:}
nkeynes@374
  1471
CLRS {:
nkeynes@374
  1472
    CLC();
nkeynes@374
  1473
    SETC_sh4r(R_S);
nkeynes@368
  1474
:}
nkeynes@374
  1475
CLRT {:  
nkeynes@374
  1476
    CLC();
nkeynes@374
  1477
    SETC_t();
nkeynes@359
  1478
:}
nkeynes@374
  1479
SETS {:  
nkeynes@374
  1480
    STC();
nkeynes@374
  1481
    SETC_sh4r(R_S);
nkeynes@359
  1482
:}
nkeynes@374
  1483
SETT {:  
nkeynes@374
  1484
    STC();
nkeynes@374
  1485
    SETC_t();
nkeynes@374
  1486
:}
nkeynes@359
  1487
nkeynes@375
  1488
/* Floating point moves */
nkeynes@375
  1489
FMOV FRm, FRn {:  
nkeynes@375
  1490
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1491
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1492
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1493
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1494
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1495
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1496
     */
nkeynes@377
  1497
    check_fpuen();
nkeynes@375
  1498
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1499
    load_fr_bank( R_EDX );
nkeynes@375
  1500
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1501
    JNE_rel8(8, doublesize);
nkeynes@375
  1502
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1503
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1504
    if( FRm&1 ) {
nkeynes@386
  1505
	JMP_rel8(24, end);
nkeynes@380
  1506
	JMP_TARGET(doublesize);
nkeynes@375
  1507
	load_xf_bank( R_ECX ); 
nkeynes@375
  1508
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1509
	if( FRn&1 ) {
nkeynes@375
  1510
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1511
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1512
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1513
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1514
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1515
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1516
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1517
	}
nkeynes@380
  1518
	JMP_TARGET(end);
nkeynes@375
  1519
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1520
	if( FRn&1 ) {
nkeynes@386
  1521
	    JMP_rel8(24, end);
nkeynes@375
  1522
	    load_xf_bank( R_ECX );
nkeynes@375
  1523
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1524
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1525
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1526
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1527
	    JMP_TARGET(end);
nkeynes@375
  1528
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1529
	    JMP_rel8(12, end);
nkeynes@375
  1530
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1531
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1532
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1533
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1534
	    JMP_TARGET(end);
nkeynes@375
  1535
	}
nkeynes@375
  1536
    }
nkeynes@375
  1537
:}
nkeynes@375
  1538
FMOV FRm, @Rn {:  
nkeynes@377
  1539
    check_fpuen();
nkeynes@375
  1540
    load_reg( R_EDX, Rn );
nkeynes@375
  1541
    check_walign32( R_EDX );
nkeynes@375
  1542
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1543
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1544
    JNE_rel8(20, doublesize);
nkeynes@377
  1545
    load_fr_bank( R_ECX );
nkeynes@375
  1546
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1547
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1548
    if( FRm&1 ) {
nkeynes@386
  1549
	JMP_rel8( 48, end );
nkeynes@380
  1550
	JMP_TARGET(doublesize);
nkeynes@375
  1551
	load_xf_bank( R_ECX );
nkeynes@380
  1552
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1553
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1554
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1555
	JMP_TARGET(end);
nkeynes@375
  1556
    } else {
nkeynes@380
  1557
	JMP_rel8( 39, end );
nkeynes@380
  1558
	JMP_TARGET(doublesize);
nkeynes@377
  1559
	load_fr_bank( R_ECX );
nkeynes@380
  1560
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1561
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1562
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1563
	JMP_TARGET(end);
nkeynes@375
  1564
    }
nkeynes@375
  1565
:}
nkeynes@375
  1566
FMOV @Rm, FRn {:  
nkeynes@377
  1567
    check_fpuen();
nkeynes@375
  1568
    load_reg( R_EDX, Rm );
nkeynes@375
  1569
    check_ralign32( R_EDX );
nkeynes@375
  1570
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1571
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1572
    JNE_rel8(19, doublesize);
nkeynes@375
  1573
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1574
    load_fr_bank( R_ECX );
nkeynes@375
  1575
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1576
    if( FRn&1 ) {
nkeynes@386
  1577
	JMP_rel8(48, end);
nkeynes@380
  1578
	JMP_TARGET(doublesize);
nkeynes@375
  1579
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1580
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1581
	load_xf_bank( R_ECX );
nkeynes@380
  1582
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1583
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1584
	JMP_TARGET(end);
nkeynes@375
  1585
    } else {
nkeynes@380
  1586
	JMP_rel8(36, end);
nkeynes@380
  1587
	JMP_TARGET(doublesize);
nkeynes@375
  1588
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1589
	load_fr_bank( R_ECX );
nkeynes@380
  1590
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1591
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1592
	JMP_TARGET(end);
nkeynes@375
  1593
    }
nkeynes@375
  1594
:}
nkeynes@377
  1595
FMOV FRm, @-Rn {:  
nkeynes@377
  1596
    check_fpuen();
nkeynes@377
  1597
    load_reg( R_EDX, Rn );
nkeynes@377
  1598
    check_walign32( R_EDX );
nkeynes@377
  1599
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1600
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@382
  1601
    JNE_rel8(26, doublesize);
nkeynes@377
  1602
    load_fr_bank( R_ECX );
nkeynes@377
  1603
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1604
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1605
    store_reg( R_EDX, Rn );
nkeynes@377
  1606
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1607
    if( FRm&1 ) {
nkeynes@386
  1608
	JMP_rel8( 54, end );
nkeynes@380
  1609
	JMP_TARGET(doublesize);
nkeynes@377
  1610
	load_xf_bank( R_ECX );
nkeynes@380
  1611
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1612
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1613
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1614
	store_reg( R_EDX, Rn );
nkeynes@380
  1615
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1616
	JMP_TARGET(end);
nkeynes@377
  1617
    } else {
nkeynes@382
  1618
	JMP_rel8( 45, end );
nkeynes@380
  1619
	JMP_TARGET(doublesize);
nkeynes@377
  1620
	load_fr_bank( R_ECX );
nkeynes@380
  1621
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1622
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1623
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1624
	store_reg( R_EDX, Rn );
nkeynes@380
  1625
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1626
	JMP_TARGET(end);
nkeynes@377
  1627
    }
nkeynes@377
  1628
:}
nkeynes@377
  1629
FMOV @Rm+, FRn {:  
nkeynes@377
  1630
    check_fpuen();
nkeynes@377
  1631
    load_reg( R_EDX, Rm );
nkeynes@377
  1632
    check_ralign32( R_EDX );
nkeynes@377
  1633
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1634
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1635
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1636
    JNE_rel8(25, doublesize);
nkeynes@377
  1637
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1638
    store_reg( R_EAX, Rm );
nkeynes@377
  1639
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1640
    load_fr_bank( R_ECX );
nkeynes@377
  1641
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1642
    if( FRn&1 ) {
nkeynes@386
  1643
	JMP_rel8(54, end);
nkeynes@380
  1644
	JMP_TARGET(doublesize);
nkeynes@377
  1645
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1646
	store_reg(R_EAX, Rm);
nkeynes@377
  1647
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1648
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1649
	load_xf_bank( R_ECX );
nkeynes@380
  1650
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1651
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1652
	JMP_TARGET(end);
nkeynes@377
  1653
    } else {
nkeynes@380
  1654
	JMP_rel8(42, end);
nkeynes@377
  1655
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1656
	store_reg(R_EAX, Rm);
nkeynes@377
  1657
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1658
	load_fr_bank( R_ECX );
nkeynes@380
  1659
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1660
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1661
	JMP_TARGET(end);
nkeynes@377
  1662
    }
nkeynes@377
  1663
:}
nkeynes@377
  1664
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1665
    check_fpuen();
nkeynes@377
  1666
    load_reg( R_EDX, Rn );
nkeynes@377
  1667
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1668
    check_walign32( R_EDX );
nkeynes@377
  1669
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1670
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1671
    JNE_rel8(20, doublesize);
nkeynes@377
  1672
    load_fr_bank( R_ECX );
nkeynes@377
  1673
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1674
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1675
    if( FRm&1 ) {
nkeynes@386
  1676
	JMP_rel8( 48, end );
nkeynes@380
  1677
	JMP_TARGET(doublesize);
nkeynes@377
  1678
	load_xf_bank( R_ECX );
nkeynes@380
  1679
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1680
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1681
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1682
	JMP_TARGET(end);
nkeynes@377
  1683
    } else {
nkeynes@380
  1684
	JMP_rel8( 39, end );
nkeynes@380
  1685
	JMP_TARGET(doublesize);
nkeynes@377
  1686
	load_fr_bank( R_ECX );
nkeynes@380
  1687
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1688
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1689
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1690
	JMP_TARGET(end);
nkeynes@377
  1691
    }
nkeynes@377
  1692
:}
nkeynes@377
  1693
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1694
    check_fpuen();
nkeynes@377
  1695
    load_reg( R_EDX, Rm );
nkeynes@377
  1696
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1697
    check_ralign32( R_EDX );
nkeynes@377
  1698
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1699
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1700
    JNE_rel8(19, doublesize);
nkeynes@377
  1701
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1702
    load_fr_bank( R_ECX );
nkeynes@377
  1703
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1704
    if( FRn&1 ) {
nkeynes@386
  1705
	JMP_rel8(48, end);
nkeynes@380
  1706
	JMP_TARGET(doublesize);
nkeynes@377
  1707
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1708
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1709
	load_xf_bank( R_ECX );
nkeynes@380
  1710
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1711
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1712
	JMP_TARGET(end);
nkeynes@377
  1713
    } else {
nkeynes@380
  1714
	JMP_rel8(36, end);
nkeynes@380
  1715
	JMP_TARGET(doublesize);
nkeynes@377
  1716
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1717
	load_fr_bank( R_ECX );
nkeynes@380
  1718
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1719
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1720
	JMP_TARGET(end);
nkeynes@377
  1721
    }
nkeynes@377
  1722
:}
nkeynes@377
  1723
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1724
    check_fpuen();
nkeynes@377
  1725
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1726
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1727
    JNE_rel8(8, end);
nkeynes@377
  1728
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1729
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1730
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1731
    JMP_TARGET(end);
nkeynes@377
  1732
:}
nkeynes@377
  1733
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1734
    check_fpuen();
nkeynes@377
  1735
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1736
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1737
    JNE_rel8(11, end);
nkeynes@377
  1738
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1739
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1740
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1741
    JMP_TARGET(end);
nkeynes@377
  1742
:}
nkeynes@377
  1743
nkeynes@377
  1744
FLOAT FPUL, FRn {:  
nkeynes@377
  1745
    check_fpuen();
nkeynes@377
  1746
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1747
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1748
    FILD_sh4r(R_FPUL);
nkeynes@377
  1749
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1750
    JNE_rel8(5, doubleprec);
nkeynes@377
  1751
    pop_fr( R_EDX, FRn );
nkeynes@380
  1752
    JMP_rel8(3, end);
nkeynes@380
  1753
    JMP_TARGET(doubleprec);
nkeynes@377
  1754
    pop_dr( R_EDX, FRn );
nkeynes@380
  1755
    JMP_TARGET(end);
nkeynes@377
  1756
:}
nkeynes@377
  1757
FTRC FRm, FPUL {:  
nkeynes@377
  1758
    check_fpuen();
nkeynes@388
  1759
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1760
    load_fr_bank( R_EDX );
nkeynes@388
  1761
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1762
    JNE_rel8(5, doubleprec);
nkeynes@388
  1763
    push_fr( R_EDX, FRm );
nkeynes@388
  1764
    JMP_rel8(3, doop);
nkeynes@388
  1765
    JMP_TARGET(doubleprec);
nkeynes@388
  1766
    push_dr( R_EDX, FRm );
nkeynes@388
  1767
    JMP_TARGET( doop );
nkeynes@388
  1768
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1769
    FILD_r32ind( R_ECX );
nkeynes@388
  1770
    FCOMIP_st(1);
nkeynes@394
  1771
    JNA_rel8( 32, sat );
nkeynes@388
  1772
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1773
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1774
    FCOMIP_st(1);                   // 2
nkeynes@394
  1775
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1776
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1777
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1778
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1779
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1780
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1781
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1782
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1783
nkeynes@388
  1784
    JMP_TARGET(sat);
nkeynes@388
  1785
    JMP_TARGET(sat2);
nkeynes@388
  1786
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1787
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1788
    FPOP_st();
nkeynes@388
  1789
    JMP_TARGET(end);
nkeynes@377
  1790
:}
nkeynes@377
  1791
FLDS FRm, FPUL {:  
nkeynes@377
  1792
    check_fpuen();
nkeynes@377
  1793
    load_fr_bank( R_ECX );
nkeynes@377
  1794
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1795
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1796
:}
nkeynes@377
  1797
FSTS FPUL, FRn {:  
nkeynes@377
  1798
    check_fpuen();
nkeynes@377
  1799
    load_fr_bank( R_ECX );
nkeynes@377
  1800
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1801
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1802
:}
nkeynes@377
  1803
FCNVDS FRm, FPUL {:  
nkeynes@377
  1804
    check_fpuen();
nkeynes@377
  1805
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1806
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1807
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1808
    load_fr_bank( R_ECX );
nkeynes@377
  1809
    push_dr( R_ECX, FRm );
nkeynes@377
  1810
    pop_fpul();
nkeynes@380
  1811
    JMP_TARGET(end);
nkeynes@377
  1812
:}
nkeynes@377
  1813
FCNVSD FPUL, FRn {:  
nkeynes@377
  1814
    check_fpuen();
nkeynes@377
  1815
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1816
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1817
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1818
    load_fr_bank( R_ECX );
nkeynes@377
  1819
    push_fpul();
nkeynes@377
  1820
    pop_dr( R_ECX, FRn );
nkeynes@380
  1821
    JMP_TARGET(end);
nkeynes@377
  1822
:}
nkeynes@375
  1823
nkeynes@359
  1824
/* Floating point instructions */
nkeynes@374
  1825
FABS FRn {:  
nkeynes@377
  1826
    check_fpuen();
nkeynes@374
  1827
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1828
    load_fr_bank( R_EDX );
nkeynes@374
  1829
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1830
    JNE_rel8(10, doubleprec);
nkeynes@374
  1831
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1832
    FABS_st0(); // 2
nkeynes@374
  1833
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1834
    JMP_rel8(8,end); // 2
nkeynes@380
  1835
    JMP_TARGET(doubleprec);
nkeynes@374
  1836
    push_dr(R_EDX, FRn);
nkeynes@374
  1837
    FABS_st0();
nkeynes@374
  1838
    pop_dr(R_EDX, FRn);
nkeynes@380
  1839
    JMP_TARGET(end);
nkeynes@374
  1840
:}
nkeynes@377
  1841
FADD FRm, FRn {:  
nkeynes@377
  1842
    check_fpuen();
nkeynes@375
  1843
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1844
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1845
    load_fr_bank( R_EDX );
nkeynes@380
  1846
    JNE_rel8(13,doubleprec);
nkeynes@377
  1847
    push_fr(R_EDX, FRm);
nkeynes@377
  1848
    push_fr(R_EDX, FRn);
nkeynes@377
  1849
    FADDP_st(1);
nkeynes@377
  1850
    pop_fr(R_EDX, FRn);
nkeynes@380
  1851
    JMP_rel8(11,end);
nkeynes@380
  1852
    JMP_TARGET(doubleprec);
nkeynes@377
  1853
    push_dr(R_EDX, FRm);
nkeynes@377
  1854
    push_dr(R_EDX, FRn);
nkeynes@377
  1855
    FADDP_st(1);
nkeynes@377
  1856
    pop_dr(R_EDX, FRn);
nkeynes@380
  1857
    JMP_TARGET(end);
nkeynes@375
  1858
:}
nkeynes@377
  1859
FDIV FRm, FRn {:  
nkeynes@377
  1860
    check_fpuen();
nkeynes@375
  1861
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1862
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1863
    load_fr_bank( R_EDX );
nkeynes@380
  1864
    JNE_rel8(13, doubleprec);
nkeynes@377
  1865
    push_fr(R_EDX, FRn);
nkeynes@377
  1866
    push_fr(R_EDX, FRm);
nkeynes@377
  1867
    FDIVP_st(1);
nkeynes@377
  1868
    pop_fr(R_EDX, FRn);
nkeynes@380
  1869
    JMP_rel8(11, end);
nkeynes@380
  1870
    JMP_TARGET(doubleprec);
nkeynes@377
  1871
    push_dr(R_EDX, FRn);
nkeynes@377
  1872
    push_dr(R_EDX, FRm);
nkeynes@377
  1873
    FDIVP_st(1);
nkeynes@377
  1874
    pop_dr(R_EDX, FRn);
nkeynes@380
  1875
    JMP_TARGET(end);
nkeynes@375
  1876
:}
nkeynes@375
  1877
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1878
    check_fpuen();
nkeynes@375
  1879
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1880
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1881
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1882
    JNE_rel8(18, doubleprec);
nkeynes@375
  1883
    push_fr( R_EDX, 0 );
nkeynes@375
  1884
    push_fr( R_EDX, FRm );
nkeynes@375
  1885
    FMULP_st(1);
nkeynes@375
  1886
    push_fr( R_EDX, FRn );
nkeynes@375
  1887
    FADDP_st(1);
nkeynes@375
  1888
    pop_fr( R_EDX, FRn );
nkeynes@380
  1889
    JMP_rel8(16, end);
nkeynes@380
  1890
    JMP_TARGET(doubleprec);
nkeynes@375
  1891
    push_dr( R_EDX, 0 );
nkeynes@375
  1892
    push_dr( R_EDX, FRm );
nkeynes@375
  1893
    FMULP_st(1);
nkeynes@375
  1894
    push_dr( R_EDX, FRn );
nkeynes@375
  1895
    FADDP_st(1);
nkeynes@375
  1896
    pop_dr( R_EDX, FRn );
nkeynes@380
  1897
    JMP_TARGET(end);
nkeynes@375
  1898
:}
nkeynes@375
  1899
nkeynes@377
  1900
FMUL FRm, FRn {:  
nkeynes@377
  1901
    check_fpuen();
nkeynes@377
  1902
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1903
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1904
    load_fr_bank( R_EDX );
nkeynes@380
  1905
    JNE_rel8(13, doubleprec);
nkeynes@377
  1906
    push_fr(R_EDX, FRm);
nkeynes@377
  1907
    push_fr(R_EDX, FRn);
nkeynes@377
  1908
    FMULP_st(1);
nkeynes@377
  1909
    pop_fr(R_EDX, FRn);
nkeynes@380
  1910
    JMP_rel8(11, end);
nkeynes@380
  1911
    JMP_TARGET(doubleprec);
nkeynes@377
  1912
    push_dr(R_EDX, FRm);
nkeynes@377
  1913
    push_dr(R_EDX, FRn);
nkeynes@377
  1914
    FMULP_st(1);
nkeynes@377
  1915
    pop_dr(R_EDX, FRn);
nkeynes@380
  1916
    JMP_TARGET(end);
nkeynes@377
  1917
:}
nkeynes@377
  1918
FNEG FRn {:  
nkeynes@377
  1919
    check_fpuen();
nkeynes@377
  1920
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1921
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1922
    load_fr_bank( R_EDX );
nkeynes@380
  1923
    JNE_rel8(10, doubleprec);
nkeynes@377
  1924
    push_fr(R_EDX, FRn);
nkeynes@377
  1925
    FCHS_st0();
nkeynes@377
  1926
    pop_fr(R_EDX, FRn);
nkeynes@380
  1927
    JMP_rel8(8, end);
nkeynes@380
  1928
    JMP_TARGET(doubleprec);
nkeynes@377
  1929
    push_dr(R_EDX, FRn);
nkeynes@377
  1930
    FCHS_st0();
nkeynes@377
  1931
    pop_dr(R_EDX, FRn);
nkeynes@380
  1932
    JMP_TARGET(end);
nkeynes@377
  1933
:}
nkeynes@377
  1934
FSRRA FRn {:  
nkeynes@377
  1935
    check_fpuen();
nkeynes@377
  1936
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1937
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1938
    load_fr_bank( R_EDX );
nkeynes@380
  1939
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1940
    FLD1_st0();
nkeynes@377
  1941
    push_fr(R_EDX, FRn);
nkeynes@377
  1942
    FSQRT_st0();
nkeynes@377
  1943
    FDIVP_st(1);
nkeynes@377
  1944
    pop_fr(R_EDX, FRn);
nkeynes@380
  1945
    JMP_TARGET(end);
nkeynes@377
  1946
:}
nkeynes@377
  1947
FSQRT FRn {:  
nkeynes@377
  1948
    check_fpuen();
nkeynes@377
  1949
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1950
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1951
    load_fr_bank( R_EDX );
nkeynes@380
  1952
    JNE_rel8(10, doubleprec);
nkeynes@377
  1953
    push_fr(R_EDX, FRn);
nkeynes@377
  1954
    FSQRT_st0();
nkeynes@377
  1955
    pop_fr(R_EDX, FRn);
nkeynes@380
  1956
    JMP_rel8(8, end);
nkeynes@380
  1957
    JMP_TARGET(doubleprec);
nkeynes@377
  1958
    push_dr(R_EDX, FRn);
nkeynes@377
  1959
    FSQRT_st0();
nkeynes@377
  1960
    pop_dr(R_EDX, FRn);
nkeynes@380
  1961
    JMP_TARGET(end);
nkeynes@377
  1962
:}
nkeynes@377
  1963
FSUB FRm, FRn {:  
nkeynes@377
  1964
    check_fpuen();
nkeynes@377
  1965
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1966
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1967
    load_fr_bank( R_EDX );
nkeynes@380
  1968
    JNE_rel8(13, doubleprec);
nkeynes@377
  1969
    push_fr(R_EDX, FRn);
nkeynes@377
  1970
    push_fr(R_EDX, FRm);
nkeynes@388
  1971
    FSUBP_st(1);
nkeynes@377
  1972
    pop_fr(R_EDX, FRn);
nkeynes@380
  1973
    JMP_rel8(11, end);
nkeynes@380
  1974
    JMP_TARGET(doubleprec);
nkeynes@377
  1975
    push_dr(R_EDX, FRn);
nkeynes@377
  1976
    push_dr(R_EDX, FRm);
nkeynes@388
  1977
    FSUBP_st(1);
nkeynes@377
  1978
    pop_dr(R_EDX, FRn);
nkeynes@380
  1979
    JMP_TARGET(end);
nkeynes@377
  1980
:}
nkeynes@377
  1981
nkeynes@377
  1982
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1983
    check_fpuen();
nkeynes@377
  1984
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1985
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1986
    load_fr_bank( R_EDX );
nkeynes@380
  1987
    JNE_rel8(8, doubleprec);
nkeynes@377
  1988
    push_fr(R_EDX, FRm);
nkeynes@377
  1989
    push_fr(R_EDX, FRn);
nkeynes@380
  1990
    JMP_rel8(6, end);
nkeynes@380
  1991
    JMP_TARGET(doubleprec);
nkeynes@377
  1992
    push_dr(R_EDX, FRm);
nkeynes@377
  1993
    push_dr(R_EDX, FRn);
nkeynes@382
  1994
    JMP_TARGET(end);
nkeynes@377
  1995
    FCOMIP_st(1);
nkeynes@377
  1996
    SETE_t();
nkeynes@377
  1997
    FPOP_st();
nkeynes@377
  1998
:}
nkeynes@377
  1999
FCMP/GT FRm, FRn {:  
nkeynes@377
  2000
    check_fpuen();
nkeynes@377
  2001
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2002
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2003
    load_fr_bank( R_EDX );
nkeynes@380
  2004
    JNE_rel8(8, doubleprec);
nkeynes@377
  2005
    push_fr(R_EDX, FRm);
nkeynes@377
  2006
    push_fr(R_EDX, FRn);
nkeynes@380
  2007
    JMP_rel8(6, end);
nkeynes@380
  2008
    JMP_TARGET(doubleprec);
nkeynes@377
  2009
    push_dr(R_EDX, FRm);
nkeynes@377
  2010
    push_dr(R_EDX, FRn);
nkeynes@380
  2011
    JMP_TARGET(end);
nkeynes@377
  2012
    FCOMIP_st(1);
nkeynes@377
  2013
    SETA_t();
nkeynes@377
  2014
    FPOP_st();
nkeynes@377
  2015
:}
nkeynes@377
  2016
nkeynes@377
  2017
FSCA FPUL, FRn {:  
nkeynes@377
  2018
    check_fpuen();
nkeynes@388
  2019
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2020
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2021
    JNE_rel8( 21, doubleprec );
nkeynes@388
  2022
    load_fr_bank( R_ECX );
nkeynes@388
  2023
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2024
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2025
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2026
    JMP_TARGET(doubleprec);
nkeynes@377
  2027
:}
nkeynes@377
  2028
FIPR FVm, FVn {:  
nkeynes@377
  2029
    check_fpuen();
nkeynes@388
  2030
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2031
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2032
    JNE_rel8(44, doubleprec);
nkeynes@388
  2033
    
nkeynes@388
  2034
    load_fr_bank( R_ECX );
nkeynes@388
  2035
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2036
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2037
    FMULP_st(1);
nkeynes@388
  2038
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2039
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2040
    FMULP_st(1);
nkeynes@388
  2041
    FADDP_st(1);
nkeynes@388
  2042
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2043
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2044
    FMULP_st(1);
nkeynes@388
  2045
    FADDP_st(1);
nkeynes@388
  2046
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2047
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2048
    FMULP_st(1);
nkeynes@388
  2049
    FADDP_st(1);
nkeynes@388
  2050
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2051
    JMP_TARGET(doubleprec);
nkeynes@377
  2052
:}
nkeynes@377
  2053
FTRV XMTRX, FVn {:  
nkeynes@377
  2054
    check_fpuen();
nkeynes@388
  2055
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2056
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2057
    JNE_rel8( 30, doubleprec );
nkeynes@388
  2058
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2059
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2060
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2061
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2062
    JMP_TARGET(doubleprec);
nkeynes@377
  2063
:}
nkeynes@377
  2064
nkeynes@377
  2065
FRCHG {:  
nkeynes@377
  2066
    check_fpuen();
nkeynes@377
  2067
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2068
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2069
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2070
    update_fr_bank( R_ECX );
nkeynes@377
  2071
:}
nkeynes@377
  2072
FSCHG {:  
nkeynes@377
  2073
    check_fpuen();
nkeynes@377
  2074
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2075
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2076
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2077
:}
nkeynes@359
  2078
nkeynes@359
  2079
/* Processor control instructions */
nkeynes@368
  2080
LDC Rm, SR {:
nkeynes@386
  2081
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2082
	SLOTILLEGAL();
nkeynes@386
  2083
    } else {
nkeynes@386
  2084
	check_priv();
nkeynes@386
  2085
	load_reg( R_EAX, Rm );
nkeynes@386
  2086
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2087
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2088
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2089
    }
nkeynes@368
  2090
:}
nkeynes@359
  2091
LDC Rm, GBR {: 
nkeynes@359
  2092
    load_reg( R_EAX, Rm );
nkeynes@359
  2093
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2094
:}
nkeynes@359
  2095
LDC Rm, VBR {:  
nkeynes@386
  2096
    check_priv();
nkeynes@359
  2097
    load_reg( R_EAX, Rm );
nkeynes@359
  2098
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2099
:}
nkeynes@359
  2100
LDC Rm, SSR {:  
nkeynes@386
  2101
    check_priv();
nkeynes@359
  2102
    load_reg( R_EAX, Rm );
nkeynes@359
  2103
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2104
:}
nkeynes@359
  2105
LDC Rm, SGR {:  
nkeynes@386
  2106
    check_priv();
nkeynes@359
  2107
    load_reg( R_EAX, Rm );
nkeynes@359
  2108
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2109
:}
nkeynes@359
  2110
LDC Rm, SPC {:  
nkeynes@386
  2111
    check_priv();
nkeynes@359
  2112
    load_reg( R_EAX, Rm );
nkeynes@359
  2113
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2114
:}
nkeynes@359
  2115
LDC Rm, DBR {:  
nkeynes@386
  2116
    check_priv();
nkeynes@359
  2117
    load_reg( R_EAX, Rm );
nkeynes@359
  2118
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2119
:}
nkeynes@374
  2120
LDC Rm, Rn_BANK {:  
nkeynes@386
  2121
    check_priv();
nkeynes@374
  2122
    load_reg( R_EAX, Rm );
nkeynes@374
  2123
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  2124
:}
nkeynes@359
  2125
LDC.L @Rm+, GBR {:  
nkeynes@359
  2126
    load_reg( R_EAX, Rm );
nkeynes@395
  2127
    check_ralign32( R_EAX );
nkeynes@359
  2128
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2129
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2130
    store_reg( R_EAX, Rm );
nkeynes@359
  2131
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2132
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2133
:}
nkeynes@368
  2134
LDC.L @Rm+, SR {:
nkeynes@386
  2135
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2136
	SLOTILLEGAL();
nkeynes@386
  2137
    } else {
nkeynes@386
  2138
	check_priv();
nkeynes@386
  2139
	load_reg( R_EAX, Rm );
nkeynes@395
  2140
	check_ralign32( R_EAX );
nkeynes@386
  2141
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2142
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2143
	store_reg( R_EAX, Rm );
nkeynes@386
  2144
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2145
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2146
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2147
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2148
    }
nkeynes@359
  2149
:}
nkeynes@359
  2150
LDC.L @Rm+, VBR {:  
nkeynes@386
  2151
    check_priv();
nkeynes@359
  2152
    load_reg( R_EAX, Rm );
nkeynes@395
  2153
    check_ralign32( R_EAX );
nkeynes@359
  2154
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2155
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2156
    store_reg( R_EAX, Rm );
nkeynes@359
  2157
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2158
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2159
:}
nkeynes@359
  2160
LDC.L @Rm+, SSR {:
nkeynes@386
  2161
    check_priv();
nkeynes@359
  2162
    load_reg( R_EAX, Rm );
nkeynes@359
  2163
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2164
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2165
    store_reg( R_EAX, Rm );
nkeynes@359
  2166
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2167
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2168
:}
nkeynes@359
  2169
LDC.L @Rm+, SGR {:  
nkeynes@386
  2170
    check_priv();
nkeynes@359
  2171
    load_reg( R_EAX, Rm );
nkeynes@395
  2172
    check_ralign32( R_EAX );
nkeynes@359
  2173
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2174
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2175
    store_reg( R_EAX, Rm );
nkeynes@359
  2176
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2177
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2178
:}
nkeynes@359
  2179
LDC.L @Rm+, SPC {:  
nkeynes@386
  2180
    check_priv();
nkeynes@359
  2181
    load_reg( R_EAX, Rm );
nkeynes@395
  2182
    check_ralign32( R_EAX );
nkeynes@359
  2183
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2184
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2185
    store_reg( R_EAX, Rm );
nkeynes@359
  2186
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2187
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2188
:}
nkeynes@359
  2189
LDC.L @Rm+, DBR {:  
nkeynes@386
  2190
    check_priv();
nkeynes@359
  2191
    load_reg( R_EAX, Rm );
nkeynes@395
  2192
    check_ralign32( R_EAX );
nkeynes@359
  2193
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2194
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2195
    store_reg( R_EAX, Rm );
nkeynes@359
  2196
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2197
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2198
:}
nkeynes@359
  2199
LDC.L @Rm+, Rn_BANK {:  
nkeynes@386
  2200
    check_priv();
nkeynes@374
  2201
    load_reg( R_EAX, Rm );
nkeynes@395
  2202
    check_ralign32( R_EAX );
nkeynes@374
  2203
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2204
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2205
    store_reg( R_EAX, Rm );
nkeynes@374
  2206
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2207
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  2208
:}
nkeynes@359
  2209
LDS Rm, FPSCR {:  
nkeynes@359
  2210
    load_reg( R_EAX, Rm );
nkeynes@359
  2211
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2212
    update_fr_bank( R_EAX );
nkeynes@359
  2213
:}
nkeynes@359
  2214
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2215
    load_reg( R_EAX, Rm );
nkeynes@395
  2216
    check_ralign32( R_EAX );
nkeynes@359
  2217
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2218
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2219
    store_reg( R_EAX, Rm );
nkeynes@359
  2220
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2221
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2222
    update_fr_bank( R_EAX );
nkeynes@359
  2223
:}
nkeynes@359
  2224
LDS Rm, FPUL {:  
nkeynes@359
  2225
    load_reg( R_EAX, Rm );
nkeynes@359
  2226
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2227
:}
nkeynes@359
  2228
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2229
    load_reg( R_EAX, Rm );
nkeynes@395
  2230
    check_ralign32( R_EAX );
nkeynes@359
  2231
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2232
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2233
    store_reg( R_EAX, Rm );
nkeynes@359
  2234
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2235
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2236
:}
nkeynes@359
  2237
LDS Rm, MACH {: 
nkeynes@359
  2238
    load_reg( R_EAX, Rm );
nkeynes@359
  2239
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2240
:}
nkeynes@359
  2241
LDS.L @Rm+, MACH {:  
nkeynes@359
  2242
    load_reg( R_EAX, Rm );
nkeynes@395
  2243
    check_ralign32( R_EAX );
nkeynes@359
  2244
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2245
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2246
    store_reg( R_EAX, Rm );
nkeynes@359
  2247
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2248
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2249
:}
nkeynes@359
  2250
LDS Rm, MACL {:  
nkeynes@359
  2251
    load_reg( R_EAX, Rm );
nkeynes@359
  2252
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2253
:}
nkeynes@359
  2254
LDS.L @Rm+, MACL {:  
nkeynes@359
  2255
    load_reg( R_EAX, Rm );
nkeynes@395
  2256
    check_ralign32( R_EAX );
nkeynes@359
  2257
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2258
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2259
    store_reg( R_EAX, Rm );
nkeynes@359
  2260
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2261
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2262
:}
nkeynes@359
  2263
LDS Rm, PR {:  
nkeynes@359
  2264
    load_reg( R_EAX, Rm );
nkeynes@359
  2265
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2266
:}
nkeynes@359
  2267
LDS.L @Rm+, PR {:  
nkeynes@359
  2268
    load_reg( R_EAX, Rm );
nkeynes@395
  2269
    check_ralign32( R_EAX );
nkeynes@359
  2270
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2271
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2272
    store_reg( R_EAX, Rm );
nkeynes@359
  2273
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2274
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2275
:}
nkeynes@359
  2276
LDTLB {:  :}
nkeynes@359
  2277
OCBI @Rn {:  :}
nkeynes@359
  2278
OCBP @Rn {:  :}
nkeynes@359
  2279
OCBWB @Rn {:  :}
nkeynes@374
  2280
PREF @Rn {:
nkeynes@374
  2281
    load_reg( R_EAX, Rn );
nkeynes@374
  2282
    PUSH_r32( R_EAX );
nkeynes@374
  2283
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2284
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2285
    JNE_rel8(7, end);
nkeynes@374
  2286
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2287
    JMP_TARGET(end);
nkeynes@377
  2288
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2289
:}
nkeynes@388
  2290
SLEEP {: 
nkeynes@388
  2291
    check_priv();
nkeynes@388
  2292
    call_func0( sh4_sleep );
nkeynes@388
  2293
    sh4_x86.exit_code = 0;
nkeynes@388
  2294
    sh4_x86.in_delay_slot = FALSE;
nkeynes@394
  2295
    INC_r32(R_ESI);
nkeynes@388
  2296
    return 1;
nkeynes@388
  2297
:}
nkeynes@386
  2298
STC SR, Rn {:
nkeynes@386
  2299
    check_priv();
nkeynes@386
  2300
    call_func0(sh4_read_sr);
nkeynes@386
  2301
    store_reg( R_EAX, Rn );
nkeynes@359
  2302
:}
nkeynes@359
  2303
STC GBR, Rn {:  
nkeynes@359
  2304
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2305
    store_reg( R_EAX, Rn );
nkeynes@359
  2306
:}
nkeynes@359
  2307
STC VBR, Rn {:  
nkeynes@386
  2308
    check_priv();
nkeynes@359
  2309
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2310
    store_reg( R_EAX, Rn );
nkeynes@359
  2311
:}
nkeynes@359
  2312
STC SSR, Rn {:  
nkeynes@386
  2313
    check_priv();
nkeynes@359
  2314
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2315
    store_reg( R_EAX, Rn );
nkeynes@359
  2316
:}
nkeynes@359
  2317
STC SPC, Rn {:  
nkeynes@386
  2318
    check_priv();
nkeynes@359
  2319
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2320
    store_reg( R_EAX, Rn );
nkeynes@359
  2321
:}
nkeynes@359
  2322
STC SGR, Rn {:  
nkeynes@386
  2323
    check_priv();
nkeynes@359
  2324
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2325
    store_reg( R_EAX, Rn );
nkeynes@359
  2326
:}
nkeynes@359
  2327
STC DBR, Rn {:  
nkeynes@386
  2328
    check_priv();
nkeynes@359
  2329
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2330
    store_reg( R_EAX, Rn );
nkeynes@359
  2331
:}
nkeynes@374
  2332
STC Rm_BANK, Rn {:
nkeynes@386
  2333
    check_priv();
nkeynes@374
  2334
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2335
    store_reg( R_EAX, Rn );
nkeynes@359
  2336
:}
nkeynes@374
  2337
STC.L SR, @-Rn {:
nkeynes@386
  2338
    check_priv();
nkeynes@395
  2339
    call_func0( sh4_read_sr );
nkeynes@368
  2340
    load_reg( R_ECX, Rn );
nkeynes@395
  2341
    check_walign32( R_ECX );
nkeynes@382
  2342
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2343
    store_reg( R_ECX, Rn );
nkeynes@368
  2344
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2345
:}
nkeynes@359
  2346
STC.L VBR, @-Rn {:  
nkeynes@386
  2347
    check_priv();
nkeynes@359
  2348
    load_reg( R_ECX, Rn );
nkeynes@395
  2349
    check_walign32( R_ECX );
nkeynes@382
  2350
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2351
    store_reg( R_ECX, Rn );
nkeynes@359
  2352
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2353
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2354
:}
nkeynes@359
  2355
STC.L SSR, @-Rn {:  
nkeynes@386
  2356
    check_priv();
nkeynes@359
  2357
    load_reg( R_ECX, Rn );
nkeynes@395
  2358
    check_walign32( R_ECX );
nkeynes@382
  2359
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2360
    store_reg( R_ECX, Rn );
nkeynes@359
  2361
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2362
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2363
:}
nkeynes@359
  2364
STC.L SPC, @-Rn {:  
nkeynes@386
  2365
    check_priv();
nkeynes@359
  2366
    load_reg( R_ECX, Rn );
nkeynes@395
  2367
    check_walign32( R_ECX );
nkeynes@382
  2368
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2369
    store_reg( R_ECX, Rn );
nkeynes@359
  2370
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2371
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2372
:}
nkeynes@359
  2373
STC.L SGR, @-Rn {:  
nkeynes@386
  2374
    check_priv();
nkeynes@359
  2375
    load_reg( R_ECX, Rn );
nkeynes@395
  2376
    check_walign32( R_ECX );
nkeynes@382
  2377
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2378
    store_reg( R_ECX, Rn );
nkeynes@359
  2379
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2380
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2381
:}
nkeynes@359
  2382
STC.L DBR, @-Rn {:  
nkeynes@386
  2383
    check_priv();
nkeynes@359
  2384
    load_reg( R_ECX, Rn );
nkeynes@395
  2385
    check_walign32( R_ECX );
nkeynes@382
  2386
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2387
    store_reg( R_ECX, Rn );
nkeynes@359
  2388
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2389
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2390
:}
nkeynes@374
  2391
STC.L Rm_BANK, @-Rn {:  
nkeynes@386
  2392
    check_priv();
nkeynes@374
  2393
    load_reg( R_ECX, Rn );
nkeynes@395
  2394
    check_walign32( R_ECX );
nkeynes@382
  2395
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2396
    store_reg( R_ECX, Rn );
nkeynes@374
  2397
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2398
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2399
:}
nkeynes@359
  2400
STC.L GBR, @-Rn {:  
nkeynes@359
  2401
    load_reg( R_ECX, Rn );
nkeynes@395
  2402
    check_walign32( R_ECX );
nkeynes@382
  2403
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2404
    store_reg( R_ECX, Rn );
nkeynes@359
  2405
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2406
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2407
:}
nkeynes@359
  2408
STS FPSCR, Rn {:  
nkeynes@359
  2409
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2410
    store_reg( R_EAX, Rn );
nkeynes@359
  2411
:}
nkeynes@359
  2412
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2413
    load_reg( R_ECX, Rn );
nkeynes@395
  2414
    check_walign32( R_ECX );
nkeynes@382
  2415
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2416
    store_reg( R_ECX, Rn );
nkeynes@359
  2417
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2418
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2419
:}
nkeynes@359
  2420
STS FPUL, Rn {:  
nkeynes@359
  2421
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2422
    store_reg( R_EAX, Rn );
nkeynes@359
  2423
:}
nkeynes@359
  2424
STS.L FPUL, @-Rn {:  
nkeynes@359
  2425
    load_reg( R_ECX, Rn );
nkeynes@395
  2426
    check_walign32( R_ECX );
nkeynes@382
  2427
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2428
    store_reg( R_ECX, Rn );
nkeynes@359
  2429
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2430
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2431
:}
nkeynes@359
  2432
STS MACH, Rn {:  
nkeynes@359
  2433
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2434
    store_reg( R_EAX, Rn );
nkeynes@359
  2435
:}
nkeynes@359
  2436
STS.L MACH, @-Rn {:  
nkeynes@359
  2437
    load_reg( R_ECX, Rn );
nkeynes@395
  2438
    check_walign32( R_ECX );
nkeynes@382
  2439
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2440
    store_reg( R_ECX, Rn );
nkeynes@359
  2441
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2442
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2443
:}
nkeynes@359
  2444
STS MACL, Rn {:  
nkeynes@359
  2445
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2446
    store_reg( R_EAX, Rn );
nkeynes@359
  2447
:}
nkeynes@359
  2448
STS.L MACL, @-Rn {:  
nkeynes@359
  2449
    load_reg( R_ECX, Rn );
nkeynes@395
  2450
    check_walign32( R_ECX );
nkeynes@382
  2451
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2452
    store_reg( R_ECX, Rn );
nkeynes@359
  2453
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2454
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2455
:}
nkeynes@359
  2456
STS PR, Rn {:  
nkeynes@359
  2457
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2458
    store_reg( R_EAX, Rn );
nkeynes@359
  2459
:}
nkeynes@359
  2460
STS.L PR, @-Rn {:  
nkeynes@359
  2461
    load_reg( R_ECX, Rn );
nkeynes@395
  2462
    check_walign32( R_ECX );
nkeynes@382
  2463
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2464
    store_reg( R_ECX, Rn );
nkeynes@359
  2465
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2466
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2467
:}
nkeynes@359
  2468
nkeynes@359
  2469
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2470
%%
nkeynes@374
  2471
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2472
	ADD_imm8s_r32(2,R_ESI);
nkeynes@374
  2473
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2474
	return 1;
nkeynes@386
  2475
    } else {
nkeynes@386
  2476
	INC_r32(R_ESI);
nkeynes@374
  2477
    }
nkeynes@359
  2478
    return 0;
nkeynes@359
  2479
}
.