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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 295:6637664291a8
prev284:808617ee7135
next304:2855cf8709a5
author nkeynes
date Tue Jan 16 10:34:46 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Bug 24: Initial implementation of "save scene" function
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.40 2007-01-16 10:34:46 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_line_event( int eventid, int line );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 31945 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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/**
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 * Event handler for the retrace callback (fires on line 0 normally)
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 */
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static void pvr2_retrace_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    pvr2_schedule_line_event( EVENT_RETRACE, 0 );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 );
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    }
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}
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.timing = ntsc_timing;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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{
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    if( pvr2_state.save_next_render_filename != NULL ) {
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	g_free( pvr2_state.save_next_render_filename );
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    } 
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    pvr2_state.save_next_render_filename = g_strdup(filename);
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    return TRUE;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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   264
    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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   269
	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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   273
						buffer->colour_format );
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	}
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   275
	if( !bEnabled ) {
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   276
	    display_driver->display_blank_frame( 0 );
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   277
	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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   278
	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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   279
	    display_driver->display_blank_frame( colour );
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   280
	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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   281
	    display_driver->display_frame( buffer );
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   282
	}
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   283
    }
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   284
    pvr2_state.frame_count++;
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   285
}
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   286
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   287
/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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 */
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   291
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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   292
{
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   293
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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   294
        MMIO_WRITE( PVR2, reg, val );
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   295
        return;
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   296
    }
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   297
    
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   298
    switch(reg) {
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   299
    case PVRID:
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   300
    case PVRVER:
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   301
    case GUNPOS: /* Read only registers */
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   302
	break;
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   303
    case PVRRESET:
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   304
	val &= 0x00000007; /* Do stuff? */
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   305
	MMIO_WRITE( PVR2, reg, val );
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   306
	break;
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   307
    case RENDER_START: /* Don't really care what value */
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   308
	if( pvr2_state.save_next_render_filename != NULL ) {
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   309
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
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   310
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
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   311
	    }
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   312
	    g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   313
	    pvr2_state.save_next_render_filename = NULL;
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   314
	}
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   315
	pvr2_render_scene();
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   316
	break;
nkeynes@191
   317
    case RENDER_POLYBASE:
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   318
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   319
    	break;
nkeynes@191
   320
    case RENDER_TSPCFG:
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   321
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   322
    	break;
nkeynes@197
   323
    case DISP_BORDER:
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   324
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   325
    	break;
nkeynes@197
   326
    case DISP_MODE:
nkeynes@191
   327
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   328
    	break;
nkeynes@191
   329
    case RENDER_MODE:
nkeynes@191
   330
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   331
    	break;
nkeynes@191
   332
    case RENDER_SIZE:
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   333
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   334
    	break;
nkeynes@197
   335
    case DISP_ADDR1:
nkeynes@189
   336
	val &= 0x00FFFFFC;
nkeynes@189
   337
	MMIO_WRITE( PVR2, reg, val );
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   338
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   339
	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
nkeynes@265
   340
	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
nkeynes@108
   341
	    pvr2_display_frame();
nkeynes@108
   342
	}
nkeynes@108
   343
	break;
nkeynes@197
   344
    case DISP_ADDR2:
nkeynes@191
   345
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@191
   346
    	break;
nkeynes@197
   347
    case DISP_SIZE:
nkeynes@191
   348
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   349
    	break;
nkeynes@191
   350
    case RENDER_ADDR1:
nkeynes@191
   351
    case RENDER_ADDR2:
nkeynes@191
   352
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   353
    	break;
nkeynes@191
   354
    case RENDER_HCLIP:
nkeynes@191
   355
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   356
	break;
nkeynes@191
   357
    case RENDER_VCLIP:
nkeynes@191
   358
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   359
	break;
nkeynes@197
   360
    case DISP_HPOSIRQ:
nkeynes@191
   361
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   362
	break;
nkeynes@197
   363
    case DISP_VPOSIRQ:
nkeynes@189
   364
	val = val & 0x03FF03FF;
nkeynes@189
   365
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   366
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   367
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@274
   368
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
nkeynes@274
   369
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
nkeynes@189
   370
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   371
	break;
nkeynes@197
   372
    case RENDER_NEARCLIP:
nkeynes@197
   373
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   374
	break;
nkeynes@191
   375
    case RENDER_SHADOW:
nkeynes@191
   376
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   377
	break;
nkeynes@191
   378
    case RENDER_OBJCFG:
nkeynes@191
   379
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   380
    	break;
nkeynes@191
   381
    case RENDER_TSPCLIP:
nkeynes@191
   382
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   383
    	break;
nkeynes@197
   384
    case RENDER_FARCLIP:
nkeynes@197
   385
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   386
	break;
nkeynes@191
   387
    case RENDER_BGPLANE:
nkeynes@191
   388
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   389
    	break;
nkeynes@191
   390
    case RENDER_ISPCFG:
nkeynes@191
   391
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   392
    	break;
nkeynes@197
   393
    case VRAM_CFG1:
nkeynes@197
   394
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   395
	break;
nkeynes@197
   396
    case VRAM_CFG2:
nkeynes@197
   397
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   398
	break;
nkeynes@197
   399
    case VRAM_CFG3:
nkeynes@197
   400
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   401
	break;
nkeynes@197
   402
    case RENDER_FOGTBLCOL:
nkeynes@197
   403
    case RENDER_FOGVRTCOL:
nkeynes@197
   404
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   405
	break;
nkeynes@197
   406
    case RENDER_FOGCOEFF:
nkeynes@197
   407
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   408
	break;
nkeynes@197
   409
    case RENDER_CLAMPHI:
nkeynes@197
   410
    case RENDER_CLAMPLO:
nkeynes@197
   411
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   412
	break;
nkeynes@261
   413
    case RENDER_TEXSIZE:
nkeynes@261
   414
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   415
	break;
nkeynes@261
   416
    case RENDER_PALETTE:
nkeynes@261
   417
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   418
	break;
nkeynes@261
   419
nkeynes@261
   420
	/********** CRTC registers *************/
nkeynes@197
   421
    case DISP_HBORDER:
nkeynes@197
   422
    case DISP_VBORDER:
nkeynes@197
   423
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   424
	break;
nkeynes@261
   425
    case DISP_TOTAL:
nkeynes@261
   426
	val = val & 0x03FF03FF;
nkeynes@261
   427
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   428
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   429
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   430
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   431
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   432
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   433
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@265
   434
	pvr2_schedule_line_event( EVENT_RETRACE, 0 );
nkeynes@274
   435
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
nkeynes@274
   436
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
nkeynes@261
   437
	break;
nkeynes@261
   438
    case DISP_SYNCCFG:
nkeynes@261
   439
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   440
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   441
	break;
nkeynes@261
   442
    case DISP_SYNCTIME:
nkeynes@261
   443
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   444
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   445
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   446
	break;
nkeynes@197
   447
    case DISP_CFG2:
nkeynes@197
   448
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   449
	break;
nkeynes@197
   450
    case DISP_HPOS:
nkeynes@261
   451
	val = val & 0x03FF;
nkeynes@261
   452
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   453
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   454
	break;
nkeynes@197
   455
    case DISP_VPOS:
nkeynes@197
   456
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   457
	break;
nkeynes@261
   458
nkeynes@261
   459
	/*********** Tile accelerator registers ***********/
nkeynes@261
   460
    case TA_POLYPOS:
nkeynes@261
   461
    case TA_LISTPOS:
nkeynes@261
   462
	/* Readonly registers */
nkeynes@197
   463
	break;
nkeynes@189
   464
    case TA_TILEBASE:
nkeynes@193
   465
    case TA_LISTEND:
nkeynes@189
   466
    case TA_LISTBASE:
nkeynes@191
   467
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   468
	break;
nkeynes@191
   469
    case RENDER_TILEBASE:
nkeynes@189
   470
    case TA_POLYBASE:
nkeynes@189
   471
    case TA_POLYEND:
nkeynes@191
   472
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   473
	break;
nkeynes@189
   474
    case TA_TILESIZE:
nkeynes@191
   475
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   476
	break;
nkeynes@189
   477
    case TA_TILECFG:
nkeynes@191
   478
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   479
	break;
nkeynes@261
   480
    case TA_INIT:
nkeynes@261
   481
	if( val & 0x80000000 )
nkeynes@261
   482
	    pvr2_ta_init();
nkeynes@261
   483
	break;
nkeynes@261
   484
    case TA_REINIT:
nkeynes@261
   485
	break;
nkeynes@261
   486
	/**************** Scaler registers? ****************/
nkeynes@261
   487
    case SCALERCFG:
nkeynes@269
   488
	/* KOS suggests bits as follows:
nkeynes@269
   489
	 *   0: enable vertical scaling
nkeynes@269
   490
	 *  10: ???
nkeynes@269
   491
	 *  16: enable FSAA
nkeynes@269
   492
	 */
nkeynes@261
   493
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   494
	break;
nkeynes@261
   495
nkeynes@197
   496
    case YUV_ADDR:
nkeynes@284
   497
	val = val & 0x00FFFFF8;
nkeynes@284
   498
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   499
	pvr2_yuv_init( val );
nkeynes@197
   500
	break;
nkeynes@197
   501
    case YUV_CFG:
nkeynes@197
   502
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   503
	pvr2_yuv_set_config(val);
nkeynes@197
   504
	break;
nkeynes@261
   505
nkeynes@261
   506
	/**************** Unknowns ***************/
nkeynes@261
   507
    case PVRUNK1:
nkeynes@261
   508
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   509
    	break;
nkeynes@261
   510
    case PVRUNK2:
nkeynes@261
   511
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   512
	break;
nkeynes@261
   513
    case PVRUNK3:
nkeynes@261
   514
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   515
	break;
nkeynes@261
   516
    case PVRUNK5:
nkeynes@261
   517
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   518
	break;
nkeynes@261
   519
    case PVRUNK6:
nkeynes@261
   520
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   521
	break;
nkeynes@197
   522
    case PVRUNK7:
nkeynes@197
   523
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   524
	break;
nkeynes@1
   525
    }
nkeynes@1
   526
}
nkeynes@1
   527
nkeynes@261
   528
/**
nkeynes@261
   529
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   530
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   531
 * The register reads (LSB to MSB) as:
nkeynes@261
   532
 *     0..9  Current scan line
nkeynes@261
   533
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   534
 *     11    Display active (including border and overscan)
nkeynes@261
   535
 *     12    Horizontal sync off
nkeynes@261
   536
 *     13    Vertical sync off
nkeynes@261
   537
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   538
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   539
 */
nkeynes@261
   540
uint32_t pvr2_get_sync_status()
nkeynes@261
   541
{
nkeynes@265
   542
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   543
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   544
nkeynes@265
   545
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   546
	result |= 0x0400;
nkeynes@261
   547
    }
nkeynes@265
   548
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   549
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   550
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   551
	}
nkeynes@265
   552
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   553
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   554
		result |= 0x2800; /* Display active */
nkeynes@261
   555
	    } else {
nkeynes@261
   556
		result |= 0x2000; /* Front porch */
nkeynes@261
   557
	    }
nkeynes@261
   558
	}
nkeynes@261
   559
    } else {
nkeynes@269
   560
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   561
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   562
		result |= 0x3800; /* Display active */
nkeynes@269
   563
	    } else {
nkeynes@269
   564
		result |= 0x3000;
nkeynes@269
   565
	    }
nkeynes@261
   566
	} else {
nkeynes@261
   567
	    result |= 0x1000; /* Back porch */
nkeynes@261
   568
	}
nkeynes@261
   569
    }
nkeynes@261
   570
    return result;
nkeynes@261
   571
}
nkeynes@261
   572
nkeynes@265
   573
/**
nkeynes@265
   574
 * Schedule an event for the start of the given line. If the line is actually
nkeynes@265
   575
 * the current line, schedules it for the next field. 
nkeynes@265
   576
 * The raster position should be updated before calling this method.
nkeynes@265
   577
 */
nkeynes@265
   578
static void pvr2_schedule_line_event( int eventid, int line )
nkeynes@265
   579
{
nkeynes@265
   580
    uint32_t time;
nkeynes@265
   581
    if( line <= pvr2_state.line_count ) {
nkeynes@265
   582
	time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
nkeynes@265
   583
	    - pvr2_state.line_remainder;
nkeynes@265
   584
    } else {
nkeynes@265
   585
	time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
nkeynes@265
   586
    }
nkeynes@265
   587
nkeynes@265
   588
    if( line < pvr2_state.total_lines ) {
nkeynes@265
   589
	event_schedule( eventid, time );
nkeynes@265
   590
    } else {
nkeynes@265
   591
	event_cancel( eventid );
nkeynes@265
   592
    }
nkeynes@265
   593
}
nkeynes@265
   594
nkeynes@265
   595
/**
nkeynes@265
   596
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   597
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   598
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   599
 * The raster position should be updated before calling this
nkeynes@265
   600
 * method.
nkeynes@265
   601
 */
nkeynes@274
   602
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines )
nkeynes@265
   603
{
nkeynes@265
   604
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   605
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   606
	field = !field;
nkeynes@265
   607
    }
nkeynes@265
   608
nkeynes@265
   609
    line <<= 1;
nkeynes@265
   610
    if( field ) {
nkeynes@265
   611
	line += 1;
nkeynes@265
   612
    }
nkeynes@274
   613
    
nkeynes@274
   614
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   615
	uint32_t lines;
nkeynes@274
   616
	uint32_t time;
nkeynes@274
   617
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   618
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   619
	} else {
nkeynes@274
   620
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   621
	}
nkeynes@274
   622
	if( lines <= minimum_lines ) {
nkeynes@274
   623
	    lines += pvr2_state.total_lines;
nkeynes@274
   624
	}
nkeynes@274
   625
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder;
nkeynes@274
   626
	event_schedule( eventid, time );
nkeynes@274
   627
    } else {
nkeynes@274
   628
	event_cancel( eventid );
nkeynes@274
   629
    }
nkeynes@265
   630
}
nkeynes@265
   631
nkeynes@1
   632
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   633
{
nkeynes@1
   634
    switch( reg ) {
nkeynes@261
   635
        case DISP_SYNCSTAT:
nkeynes@261
   636
            return pvr2_get_sync_status();
nkeynes@1
   637
        default:
nkeynes@1
   638
            return MMIO_READ( PVR2, reg );
nkeynes@1
   639
    }
nkeynes@1
   640
}
nkeynes@19
   641
nkeynes@85
   642
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   643
nkeynes@19
   644
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   645
{
nkeynes@197
   646
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   647
}
nkeynes@56
   648
nkeynes@56
   649
nkeynes@65
   650
nkeynes@98
   651
nkeynes@56
   652
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   653
{
nkeynes@56
   654
    return 0xFFFFFFFF;
nkeynes@56
   655
}
nkeynes@56
   656
nkeynes@56
   657
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   658
{
nkeynes@189
   659
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   660
}
nkeynes@56
   661
.