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lxdream.org :: lxdream/src/sh4/mmu.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.h
changeset 1217:677b1d85f1b4
prev1067:d3c00ffccfcd
author nkeynes
date Mon Feb 13 20:00:27 2012 +1000 (9 years ago)
permissions -rw-r--r--
last change Fix MMU on non-translated platforms
- reintroduce old VMA translation functions (slightly modified)
- modify shadow processing to work on post-translated memory ops
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * MMU/TLB definitions.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef lxdream_sh4_mmu_H
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#define lxdream_sh4_mmu_H 1
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#include "lxdream.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/************************** UTLB/ITLB Definitions ***************************/
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/* mmucr register bits */
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#define MMUCR_AT   0x00000001 /* Address Translation enabled */
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#define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
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#define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
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#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
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#define MMUCR_URC  0x0000FC00 /* UTLB access counter */
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#define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
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#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
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#define MMUCR_MASK 0xFCFCFF05
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#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
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#define IS_TLB_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
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#define IS_SV_ENABLED() (MMIO_READ(MMU,MMUCR)&MMUCR_SV)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used in this implementation
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};
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#define TLB_FUNC_SIZE 48
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struct utlb_page_entry {
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    struct mem_region_fn fn;
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    struct mem_region_fn *user_fn;
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    mem_region_fn_t target;
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    unsigned char code[TLB_FUNC_SIZE*9];
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};
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struct utlb_1k_entry {
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    struct mem_region_fn fn;
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    struct mem_region_fn user_fn;
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    struct mem_region_fn *subpages[4];
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    struct mem_region_fn *user_subpages[4];
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    unsigned char code[TLB_FUNC_SIZE*18];
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};
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struct utlb_default_regions {
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    mem_region_fn_t tlb_miss;
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    mem_region_fn_t tlb_prot;
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    mem_region_fn_t tlb_multihit;
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};
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/** Set the MMU's target external address space
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 * @return the previous address space.
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 */
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mem_region_fn_t *mmu_set_ext_address_space( mem_region_fn_t *space );
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/* Address translation functions */
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sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma );
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mem_region_fn_t FASTCALL mmu_get_region_for_vma_read( sh4vma_t *addr );
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mem_region_fn_t FASTCALL mmu_get_region_for_vma_write( sh4vma_t *addr );
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mem_region_fn_t FASTCALL mmu_get_region_for_vma_prefetch( sh4vma_t *addr );
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/* Translator provided helpers */
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void mmu_utlb_init_vtable( struct utlb_entry *ent, struct utlb_page_entry *page, gboolean writable ); 
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void mmu_utlb_1k_init_vtable( struct utlb_1k_entry *ent ); 
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void mmu_utlb_init_storequeue_vtable( struct utlb_entry *ent, struct utlb_page_entry *page );
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extern uint32_t mmu_urc;
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extern uint32_t mmu_urb;
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/** Primary SH4 address space (privileged and user access)
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 * Page map (4KB) of the entire 32-bit address space
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 * Note: only callable from the SH4 cores as it depends on the caller setting
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 * up an appropriate exception environment. 
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 **/
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extern struct mem_region_fn **sh4_address_space;
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extern struct mem_region_fn **sh4_user_address_space;
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/************ Storequeue/cache functions ***********/
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void FASTCALL ccn_storequeue_write_long( sh4addr_t addr, uint32_t val );
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int32_t FASTCALL ccn_storequeue_read_long( sh4addr_t addr );
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/** Default storequeue prefetch when TLB is disabled */
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void FASTCALL ccn_storequeue_prefetch( sh4addr_t addr ); 
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/** TLB-enabled variant of the storequeue prefetch */
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void FASTCALL ccn_storequeue_prefetch_tlb( sh4addr_t addr );
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/** Non-storequeue prefetch */
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void FASTCALL ccn_prefetch( sh4addr_t addr );
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/** Non-cached prefetch (ie, no-op) */
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void FASTCALL ccn_uncached_prefetch( sh4addr_t addr );
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extern struct mem_region_fn mem_region_address_error;
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extern struct mem_region_fn mem_region_tlb_miss;
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extern struct mem_region_fn mem_region_tlb_multihit;
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extern struct mem_region_fn mem_region_tlb_protected;
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extern struct mem_region_fn p4_region_storequeue; 
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extern struct mem_region_fn p4_region_storequeue_multihit; 
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extern struct mem_region_fn p4_region_storequeue_miss; 
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extern struct mem_region_fn p4_region_storequeue_protected; 
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extern struct mem_region_fn p4_region_storequeue_sqmd; 
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extern struct mem_region_fn p4_region_storequeue_sqmd_miss; 
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extern struct mem_region_fn p4_region_storequeue_sqmd_multihit; 
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extern struct mem_region_fn p4_region_storequeue_sqmd_protected; 
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#ifdef __cplusplus
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}
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#endif
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#endif /* !lxdream_sh4_mmu_H */
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