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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 1217:677b1d85f1b4
prev1193:dff55bdc4f46
next1231:d63c808ddcd3
author nkeynes
date Mon Feb 13 20:00:27 2012 +1000 (7 years ago)
permissions -rw-r--r--
last change Fix MMU on non-translated platforms
- reintroduce old VMA translation functions (slightly modified)
- modify shadow processing to work on post-translated memory ops
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <assert.h>
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#include <math.h>
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#include "dream.h"
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#include "dreamcast.h"
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#include "eventq.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4stat.h"
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#include "sh4/mmu.h"
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#define SH4_CALLTRACE 1
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#define MAX_INT 0x7FFFFFFF
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#define MIN_INT 0x80000000
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#define MAX_INTF 2147483647.0
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#define MIN_INTF -2147483648.0
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/********************** SH4 Module Definition ****************************/
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uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
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{
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    int i;
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    if( sh4_breakpoint_count == 0 ) {
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	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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	        sh4_handle_pending_events();
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	    }
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	    if( !sh4_execute_instruction() ) {
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		break;
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	    }
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	}
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    } else {
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	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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	        sh4_handle_pending_events();
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	    }
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	    if( !sh4_execute_instruction() )
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		break;
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#ifdef ENABLE_DEBUG_MODE
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	    for( i=0; i<sh4_breakpoint_count; i++ ) {
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		if( sh4_breakpoints[i].address == sh4r.pc ) {
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		    break;
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		}
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	    }
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	    if( i != sh4_breakpoint_count ) {
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	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
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	    }
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#endif	
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	}
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    return nanosecs;
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}
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/********************** SH4 emulation core  ****************************/
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#if(SH4_CALLTRACE == 1)
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#define MAX_CALLSTACK 32
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static struct call_stack {
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    sh4addr_t call_addr;
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    sh4addr_t target_addr;
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    sh4addr_t stack_pointer;
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} call_stack[MAX_CALLSTACK];
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static int call_stack_depth = 0;
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int sh4_call_trace_on = 0;
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static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
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{
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    if( call_stack_depth < MAX_CALLSTACK ) {
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	call_stack[call_stack_depth].call_addr = source;
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	call_stack[call_stack_depth].target_addr = dest;
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	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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    }
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    call_stack_depth++;
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}
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static inline void trace_return( sh4addr_t source, sh4addr_t dest )
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{
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    if( call_stack_depth > 0 ) {
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	call_stack_depth--;
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    }
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}
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void fprint_stack_trace( FILE *f )
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{
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    int i = call_stack_depth -1;
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    if( i >= MAX_CALLSTACK )
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	i = MAX_CALLSTACK - 1;
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    for( ; i >= 0; i-- ) {
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	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
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		 (call_stack_depth - i), call_stack[i].call_addr,
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		 call_stack[i].target_addr, call_stack[i].stack_pointer );
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    }
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}
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#define TRACE_CALL( source, dest ) trace_call(source, dest)
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#define TRACE_RETURN( source, dest ) trace_return(source, dest)
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#else
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#define TRACE_CALL( dest, rts ) 
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#define TRACE_RETURN( source, dest )
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#endif
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static gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
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    if( sh4r.in_delay_slot ) {
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        sh4_raise_exception(slot_code);
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    } else {
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        sh4_raise_exception(normal_code);
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    }
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    return TRUE;
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}
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#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL ); }
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#define CHECKRALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKRALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKRALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKWALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKWALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKWALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { sh4_raise_exception(EXC_SLOT_ILLEGAL); return TRUE; }
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#define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
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#define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
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#define MEM_READ_BYTE( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_read(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { val = fntmp->read_byte(addrtmp); }
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#define MEM_READ_BYTE_FOR_WRITE( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_write(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { val = fntmp->read_byte_for_write(addrtmp); }
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#define MEM_READ_WORD( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_read(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { val = fntmp->read_word(addrtmp); }
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#define MEM_READ_LONG( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_read(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { val = fntmp->read_long(addrtmp); }
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#define MEM_WRITE_BYTE( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_write(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { fntmp->write_byte(addrtmp,val); }
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#define MEM_WRITE_WORD( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_write(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { fntmp->write_word(addrtmp,val); }
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#define MEM_WRITE_LONG( addr, val ) addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_write(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { fntmp->write_long(addrtmp,val); }
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#define MEM_PREFETCH( addr )  addrtmp = addr; if( (fntmp = mmu_get_region_for_vma_prefetch(&addrtmp)) == NULL ) { sh4r.in_delay_slot = 0; return TRUE; } else { fntmp->prefetch(addrtmp); }
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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	CHECKRALIGN64(addr); \
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        if( reg & 1 ) { \
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            MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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            MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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        CHECKRALIGN32(addr); \
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        MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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    }
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#define MEM_FP_WRITE( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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        CHECKWALIGN64(addr); \
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        if( reg & 1 ) { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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    	CHECKWALIGN32(addr); \
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        MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
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    }
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#define UNDEF(ir)
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#define UNIMP(ir)
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/**
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 * Perform instruction-completion following core exit of a partially completed
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 * instruction. NOTE: This is only allowed on memory writes, operation is not
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 * guaranteed in any other case.
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 */
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void sh4_finalize_instruction( void )
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{
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    unsigned short ir;
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    uint32_t tmp;
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   217
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    if( IS_SYSCALL(sh4r.pc) ) {
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        return;
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   220
    }
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    assert( IS_IN_ICACHE(sh4r.pc) );
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    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
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    /**
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     * Note - we can't take an exit on a control transfer instruction itself,
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     * which means the exit must have happened in the delay slot. So for these
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     * cases, finalize the delay slot instruction, and re-execute the control transfer.
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     *
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     * For delay slots which modify the argument used in the branch instruction,
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     * we pretty much just assume that that can't have already happened in an exit case.
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     */
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   232
    
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   233
%%
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BRA disp {: 
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    sh4r.pc += 2; 
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    sh4_finalize_instruction(); 
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   237
    sh4r.pc += disp;
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:}
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   239
BRAF Rn {: 
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   240
    sh4r.pc += 2; 
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   241
    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction(); 
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   243
    sh4r.pc += tmp;
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:}
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   245
BSR disp {: 
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   246
    /* Note: PR is already set */ 
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   247
    sh4r.pc += 2;
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   248
    sh4_finalize_instruction();
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   249
    sh4r.pc += disp;
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   250
:}
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   251
BSRF Rn {:
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   252
    /* Note: PR is already set */ 
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   253
    sh4r.pc += 2;
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   254
    tmp = sh4r.r[Rn];
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   255
    sh4_finalize_instruction();
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   256
    sh4r.pc += tmp;
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   257
:}
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   258
BF/S disp {: 
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   259
    sh4r.pc += 2;
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   260
    sh4_finalize_instruction();
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   261
    if( !sh4r.t ) {
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   262
        sh4r.pc += disp;
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   263
    }
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   264
:}
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   265
BT/S disp {: 
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   266
    sh4r.pc += 2;
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   267
    sh4_finalize_instruction();
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   268
    if( sh4r.t ) {
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   269
        sh4r.pc += disp;
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   270
    }
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   271
:}
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   272
JMP @Rn {:
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   273
    sh4r.pc += 2;
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   274
    tmp = sh4r.r[Rn];
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   275
    sh4_finalize_instruction();
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   276
    sh4r.pc = tmp;
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   277
    sh4r.new_pc = tmp + 2;
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   278
    sh4r.slice_cycle += sh4_cpu_period;
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   279
    return;
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:}
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   281
JSR @Rn {: 
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   282
    /* Note: PR is already set */ 
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   283
    sh4r.pc += 2;
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   284
    tmp = sh4r.r[Rn];
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   285
    sh4_finalize_instruction();
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   286
    sh4r.pc = tmp;
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   287
    sh4r.new_pc = tmp + 2;
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   288
    sh4r.slice_cycle += sh4_cpu_period;
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   289
    return;
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   290
:}
nkeynes@948
   291
RTS {: 
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   292
    sh4r.pc += 2;
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   293
    sh4_finalize_instruction();
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   294
    sh4r.pc = sh4r.pr;
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   295
    sh4r.new_pc = sh4r.pr + 2;
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   296
    sh4r.slice_cycle += sh4_cpu_period;
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   297
    return;
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   298
:}
nkeynes@948
   299
RTE {: 
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   300
    /* SR is already set */
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   301
    sh4r.pc += 2;
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   302
    sh4_finalize_instruction();
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   303
    sh4r.pc = sh4r.spc;
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   304
    sh4r.new_pc = sh4r.pr + 2;
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   305
    sh4r.slice_cycle += sh4_cpu_period;
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   306
    return;
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   307
:}
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   308
MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
nkeynes@948
   309
MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
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   310
MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
nkeynes@970
   311
MOV.B @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] ++;  } :}
nkeynes@970
   312
MOV.W @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
nkeynes@970
   313
MOV.L @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
nkeynes@948
   314
%%
nkeynes@974
   315
    sh4r.in_delay_slot = 0;
nkeynes@948
   316
    sh4r.pc += 2;
nkeynes@948
   317
    sh4r.new_pc = sh4r.pc+2;
nkeynes@948
   318
    sh4r.slice_cycle += sh4_cpu_period;
nkeynes@948
   319
}
nkeynes@948
   320
nkeynes@986
   321
#undef UNDEF
nkeynes@986
   322
#undef UNIMP
nkeynes@948
   323
nkeynes@948
   324
#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
nkeynes@948
   325
#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
nkeynes@948
   326
nkeynes@948
   327
nkeynes@359
   328
gboolean sh4_execute_instruction( void )
nkeynes@359
   329
{
nkeynes@359
   330
    uint32_t pc;
nkeynes@359
   331
    unsigned short ir;
nkeynes@359
   332
    uint32_t tmp;
nkeynes@359
   333
    float ftmp;
nkeynes@359
   334
    double dtmp;
nkeynes@1217
   335
    sh4addr_t addrtmp; // temporary holder for memory addresses
nkeynes@1217
   336
    mem_region_fn_t fntmp;
nkeynes@1217
   337
    
nkeynes@927
   338
nkeynes@359
   339
#define R0 sh4r.r[0]
nkeynes@359
   340
    pc = sh4r.pc;
nkeynes@359
   341
    if( pc > 0xFFFFFF00 ) {
nkeynes@359
   342
	/* SYSCALL Magic */
nkeynes@1103
   343
        sh4r.in_delay_slot = 0;
nkeynes@1103
   344
        sh4r.pc = sh4r.pr;
nkeynes@1103
   345
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   346
	syscall_invoke( pc );
nkeynes@671
   347
        return TRUE;
nkeynes@359
   348
    }
nkeynes@359
   349
    CHECKRALIGN16(pc);
nkeynes@359
   350
nkeynes@671
   351
#ifdef ENABLE_SH4STATS
nkeynes@671
   352
    sh4_stats_add_by_pc(sh4r.pc);
nkeynes@671
   353
#endif
nkeynes@671
   354
nkeynes@359
   355
    /* Read instruction */
nkeynes@586
   356
    if( !IS_IN_ICACHE(pc) ) {
nkeynes@974
   357
        gboolean delay_slot = sh4r.in_delay_slot;
nkeynes@586
   358
	if( !mmu_update_icache(pc) ) {
nkeynes@974
   359
	    if( delay_slot ) {
nkeynes@974
   360
	        sh4r.spc -= 2;
nkeynes@974
   361
	    }
nkeynes@586
   362
	    // Fault - look for the fault handler
nkeynes@586
   363
	    if( !mmu_update_icache(sh4r.pc) ) {
nkeynes@586
   364
		// double fault - halt
nkeynes@586
   365
		ERROR( "Double fault - halting" );
nkeynes@740
   366
		sh4_core_exit(CORE_EXIT_HALT);
nkeynes@586
   367
		return FALSE;
nkeynes@586
   368
	    }
nkeynes@359
   369
	}
nkeynes@586
   370
	pc = sh4r.pc;
nkeynes@359
   371
    }
nkeynes@586
   372
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   373
    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
nkeynes@948
   374
    
nkeynes@948
   375
    /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
nkeynes@948
   376
     * be visible until after the instruction has executed (for exception 
nkeynes@948
   377
     * correctness)
nkeynes@948
   378
     */
nkeynes@948
   379
    if( sh4r.in_delay_slot ) {
nkeynes@948
   380
    	sh4r.pc -= 2;
nkeynes@948
   381
    }
nkeynes@359
   382
%%
nkeynes@359
   383
AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
nkeynes@359
   384
AND #imm, R0 {: R0 &= imm; :}
nkeynes@1125
   385
 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
nkeynes@359
   386
NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
nkeynes@359
   387
OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
nkeynes@359
   388
OR #imm, R0  {: R0 |= imm; :}
nkeynes@1125
   389
 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
nkeynes@359
   390
TAS.B @Rn {:
nkeynes@1125
   391
    MEM_READ_BYTE_FOR_WRITE( sh4r.r[Rn], tmp );
nkeynes@359
   392
    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@359
   393
    MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
nkeynes@359
   394
:}
nkeynes@359
   395
TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
nkeynes@359
   396
TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
nkeynes@586
   397
 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
nkeynes@359
   398
XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
nkeynes@359
   399
XOR #imm, R0 {: R0 ^= imm; :}
nkeynes@1125
   400
 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
nkeynes@359
   401
XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   402
nkeynes@359
   403
ROTL Rn {:
nkeynes@359
   404
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   405
    sh4r.r[Rn] <<= 1;
nkeynes@359
   406
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   407
:}
nkeynes@359
   408
ROTR Rn {:
nkeynes@359
   409
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   410
    sh4r.r[Rn] >>= 1;
nkeynes@359
   411
    sh4r.r[Rn] |= (sh4r.t << 31);
nkeynes@359
   412
:}
nkeynes@359
   413
ROTCL Rn {:
nkeynes@359
   414
    tmp = sh4r.r[Rn] >> 31;
nkeynes@359
   415
    sh4r.r[Rn] <<= 1;
nkeynes@359
   416
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   417
    sh4r.t = tmp;
nkeynes@359
   418
:}
nkeynes@359
   419
ROTCR Rn {:
nkeynes@359
   420
    tmp = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   421
    sh4r.r[Rn] >>= 1;
nkeynes@359
   422
    sh4r.r[Rn] |= (sh4r.t << 31 );
nkeynes@359
   423
    sh4r.t = tmp;
nkeynes@359
   424
:}
nkeynes@359
   425
SHAD Rm, Rn {:
nkeynes@359
   426
    tmp = sh4r.r[Rm];
nkeynes@359
   427
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   428
    else if( (tmp & 0x1F) == 0 )  
nkeynes@359
   429
        sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
nkeynes@359
   430
    else 
nkeynes@359
   431
	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
nkeynes@359
   432
:}
nkeynes@359
   433
SHLD Rm, Rn {:
nkeynes@359
   434
    tmp = sh4r.r[Rm];
nkeynes@359
   435
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   436
    else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
nkeynes@359
   437
    else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
nkeynes@359
   438
:}
nkeynes@359
   439
SHAL Rn {:
nkeynes@359
   440
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   441
    sh4r.r[Rn] <<= 1;
nkeynes@359
   442
:}
nkeynes@359
   443
SHAR Rn {:
nkeynes@359
   444
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   445
    sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
nkeynes@359
   446
:}
nkeynes@359
   447
SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
nkeynes@359
   448
SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
nkeynes@359
   449
SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
nkeynes@359
   450
SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
nkeynes@359
   451
SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
nkeynes@359
   452
SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
nkeynes@359
   453
SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
nkeynes@359
   454
SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
nkeynes@359
   455
nkeynes@359
   456
EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
nkeynes@359
   457
EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
nkeynes@359
   458
EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
nkeynes@359
   459
EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
nkeynes@359
   460
SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
nkeynes@359
   461
SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   462
nkeynes@359
   463
CLRT {: sh4r.t = 0; :}
nkeynes@359
   464
SETT {: sh4r.t = 1; :}
nkeynes@359
   465
CLRMAC {: sh4r.mac = 0; :}
nkeynes@550
   466
LDTLB {: MMU_ldtlb(); :}
nkeynes@359
   467
CLRS {: sh4r.s = 0; :}
nkeynes@359
   468
SETS {: sh4r.s = 1; :}
nkeynes@359
   469
MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
nkeynes@359
   470
NOP {: /* NOP */ :}
nkeynes@359
   471
nkeynes@359
   472
PREF @Rn {:
nkeynes@946
   473
    MEM_PREFETCH(sh4r.r[Rn]);
nkeynes@359
   474
:}
nkeynes@359
   475
OCBI @Rn {: :}
nkeynes@359
   476
OCBP @Rn {: :}
nkeynes@359
   477
OCBWB @Rn {: :}
nkeynes@359
   478
MOVCA.L R0, @Rn {:
nkeynes@359
   479
    tmp = sh4r.r[Rn];
nkeynes@359
   480
    CHECKWALIGN32(tmp);
nkeynes@359
   481
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   482
:}
nkeynes@359
   483
MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   484
MOV.W Rm, @(R0, Rn) {: 
nkeynes@359
   485
    CHECKWALIGN16( R0 + sh4r.r[Rn] );
nkeynes@359
   486
    MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   487
:}
nkeynes@359
   488
MOV.L Rm, @(R0, Rn) {:
nkeynes@359
   489
    CHECKWALIGN32( R0 + sh4r.r[Rn] );
nkeynes@359
   490
    MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   491
:}
nkeynes@586
   492
MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   493
MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
nkeynes@586
   494
    MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   495
:}
nkeynes@359
   496
MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
nkeynes@586
   497
    MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   498
:}
nkeynes@359
   499
MOV.L Rm, @(disp, Rn) {:
nkeynes@359
   500
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   501
    CHECKWALIGN32( tmp );
nkeynes@359
   502
    MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
nkeynes@359
   503
:}
nkeynes@359
   504
MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   505
MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   506
MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@587
   507
 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
nkeynes@587
   508
 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
nkeynes@587
   509
 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
nkeynes@359
   510
MOV.L @(disp, Rm), Rn {:
nkeynes@359
   511
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   512
    CHECKRALIGN32( tmp );
nkeynes@586
   513
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   514
:}
nkeynes@586
   515
MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   516
 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   517
 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   518
MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
nkeynes@970
   519
 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] ++; } :}
nkeynes@970
   520
 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
nkeynes@970
   521
 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
nkeynes@359
   522
MOV.L @(disp, PC), Rn {:
nkeynes@359
   523
    CHECKSLOTILLEGAL();
nkeynes@359
   524
    tmp = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@586
   525
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   526
:}
nkeynes@359
   527
MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   528
MOV.W R0, @(disp, GBR) {:
nkeynes@359
   529
    tmp = sh4r.gbr + disp;
nkeynes@359
   530
    CHECKWALIGN16( tmp );
nkeynes@359
   531
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   532
:}
nkeynes@359
   533
MOV.L R0, @(disp, GBR) {:
nkeynes@359
   534
    tmp = sh4r.gbr + disp;
nkeynes@359
   535
    CHECKWALIGN32( tmp );
nkeynes@359
   536
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   537
:}
nkeynes@586
   538
 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   539
MOV.W @(disp, GBR), R0 {: 
nkeynes@359
   540
    tmp = sh4r.gbr + disp;
nkeynes@359
   541
    CHECKRALIGN16( tmp );
nkeynes@586
   542
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   543
:}
nkeynes@359
   544
MOV.L @(disp, GBR), R0 {:
nkeynes@359
   545
    tmp = sh4r.gbr + disp;
nkeynes@359
   546
    CHECKRALIGN32( tmp );
nkeynes@586
   547
    MEM_READ_LONG( tmp, R0 );
nkeynes@359
   548
:}
nkeynes@359
   549
MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
nkeynes@359
   550
MOV.W R0, @(disp, Rn) {: 
nkeynes@359
   551
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   552
    CHECKWALIGN16( tmp );
nkeynes@359
   553
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   554
:}
nkeynes@586
   555
 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
nkeynes@359
   556
MOV.W @(disp, Rm), R0 {: 
nkeynes@359
   557
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   558
    CHECKRALIGN16( tmp );
nkeynes@586
   559
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   560
:}
nkeynes@359
   561
MOV.W @(disp, PC), Rn {:
nkeynes@359
   562
    CHECKSLOTILLEGAL();
nkeynes@359
   563
    tmp = pc + 4 + disp;
nkeynes@586
   564
    MEM_READ_WORD( tmp, sh4r.r[Rn] );
nkeynes@359
   565
:}
nkeynes@359
   566
MOVA @(disp, PC), R0 {:
nkeynes@359
   567
    CHECKSLOTILLEGAL();
nkeynes@359
   568
    R0 = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@359
   569
:}
nkeynes@359
   570
MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
nkeynes@359
   571
nkeynes@732
   572
FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
nkeynes@732
   573
FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
nkeynes@732
   574
FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
nkeynes@732
   575
FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
nkeynes@732
   576
FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
nkeynes@732
   577
 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
nkeynes@732
   578
FMOV FRm, FRn {: 
nkeynes@732
   579
    if( IS_FPU_DOUBLESIZE() )
nkeynes@732
   580
	DR(FRn) = DR(FRm);
nkeynes@732
   581
    else
nkeynes@732
   582
	FR(FRn) = FR(FRm);
nkeynes@732
   583
:}
nkeynes@732
   584
nkeynes@359
   585
CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
nkeynes@359
   586
CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
nkeynes@359
   587
CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   588
CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   589
CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   590
CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   591
CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
nkeynes@359
   592
CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
nkeynes@359
   593
CMP/STR Rm, Rn {: 
nkeynes@359
   594
    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@359
   595
    tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
nkeynes@359
   596
    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@359
   597
             (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@359
   598
:}
nkeynes@359
   599
nkeynes@359
   600
ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
nkeynes@359
   601
ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
nkeynes@359
   602
ADDC Rm, Rn {:
nkeynes@359
   603
    tmp = sh4r.r[Rn];
nkeynes@359
   604
    sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
nkeynes@359
   605
    sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@359
   606
:}
nkeynes@359
   607
ADDV Rm, Rn {:
nkeynes@359
   608
    tmp = sh4r.r[Rn] + sh4r.r[Rm];
nkeynes@359
   609
    sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@359
   610
    sh4r.r[Rn] = tmp;
nkeynes@359
   611
:}
nkeynes@359
   612
DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
nkeynes@359
   613
DIV0S Rm, Rn {: 
nkeynes@359
   614
    sh4r.q = sh4r.r[Rn]>>31;
nkeynes@359
   615
    sh4r.m = sh4r.r[Rm]>>31;
nkeynes@359
   616
    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@359
   617
:}
nkeynes@359
   618
DIV1 Rm, Rn {:
nkeynes@384
   619
    /* This is derived from the sh4 manual with some simplifications */
nkeynes@359
   620
    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@359
   621
nkeynes@359
   622
    dir = sh4r.q ^ sh4r.m;
nkeynes@359
   623
    sh4r.q = (sh4r.r[Rn] >> 31);
nkeynes@359
   624
    tmp2 = sh4r.r[Rm];
nkeynes@359
   625
    sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
nkeynes@359
   626
    tmp0 = sh4r.r[Rn];
nkeynes@359
   627
    if( dir ) {
nkeynes@359
   628
         sh4r.r[Rn] += tmp2;
nkeynes@359
   629
         tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
nkeynes@359
   630
    } else {
nkeynes@359
   631
         sh4r.r[Rn] -= tmp2;
nkeynes@359
   632
         tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
nkeynes@359
   633
    }
nkeynes@359
   634
    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@359
   635
    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@359
   636
:}
nkeynes@359
   637
DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
nkeynes@359
   638
DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
nkeynes@359
   639
DT Rn {:
nkeynes@359
   640
    sh4r.r[Rn] --;
nkeynes@359
   641
    sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
nkeynes@359
   642
:}
nkeynes@359
   643
MAC.W @Rm+, @Rn+ {:
nkeynes@587
   644
    int32_t stmp;
nkeynes@587
   645
    if( Rm == Rn ) {
nkeynes@587
   646
	CHECKRALIGN16(sh4r.r[Rn]);
nkeynes@587
   647
	MEM_READ_WORD( sh4r.r[Rn], tmp );
nkeynes@587
   648
	stmp = SIGNEXT16(tmp);
nkeynes@587
   649
	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
nkeynes@587
   650
	stmp *= SIGNEXT16(tmp);
nkeynes@587
   651
	sh4r.r[Rn] += 4;
nkeynes@587
   652
    } else {
nkeynes@587
   653
	CHECKRALIGN16( sh4r.r[Rn] );
nkeynes@587
   654
	MEM_READ_WORD(sh4r.r[Rn], tmp);
nkeynes@587
   655
	stmp = SIGNEXT16(tmp);
nkeynes@1193
   656
	CHECKRALIGN16( sh4r.r[Rm] );
nkeynes@587
   657
	MEM_READ_WORD(sh4r.r[Rm], tmp);
nkeynes@587
   658
	stmp = stmp * SIGNEXT16(tmp);
nkeynes@587
   659
	sh4r.r[Rn] += 2;
nkeynes@587
   660
	sh4r.r[Rm] += 2;
nkeynes@587
   661
    }
nkeynes@359
   662
    if( sh4r.s ) {
nkeynes@359
   663
	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
nkeynes@359
   664
	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
nkeynes@359
   665
	    sh4r.mac = 0x000000017FFFFFFFLL;
nkeynes@359
   666
	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
nkeynes@359
   667
	    sh4r.mac = 0x0000000180000000LL;
nkeynes@359
   668
	} else {
nkeynes@359
   669
	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   670
		((uint32_t)(sh4r.mac + stmp));
nkeynes@359
   671
	}
nkeynes@359
   672
    } else {
nkeynes@359
   673
	sh4r.mac += SIGNEXT32(stmp);
nkeynes@359
   674
    }
nkeynes@359
   675
:}
nkeynes@359
   676
MAC.L @Rm+, @Rn+ {:
nkeynes@587
   677
    int64_t tmpl;
nkeynes@587
   678
    if( Rm == Rn ) {
nkeynes@587
   679
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   680
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   681
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   682
	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
nkeynes@587
   683
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   684
	sh4r.r[Rn] += 8;
nkeynes@587
   685
    } else {
nkeynes@587
   686
	CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@587
   687
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   688
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   689
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   690
	MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@587
   691
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   692
	sh4r.r[Rn] += 4;
nkeynes@587
   693
	sh4r.r[Rm] += 4;
nkeynes@587
   694
    }
nkeynes@359
   695
    if( sh4r.s ) {
nkeynes@359
   696
        /* 48-bit Saturation. Yuch */
nkeynes@359
   697
        if( tmpl < (int64_t)0xFFFF800000000000LL )
nkeynes@359
   698
            tmpl = 0xFFFF800000000000LL;
nkeynes@359
   699
        else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@359
   700
            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@359
   701
    }
nkeynes@359
   702
    sh4r.mac = tmpl;
nkeynes@359
   703
:}
nkeynes@359
   704
MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   705
                        (sh4r.r[Rm] * sh4r.r[Rn]); :}
nkeynes@359
   706
MULU.W Rm, Rn {:
nkeynes@359
   707
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   708
               (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
nkeynes@359
   709
:}
nkeynes@359
   710
MULS.W Rm, Rn {:
nkeynes@359
   711
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   712
               (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
nkeynes@359
   713
:}
nkeynes@359
   714
NEGC Rm, Rn {:
nkeynes@359
   715
    tmp = 0 - sh4r.r[Rm];
nkeynes@359
   716
    sh4r.r[Rn] = tmp - sh4r.t;
nkeynes@359
   717
    sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
nkeynes@359
   718
:}
nkeynes@359
   719
NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
nkeynes@359
   720
SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
nkeynes@359
   721
SUBC Rm, Rn {: 
nkeynes@359
   722
    tmp = sh4r.r[Rn];
nkeynes@359
   723
    sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
nkeynes@359
   724
    sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
nkeynes@359
   725
:}
nkeynes@1083
   726
SUBV Rm, Rn {:
nkeynes@1083
   727
    tmp = sh4r.r[Rn] - sh4r.r[Rm];
nkeynes@1083
   728
    sh4r.t = ( (sh4r.r[Rn]>>31) != (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@1083
   729
    sh4r.r[Rn] = tmp;
nkeynes@1083
   730
:}
nkeynes@359
   731
BRAF Rn {:
nkeynes@359
   732
     CHECKSLOTILLEGAL();
nkeynes@359
   733
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   734
     sh4r.in_delay_slot = 1;
nkeynes@359
   735
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   736
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   737
     return TRUE;
nkeynes@359
   738
:}
nkeynes@359
   739
BSRF Rn {:
nkeynes@359
   740
     CHECKSLOTILLEGAL();
nkeynes@359
   741
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   742
     sh4r.in_delay_slot = 1;
nkeynes@359
   743
     sh4r.pr = sh4r.pc + 4;
nkeynes@359
   744
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   745
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   746
     TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   747
     return TRUE;
nkeynes@359
   748
:}
nkeynes@359
   749
BT disp {:
nkeynes@359
   750
    CHECKSLOTILLEGAL();
nkeynes@359
   751
    if( sh4r.t ) {
nkeynes@359
   752
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   753
        sh4r.pc += disp + 4;
nkeynes@359
   754
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   755
        return TRUE;
nkeynes@359
   756
    }
nkeynes@359
   757
:}
nkeynes@359
   758
BF disp {:
nkeynes@359
   759
    CHECKSLOTILLEGAL();
nkeynes@359
   760
    if( !sh4r.t ) {
nkeynes@359
   761
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   762
        sh4r.pc += disp + 4;
nkeynes@359
   763
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   764
        return TRUE;
nkeynes@359
   765
    }
nkeynes@359
   766
:}
nkeynes@359
   767
BT/S disp {:
nkeynes@359
   768
    CHECKSLOTILLEGAL();
nkeynes@359
   769
    if( sh4r.t ) {
nkeynes@359
   770
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   771
        sh4r.in_delay_slot = 1;
nkeynes@359
   772
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   773
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   774
        sh4r.in_delay_slot = 1;
nkeynes@359
   775
        return TRUE;
nkeynes@359
   776
    }
nkeynes@359
   777
:}
nkeynes@359
   778
BF/S disp {:
nkeynes@359
   779
    CHECKSLOTILLEGAL();
nkeynes@359
   780
    if( !sh4r.t ) {
nkeynes@359
   781
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   782
        sh4r.in_delay_slot = 1;
nkeynes@359
   783
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   784
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   785
        return TRUE;
nkeynes@359
   786
    }
nkeynes@359
   787
:}
nkeynes@359
   788
BRA disp {:
nkeynes@359
   789
    CHECKSLOTILLEGAL();
nkeynes@359
   790
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   791
    sh4r.in_delay_slot = 1;
nkeynes@359
   792
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   793
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   794
    return TRUE;
nkeynes@359
   795
:}
nkeynes@359
   796
BSR disp {:
nkeynes@359
   797
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   798
    CHECKSLOTILLEGAL();
nkeynes@359
   799
    sh4r.in_delay_slot = 1;
nkeynes@359
   800
    sh4r.pr = pc + 4;
nkeynes@359
   801
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   802
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   803
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   804
    return TRUE;
nkeynes@359
   805
:}
nkeynes@359
   806
TRAPA #imm {:
nkeynes@359
   807
    CHECKSLOTILLEGAL();
nkeynes@359
   808
    sh4r.pc += 2;
nkeynes@586
   809
    sh4_raise_trap( imm );
nkeynes@586
   810
    return TRUE;
nkeynes@359
   811
:}
nkeynes@359
   812
RTS {: 
nkeynes@359
   813
    CHECKSLOTILLEGAL();
nkeynes@359
   814
    CHECKDEST( sh4r.pr );
nkeynes@359
   815
    sh4r.in_delay_slot = 1;
nkeynes@359
   816
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   817
    sh4r.new_pc = sh4r.pr;
nkeynes@359
   818
    TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@359
   819
    return TRUE;
nkeynes@359
   820
:}
nkeynes@359
   821
SLEEP {:
nkeynes@359
   822
    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@359
   823
	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@359
   824
    } else {
nkeynes@359
   825
	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@359
   826
    }
nkeynes@359
   827
    return FALSE; /* Halt CPU */
nkeynes@359
   828
:}
nkeynes@359
   829
RTE {:
nkeynes@359
   830
    CHECKPRIV();
nkeynes@359
   831
    CHECKDEST( sh4r.spc );
nkeynes@359
   832
    CHECKSLOTILLEGAL();
nkeynes@359
   833
    sh4r.in_delay_slot = 1;
nkeynes@359
   834
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   835
    sh4r.new_pc = sh4r.spc;
nkeynes@374
   836
    sh4_write_sr( sh4r.ssr );
nkeynes@359
   837
    return TRUE;
nkeynes@359
   838
:}
nkeynes@359
   839
JMP @Rn {:
nkeynes@359
   840
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   841
    CHECKSLOTILLEGAL();
nkeynes@359
   842
    sh4r.in_delay_slot = 1;
nkeynes@359
   843
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   844
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   845
    return TRUE;
nkeynes@359
   846
:}
nkeynes@359
   847
JSR @Rn {:
nkeynes@359
   848
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   849
    CHECKSLOTILLEGAL();
nkeynes@359
   850
    sh4r.in_delay_slot = 1;
nkeynes@359
   851
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   852
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   853
    sh4r.pr = pc + 4;
nkeynes@359
   854
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   855
    return TRUE;
nkeynes@359
   856
:}
nkeynes@359
   857
STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
nkeynes@359
   858
STS.L MACH, @-Rn {:
nkeynes@587
   859
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   860
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
nkeynes@359
   861
    sh4r.r[Rn] -= 4;
nkeynes@359
   862
:}
nkeynes@359
   863
STC.L SR, @-Rn {:
nkeynes@359
   864
    CHECKPRIV();
nkeynes@587
   865
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   866
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
nkeynes@359
   867
    sh4r.r[Rn] -= 4;
nkeynes@359
   868
:}
nkeynes@359
   869
LDS.L @Rm+, MACH {:
nkeynes@359
   870
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   871
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   872
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@586
   873
	(((uint64_t)tmp)<<32);
nkeynes@359
   874
    sh4r.r[Rm] += 4;
nkeynes@359
   875
:}
nkeynes@359
   876
LDC.L @Rm+, SR {:
nkeynes@359
   877
    CHECKSLOTILLEGAL();
nkeynes@359
   878
    CHECKPRIV();
nkeynes@359
   879
    CHECKWALIGN32( sh4r.r[Rm] );
nkeynes@586
   880
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@586
   881
    sh4_write_sr( tmp );
nkeynes@359
   882
    sh4r.r[Rm] +=4;
nkeynes@359
   883
:}
nkeynes@359
   884
LDS Rm, MACH {:
nkeynes@359
   885
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@359
   886
               (((uint64_t)sh4r.r[Rm])<<32);
nkeynes@359
   887
:}
nkeynes@359
   888
LDC Rm, SR {:
nkeynes@359
   889
    CHECKSLOTILLEGAL();
nkeynes@359
   890
    CHECKPRIV();
nkeynes@374
   891
    sh4_write_sr( sh4r.r[Rm] );
nkeynes@359
   892
:}
nkeynes@359
   893
LDC Rm, SGR {:
nkeynes@359
   894
    CHECKPRIV();
nkeynes@359
   895
    sh4r.sgr = sh4r.r[Rm];
nkeynes@359
   896
:}
nkeynes@359
   897
LDC.L @Rm+, SGR {:
nkeynes@359
   898
    CHECKPRIV();
nkeynes@359
   899
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   900
    MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
nkeynes@359
   901
    sh4r.r[Rm] +=4;
nkeynes@359
   902
:}
nkeynes@359
   903
STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
nkeynes@359
   904
STS.L MACL, @-Rn {:
nkeynes@587
   905
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   906
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
nkeynes@359
   907
    sh4r.r[Rn] -= 4;
nkeynes@359
   908
:}
nkeynes@359
   909
STC.L GBR, @-Rn {:
nkeynes@587
   910
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   911
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
nkeynes@359
   912
    sh4r.r[Rn] -= 4;
nkeynes@359
   913
:}
nkeynes@359
   914
LDS.L @Rm+, MACL {:
nkeynes@359
   915
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   916
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   917
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@586
   918
               (uint64_t)((uint32_t)tmp);
nkeynes@359
   919
    sh4r.r[Rm] += 4;
nkeynes@359
   920
:}
nkeynes@359
   921
LDC.L @Rm+, GBR {:
nkeynes@359
   922
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   923
    MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
nkeynes@359
   924
    sh4r.r[Rm] +=4;
nkeynes@359
   925
:}
nkeynes@359
   926
LDS Rm, MACL {:
nkeynes@359
   927
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   928
               (uint64_t)((uint32_t)(sh4r.r[Rm]));
nkeynes@359
   929
:}
nkeynes@359
   930
LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
nkeynes@359
   931
STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
nkeynes@359
   932
STS.L PR, @-Rn {:
nkeynes@587
   933
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   934
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
nkeynes@359
   935
    sh4r.r[Rn] -= 4;
nkeynes@359
   936
:}
nkeynes@359
   937
STC.L VBR, @-Rn {:
nkeynes@359
   938
    CHECKPRIV();
nkeynes@587
   939
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   940
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
nkeynes@359
   941
    sh4r.r[Rn] -= 4;
nkeynes@359
   942
:}
nkeynes@359
   943
LDS.L @Rm+, PR {:
nkeynes@359
   944
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   945
    MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
nkeynes@359
   946
    sh4r.r[Rm] += 4;
nkeynes@359
   947
:}
nkeynes@359
   948
LDC.L @Rm+, VBR {:
nkeynes@359
   949
    CHECKPRIV();
nkeynes@359
   950
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   951
    MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
nkeynes@359
   952
    sh4r.r[Rm] +=4;
nkeynes@359
   953
:}
nkeynes@359
   954
LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
nkeynes@359
   955
LDC Rm, VBR {:
nkeynes@359
   956
    CHECKPRIV();
nkeynes@359
   957
    sh4r.vbr = sh4r.r[Rm];
nkeynes@359
   958
:}
nkeynes@359
   959
STC SGR, Rn {:
nkeynes@359
   960
    CHECKPRIV();
nkeynes@359
   961
    sh4r.r[Rn] = sh4r.sgr;
nkeynes@359
   962
:}
nkeynes@359
   963
STC.L SGR, @-Rn {:
nkeynes@359
   964
    CHECKPRIV();
nkeynes@587
   965
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   966
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
nkeynes@359
   967
    sh4r.r[Rn] -= 4;
nkeynes@359
   968
:}
nkeynes@359
   969
STC.L SSR, @-Rn {:
nkeynes@359
   970
    CHECKPRIV();
nkeynes@587
   971
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   972
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
nkeynes@359
   973
    sh4r.r[Rn] -= 4;
nkeynes@359
   974
:}
nkeynes@359
   975
LDC.L @Rm+, SSR {:
nkeynes@359
   976
    CHECKPRIV();
nkeynes@359
   977
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   978
    MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
nkeynes@359
   979
    sh4r.r[Rm] +=4;
nkeynes@359
   980
:}
nkeynes@359
   981
LDC Rm, SSR {:
nkeynes@359
   982
    CHECKPRIV();
nkeynes@359
   983
    sh4r.ssr = sh4r.r[Rm];
nkeynes@359
   984
:}
nkeynes@359
   985
STC.L SPC, @-Rn {:
nkeynes@359
   986
    CHECKPRIV();
nkeynes@587
   987
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   988
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
nkeynes@359
   989
    sh4r.r[Rn] -= 4;
nkeynes@359
   990
:}
nkeynes@359
   991
LDC.L @Rm+, SPC {:
nkeynes@359
   992
    CHECKPRIV();
nkeynes@359
   993
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   994
    MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
nkeynes@359
   995
    sh4r.r[Rm] +=4;
nkeynes@359
   996
:}
nkeynes@359
   997
LDC Rm, SPC {:
nkeynes@359
   998
    CHECKPRIV();
nkeynes@359
   999
    sh4r.spc = sh4r.r[Rm];
nkeynes@359
  1000
:}
nkeynes@626
  1001
STS FPUL, Rn {: 
nkeynes@626
  1002
    CHECKFPUEN();
nkeynes@669
  1003
    sh4r.r[Rn] = FPULi; 
nkeynes@626
  1004
:}
nkeynes@359
  1005
STS.L FPUL, @-Rn {:
nkeynes@626
  1006
    CHECKFPUEN();
nkeynes@587
  1007
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@669
  1008
    MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
nkeynes@359
  1009
    sh4r.r[Rn] -= 4;
nkeynes@359
  1010
:}
nkeynes@359
  1011
LDS.L @Rm+, FPUL {:
nkeynes@626
  1012
    CHECKFPUEN();
nkeynes@359
  1013
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1014
    MEM_READ_LONG(sh4r.r[Rm], FPULi);
nkeynes@359
  1015
    sh4r.r[Rm] +=4;
nkeynes@359
  1016
:}
nkeynes@626
  1017
LDS Rm, FPUL {:
nkeynes@626
  1018
    CHECKFPUEN();
nkeynes@669
  1019
    FPULi = sh4r.r[Rm]; 
nkeynes@626
  1020
:}
nkeynes@626
  1021
STS FPSCR, Rn {: 
nkeynes@626
  1022
    CHECKFPUEN();
nkeynes@626
  1023
    sh4r.r[Rn] = sh4r.fpscr; 
nkeynes@626
  1024
:}
nkeynes@359
  1025
STS.L FPSCR, @-Rn {:
nkeynes@626
  1026
    CHECKFPUEN();
nkeynes@587
  1027
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1028
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
nkeynes@359
  1029
    sh4r.r[Rn] -= 4;
nkeynes@359
  1030
:}
nkeynes@359
  1031
LDS.L @Rm+, FPSCR {:
nkeynes@626
  1032
    CHECKFPUEN();
nkeynes@359
  1033
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1034
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
  1035
    sh4r.r[Rm] +=4;
nkeynes@669
  1036
    sh4_write_fpscr( tmp );
nkeynes@359
  1037
:}
nkeynes@374
  1038
LDS Rm, FPSCR {: 
nkeynes@626
  1039
    CHECKFPUEN();
nkeynes@669
  1040
    sh4_write_fpscr( sh4r.r[Rm] );
nkeynes@374
  1041
:}
nkeynes@359
  1042
STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
nkeynes@359
  1043
STC.L DBR, @-Rn {:
nkeynes@359
  1044
    CHECKPRIV();
nkeynes@587
  1045
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1046
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
nkeynes@359
  1047
    sh4r.r[Rn] -= 4;
nkeynes@359
  1048
:}
nkeynes@359
  1049
LDC.L @Rm+, DBR {:
nkeynes@359
  1050
    CHECKPRIV();
nkeynes@359
  1051
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1052
    MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
nkeynes@359
  1053
    sh4r.r[Rm] +=4;
nkeynes@359
  1054
:}
nkeynes@359
  1055
LDC Rm, DBR {:
nkeynes@359
  1056
    CHECKPRIV();
nkeynes@359
  1057
    sh4r.dbr = sh4r.r[Rm];
nkeynes@359
  1058
:}
nkeynes@359
  1059
STC.L Rm_BANK, @-Rn {:
nkeynes@359
  1060
    CHECKPRIV();
nkeynes@587
  1061
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1062
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
nkeynes@359
  1063
    sh4r.r[Rn] -= 4;
nkeynes@359
  1064
:}
nkeynes@359
  1065
LDC.L @Rm+, Rn_BANK {:
nkeynes@359
  1066
    CHECKPRIV();
nkeynes@359
  1067
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1068
    MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
nkeynes@359
  1069
    sh4r.r[Rm] += 4;
nkeynes@359
  1070
:}
nkeynes@359
  1071
LDC Rm, Rn_BANK {:
nkeynes@359
  1072
    CHECKPRIV();
nkeynes@359
  1073
    sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
nkeynes@359
  1074
:}
nkeynes@359
  1075
STC SR, Rn {: 
nkeynes@359
  1076
    CHECKPRIV();
nkeynes@359
  1077
    sh4r.r[Rn] = sh4_read_sr();
nkeynes@359
  1078
:}
nkeynes@359
  1079
STC GBR, Rn {:
nkeynes@359
  1080
    sh4r.r[Rn] = sh4r.gbr;
nkeynes@359
  1081
:}
nkeynes@359
  1082
STC VBR, Rn {:
nkeynes@359
  1083
    CHECKPRIV();
nkeynes@359
  1084
    sh4r.r[Rn] = sh4r.vbr;
nkeynes@359
  1085
:}
nkeynes@359
  1086
STC SSR, Rn {:
nkeynes@359
  1087
    CHECKPRIV();
nkeynes@359
  1088
    sh4r.r[Rn] = sh4r.ssr;
nkeynes@359
  1089
:}
nkeynes@359
  1090
STC SPC, Rn {:
nkeynes@359
  1091
    CHECKPRIV();
nkeynes@359
  1092
    sh4r.r[Rn] = sh4r.spc;
nkeynes@359
  1093
:}
nkeynes@359
  1094
STC Rm_BANK, Rn {:
nkeynes@359
  1095
    CHECKPRIV();
nkeynes@359
  1096
    sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
nkeynes@359
  1097
:}
nkeynes@359
  1098
nkeynes@359
  1099
FADD FRm, FRn {:
nkeynes@359
  1100
    CHECKFPUEN();
nkeynes@359
  1101
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1102
	DR(FRn) += DR(FRm);
nkeynes@359
  1103
    } else {
nkeynes@359
  1104
	FR(FRn) += FR(FRm);
nkeynes@359
  1105
    }
nkeynes@359
  1106
:}
nkeynes@359
  1107
FSUB FRm, FRn {:
nkeynes@359
  1108
    CHECKFPUEN();
nkeynes@359
  1109
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1110
	DR(FRn) -= DR(FRm);
nkeynes@359
  1111
    } else {
nkeynes@359
  1112
	FR(FRn) -= FR(FRm);
nkeynes@359
  1113
    }
nkeynes@359
  1114
:}
nkeynes@359
  1115
nkeynes@359
  1116
FMUL FRm, FRn {:
nkeynes@359
  1117
    CHECKFPUEN();
nkeynes@359
  1118
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1119
	DR(FRn) *= DR(FRm);
nkeynes@359
  1120
    } else {
nkeynes@359
  1121
	FR(FRn) *= FR(FRm);
nkeynes@359
  1122
    }
nkeynes@359
  1123
:}
nkeynes@359
  1124
nkeynes@359
  1125
FDIV FRm, FRn {:
nkeynes@359
  1126
    CHECKFPUEN();
nkeynes@359
  1127
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1128
	DR(FRn) /= DR(FRm);
nkeynes@359
  1129
    } else {
nkeynes@359
  1130
	FR(FRn) /= FR(FRm);
nkeynes@359
  1131
    }
nkeynes@359
  1132
:}
nkeynes@359
  1133
nkeynes@359
  1134
FCMP/EQ FRm, FRn {:
nkeynes@359
  1135
    CHECKFPUEN();
nkeynes@359
  1136
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1137
	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
nkeynes@359
  1138
    } else {
nkeynes@359
  1139
	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
nkeynes@359
  1140
    }
nkeynes@359
  1141
:}
nkeynes@359
  1142
nkeynes@359
  1143
FCMP/GT FRm, FRn {:
nkeynes@359
  1144
    CHECKFPUEN();
nkeynes@359
  1145
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1146
	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
nkeynes@359
  1147
    } else {
nkeynes@359
  1148
	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
nkeynes@359
  1149
    }
nkeynes@359
  1150
:}
nkeynes@359
  1151
nkeynes@359
  1152
FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
nkeynes@359
  1153
FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
nkeynes@359
  1154
FLOAT FPUL, FRn {: 
nkeynes@359
  1155
    CHECKFPUEN();
nkeynes@374
  1156
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1157
	if( FRn&1 ) { // No, really...
nkeynes@374
  1158
	    dtmp = (double)FPULi;
nkeynes@374
  1159
	    FR(FRn) = *(((float *)&dtmp)+1);
nkeynes@374
  1160
	} else {
nkeynes@374
  1161
	    DRF(FRn>>1) = (double)FPULi;
nkeynes@374
  1162
	}
nkeynes@374
  1163
    } else {
nkeynes@359
  1164
	FR(FRn) = (float)FPULi;
nkeynes@374
  1165
    }
nkeynes@359
  1166
:}
nkeynes@359
  1167
FTRC FRm, FPUL {:
nkeynes@359
  1168
    CHECKFPUEN();
nkeynes@359
  1169
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1170
	if( FRm&1 ) {
nkeynes@374
  1171
	    dtmp = 0;
nkeynes@374
  1172
	    *(((float *)&dtmp)+1) = FR(FRm);
nkeynes@374
  1173
	} else {
nkeynes@374
  1174
	    dtmp = DRF(FRm>>1);
nkeynes@374
  1175
	}
nkeynes@359
  1176
        if( dtmp >= MAX_INTF )
nkeynes@359
  1177
            FPULi = MAX_INT;
nkeynes@359
  1178
        else if( dtmp <= MIN_INTF )
nkeynes@359
  1179
            FPULi = MIN_INT;
nkeynes@359
  1180
        else 
nkeynes@359
  1181
            FPULi = (int32_t)dtmp;
nkeynes@359
  1182
    } else {
nkeynes@359
  1183
	ftmp = FR(FRm);
nkeynes@359
  1184
	if( ftmp >= MAX_INTF )
nkeynes@359
  1185
	    FPULi = MAX_INT;
nkeynes@359
  1186
	else if( ftmp <= MIN_INTF )
nkeynes@359
  1187
	    FPULi = MIN_INT;
nkeynes@359
  1188
	else
nkeynes@359
  1189
	    FPULi = (int32_t)ftmp;
nkeynes@359
  1190
    }
nkeynes@359
  1191
:}
nkeynes@359
  1192
FNEG FRn {:
nkeynes@359
  1193
    CHECKFPUEN();
nkeynes@359
  1194
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1195
	DR(FRn) = -DR(FRn);
nkeynes@359
  1196
    } else {
nkeynes@359
  1197
        FR(FRn) = -FR(FRn);
nkeynes@359
  1198
    }
nkeynes@359
  1199
:}
nkeynes@359
  1200
FABS FRn {:
nkeynes@359
  1201
    CHECKFPUEN();
nkeynes@359
  1202
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1203
	DR(FRn) = fabs(DR(FRn));
nkeynes@359
  1204
    } else {
nkeynes@359
  1205
        FR(FRn) = fabsf(FR(FRn));
nkeynes@359
  1206
    }
nkeynes@359
  1207
:}
nkeynes@359
  1208
FSQRT FRn {:
nkeynes@359
  1209
    CHECKFPUEN();
nkeynes@359
  1210
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1211
	DR(FRn) = sqrt(DR(FRn));
nkeynes@359
  1212
    } else {
nkeynes@359
  1213
        FR(FRn) = sqrtf(FR(FRn));
nkeynes@359
  1214
    }
nkeynes@359
  1215
:}
nkeynes@359
  1216
FLDI0 FRn {:
nkeynes@359
  1217
    CHECKFPUEN();
nkeynes@359
  1218
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1219
	DR(FRn) = 0.0;
nkeynes@359
  1220
    } else {
nkeynes@359
  1221
        FR(FRn) = 0.0;
nkeynes@359
  1222
    }
nkeynes@359
  1223
:}
nkeynes@359
  1224
FLDI1 FRn {:
nkeynes@359
  1225
    CHECKFPUEN();
nkeynes@359
  1226
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1227
	DR(FRn) = 1.0;
nkeynes@359
  1228
    } else {
nkeynes@359
  1229
        FR(FRn) = 1.0;
nkeynes@359
  1230
    }
nkeynes@359
  1231
:}
nkeynes@359
  1232
FMAC FR0, FRm, FRn {:
nkeynes@359
  1233
    CHECKFPUEN();
nkeynes@359
  1234
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1235
        DR(FRn) += DR(FRm)*DR(0);
nkeynes@359
  1236
    } else {
nkeynes@359
  1237
	FR(FRn) += FR(FRm)*FR(0);
nkeynes@359
  1238
    }
nkeynes@359
  1239
:}
nkeynes@374
  1240
FRCHG {: 
nkeynes@374
  1241
    CHECKFPUEN(); 
nkeynes@374
  1242
    sh4r.fpscr ^= FPSCR_FR; 
nkeynes@669
  1243
    sh4_switch_fr_banks();
nkeynes@374
  1244
:}
nkeynes@359
  1245
FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
nkeynes@359
  1246
FCNVSD FPUL, FRn {:
nkeynes@359
  1247
    CHECKFPUEN();
nkeynes@359
  1248
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1249
	DR(FRn) = (double)FPULf;
nkeynes@359
  1250
    }
nkeynes@359
  1251
:}
nkeynes@359
  1252
FCNVDS FRm, FPUL {:
nkeynes@359
  1253
    CHECKFPUEN();
nkeynes@359
  1254
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1255
	FPULf = (float)DR(FRm);
nkeynes@359
  1256
    }
nkeynes@359
  1257
:}
nkeynes@359
  1258
nkeynes@359
  1259
FSRRA FRn {:
nkeynes@359
  1260
    CHECKFPUEN();
nkeynes@359
  1261
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@1192
  1262
	FR(FRn) = 1.0/sqrt(FR(FRn));
nkeynes@359
  1263
    }
nkeynes@359
  1264
:}
nkeynes@359
  1265
FIPR FVm, FVn {:
nkeynes@359
  1266
    CHECKFPUEN();
nkeynes@359
  1267
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1268
        int tmp2 = FVn<<2;
nkeynes@359
  1269
        tmp = FVm<<2;
nkeynes@359
  1270
        FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@359
  1271
            FR(tmp+1)*FR(tmp2+1) +
nkeynes@359
  1272
            FR(tmp+2)*FR(tmp2+2) +
nkeynes@359
  1273
            FR(tmp+3)*FR(tmp2+3);
nkeynes@359
  1274
    }
nkeynes@359
  1275
:}
nkeynes@359
  1276
FSCA FPUL, FRn {:
nkeynes@359
  1277
    CHECKFPUEN();
nkeynes@359
  1278
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1279
	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
nkeynes@359
  1280
    }
nkeynes@359
  1281
:}
nkeynes@359
  1282
FTRV XMTRX, FVn {:
nkeynes@359
  1283
    CHECKFPUEN();
nkeynes@359
  1284
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1285
	sh4_ftrv((float *)&(DRF(FVn<<1)) );
nkeynes@359
  1286
    }
nkeynes@359
  1287
:}
nkeynes@359
  1288
UNDEF {:
nkeynes@359
  1289
    UNDEF(ir);
nkeynes@359
  1290
:}
nkeynes@359
  1291
%%
nkeynes@359
  1292
    sh4r.pc = sh4r.new_pc;
nkeynes@359
  1293
    sh4r.new_pc += 2;
nkeynes@927
  1294
nkeynes@359
  1295
    sh4r.in_delay_slot = 0;
nkeynes@359
  1296
    return TRUE;
nkeynes@359
  1297
}
.