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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 926:68f3e0fe02f1
prev911:2f6ba75b84d1
next927:17b6b9e245d8
author nkeynes
date Sun Dec 14 07:50:48 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Setup a 'proper' stackframe in translated blocks. This doesn't affect performance noticeably,
but does ensure that
a) The stack is aligned correctly on OS X with no extra effort, and
b) We can't mess up the stack and crash that way anymore.
Replace all PUSH/POP instructions (outside of prologue/epilogue) with ESP-rel moves to stack
local variables.
Finally merge ia32mac and ia32abi together, since they're pretty much the same now anyway (and
thereby simplifying maintenance a good deal)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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   307
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   308
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   309
 */
nkeynes@586
   310
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   311
nkeynes@590
   312
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   313
nkeynes@539
   314
/****** Import appropriate calling conventions ******/
nkeynes@675
   315
#if SIZEOF_VOID_P == 8
nkeynes@539
   316
#include "sh4/ia64abi.h"
nkeynes@675
   317
#else /* 32-bit system */
nkeynes@539
   318
#include "sh4/ia32abi.h"
nkeynes@539
   319
#endif
nkeynes@539
   320
nkeynes@901
   321
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   322
{
nkeynes@901
   323
	enter_block();
nkeynes@901
   324
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   325
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   326
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   327
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   328
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   329
    sh4_x86.block_start_pc = pc;
nkeynes@901
   330
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   331
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   332
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   333
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   334
}
nkeynes@901
   335
nkeynes@901
   336
nkeynes@593
   337
uint32_t sh4_translate_end_block_size()
nkeynes@593
   338
{
nkeynes@596
   339
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   340
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   341
    } else {
nkeynes@901
   342
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   343
    }
nkeynes@593
   344
}
nkeynes@593
   345
nkeynes@593
   346
nkeynes@590
   347
/**
nkeynes@590
   348
 * Embed a breakpoint into the generated code
nkeynes@590
   349
 */
nkeynes@586
   350
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   351
{
nkeynes@591
   352
    load_imm32( R_EAX, pc );
nkeynes@591
   353
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   355
}
nkeynes@590
   356
nkeynes@601
   357
nkeynes@601
   358
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   359
nkeynes@590
   360
/**
nkeynes@590
   361
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   362
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   363
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   364
 *
nkeynes@601
   365
 * Performs:
nkeynes@601
   366
 *   Set PC = endpc
nkeynes@601
   367
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   368
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   369
 *   Call sh4_execute_instruction
nkeynes@601
   370
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   371
 */
nkeynes@601
   372
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   373
{
nkeynes@590
   374
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   375
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   376
    
nkeynes@601
   377
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   378
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   379
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   380
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   381
nkeynes@590
   382
    call_func0( sh4_execute_instruction );    
nkeynes@601
   383
    load_spreg( R_EAX, R_PC );
nkeynes@590
   384
    if( sh4_x86.tlb_on ) {
nkeynes@590
   385
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   386
    } else {
nkeynes@590
   387
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   388
    }
nkeynes@926
   389
    exit_block();
nkeynes@590
   390
} 
nkeynes@539
   391
nkeynes@359
   392
/**
nkeynes@359
   393
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   394
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   395
 * 
nkeynes@586
   396
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   397
 *
nkeynes@359
   398
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   399
 * (eg a branch or 
nkeynes@359
   400
 */
nkeynes@590
   401
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   402
{
nkeynes@388
   403
    uint32_t ir;
nkeynes@586
   404
    /* Read instruction from icache */
nkeynes@586
   405
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   406
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   407
    
nkeynes@586
   408
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   409
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   410
    }
nkeynes@359
   411
%%
nkeynes@359
   412
/* ALU operations */
nkeynes@359
   413
ADD Rm, Rn {:
nkeynes@671
   414
    COUNT_INST(I_ADD);
nkeynes@359
   415
    load_reg( R_EAX, Rm );
nkeynes@359
   416
    load_reg( R_ECX, Rn );
nkeynes@359
   417
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   418
    store_reg( R_ECX, Rn );
nkeynes@417
   419
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   420
:}
nkeynes@359
   421
ADD #imm, Rn {:  
nkeynes@671
   422
    COUNT_INST(I_ADDI);
nkeynes@359
   423
    load_reg( R_EAX, Rn );
nkeynes@359
   424
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   425
    store_reg( R_EAX, Rn );
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   427
:}
nkeynes@359
   428
ADDC Rm, Rn {:
nkeynes@671
   429
    COUNT_INST(I_ADDC);
nkeynes@417
   430
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   431
        LDC_t();
nkeynes@417
   432
    }
nkeynes@359
   433
    load_reg( R_EAX, Rm );
nkeynes@359
   434
    load_reg( R_ECX, Rn );
nkeynes@359
   435
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   436
    store_reg( R_ECX, Rn );
nkeynes@359
   437
    SETC_t();
nkeynes@417
   438
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   439
:}
nkeynes@359
   440
ADDV Rm, Rn {:
nkeynes@671
   441
    COUNT_INST(I_ADDV);
nkeynes@359
   442
    load_reg( R_EAX, Rm );
nkeynes@359
   443
    load_reg( R_ECX, Rn );
nkeynes@359
   444
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   445
    store_reg( R_ECX, Rn );
nkeynes@359
   446
    SETO_t();
nkeynes@417
   447
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   448
:}
nkeynes@359
   449
AND Rm, Rn {:
nkeynes@671
   450
    COUNT_INST(I_AND);
nkeynes@359
   451
    load_reg( R_EAX, Rm );
nkeynes@359
   452
    load_reg( R_ECX, Rn );
nkeynes@359
   453
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   454
    store_reg( R_ECX, Rn );
nkeynes@417
   455
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   456
:}
nkeynes@359
   457
AND #imm, R0 {:  
nkeynes@671
   458
    COUNT_INST(I_ANDI);
nkeynes@359
   459
    load_reg( R_EAX, 0 );
nkeynes@359
   460
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   461
    store_reg( R_EAX, 0 );
nkeynes@417
   462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   463
:}
nkeynes@359
   464
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   465
    COUNT_INST(I_ANDB);
nkeynes@359
   466
    load_reg( R_EAX, 0 );
nkeynes@359
   467
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   468
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   469
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
   470
    MOV_r32_esp8(R_EAX, 0);
nkeynes@905
   471
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   472
    MOV_esp8_r32(0, R_EAX);
nkeynes@905
   473
    AND_imm32_r32(imm, R_EDX );
nkeynes@905
   474
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   476
:}
nkeynes@359
   477
CMP/EQ Rm, Rn {:  
nkeynes@671
   478
    COUNT_INST(I_CMPEQ);
nkeynes@359
   479
    load_reg( R_EAX, Rm );
nkeynes@359
   480
    load_reg( R_ECX, Rn );
nkeynes@359
   481
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   482
    SETE_t();
nkeynes@417
   483
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   484
:}
nkeynes@359
   485
CMP/EQ #imm, R0 {:  
nkeynes@671
   486
    COUNT_INST(I_CMPEQI);
nkeynes@359
   487
    load_reg( R_EAX, 0 );
nkeynes@359
   488
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   489
    SETE_t();
nkeynes@417
   490
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   491
:}
nkeynes@359
   492
CMP/GE Rm, Rn {:  
nkeynes@671
   493
    COUNT_INST(I_CMPGE);
nkeynes@359
   494
    load_reg( R_EAX, Rm );
nkeynes@359
   495
    load_reg( R_ECX, Rn );
nkeynes@359
   496
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   497
    SETGE_t();
nkeynes@417
   498
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/GT Rm, Rn {: 
nkeynes@671
   501
    COUNT_INST(I_CMPGT);
nkeynes@359
   502
    load_reg( R_EAX, Rm );
nkeynes@359
   503
    load_reg( R_ECX, Rn );
nkeynes@359
   504
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   505
    SETG_t();
nkeynes@417
   506
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   507
:}
nkeynes@359
   508
CMP/HI Rm, Rn {:  
nkeynes@671
   509
    COUNT_INST(I_CMPHI);
nkeynes@359
   510
    load_reg( R_EAX, Rm );
nkeynes@359
   511
    load_reg( R_ECX, Rn );
nkeynes@359
   512
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   513
    SETA_t();
nkeynes@417
   514
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   515
:}
nkeynes@359
   516
CMP/HS Rm, Rn {: 
nkeynes@671
   517
    COUNT_INST(I_CMPHS);
nkeynes@359
   518
    load_reg( R_EAX, Rm );
nkeynes@359
   519
    load_reg( R_ECX, Rn );
nkeynes@359
   520
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   521
    SETAE_t();
nkeynes@417
   522
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   523
 :}
nkeynes@359
   524
CMP/PL Rn {: 
nkeynes@671
   525
    COUNT_INST(I_CMPPL);
nkeynes@359
   526
    load_reg( R_EAX, Rn );
nkeynes@359
   527
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   528
    SETG_t();
nkeynes@417
   529
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   530
:}
nkeynes@359
   531
CMP/PZ Rn {:  
nkeynes@671
   532
    COUNT_INST(I_CMPPZ);
nkeynes@359
   533
    load_reg( R_EAX, Rn );
nkeynes@359
   534
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   535
    SETGE_t();
nkeynes@417
   536
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   537
:}
nkeynes@361
   538
CMP/STR Rm, Rn {:  
nkeynes@671
   539
    COUNT_INST(I_CMPSTR);
nkeynes@368
   540
    load_reg( R_EAX, Rm );
nkeynes@368
   541
    load_reg( R_ECX, Rn );
nkeynes@368
   542
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   543
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   544
    JE_rel8(target1);
nkeynes@669
   545
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   546
    JE_rel8(target2);
nkeynes@669
   547
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   548
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   549
    JE_rel8(target3);
nkeynes@669
   550
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   551
    JMP_TARGET(target1);
nkeynes@380
   552
    JMP_TARGET(target2);
nkeynes@380
   553
    JMP_TARGET(target3);
nkeynes@368
   554
    SETE_t();
nkeynes@417
   555
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   556
:}
nkeynes@361
   557
DIV0S Rm, Rn {:
nkeynes@671
   558
    COUNT_INST(I_DIV0S);
nkeynes@361
   559
    load_reg( R_EAX, Rm );
nkeynes@386
   560
    load_reg( R_ECX, Rn );
nkeynes@361
   561
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   562
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   563
    store_spreg( R_EAX, R_M );
nkeynes@361
   564
    store_spreg( R_ECX, R_Q );
nkeynes@361
   565
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   566
    SETNE_t();
nkeynes@417
   567
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   568
:}
nkeynes@361
   569
DIV0U {:  
nkeynes@671
   570
    COUNT_INST(I_DIV0U);
nkeynes@361
   571
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   572
    store_spreg( R_EAX, R_Q );
nkeynes@361
   573
    store_spreg( R_EAX, R_M );
nkeynes@361
   574
    store_spreg( R_EAX, R_T );
nkeynes@417
   575
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   576
:}
nkeynes@386
   577
DIV1 Rm, Rn {:
nkeynes@671
   578
    COUNT_INST(I_DIV1);
nkeynes@386
   579
    load_spreg( R_ECX, R_M );
nkeynes@386
   580
    load_reg( R_EAX, Rn );
nkeynes@417
   581
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   582
	LDC_t();
nkeynes@417
   583
    }
nkeynes@386
   584
    RCL1_r32( R_EAX );
nkeynes@386
   585
    SETC_r8( R_DL ); // Q'
nkeynes@386
   586
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   587
    JE_rel8(mqequal);
nkeynes@386
   588
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   589
    JMP_rel8(end);
nkeynes@380
   590
    JMP_TARGET(mqequal);
nkeynes@386
   591
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   592
    JMP_TARGET(end);
nkeynes@386
   593
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   594
    SETC_r8(R_AL); // tmp1
nkeynes@386
   595
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   596
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   597
    store_spreg( R_ECX, R_Q );
nkeynes@386
   598
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   599
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   600
    store_spreg( R_EAX, R_T );
nkeynes@417
   601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   602
:}
nkeynes@361
   603
DMULS.L Rm, Rn {:  
nkeynes@671
   604
    COUNT_INST(I_DMULS);
nkeynes@361
   605
    load_reg( R_EAX, Rm );
nkeynes@361
   606
    load_reg( R_ECX, Rn );
nkeynes@361
   607
    IMUL_r32(R_ECX);
nkeynes@361
   608
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   609
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   610
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   611
:}
nkeynes@361
   612
DMULU.L Rm, Rn {:  
nkeynes@671
   613
    COUNT_INST(I_DMULU);
nkeynes@361
   614
    load_reg( R_EAX, Rm );
nkeynes@361
   615
    load_reg( R_ECX, Rn );
nkeynes@361
   616
    MUL_r32(R_ECX);
nkeynes@361
   617
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   618
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   620
:}
nkeynes@359
   621
DT Rn {:  
nkeynes@671
   622
    COUNT_INST(I_DT);
nkeynes@359
   623
    load_reg( R_EAX, Rn );
nkeynes@382
   624
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   625
    store_reg( R_EAX, Rn );
nkeynes@359
   626
    SETE_t();
nkeynes@417
   627
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   628
:}
nkeynes@359
   629
EXTS.B Rm, Rn {:  
nkeynes@671
   630
    COUNT_INST(I_EXTSB);
nkeynes@359
   631
    load_reg( R_EAX, Rm );
nkeynes@359
   632
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   633
    store_reg( R_EAX, Rn );
nkeynes@359
   634
:}
nkeynes@361
   635
EXTS.W Rm, Rn {:  
nkeynes@671
   636
    COUNT_INST(I_EXTSW);
nkeynes@361
   637
    load_reg( R_EAX, Rm );
nkeynes@361
   638
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   639
    store_reg( R_EAX, Rn );
nkeynes@361
   640
:}
nkeynes@361
   641
EXTU.B Rm, Rn {:  
nkeynes@671
   642
    COUNT_INST(I_EXTUB);
nkeynes@361
   643
    load_reg( R_EAX, Rm );
nkeynes@361
   644
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   645
    store_reg( R_EAX, Rn );
nkeynes@361
   646
:}
nkeynes@361
   647
EXTU.W Rm, Rn {:  
nkeynes@671
   648
    COUNT_INST(I_EXTUW);
nkeynes@361
   649
    load_reg( R_EAX, Rm );
nkeynes@361
   650
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   651
    store_reg( R_EAX, Rn );
nkeynes@361
   652
:}
nkeynes@586
   653
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   654
    COUNT_INST(I_MACL);
nkeynes@586
   655
    if( Rm == Rn ) {
nkeynes@586
   656
	load_reg( R_EAX, Rm );
nkeynes@586
   657
	check_ralign32( R_EAX );
nkeynes@586
   658
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   659
	MOV_r32_esp8(R_EAX, 0);
nkeynes@586
   660
	load_reg( R_EAX, Rn );
nkeynes@586
   661
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@926
   662
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   663
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   664
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   665
	// adding a page-boundary check to skip the second translation
nkeynes@586
   666
    } else {
nkeynes@586
   667
	load_reg( R_EAX, Rm );
nkeynes@586
   668
	check_ralign32( R_EAX );
nkeynes@586
   669
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   670
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   671
	load_reg( R_EAX, Rn );
nkeynes@926
   672
	check_ralign32( R_EAX );
nkeynes@926
   673
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   674
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   675
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   676
    }
nkeynes@586
   677
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   678
    MOV_r32_esp8( R_EAX, 4 );
nkeynes@926
   679
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   680
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   681
    MOV_esp8_r32( 4, R_ECX );
nkeynes@586
   682
nkeynes@386
   683
    IMUL_r32( R_ECX );
nkeynes@386
   684
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   685
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   686
nkeynes@386
   687
    load_spreg( R_ECX, R_S );
nkeynes@386
   688
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   689
    JE_rel8( nosat );
nkeynes@386
   690
    call_func0( signsat48 );
nkeynes@386
   691
    JMP_TARGET( nosat );
nkeynes@417
   692
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   693
:}
nkeynes@386
   694
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   695
    COUNT_INST(I_MACW);
nkeynes@586
   696
    if( Rm == Rn ) {
nkeynes@586
   697
	load_reg( R_EAX, Rm );
nkeynes@586
   698
	check_ralign16( R_EAX );
nkeynes@586
   699
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   700
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@586
   701
	load_reg( R_EAX, Rn );
nkeynes@586
   702
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@926
   703
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   704
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   705
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   706
	// adding a page-boundary check to skip the second translation
nkeynes@586
   707
    } else {
nkeynes@586
   708
	load_reg( R_EAX, Rm );
nkeynes@586
   709
	check_ralign16( R_EAX );
nkeynes@586
   710
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   711
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   712
	load_reg( R_EAX, Rn );
nkeynes@926
   713
	check_ralign16( R_EAX );
nkeynes@926
   714
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   715
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   716
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   717
    }
nkeynes@586
   718
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   719
    MOV_r32_esp8( R_EAX, 4 );
nkeynes@926
   720
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   721
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   722
    MOV_esp8_r32( 4, R_ECX );
nkeynes@926
   723
nkeynes@386
   724
    IMUL_r32( R_ECX );
nkeynes@386
   725
    load_spreg( R_ECX, R_S );
nkeynes@386
   726
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   727
    JE_rel8( nosat );
nkeynes@386
   728
nkeynes@386
   729
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   730
    JNO_rel8( end );            // 2
nkeynes@386
   731
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   732
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   733
    JS_rel8( positive );        // 2
nkeynes@386
   734
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   735
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   736
    JMP_rel8(end2);           // 2
nkeynes@386
   737
nkeynes@386
   738
    JMP_TARGET(positive);
nkeynes@386
   739
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   740
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   741
    JMP_rel8(end3);            // 2
nkeynes@386
   742
nkeynes@386
   743
    JMP_TARGET(nosat);
nkeynes@386
   744
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   745
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   746
    JMP_TARGET(end);
nkeynes@386
   747
    JMP_TARGET(end2);
nkeynes@386
   748
    JMP_TARGET(end3);
nkeynes@417
   749
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   750
:}
nkeynes@359
   751
MOVT Rn {:  
nkeynes@671
   752
    COUNT_INST(I_MOVT);
nkeynes@359
   753
    load_spreg( R_EAX, R_T );
nkeynes@359
   754
    store_reg( R_EAX, Rn );
nkeynes@359
   755
:}
nkeynes@361
   756
MUL.L Rm, Rn {:  
nkeynes@671
   757
    COUNT_INST(I_MULL);
nkeynes@361
   758
    load_reg( R_EAX, Rm );
nkeynes@361
   759
    load_reg( R_ECX, Rn );
nkeynes@361
   760
    MUL_r32( R_ECX );
nkeynes@361
   761
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   762
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   763
:}
nkeynes@374
   764
MULS.W Rm, Rn {:
nkeynes@671
   765
    COUNT_INST(I_MULSW);
nkeynes@374
   766
    load_reg16s( R_EAX, Rm );
nkeynes@374
   767
    load_reg16s( R_ECX, Rn );
nkeynes@374
   768
    MUL_r32( R_ECX );
nkeynes@374
   769
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   770
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   771
:}
nkeynes@374
   772
MULU.W Rm, Rn {:  
nkeynes@671
   773
    COUNT_INST(I_MULUW);
nkeynes@374
   774
    load_reg16u( R_EAX, Rm );
nkeynes@374
   775
    load_reg16u( R_ECX, Rn );
nkeynes@374
   776
    MUL_r32( R_ECX );
nkeynes@374
   777
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   778
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   779
:}
nkeynes@359
   780
NEG Rm, Rn {:
nkeynes@671
   781
    COUNT_INST(I_NEG);
nkeynes@359
   782
    load_reg( R_EAX, Rm );
nkeynes@359
   783
    NEG_r32( R_EAX );
nkeynes@359
   784
    store_reg( R_EAX, Rn );
nkeynes@417
   785
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   786
:}
nkeynes@359
   787
NEGC Rm, Rn {:  
nkeynes@671
   788
    COUNT_INST(I_NEGC);
nkeynes@359
   789
    load_reg( R_EAX, Rm );
nkeynes@359
   790
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   791
    LDC_t();
nkeynes@359
   792
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   793
    store_reg( R_ECX, Rn );
nkeynes@359
   794
    SETC_t();
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   796
:}
nkeynes@359
   797
NOT Rm, Rn {:  
nkeynes@671
   798
    COUNT_INST(I_NOT);
nkeynes@359
   799
    load_reg( R_EAX, Rm );
nkeynes@359
   800
    NOT_r32( R_EAX );
nkeynes@359
   801
    store_reg( R_EAX, Rn );
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   803
:}
nkeynes@359
   804
OR Rm, Rn {:  
nkeynes@671
   805
    COUNT_INST(I_OR);
nkeynes@359
   806
    load_reg( R_EAX, Rm );
nkeynes@359
   807
    load_reg( R_ECX, Rn );
nkeynes@359
   808
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   809
    store_reg( R_ECX, Rn );
nkeynes@417
   810
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   811
:}
nkeynes@359
   812
OR #imm, R0 {:
nkeynes@671
   813
    COUNT_INST(I_ORI);
nkeynes@359
   814
    load_reg( R_EAX, 0 );
nkeynes@359
   815
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   816
    store_reg( R_EAX, 0 );
nkeynes@417
   817
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   818
:}
nkeynes@374
   819
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   820
    COUNT_INST(I_ORB);
nkeynes@374
   821
    load_reg( R_EAX, 0 );
nkeynes@374
   822
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   823
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   824
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
   825
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
   826
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   827
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
   828
    OR_imm32_r32(imm, R_EDX );
nkeynes@905
   829
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   830
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   831
:}
nkeynes@359
   832
ROTCL Rn {:
nkeynes@671
   833
    COUNT_INST(I_ROTCL);
nkeynes@359
   834
    load_reg( R_EAX, Rn );
nkeynes@417
   835
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   836
	LDC_t();
nkeynes@417
   837
    }
nkeynes@359
   838
    RCL1_r32( R_EAX );
nkeynes@359
   839
    store_reg( R_EAX, Rn );
nkeynes@359
   840
    SETC_t();
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   842
:}
nkeynes@359
   843
ROTCR Rn {:  
nkeynes@671
   844
    COUNT_INST(I_ROTCR);
nkeynes@359
   845
    load_reg( R_EAX, Rn );
nkeynes@417
   846
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   847
	LDC_t();
nkeynes@417
   848
    }
nkeynes@359
   849
    RCR1_r32( R_EAX );
nkeynes@359
   850
    store_reg( R_EAX, Rn );
nkeynes@359
   851
    SETC_t();
nkeynes@417
   852
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   853
:}
nkeynes@359
   854
ROTL Rn {:  
nkeynes@671
   855
    COUNT_INST(I_ROTL);
nkeynes@359
   856
    load_reg( R_EAX, Rn );
nkeynes@359
   857
    ROL1_r32( R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, Rn );
nkeynes@359
   859
    SETC_t();
nkeynes@417
   860
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   861
:}
nkeynes@359
   862
ROTR Rn {:  
nkeynes@671
   863
    COUNT_INST(I_ROTR);
nkeynes@359
   864
    load_reg( R_EAX, Rn );
nkeynes@359
   865
    ROR1_r32( R_EAX );
nkeynes@359
   866
    store_reg( R_EAX, Rn );
nkeynes@359
   867
    SETC_t();
nkeynes@417
   868
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   869
:}
nkeynes@359
   870
SHAD Rm, Rn {:
nkeynes@671
   871
    COUNT_INST(I_SHAD);
nkeynes@359
   872
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   873
    load_reg( R_EAX, Rn );
nkeynes@361
   874
    load_reg( R_ECX, Rm );
nkeynes@361
   875
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   876
    JGE_rel8(doshl);
nkeynes@361
   877
                    
nkeynes@361
   878
    NEG_r32( R_ECX );      // 2
nkeynes@361
   879
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   880
    JE_rel8(emptysar);     // 2
nkeynes@361
   881
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   882
    JMP_rel8(end);          // 2
nkeynes@386
   883
nkeynes@386
   884
    JMP_TARGET(emptysar);
nkeynes@386
   885
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   886
    JMP_rel8(end2);
nkeynes@382
   887
nkeynes@380
   888
    JMP_TARGET(doshl);
nkeynes@361
   889
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   890
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   891
    JMP_TARGET(end);
nkeynes@386
   892
    JMP_TARGET(end2);
nkeynes@361
   893
    store_reg( R_EAX, Rn );
nkeynes@417
   894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   895
:}
nkeynes@359
   896
SHLD Rm, Rn {:  
nkeynes@671
   897
    COUNT_INST(I_SHLD);
nkeynes@368
   898
    load_reg( R_EAX, Rn );
nkeynes@368
   899
    load_reg( R_ECX, Rm );
nkeynes@382
   900
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   901
    JGE_rel8(doshl);
nkeynes@368
   902
nkeynes@382
   903
    NEG_r32( R_ECX );      // 2
nkeynes@382
   904
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   905
    JE_rel8(emptyshr );
nkeynes@382
   906
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   907
    JMP_rel8(end);          // 2
nkeynes@386
   908
nkeynes@386
   909
    JMP_TARGET(emptyshr);
nkeynes@386
   910
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   911
    JMP_rel8(end2);
nkeynes@382
   912
nkeynes@382
   913
    JMP_TARGET(doshl);
nkeynes@382
   914
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   915
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   916
    JMP_TARGET(end);
nkeynes@386
   917
    JMP_TARGET(end2);
nkeynes@368
   918
    store_reg( R_EAX, Rn );
nkeynes@417
   919
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   920
:}
nkeynes@359
   921
SHAL Rn {: 
nkeynes@671
   922
    COUNT_INST(I_SHAL);
nkeynes@359
   923
    load_reg( R_EAX, Rn );
nkeynes@359
   924
    SHL1_r32( R_EAX );
nkeynes@397
   925
    SETC_t();
nkeynes@359
   926
    store_reg( R_EAX, Rn );
nkeynes@417
   927
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   928
:}
nkeynes@359
   929
SHAR Rn {:  
nkeynes@671
   930
    COUNT_INST(I_SHAR);
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SAR1_r32( R_EAX );
nkeynes@397
   933
    SETC_t();
nkeynes@359
   934
    store_reg( R_EAX, Rn );
nkeynes@417
   935
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   936
:}
nkeynes@359
   937
SHLL Rn {:  
nkeynes@671
   938
    COUNT_INST(I_SHLL);
nkeynes@359
   939
    load_reg( R_EAX, Rn );
nkeynes@359
   940
    SHL1_r32( R_EAX );
nkeynes@397
   941
    SETC_t();
nkeynes@359
   942
    store_reg( R_EAX, Rn );
nkeynes@417
   943
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   944
:}
nkeynes@359
   945
SHLL2 Rn {:
nkeynes@671
   946
    COUNT_INST(I_SHLL);
nkeynes@359
   947
    load_reg( R_EAX, Rn );
nkeynes@359
   948
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   949
    store_reg( R_EAX, Rn );
nkeynes@417
   950
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   951
:}
nkeynes@359
   952
SHLL8 Rn {:  
nkeynes@671
   953
    COUNT_INST(I_SHLL);
nkeynes@359
   954
    load_reg( R_EAX, Rn );
nkeynes@359
   955
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   956
    store_reg( R_EAX, Rn );
nkeynes@417
   957
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   958
:}
nkeynes@359
   959
SHLL16 Rn {:  
nkeynes@671
   960
    COUNT_INST(I_SHLL);
nkeynes@359
   961
    load_reg( R_EAX, Rn );
nkeynes@359
   962
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   963
    store_reg( R_EAX, Rn );
nkeynes@417
   964
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
:}
nkeynes@359
   966
SHLR Rn {:  
nkeynes@671
   967
    COUNT_INST(I_SHLR);
nkeynes@359
   968
    load_reg( R_EAX, Rn );
nkeynes@359
   969
    SHR1_r32( R_EAX );
nkeynes@397
   970
    SETC_t();
nkeynes@359
   971
    store_reg( R_EAX, Rn );
nkeynes@417
   972
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   973
:}
nkeynes@359
   974
SHLR2 Rn {:  
nkeynes@671
   975
    COUNT_INST(I_SHLR);
nkeynes@359
   976
    load_reg( R_EAX, Rn );
nkeynes@359
   977
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   978
    store_reg( R_EAX, Rn );
nkeynes@417
   979
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   980
:}
nkeynes@359
   981
SHLR8 Rn {:  
nkeynes@671
   982
    COUNT_INST(I_SHLR);
nkeynes@359
   983
    load_reg( R_EAX, Rn );
nkeynes@359
   984
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   985
    store_reg( R_EAX, Rn );
nkeynes@417
   986
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   987
:}
nkeynes@359
   988
SHLR16 Rn {:  
nkeynes@671
   989
    COUNT_INST(I_SHLR);
nkeynes@359
   990
    load_reg( R_EAX, Rn );
nkeynes@359
   991
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   992
    store_reg( R_EAX, Rn );
nkeynes@417
   993
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   994
:}
nkeynes@359
   995
SUB Rm, Rn {:  
nkeynes@671
   996
    COUNT_INST(I_SUB);
nkeynes@359
   997
    load_reg( R_EAX, Rm );
nkeynes@359
   998
    load_reg( R_ECX, Rn );
nkeynes@359
   999
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1000
    store_reg( R_ECX, Rn );
nkeynes@417
  1001
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1002
:}
nkeynes@359
  1003
SUBC Rm, Rn {:  
nkeynes@671
  1004
    COUNT_INST(I_SUBC);
nkeynes@359
  1005
    load_reg( R_EAX, Rm );
nkeynes@359
  1006
    load_reg( R_ECX, Rn );
nkeynes@417
  1007
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1008
	LDC_t();
nkeynes@417
  1009
    }
nkeynes@359
  1010
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1011
    store_reg( R_ECX, Rn );
nkeynes@394
  1012
    SETC_t();
nkeynes@417
  1013
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1014
:}
nkeynes@359
  1015
SUBV Rm, Rn {:  
nkeynes@671
  1016
    COUNT_INST(I_SUBV);
nkeynes@359
  1017
    load_reg( R_EAX, Rm );
nkeynes@359
  1018
    load_reg( R_ECX, Rn );
nkeynes@359
  1019
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
    store_reg( R_ECX, Rn );
nkeynes@359
  1021
    SETO_t();
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1023
:}
nkeynes@359
  1024
SWAP.B Rm, Rn {:  
nkeynes@671
  1025
    COUNT_INST(I_SWAPB);
nkeynes@359
  1026
    load_reg( R_EAX, Rm );
nkeynes@601
  1027
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1028
    store_reg( R_EAX, Rn );
nkeynes@359
  1029
:}
nkeynes@359
  1030
SWAP.W Rm, Rn {:  
nkeynes@671
  1031
    COUNT_INST(I_SWAPB);
nkeynes@359
  1032
    load_reg( R_EAX, Rm );
nkeynes@359
  1033
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1034
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1035
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1036
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1037
    store_reg( R_ECX, Rn );
nkeynes@417
  1038
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1039
:}
nkeynes@361
  1040
TAS.B @Rn {:  
nkeynes@671
  1041
    COUNT_INST(I_TASB);
nkeynes@586
  1042
    load_reg( R_EAX, Rn );
nkeynes@586
  1043
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  1044
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1045
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1046
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1047
    SETE_t();
nkeynes@905
  1048
    OR_imm8_r8( 0x80, R_DL );
nkeynes@926
  1049
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1050
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1052
:}
nkeynes@361
  1053
TST Rm, Rn {:  
nkeynes@671
  1054
    COUNT_INST(I_TST);
nkeynes@361
  1055
    load_reg( R_EAX, Rm );
nkeynes@361
  1056
    load_reg( R_ECX, Rn );
nkeynes@361
  1057
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1058
    SETE_t();
nkeynes@417
  1059
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1060
:}
nkeynes@368
  1061
TST #imm, R0 {:  
nkeynes@671
  1062
    COUNT_INST(I_TSTI);
nkeynes@368
  1063
    load_reg( R_EAX, 0 );
nkeynes@368
  1064
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1065
    SETE_t();
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1067
:}
nkeynes@368
  1068
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1069
    COUNT_INST(I_TSTB);
nkeynes@368
  1070
    load_reg( R_EAX, 0);
nkeynes@368
  1071
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1072
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1073
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1074
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1075
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1076
    SETE_t();
nkeynes@417
  1077
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1078
:}
nkeynes@359
  1079
XOR Rm, Rn {:  
nkeynes@671
  1080
    COUNT_INST(I_XOR);
nkeynes@359
  1081
    load_reg( R_EAX, Rm );
nkeynes@359
  1082
    load_reg( R_ECX, Rn );
nkeynes@359
  1083
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1084
    store_reg( R_ECX, Rn );
nkeynes@417
  1085
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1086
:}
nkeynes@359
  1087
XOR #imm, R0 {:  
nkeynes@671
  1088
    COUNT_INST(I_XORI);
nkeynes@359
  1089
    load_reg( R_EAX, 0 );
nkeynes@359
  1090
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1091
    store_reg( R_EAX, 0 );
nkeynes@417
  1092
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1093
:}
nkeynes@359
  1094
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1095
    COUNT_INST(I_XORB);
nkeynes@359
  1096
    load_reg( R_EAX, 0 );
nkeynes@359
  1097
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1098
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1099
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  1100
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1101
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@926
  1102
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1103
    XOR_imm32_r32( imm, R_EDX );
nkeynes@905
  1104
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1106
:}
nkeynes@361
  1107
XTRCT Rm, Rn {:
nkeynes@671
  1108
    COUNT_INST(I_XTRCT);
nkeynes@361
  1109
    load_reg( R_EAX, Rm );
nkeynes@394
  1110
    load_reg( R_ECX, Rn );
nkeynes@394
  1111
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1112
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1113
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1114
    store_reg( R_ECX, Rn );
nkeynes@417
  1115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1116
:}
nkeynes@359
  1117
nkeynes@359
  1118
/* Data move instructions */
nkeynes@359
  1119
MOV Rm, Rn {:  
nkeynes@671
  1120
    COUNT_INST(I_MOV);
nkeynes@359
  1121
    load_reg( R_EAX, Rm );
nkeynes@359
  1122
    store_reg( R_EAX, Rn );
nkeynes@359
  1123
:}
nkeynes@359
  1124
MOV #imm, Rn {:  
nkeynes@671
  1125
    COUNT_INST(I_MOVI);
nkeynes@359
  1126
    load_imm32( R_EAX, imm );
nkeynes@359
  1127
    store_reg( R_EAX, Rn );
nkeynes@359
  1128
:}
nkeynes@359
  1129
MOV.B Rm, @Rn {:  
nkeynes@671
  1130
    COUNT_INST(I_MOVB);
nkeynes@586
  1131
    load_reg( R_EAX, Rn );
nkeynes@586
  1132
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1133
    load_reg( R_EDX, Rm );
nkeynes@586
  1134
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1136
:}
nkeynes@359
  1137
MOV.B Rm, @-Rn {:  
nkeynes@671
  1138
    COUNT_INST(I_MOVB);
nkeynes@586
  1139
    load_reg( R_EAX, Rn );
nkeynes@586
  1140
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1141
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1142
    load_reg( R_EDX, Rm );
nkeynes@586
  1143
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1144
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1148
    COUNT_INST(I_MOVB);
nkeynes@359
  1149
    load_reg( R_EAX, 0 );
nkeynes@359
  1150
    load_reg( R_ECX, Rn );
nkeynes@586
  1151
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1152
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1153
    load_reg( R_EDX, Rm );
nkeynes@586
  1154
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1156
:}
nkeynes@359
  1157
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1158
    COUNT_INST(I_MOVB);
nkeynes@586
  1159
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1160
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1161
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1162
    load_reg( R_EDX, 0 );
nkeynes@586
  1163
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1165
:}
nkeynes@359
  1166
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1167
    COUNT_INST(I_MOVB);
nkeynes@586
  1168
    load_reg( R_EAX, Rn );
nkeynes@586
  1169
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1170
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1171
    load_reg( R_EDX, 0 );
nkeynes@586
  1172
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1174
:}
nkeynes@359
  1175
MOV.B @Rm, Rn {:  
nkeynes@671
  1176
    COUNT_INST(I_MOVB);
nkeynes@586
  1177
    load_reg( R_EAX, Rm );
nkeynes@586
  1178
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1179
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1180
    store_reg( R_EAX, Rn );
nkeynes@417
  1181
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1182
:}
nkeynes@359
  1183
MOV.B @Rm+, Rn {:  
nkeynes@671
  1184
    COUNT_INST(I_MOVB);
nkeynes@586
  1185
    load_reg( R_EAX, Rm );
nkeynes@586
  1186
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1187
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1188
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1189
    store_reg( R_EAX, Rn );
nkeynes@417
  1190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
:}
nkeynes@359
  1192
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1193
    COUNT_INST(I_MOVB);
nkeynes@359
  1194
    load_reg( R_EAX, 0 );
nkeynes@359
  1195
    load_reg( R_ECX, Rm );
nkeynes@586
  1196
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1197
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1198
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1199
    store_reg( R_EAX, Rn );
nkeynes@417
  1200
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1201
:}
nkeynes@359
  1202
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1203
    COUNT_INST(I_MOVB);
nkeynes@586
  1204
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1205
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1206
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1207
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1208
    store_reg( R_EAX, 0 );
nkeynes@417
  1209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1210
:}
nkeynes@359
  1211
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1212
    COUNT_INST(I_MOVB);
nkeynes@586
  1213
    load_reg( R_EAX, Rm );
nkeynes@586
  1214
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1215
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1216
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1217
    store_reg( R_EAX, 0 );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1219
:}
nkeynes@374
  1220
MOV.L Rm, @Rn {:
nkeynes@671
  1221
    COUNT_INST(I_MOVL);
nkeynes@586
  1222
    load_reg( R_EAX, Rn );
nkeynes@586
  1223
    check_walign32(R_EAX);
nkeynes@586
  1224
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1225
    load_reg( R_EDX, Rm );
nkeynes@586
  1226
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1227
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1228
:}
nkeynes@361
  1229
MOV.L Rm, @-Rn {:  
nkeynes@671
  1230
    COUNT_INST(I_MOVL);
nkeynes@586
  1231
    load_reg( R_EAX, Rn );
nkeynes@586
  1232
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1233
    check_walign32( R_EAX );
nkeynes@586
  1234
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1235
    load_reg( R_EDX, Rm );
nkeynes@586
  1236
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1237
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1238
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1239
:}
nkeynes@361
  1240
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1241
    COUNT_INST(I_MOVL);
nkeynes@361
  1242
    load_reg( R_EAX, 0 );
nkeynes@361
  1243
    load_reg( R_ECX, Rn );
nkeynes@586
  1244
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1245
    check_walign32( R_EAX );
nkeynes@586
  1246
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1247
    load_reg( R_EDX, Rm );
nkeynes@586
  1248
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1250
:}
nkeynes@361
  1251
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1252
    COUNT_INST(I_MOVL);
nkeynes@586
  1253
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1254
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1255
    check_walign32( R_EAX );
nkeynes@586
  1256
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1257
    load_reg( R_EDX, 0 );
nkeynes@586
  1258
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1260
:}
nkeynes@361
  1261
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1262
    COUNT_INST(I_MOVL);
nkeynes@586
  1263
    load_reg( R_EAX, Rn );
nkeynes@586
  1264
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1265
    check_walign32( R_EAX );
nkeynes@586
  1266
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1267
    load_reg( R_EDX, Rm );
nkeynes@586
  1268
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1269
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1270
:}
nkeynes@361
  1271
MOV.L @Rm, Rn {:  
nkeynes@671
  1272
    COUNT_INST(I_MOVL);
nkeynes@586
  1273
    load_reg( R_EAX, Rm );
nkeynes@586
  1274
    check_ralign32( R_EAX );
nkeynes@586
  1275
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1276
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1277
    store_reg( R_EAX, Rn );
nkeynes@417
  1278
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1279
:}
nkeynes@361
  1280
MOV.L @Rm+, Rn {:  
nkeynes@671
  1281
    COUNT_INST(I_MOVL);
nkeynes@361
  1282
    load_reg( R_EAX, Rm );
nkeynes@382
  1283
    check_ralign32( R_EAX );
nkeynes@586
  1284
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1285
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1286
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1287
    store_reg( R_EAX, Rn );
nkeynes@417
  1288
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1289
:}
nkeynes@361
  1290
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1291
    COUNT_INST(I_MOVL);
nkeynes@361
  1292
    load_reg( R_EAX, 0 );
nkeynes@361
  1293
    load_reg( R_ECX, Rm );
nkeynes@586
  1294
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1295
    check_ralign32( R_EAX );
nkeynes@586
  1296
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1297
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1298
    store_reg( R_EAX, Rn );
nkeynes@417
  1299
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1300
:}
nkeynes@361
  1301
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1302
    COUNT_INST(I_MOVL);
nkeynes@586
  1303
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1304
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1305
    check_ralign32( R_EAX );
nkeynes@586
  1306
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1307
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1308
    store_reg( R_EAX, 0 );
nkeynes@417
  1309
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1310
:}
nkeynes@361
  1311
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1312
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1313
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1314
	SLOTILLEGAL();
nkeynes@374
  1315
    } else {
nkeynes@388
  1316
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1317
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1318
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1319
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1320
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1321
nkeynes@586
  1322
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1323
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1324
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1325
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1326
	    // behaviour though.
nkeynes@586
  1327
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1328
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1329
	} else {
nkeynes@586
  1330
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1331
	    // different virtual address than the translation was done with,
nkeynes@586
  1332
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1333
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1334
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1335
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1336
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1337
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1338
	}
nkeynes@382
  1339
	store_reg( R_EAX, Rn );
nkeynes@374
  1340
    }
nkeynes@361
  1341
:}
nkeynes@361
  1342
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1343
    COUNT_INST(I_MOVL);
nkeynes@586
  1344
    load_reg( R_EAX, Rm );
nkeynes@586
  1345
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1346
    check_ralign32( R_EAX );
nkeynes@586
  1347
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1348
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1349
    store_reg( R_EAX, Rn );
nkeynes@417
  1350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1351
:}
nkeynes@361
  1352
MOV.W Rm, @Rn {:  
nkeynes@671
  1353
    COUNT_INST(I_MOVW);
nkeynes@586
  1354
    load_reg( R_EAX, Rn );
nkeynes@586
  1355
    check_walign16( R_EAX );
nkeynes@586
  1356
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1357
    load_reg( R_EDX, Rm );
nkeynes@586
  1358
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1359
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1360
:}
nkeynes@361
  1361
MOV.W Rm, @-Rn {:  
nkeynes@671
  1362
    COUNT_INST(I_MOVW);
nkeynes@586
  1363
    load_reg( R_EAX, Rn );
nkeynes@586
  1364
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1365
    check_walign16( R_EAX );
nkeynes@586
  1366
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1367
    load_reg( R_EDX, Rm );
nkeynes@586
  1368
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1369
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1370
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1371
:}
nkeynes@361
  1372
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1373
    COUNT_INST(I_MOVW);
nkeynes@361
  1374
    load_reg( R_EAX, 0 );
nkeynes@361
  1375
    load_reg( R_ECX, Rn );
nkeynes@586
  1376
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1377
    check_walign16( R_EAX );
nkeynes@586
  1378
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1379
    load_reg( R_EDX, Rm );
nkeynes@586
  1380
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1382
:}
nkeynes@361
  1383
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1384
    COUNT_INST(I_MOVW);
nkeynes@586
  1385
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1386
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1387
    check_walign16( R_EAX );
nkeynes@586
  1388
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1389
    load_reg( R_EDX, 0 );
nkeynes@586
  1390
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1392
:}
nkeynes@361
  1393
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1394
    COUNT_INST(I_MOVW);
nkeynes@586
  1395
    load_reg( R_EAX, Rn );
nkeynes@586
  1396
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1397
    check_walign16( R_EAX );
nkeynes@586
  1398
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1399
    load_reg( R_EDX, 0 );
nkeynes@586
  1400
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1402
:}
nkeynes@361
  1403
MOV.W @Rm, Rn {:  
nkeynes@671
  1404
    COUNT_INST(I_MOVW);
nkeynes@586
  1405
    load_reg( R_EAX, Rm );
nkeynes@586
  1406
    check_ralign16( R_EAX );
nkeynes@586
  1407
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1408
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1409
    store_reg( R_EAX, Rn );
nkeynes@417
  1410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1411
:}
nkeynes@361
  1412
MOV.W @Rm+, Rn {:  
nkeynes@671
  1413
    COUNT_INST(I_MOVW);
nkeynes@361
  1414
    load_reg( R_EAX, Rm );
nkeynes@374
  1415
    check_ralign16( R_EAX );
nkeynes@586
  1416
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1417
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1418
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1419
    store_reg( R_EAX, Rn );
nkeynes@417
  1420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1421
:}
nkeynes@361
  1422
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1423
    COUNT_INST(I_MOVW);
nkeynes@361
  1424
    load_reg( R_EAX, 0 );
nkeynes@361
  1425
    load_reg( R_ECX, Rm );
nkeynes@586
  1426
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1427
    check_ralign16( R_EAX );
nkeynes@586
  1428
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1429
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1430
    store_reg( R_EAX, Rn );
nkeynes@417
  1431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1432
:}
nkeynes@361
  1433
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1434
    COUNT_INST(I_MOVW);
nkeynes@586
  1435
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1436
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1437
    check_ralign16( R_EAX );
nkeynes@586
  1438
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1439
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1440
    store_reg( R_EAX, 0 );
nkeynes@417
  1441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1442
:}
nkeynes@361
  1443
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1444
    COUNT_INST(I_MOVW);
nkeynes@374
  1445
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1446
	SLOTILLEGAL();
nkeynes@374
  1447
    } else {
nkeynes@586
  1448
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1449
	uint32_t target = pc + disp + 4;
nkeynes@586
  1450
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1451
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1452
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1453
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1454
	} else {
nkeynes@586
  1455
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1456
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1457
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1458
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1459
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1460
	}
nkeynes@374
  1461
	store_reg( R_EAX, Rn );
nkeynes@374
  1462
    }
nkeynes@361
  1463
:}
nkeynes@361
  1464
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1465
    COUNT_INST(I_MOVW);
nkeynes@586
  1466
    load_reg( R_EAX, Rm );
nkeynes@586
  1467
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1468
    check_ralign16( R_EAX );
nkeynes@586
  1469
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1470
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1471
    store_reg( R_EAX, 0 );
nkeynes@417
  1472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1473
:}
nkeynes@361
  1474
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1475
    COUNT_INST(I_MOVA);
nkeynes@374
  1476
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1477
	SLOTILLEGAL();
nkeynes@374
  1478
    } else {
nkeynes@586
  1479
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1480
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1481
	store_reg( R_ECX, 0 );
nkeynes@586
  1482
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1483
    }
nkeynes@361
  1484
:}
nkeynes@361
  1485
MOVCA.L R0, @Rn {:  
nkeynes@671
  1486
    COUNT_INST(I_MOVCA);
nkeynes@586
  1487
    load_reg( R_EAX, Rn );
nkeynes@586
  1488
    check_walign32( R_EAX );
nkeynes@586
  1489
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1490
    load_reg( R_EDX, 0 );
nkeynes@586
  1491
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1492
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1493
:}
nkeynes@359
  1494
nkeynes@359
  1495
/* Control transfer instructions */
nkeynes@374
  1496
BF disp {:
nkeynes@671
  1497
    COUNT_INST(I_BF);
nkeynes@374
  1498
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1499
	SLOTILLEGAL();
nkeynes@374
  1500
    } else {
nkeynes@586
  1501
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1502
	JT_rel8( nottaken );
nkeynes@586
  1503
	exit_block_rel(target, pc+2 );
nkeynes@380
  1504
	JMP_TARGET(nottaken);
nkeynes@408
  1505
	return 2;
nkeynes@374
  1506
    }
nkeynes@374
  1507
:}
nkeynes@374
  1508
BF/S disp {:
nkeynes@671
  1509
    COUNT_INST(I_BFS);
nkeynes@374
  1510
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1511
	SLOTILLEGAL();
nkeynes@374
  1512
    } else {
nkeynes@590
  1513
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1514
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1515
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1516
	    JT_rel8(nottaken);
nkeynes@601
  1517
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1518
	    JMP_TARGET(nottaken);
nkeynes@601
  1519
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1520
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1521
	    exit_block_emu(pc+2);
nkeynes@601
  1522
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1523
	    return 2;
nkeynes@601
  1524
	} else {
nkeynes@601
  1525
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1526
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1527
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1528
	    }
nkeynes@601
  1529
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1530
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1531
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1532
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1533
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1534
	    
nkeynes@601
  1535
	    // not taken
nkeynes@601
  1536
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1537
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1538
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1539
	    return 4;
nkeynes@417
  1540
	}
nkeynes@374
  1541
    }
nkeynes@374
  1542
:}
nkeynes@374
  1543
BRA disp {:  
nkeynes@671
  1544
    COUNT_INST(I_BRA);
nkeynes@374
  1545
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1546
	SLOTILLEGAL();
nkeynes@374
  1547
    } else {
nkeynes@590
  1548
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1549
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1550
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1551
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1552
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1553
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1554
	    exit_block_emu(pc+2);
nkeynes@601
  1555
	    return 2;
nkeynes@601
  1556
	} else {
nkeynes@601
  1557
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1558
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1559
	    return 4;
nkeynes@601
  1560
	}
nkeynes@374
  1561
    }
nkeynes@374
  1562
:}
nkeynes@374
  1563
BRAF Rn {:  
nkeynes@671
  1564
    COUNT_INST(I_BRAF);
nkeynes@374
  1565
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1566
	SLOTILLEGAL();
nkeynes@374
  1567
    } else {
nkeynes@590
  1568
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1569
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1570
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1571
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1572
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1573
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1574
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1575
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1576
	    exit_block_emu(pc+2);
nkeynes@601
  1577
	    return 2;
nkeynes@601
  1578
	} else {
nkeynes@601
  1579
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1580
	    exit_block_newpcset(pc+2);
nkeynes@601
  1581
	    return 4;
nkeynes@601
  1582
	}
nkeynes@374
  1583
    }
nkeynes@374
  1584
:}
nkeynes@374
  1585
BSR disp {:  
nkeynes@671
  1586
    COUNT_INST(I_BSR);
nkeynes@374
  1587
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1588
	SLOTILLEGAL();
nkeynes@374
  1589
    } else {
nkeynes@590
  1590
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1591
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1592
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1593
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1594
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1595
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1596
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1597
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1598
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1599
	    exit_block_emu(pc+2);
nkeynes@601
  1600
	    return 2;
nkeynes@601
  1601
	} else {
nkeynes@601
  1602
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1603
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1604
	    return 4;
nkeynes@601
  1605
	}
nkeynes@374
  1606
    }
nkeynes@374
  1607
:}
nkeynes@374
  1608
BSRF Rn {:  
nkeynes@671
  1609
    COUNT_INST(I_BSRF);
nkeynes@374
  1610
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1611
	SLOTILLEGAL();
nkeynes@374
  1612
    } else {
nkeynes@590
  1613
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1614
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1615
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1616
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1617
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1618
nkeynes@601
  1619
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1620
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1621
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1622
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1623
	    exit_block_emu(pc+2);
nkeynes@601
  1624
	    return 2;
nkeynes@601
  1625
	} else {
nkeynes@601
  1626
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1627
	    exit_block_newpcset(pc+2);
nkeynes@601
  1628
	    return 4;
nkeynes@601
  1629
	}
nkeynes@374
  1630
    }
nkeynes@374
  1631
:}
nkeynes@374
  1632
BT disp {:
nkeynes@671
  1633
    COUNT_INST(I_BT);
nkeynes@374
  1634
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1635
	SLOTILLEGAL();
nkeynes@374
  1636
    } else {
nkeynes@586
  1637
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1638
	JF_rel8( nottaken );
nkeynes@586
  1639
	exit_block_rel(target, pc+2 );
nkeynes@380
  1640
	JMP_TARGET(nottaken);
nkeynes@408
  1641
	return 2;
nkeynes@374
  1642
    }
nkeynes@374
  1643
:}
nkeynes@374
  1644
BT/S disp {:
nkeynes@671
  1645
    COUNT_INST(I_BTS);
nkeynes@374
  1646
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1647
	SLOTILLEGAL();
nkeynes@374
  1648
    } else {
nkeynes@590
  1649
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1650
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1651
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1652
	    JF_rel8(nottaken);
nkeynes@601
  1653
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1654
	    JMP_TARGET(nottaken);
nkeynes@601
  1655
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1656
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1657
	    exit_block_emu(pc+2);
nkeynes@601
  1658
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1659
	    return 2;
nkeynes@601
  1660
	} else {
nkeynes@601
  1661
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1662
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1663
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1664
	    }
nkeynes@601
  1665
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1666
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1667
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1668
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1669
	    // not taken
nkeynes@601
  1670
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1671
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1672
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1673
	    return 4;
nkeynes@417
  1674
	}
nkeynes@374
  1675
    }
nkeynes@374
  1676
:}
nkeynes@374
  1677
JMP @Rn {:  
nkeynes@671
  1678
    COUNT_INST(I_JMP);
nkeynes@374
  1679
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1680
	SLOTILLEGAL();
nkeynes@374
  1681
    } else {
nkeynes@408
  1682
	load_reg( R_ECX, Rn );
nkeynes@590
  1683
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1684
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1685
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1686
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1687
	    exit_block_emu(pc+2);
nkeynes@601
  1688
	    return 2;
nkeynes@601
  1689
	} else {
nkeynes@601
  1690
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1691
	    exit_block_newpcset(pc+2);
nkeynes@601
  1692
	    return 4;
nkeynes@601
  1693
	}
nkeynes@374
  1694
    }
nkeynes@374
  1695
:}
nkeynes@374
  1696
JSR @Rn {:  
nkeynes@671
  1697
    COUNT_INST(I_JSR);
nkeynes@374
  1698
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1699
	SLOTILLEGAL();
nkeynes@374
  1700
    } else {
nkeynes@590
  1701
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1702
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1703
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1704
	load_reg( R_ECX, Rn );
nkeynes@590
  1705
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1706
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1707
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1708
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1709
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1710
	    exit_block_emu(pc+2);
nkeynes@601
  1711
	    return 2;
nkeynes@601
  1712
	} else {
nkeynes@601
  1713
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1714
	    exit_block_newpcset(pc+2);
nkeynes@601
  1715
	    return 4;
nkeynes@601
  1716
	}
nkeynes@374
  1717
    }
nkeynes@374
  1718
:}
nkeynes@374
  1719
RTE {:  
nkeynes@671
  1720
    COUNT_INST(I_RTE);
nkeynes@374
  1721
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1722
	SLOTILLEGAL();
nkeynes@374
  1723
    } else {
nkeynes@408
  1724
	check_priv();
nkeynes@408
  1725
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1726
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1727
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1728
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1729
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1730
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1731
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1732
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1733
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1734
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1735
	    exit_block_emu(pc+2);
nkeynes@601
  1736
	    return 2;
nkeynes@601
  1737
	} else {
nkeynes@601
  1738
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1739
	    exit_block_newpcset(pc+2);
nkeynes@601
  1740
	    return 4;
nkeynes@601
  1741
	}
nkeynes@374
  1742
    }
nkeynes@374
  1743
:}
nkeynes@374
  1744
RTS {:  
nkeynes@671
  1745
    COUNT_INST(I_RTS);
nkeynes@374
  1746
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1747
	SLOTILLEGAL();
nkeynes@374
  1748
    } else {
nkeynes@408
  1749
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1750
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1751
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1752
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1753
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1754
	    exit_block_emu(pc+2);
nkeynes@601
  1755
	    return 2;
nkeynes@601
  1756
	} else {
nkeynes@601
  1757
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1758
	    exit_block_newpcset(pc+2);
nkeynes@601
  1759
	    return 4;
nkeynes@601
  1760
	}
nkeynes@374
  1761
    }
nkeynes@374
  1762
:}
nkeynes@374
  1763
TRAPA #imm {:  
nkeynes@671
  1764
    COUNT_INST(I_TRAPA);
nkeynes@374
  1765
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1766
	SLOTILLEGAL();
nkeynes@374
  1767
    } else {
nkeynes@590
  1768
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1769
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1770
	load_imm32( R_EAX, imm );
nkeynes@527
  1771
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1772
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1773
	exit_block_pcset(pc);
nkeynes@409
  1774
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1775
	return 2;
nkeynes@374
  1776
    }
nkeynes@374
  1777
:}
nkeynes@374
  1778
UNDEF {:  
nkeynes@671
  1779
    COUNT_INST(I_UNDEF);
nkeynes@374
  1780
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1781
	SLOTILLEGAL();
nkeynes@374
  1782
    } else {
nkeynes@586
  1783
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1784
	return 2;
nkeynes@374
  1785
    }
nkeynes@368
  1786
:}
nkeynes@374
  1787
nkeynes@374
  1788
CLRMAC {:  
nkeynes@671
  1789
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1790
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1791
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1792
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1793
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1794
:}
nkeynes@374
  1795
CLRS {:
nkeynes@671
  1796
    COUNT_INST(I_CLRS);
nkeynes@374
  1797
    CLC();
nkeynes@374
  1798
    SETC_sh4r(R_S);
nkeynes@872
  1799
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1800
:}
nkeynes@374
  1801
CLRT {:  
nkeynes@671
  1802
    COUNT_INST(I_CLRT);
nkeynes@374
  1803
    CLC();
nkeynes@374
  1804
    SETC_t();
nkeynes@417
  1805
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1806
:}
nkeynes@374
  1807
SETS {:  
nkeynes@671
  1808
    COUNT_INST(I_SETS);
nkeynes@374
  1809
    STC();
nkeynes@374
  1810
    SETC_sh4r(R_S);
nkeynes@872
  1811
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1812
:}
nkeynes@374
  1813
SETT {:  
nkeynes@671
  1814
    COUNT_INST(I_SETT);
nkeynes@374
  1815
    STC();
nkeynes@374
  1816
    SETC_t();
nkeynes@417
  1817
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1818
:}
nkeynes@359
  1819
nkeynes@375
  1820
/* Floating point moves */
nkeynes@375
  1821
FMOV FRm, FRn {:  
nkeynes@671
  1822
    COUNT_INST(I_FMOV1);
nkeynes@377
  1823
    check_fpuen();
nkeynes@901
  1824
    if( sh4_x86.double_size ) {
nkeynes@901
  1825
        load_dr0( R_EAX, FRm );
nkeynes@901
  1826
        load_dr1( R_ECX, FRm );
nkeynes@901
  1827
        store_dr0( R_EAX, FRn );
nkeynes@901
  1828
        store_dr1( R_ECX, FRn );
nkeynes@901
  1829
    } else {
nkeynes@901
  1830
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1831
        store_fr( R_EAX, FRn );
nkeynes@901
  1832
    }
nkeynes@375
  1833
:}
nkeynes@416
  1834
FMOV FRm, @Rn {: 
nkeynes@671
  1835
    COUNT_INST(I_FMOV2);
nkeynes@586
  1836
    check_fpuen();
nkeynes@586
  1837
    load_reg( R_EAX, Rn );
nkeynes@901
  1838
    if( sh4_x86.double_size ) {
nkeynes@901
  1839
        check_walign64( R_EAX );
nkeynes@901
  1840
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1841
        load_dr0( R_EDX, FRm );
nkeynes@905
  1842
        load_dr1( R_ECX, FRm );
nkeynes@905
  1843
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1844
    } else {
nkeynes@901
  1845
        check_walign32( R_EAX );
nkeynes@901
  1846
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1847
        load_fr( R_EDX, FRm );
nkeynes@905
  1848
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1849
    }
nkeynes@417
  1850
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1851
:}
nkeynes@375
  1852
FMOV @Rm, FRn {:  
nkeynes@671
  1853
    COUNT_INST(I_FMOV5);
nkeynes@586
  1854
    check_fpuen();
nkeynes@586
  1855
    load_reg( R_EAX, Rm );
nkeynes@901
  1856
    if( sh4_x86.double_size ) {
nkeynes@901
  1857
        check_ralign64( R_EAX );
nkeynes@901
  1858
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@905
  1859
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1860
        store_dr0( R_EDX, FRn );
nkeynes@901
  1861
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1862
    } else {
nkeynes@901
  1863
        check_ralign32( R_EAX );
nkeynes@901
  1864
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1865
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1866
        store_fr( R_EAX, FRn );
nkeynes@901
  1867
    }
nkeynes@417
  1868
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1869
:}
nkeynes@377
  1870
FMOV FRm, @-Rn {:  
nkeynes@671
  1871
    COUNT_INST(I_FMOV3);
nkeynes@586
  1872
    check_fpuen();
nkeynes@586
  1873
    load_reg( R_EAX, Rn );
nkeynes@901
  1874
    if( sh4_x86.double_size ) {
nkeynes@901
  1875
        check_walign64( R_EAX );
nkeynes@901
  1876
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1877
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1878
        load_dr0( R_EDX, FRm );
nkeynes@905
  1879
        load_dr1( R_ECX, FRm );
nkeynes@901
  1880
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@905
  1881
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1882
    } else {
nkeynes@901
  1883
        check_walign32( R_EAX );
nkeynes@901
  1884
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1885
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1886
        load_fr( R_EDX, FRm );
nkeynes@901
  1887
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@905
  1888
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1889
    }
nkeynes@417
  1890
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1891
:}
nkeynes@416
  1892
FMOV @Rm+, FRn {:
nkeynes@671
  1893
    COUNT_INST(I_FMOV6);
nkeynes@586
  1894
    check_fpuen();
nkeynes@586
  1895
    load_reg( R_EAX, Rm );
nkeynes@901
  1896
    if( sh4_x86.double_size ) {
nkeynes@901
  1897
        check_ralign64( R_EAX );
nkeynes@901
  1898
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1899
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@905
  1900
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1901
        store_dr0( R_EDX, FRn );
nkeynes@901
  1902
        store_dr1( R_EAX, FRn );
nkeynes@901
  1903
    } else {
nkeynes@901
  1904
        check_ralign32( R_EAX );
nkeynes@901
  1905
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1906
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1907
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1908
        store_fr( R_EAX, FRn );
nkeynes@901
  1909
    }
nkeynes@417
  1910
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1911
:}
nkeynes@377
  1912
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1913
    COUNT_INST(I_FMOV4);
nkeynes@586
  1914
    check_fpuen();
nkeynes@586
  1915
    load_reg( R_EAX, Rn );
nkeynes@586
  1916
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1917
    if( sh4_x86.double_size ) {
nkeynes@901
  1918
        check_walign64( R_EAX );
nkeynes@901
  1919
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1920
        load_dr0( R_EDX, FRm );
nkeynes@905
  1921
        load_dr1( R_ECX, FRm );
nkeynes@905
  1922
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1923
    } else {
nkeynes@901
  1924
        check_walign32( R_EAX );
nkeynes@901
  1925
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1926
        load_fr( R_EDX, FRm );
nkeynes@905
  1927
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1928
    }
nkeynes@417
  1929
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1930
:}
nkeynes@377
  1931
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1932
    COUNT_INST(I_FMOV7);
nkeynes@586
  1933
    check_fpuen();
nkeynes@586
  1934
    load_reg( R_EAX, Rm );
nkeynes@586
  1935
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1936
    if( sh4_x86.double_size ) {
nkeynes@901
  1937
        check_ralign64( R_EAX );
nkeynes@901
  1938
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1939
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1940
        store_dr0( R_ECX, FRn );
nkeynes@901
  1941
        store_dr1( R_EAX, FRn );
nkeynes@901
  1942
    } else {
nkeynes@901
  1943
        check_ralign32( R_EAX );
nkeynes@901
  1944
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1945
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1946
        store_fr( R_EAX, FRn );
nkeynes@901
  1947
    }
nkeynes@417
  1948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1949
:}
nkeynes@377
  1950
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1951
    COUNT_INST(I_FLDI0);
nkeynes@377
  1952
    check_fpuen();
nkeynes@901
  1953
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1954
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1955
        store_fr( R_EAX, FRn );
nkeynes@901
  1956
    }
nkeynes@417
  1957
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1958
:}
nkeynes@377
  1959
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1960
    COUNT_INST(I_FLDI1);
nkeynes@377
  1961
    check_fpuen();
nkeynes@901
  1962
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1963
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1964
        store_fr( R_EAX, FRn );
nkeynes@901
  1965
    }
nkeynes@377
  1966
:}
nkeynes@377
  1967
nkeynes@377
  1968
FLOAT FPUL, FRn {:  
nkeynes@671
  1969
    COUNT_INST(I_FLOAT);
nkeynes@377
  1970
    check_fpuen();
nkeynes@377
  1971
    FILD_sh4r(R_FPUL);
nkeynes@901
  1972
    if( sh4_x86.double_prec ) {
nkeynes@901
  1973
        pop_dr( FRn );
nkeynes@901
  1974
    } else {
nkeynes@901
  1975
        pop_fr( FRn );
nkeynes@901
  1976
    }
nkeynes@377
  1977
:}
nkeynes@377
  1978
FTRC FRm, FPUL {:  
nkeynes@671
  1979
    COUNT_INST(I_FTRC);
nkeynes@377
  1980
    check_fpuen();
nkeynes@901
  1981
    if( sh4_x86.double_prec ) {
nkeynes@901
  1982
        push_dr( FRm );
nkeynes@901
  1983
    } else {
nkeynes@901
  1984
        push_fr( FRm );
nkeynes@901
  1985
    }
nkeynes@789
  1986
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1987
    FILD_r32ind( R_ECX );
nkeynes@388
  1988
    FCOMIP_st(1);
nkeynes@669
  1989
    JNA_rel8( sat );
nkeynes@789
  1990
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  1991
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1992
    FCOMIP_st(1);                   // 2
nkeynes@669
  1993
    JAE_rel8( sat2 );            // 2
nkeynes@789
  1994
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  1995
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  1996
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  1997
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1998
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1999
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2000
    JMP_rel8(end);             // 2
nkeynes@388
  2001
nkeynes@388
  2002
    JMP_TARGET(sat);
nkeynes@388
  2003
    JMP_TARGET(sat2);
nkeynes@388
  2004
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2005
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2006
    FPOP_st();
nkeynes@388
  2007
    JMP_TARGET(end);
nkeynes@417
  2008
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2009
:}
nkeynes@377
  2010
FLDS FRm, FPUL {:  
nkeynes@671
  2011
    COUNT_INST(I_FLDS);
nkeynes@377
  2012
    check_fpuen();
nkeynes@669
  2013
    load_fr( R_EAX, FRm );
nkeynes@377
  2014
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2015
:}
nkeynes@377
  2016
FSTS FPUL, FRn {:  
nkeynes@671
  2017
    COUNT_INST(I_FSTS);
nkeynes@377
  2018
    check_fpuen();
nkeynes@377
  2019
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2020
    store_fr( R_EAX, FRn );
nkeynes@377
  2021
:}
nkeynes@377
  2022
FCNVDS FRm, FPUL {:  
nkeynes@671
  2023
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2024
    check_fpuen();
nkeynes@901
  2025
    if( sh4_x86.double_prec ) {
nkeynes@901
  2026
        push_dr( FRm );
nkeynes@901
  2027
        pop_fpul();
nkeynes@901
  2028
    }
nkeynes@377
  2029
:}
nkeynes@377
  2030
FCNVSD FPUL, FRn {:  
nkeynes@671
  2031
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2032
    check_fpuen();
nkeynes@901
  2033
    if( sh4_x86.double_prec ) {
nkeynes@901
  2034
        push_fpul();
nkeynes@901
  2035
        pop_dr( FRn );
nkeynes@901
  2036
    }
nkeynes@377
  2037
:}
nkeynes@375
  2038
nkeynes@359
  2039
/* Floating point instructions */
nkeynes@374
  2040
FABS FRn {:  
nkeynes@671
  2041
    COUNT_INST(I_FABS);
nkeynes@377
  2042
    check_fpuen();
nkeynes@901
  2043
    if( sh4_x86.double_prec ) {
nkeynes@901
  2044
        push_dr(FRn);
nkeynes@901
  2045
        FABS_st0();
nkeynes@901
  2046
        pop_dr(FRn);
nkeynes@901
  2047
    } else {
nkeynes@901
  2048
        push_fr(FRn);
nkeynes@901
  2049
        FABS_st0();
nkeynes@901
  2050
        pop_fr(FRn);
nkeynes@901
  2051
    }
nkeynes@374
  2052
:}
nkeynes@377
  2053
FADD FRm, FRn {:  
nkeynes@671
  2054
    COUNT_INST(I_FADD);
nkeynes@377
  2055
    check_fpuen();
nkeynes@901
  2056
    if( sh4_x86.double_prec ) {
nkeynes@901
  2057
        push_dr(FRm);
nkeynes@901
  2058
        push_dr(FRn);
nkeynes@901
  2059
        FADDP_st(1);
nkeynes@901
  2060
        pop_dr(FRn);
nkeynes@901
  2061
    } else {
nkeynes@901
  2062
        push_fr(FRm);
nkeynes@901
  2063
        push_fr(FRn);
nkeynes@901
  2064
        FADDP_st(1);
nkeynes@901
  2065
        pop_fr(FRn);
nkeynes@901
  2066
    }
nkeynes@375
  2067
:}
nkeynes@377
  2068
FDIV FRm, FRn {:  
nkeynes@671
  2069
    COUNT_INST(I_FDIV);
nkeynes@377
  2070
    check_fpuen();
nkeynes@901
  2071
    if( sh4_x86.double_prec ) {
nkeynes@901
  2072
        push_dr(FRn);
nkeynes@901
  2073
        push_dr(FRm);
nkeynes@901
  2074
        FDIVP_st(1);
nkeynes@901
  2075
        pop_dr(FRn);
nkeynes@901
  2076
    } else {
nkeynes@901
  2077
        push_fr(FRn);
nkeynes@901
  2078
        push_fr(FRm);
nkeynes@901
  2079
        FDIVP_st(1);
nkeynes@901
  2080
        pop_fr(FRn);
nkeynes@901
  2081
    }
nkeynes@375
  2082
:}
nkeynes@375
  2083
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2084
    COUNT_INST(I_FMAC);
nkeynes@377
  2085
    check_fpuen();
nkeynes@901
  2086
    if( sh4_x86.double_prec ) {
nkeynes@901
  2087
        push_dr( 0 );
nkeynes@901
  2088
        push_dr( FRm );
nkeynes@901
  2089
        FMULP_st(1);
nkeynes@901
  2090
        push_dr( FRn );
nkeynes@901
  2091
        FADDP_st(1);
nkeynes@901
  2092
        pop_dr( FRn );
nkeynes@901
  2093
    } else {
nkeynes@901
  2094
        push_fr( 0 );
nkeynes@901
  2095
        push_fr( FRm );
nkeynes@901
  2096
        FMULP_st(1);
nkeynes@901
  2097
        push_fr( FRn );
nkeynes@901
  2098
        FADDP_st(1);
nkeynes@901
  2099
        pop_fr( FRn );
nkeynes@901
  2100
    }
nkeynes@375
  2101
:}
nkeynes@375
  2102
nkeynes@377
  2103
FMUL FRm, FRn {:  
nkeynes@671
  2104
    COUNT_INST(I_FMUL);
nkeynes@377
  2105
    check_fpuen();
nkeynes@901
  2106
    if( sh4_x86.double_prec ) {
nkeynes@901
  2107
        push_dr(FRm);
nkeynes@901
  2108
        push_dr(FRn);
nkeynes@901
  2109
        FMULP_st(1);
nkeynes@901
  2110
        pop_dr(FRn);
nkeynes@901
  2111
    } else {
nkeynes@901
  2112
        push_fr(FRm);
nkeynes@901
  2113
        push_fr(FRn);
nkeynes@901
  2114
        FMULP_st(1);
nkeynes@901
  2115
        pop_fr(FRn);
nkeynes@901
  2116
    }
nkeynes@377
  2117
:}
nkeynes@377
  2118
FNEG FRn {:  
nkeynes@671
  2119
    COUNT_INST(I_FNEG);
nkeynes@377
  2120
    check_fpuen();
nkeynes@901
  2121
    if( sh4_x86.double_prec ) {
nkeynes@901
  2122
        push_dr(FRn);
nkeynes@901
  2123
        FCHS_st0();
nkeynes@901
  2124
        pop_dr(FRn);
nkeynes@901
  2125
    } else {
nkeynes@901
  2126
        push_fr(FRn);
nkeynes@901
  2127
        FCHS_st0();
nkeynes@901
  2128
        pop_fr(FRn);
nkeynes@901
  2129
    }
nkeynes@377
  2130
:}
nkeynes@377
  2131
FSRRA FRn {:  
nkeynes@671
  2132
    COUNT_INST(I_FSRRA);
nkeynes@377
  2133
    check_fpuen();
nkeynes@901
  2134
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2135
        FLD1_st0();
nkeynes@901
  2136
        push_fr(FRn);
nkeynes@901
  2137
        FSQRT_st0();
nkeynes@901
  2138
        FDIVP_st(1);
nkeynes@901
  2139
        pop_fr(FRn);
nkeynes@901
  2140
    }
nkeynes@377
  2141
:}
nkeynes@377
  2142
FSQRT FRn {:  
nkeynes@671
  2143
    COUNT_INST(I_FSQRT);
nkeynes@377
  2144
    check_fpuen();
nkeynes@901
  2145
    if( sh4_x86.double_prec ) {
nkeynes@901
  2146
        push_dr(FRn);
nkeynes@901
  2147
        FSQRT_st0();
nkeynes@901
  2148
        pop_dr(FRn);
nkeynes@901
  2149
    } else {
nkeynes@901
  2150
        push_fr(FRn);
nkeynes@901
  2151
        FSQRT_st0();
nkeynes@901
  2152
        pop_fr(FRn);
nkeynes@901
  2153
    }
nkeynes@377
  2154
:}
nkeynes@377
  2155
FSUB FRm, FRn {:  
nkeynes@671
  2156
    COUNT_INST(I_FSUB);
nkeynes@377
  2157
    check_fpuen();
nkeynes@901
  2158
    if( sh4_x86.double_prec ) {
nkeynes@901
  2159
        push_dr(FRn);
nkeynes@901
  2160
        push_dr(FRm);
nkeynes@901
  2161
        FSUBP_st(1);
nkeynes@901
  2162
        pop_dr(FRn);
nkeynes@901
  2163
    } else {
nkeynes@901
  2164
        push_fr(FRn);
nkeynes@901
  2165
        push_fr(FRm);
nkeynes@901
  2166
        FSUBP_st(1);
nkeynes@901
  2167
        pop_fr(FRn);
nkeynes@901
  2168
    }
nkeynes@377
  2169
:}
nkeynes@377
  2170
nkeynes@377
  2171
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2172
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2173
    check_fpuen();
nkeynes@901
  2174
    if( sh4_x86.double_prec ) {
nkeynes@901
  2175
        push_dr(FRm);
nkeynes@901
  2176
        push_dr(FRn);
nkeynes@901
  2177
    } else {
nkeynes@901
  2178
        push_fr(FRm);
nkeynes@901
  2179
        push_fr(FRn);
nkeynes@901
  2180
    }
nkeynes@377
  2181
    FCOMIP_st(1);
nkeynes@377
  2182
    SETE_t();
nkeynes@377
  2183
    FPOP_st();
nkeynes@901
  2184
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2185
:}
nkeynes@377
  2186
FCMP/GT FRm, FRn {:  
nkeynes@671
  2187
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2188
    check_fpuen();
nkeynes@901
  2189
    if( sh4_x86.double_prec ) {
nkeynes@901
  2190
        push_dr(FRm);
nkeynes@901
  2191
        push_dr(FRn);
nkeynes@901
  2192
    } else {
nkeynes@901
  2193
        push_fr(FRm);
nkeynes@901
  2194
        push_fr(FRn);
nkeynes@901
  2195
    }
nkeynes@377
  2196
    FCOMIP_st(1);
nkeynes@377
  2197
    SETA_t();
nkeynes@377
  2198
    FPOP_st();
nkeynes@901
  2199
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2200
:}
nkeynes@377
  2201
nkeynes@377
  2202
FSCA FPUL, FRn {:  
nkeynes@671
  2203
    COUNT_INST(I_FSCA);
nkeynes@377
  2204
    check_fpuen();
nkeynes@901
  2205
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2206
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2207
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2208
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2209
    }
nkeynes@417
  2210
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2211
:}
nkeynes@377
  2212
FIPR FVm, FVn {:  
nkeynes@671
  2213
    COUNT_INST(I_FIPR);
nkeynes@377
  2214
    check_fpuen();
nkeynes@901
  2215
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2216
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2217
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2218
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2219
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2220
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2221
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2222
        } else {
nkeynes@904
  2223
            push_fr( FVm<<2 );
nkeynes@903
  2224
            push_fr( FVn<<2 );
nkeynes@903
  2225
            FMULP_st(1);
nkeynes@903
  2226
            push_fr( (FVm<<2)+1);
nkeynes@903
  2227
            push_fr( (FVn<<2)+1);
nkeynes@903
  2228
            FMULP_st(1);
nkeynes@903
  2229
            FADDP_st(1);
nkeynes@903
  2230
            push_fr( (FVm<<2)+2);
nkeynes@903
  2231
            push_fr( (FVn<<2)+2);
nkeynes@903
  2232
            FMULP_st(1);
nkeynes@903
  2233
            FADDP_st(1);
nkeynes@903
  2234
            push_fr( (FVm<<2)+3);
nkeynes@903
  2235
            push_fr( (FVn<<2)+3);
nkeynes@903
  2236
            FMULP_st(1);
nkeynes@903
  2237
            FADDP_st(1);
nkeynes@903
  2238
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2239
        }
nkeynes@901
  2240
    }
nkeynes@377
  2241
:}
nkeynes@377
  2242
FTRV XMTRX, FVn {:  
nkeynes@671
  2243
    COUNT_INST(I_FTRV);
nkeynes@377
  2244
    check_fpuen();
nkeynes@901
  2245
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2246
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2247
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2248
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2249
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2250
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2251
nkeynes@903
  2252
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2253
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2254
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2255
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2256
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2257
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2258
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2259
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2260
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2261
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2262
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2263
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2264
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2265
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2266
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2267
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2268
        } else {
nkeynes@903
  2269
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2270
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2271
        }
nkeynes@901
  2272
    }
nkeynes@417
  2273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2274
:}
nkeynes@377
  2275
nkeynes@377
  2276
FRCHG {:  
nkeynes@671
  2277
    COUNT_INST(I_FRCHG);
nkeynes@377
  2278
    check_fpuen();
nkeynes@377
  2279
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2280
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2281
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2282
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2284
:}
nkeynes@377
  2285
FSCHG {:  
nkeynes@671
  2286
    COUNT_INST(I_FSCHG);
nkeynes@377
  2287
    check_fpuen();
nkeynes@377
  2288
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2289
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2290
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2292
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2293
:}
nkeynes@359
  2294
nkeynes@359
  2295
/* Processor control instructions */
nkeynes@368
  2296
LDC Rm, SR {:
nkeynes@671
  2297
    COUNT_INST(I_LDCSR);
nkeynes@386
  2298
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2299
	SLOTILLEGAL();
nkeynes@386
  2300
    } else {
nkeynes@386
  2301
	check_priv();
nkeynes@386
  2302
	load_reg( R_EAX, Rm );
nkeynes@386
  2303
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2304
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2305
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2306
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2307
    }
nkeynes@368
  2308
:}
nkeynes@359
  2309
LDC Rm, GBR {: 
nkeynes@671
  2310
    COUNT_INST(I_LDC);
nkeynes@359
  2311
    load_reg( R_EAX, Rm );
nkeynes@359
  2312
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2313
:}
nkeynes@359
  2314
LDC Rm, VBR {:  
nkeynes@671
  2315
    COUNT_INST(I_LDC);
nkeynes@386
  2316
    check_priv();
nkeynes@359
  2317
    load_reg( R_EAX, Rm );
nkeynes@359
  2318
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2320
:}
nkeynes@359
  2321
LDC Rm, SSR {:  
nkeynes@671
  2322
    COUNT_INST(I_LDC);
nkeynes@386
  2323
    check_priv();
nkeynes@359
  2324
    load_reg( R_EAX, Rm );
nkeynes@359
  2325
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2326
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2327
:}
nkeynes@359
  2328
LDC Rm, SGR {:  
nkeynes@671
  2329
    COUNT_INST(I_LDC);
nkeynes@386
  2330
    check_priv();
nkeynes@359
  2331
    load_reg( R_EAX, Rm );
nkeynes@359
  2332
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2334
:}
nkeynes@359
  2335
LDC Rm, SPC {:  
nkeynes@671
  2336
    COUNT_INST(I_LDC);
nkeynes@386
  2337
    check_priv();
nkeynes@359
  2338
    load_reg( R_EAX, Rm );
nkeynes@359
  2339
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2340
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2341
:}
nkeynes@359
  2342
LDC Rm, DBR {:  
nkeynes@671
  2343
    COUNT_INST(I_LDC);
nkeynes@386
  2344
    check_priv();
nkeynes@359
  2345
    load_reg( R_EAX, Rm );
nkeynes@359
  2346
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2348
:}
nkeynes@374
  2349
LDC Rm, Rn_BANK {:  
nkeynes@671
  2350
    COUNT_INST(I_LDC);
nkeynes@386
  2351
    check_priv();
nkeynes@374
  2352
    load_reg( R_EAX, Rm );
nkeynes@374
  2353
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2355
:}
nkeynes@359
  2356
LDC.L @Rm+, GBR {:  
nkeynes@671
  2357
    COUNT_INST(I_LDCM);
nkeynes@359
  2358
    load_reg( R_EAX, Rm );
nkeynes@395
  2359
    check_ralign32( R_EAX );
nkeynes@586
  2360
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2361
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2362
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2363
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2365
:}
nkeynes@368
  2366
LDC.L @Rm+, SR {:
nkeynes@671
  2367
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2368
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2369
	SLOTILLEGAL();
nkeynes@386
  2370
    } else {
nkeynes@586
  2371
	check_priv();
nkeynes@386
  2372
	load_reg( R_EAX, Rm );
nkeynes@395
  2373
	check_ralign32( R_EAX );
nkeynes@586
  2374
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2375
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2376
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2377
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2378
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2379
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2380
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2381
    }
nkeynes@359
  2382
:}
nkeynes@359
  2383
LDC.L @Rm+, VBR {:  
nkeynes@671
  2384
    COUNT_INST(I_LDCM);
nkeynes@586
  2385
    check_priv();
nkeynes@359
  2386
    load_reg( R_EAX, Rm );
nkeynes@395
  2387
    check_ralign32( R_EAX );
nkeynes@586
  2388
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2389
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2390
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2391
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2393
:}
nkeynes@359
  2394
LDC.L @Rm+, SSR {:
nkeynes@671
  2395
    COUNT_INST(I_LDCM);
nkeynes@586
  2396
    check_priv();
nkeynes@359
  2397
    load_reg( R_EAX, Rm );
nkeynes@416
  2398
    check_ralign32( R_EAX );
nkeynes@586
  2399
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2400
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2401
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2402
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2404
:}
nkeynes@359
  2405
LDC.L @Rm+, SGR {:  
nkeynes@671
  2406
    COUNT_INST(I_LDCM);
nkeynes@586
  2407
    check_priv();
nkeynes@359
  2408
    load_reg( R_EAX, Rm );
nkeynes@395
  2409
    check_ralign32( R_EAX );
nkeynes@586
  2410
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2411
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2412
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2413
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2415
:}
nkeynes@359
  2416
LDC.L @Rm+, SPC {:  
nkeynes@671
  2417
    COUNT_INST(I_LDCM);
nkeynes@586
  2418
    check_priv();
nkeynes@359
  2419
    load_reg( R_EAX, Rm );
nkeynes@395
  2420
    check_ralign32( R_EAX );
nkeynes@586
  2421
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2422
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2423
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2424
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2425
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2426
:}
nkeynes@359
  2427
LDC.L @Rm+, DBR {:  
nkeynes@671
  2428
    COUNT_INST(I_LDCM);
nkeynes@586
  2429
    check_priv();
nkeynes@359
  2430
    load_reg( R_EAX, Rm );
nkeynes@395
  2431
    check_ralign32( R_EAX );
nkeynes@586
  2432
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2433
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2434
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2435
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2437
:}
nkeynes@359
  2438
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2439
    COUNT_INST(I_LDCM);
nkeynes@586
  2440
    check_priv();
nkeynes@374
  2441
    load_reg( R_EAX, Rm );
nkeynes@395
  2442
    check_ralign32( R_EAX );
nkeynes@586
  2443
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2444
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2445
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2446
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2448
:}
nkeynes@626
  2449
LDS Rm, FPSCR {:
nkeynes@673
  2450
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2451
    check_fpuen();
nkeynes@359
  2452
    load_reg( R_EAX, Rm );
nkeynes@669
  2453
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2455
    return 2;
nkeynes@359
  2456
:}
nkeynes@359
  2457
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2458
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2459
    check_fpuen();
nkeynes@359
  2460
    load_reg( R_EAX, Rm );
nkeynes@395
  2461
    check_ralign32( R_EAX );
nkeynes@586
  2462
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2463
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2464
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2465
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2467
    return 2;
nkeynes@359
  2468
:}
nkeynes@359
  2469
LDS Rm, FPUL {:  
nkeynes@671
  2470
    COUNT_INST(I_LDS);
nkeynes@626
  2471
    check_fpuen();
nkeynes@359
  2472
    load_reg( R_EAX, Rm );
nkeynes@359
  2473
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2474
:}
nkeynes@359
  2475
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2476
    COUNT_INST(I_LDSM);
nkeynes@626
  2477
    check_fpuen();
nkeynes@359
  2478
    load_reg( R_EAX, Rm );
nkeynes@395
  2479
    check_ralign32( R_EAX );
nkeynes@586
  2480
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2481
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2482
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2483
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2485
:}
nkeynes@359
  2486
LDS Rm, MACH {: 
nkeynes@671
  2487
    COUNT_INST(I_LDS);
nkeynes@359
  2488
    load_reg( R_EAX, Rm );
nkeynes@359
  2489
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2490
:}
nkeynes@359
  2491
LDS.L @Rm+, MACH {:  
nkeynes@671
  2492
    COUNT_INST(I_LDSM);
nkeynes@359
  2493
    load_reg( R_EAX, Rm );
nkeynes@395
  2494
    check_ralign32( R_EAX );
nkeynes@586
  2495
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2496
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2497
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2498
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2499
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2500
:}
nkeynes@359
  2501
LDS Rm, MACL {:  
nkeynes@671
  2502
    COUNT_INST(I_LDS);
nkeynes@359
  2503
    load_reg( R_EAX, Rm );
nkeynes@359
  2504
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2505
:}
nkeynes@359
  2506
LDS.L @Rm+, MACL {:  
nkeynes@671
  2507
    COUNT_INST(I_LDSM);
nkeynes@359
  2508
    load_reg( R_EAX, Rm );
nkeynes@395
  2509
    check_ralign32( R_EAX );
nkeynes@586
  2510
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2511
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2512
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2513
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2514
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2515
:}
nkeynes@359
  2516
LDS Rm, PR {:  
nkeynes@671
  2517
    COUNT_INST(I_LDS);
nkeynes@359
  2518
    load_reg( R_EAX, Rm );
nkeynes@359
  2519
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2520
:}
nkeynes@359
  2521
LDS.L @Rm+, PR {:  
nkeynes@671
  2522
    COUNT_INST(I_LDSM);
nkeynes@359
  2523
    load_reg( R_EAX, Rm );
nkeynes@395
  2524
    check_ralign32( R_EAX );
nkeynes@586
  2525
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2526
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2527
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2528
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2529
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2530
:}
nkeynes@550
  2531
LDTLB {:  
nkeynes@671
  2532
    COUNT_INST(I_LDTLB);
nkeynes@553
  2533
    call_func0( MMU_ldtlb );
nkeynes@875
  2534
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2535
:}
nkeynes@671
  2536
OCBI @Rn {:
nkeynes@671
  2537
    COUNT_INST(I_OCBI);
nkeynes@671
  2538
:}
nkeynes@671
  2539
OCBP @Rn {:
nkeynes@671
  2540
    COUNT_INST(I_OCBP);
nkeynes@671
  2541
:}
nkeynes@671
  2542
OCBWB @Rn {:
nkeynes@671
  2543
    COUNT_INST(I_OCBWB);
nkeynes@671
  2544
:}
nkeynes@374
  2545
PREF @Rn {:
nkeynes@671
  2546
    COUNT_INST(I_PREF);
nkeynes@374
  2547
    load_reg( R_EAX, Rn );
nkeynes@532
  2548
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2549
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2550
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2551
    JNE_rel8(end);
nkeynes@911
  2552
    if( sh4_x86.tlb_on ) {
nkeynes@911
  2553
    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
nkeynes@911
  2554
        TEST_r32_r32( R_EAX, R_EAX );
nkeynes@911
  2555
        JE_exc(-1);
nkeynes@911
  2556
    } else {
nkeynes@911
  2557
    	call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@911
  2558
   	}
nkeynes@380
  2559
    JMP_TARGET(end);
nkeynes@417
  2560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2561
:}
nkeynes@388
  2562
SLEEP {: 
nkeynes@671
  2563
    COUNT_INST(I_SLEEP);
nkeynes@388
  2564
    check_priv();
nkeynes@388
  2565
    call_func0( sh4_sleep );
nkeynes@417
  2566
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2567
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2568
    return 2;
nkeynes@388
  2569
:}
nkeynes@386
  2570
STC SR, Rn {:
nkeynes@671
  2571
    COUNT_INST(I_STCSR);
nkeynes@386
  2572
    check_priv();
nkeynes@386
  2573
    call_func0(sh4_read_sr);
nkeynes@386
  2574
    store_reg( R_EAX, Rn );
nkeynes@417
  2575
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2576
:}
nkeynes@359
  2577
STC GBR, Rn {:  
nkeynes@671
  2578
    COUNT_INST(I_STC);
nkeynes@359
  2579
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2580
    store_reg( R_EAX, Rn );
nkeynes@359
  2581
:}
nkeynes@359
  2582
STC VBR, Rn {:  
nkeynes@671
  2583
    COUNT_INST(I_STC);
nkeynes@386
  2584
    check_priv();
nkeynes@359
  2585
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2586
    store_reg( R_EAX, Rn );
nkeynes@417
  2587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2588
:}
nkeynes@359
  2589
STC SSR, Rn {:  
nkeynes@671
  2590
    COUNT_INST(I_STC);
nkeynes@386
  2591
    check_priv();
nkeynes@359
  2592
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2593
    store_reg( R_EAX, Rn );
nkeynes@417
  2594
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2595
:}
nkeynes@359
  2596
STC SPC, Rn {:  
nkeynes@671
  2597
    COUNT_INST(I_STC);
nkeynes@386
  2598
    check_priv();
nkeynes@359
  2599
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2600
    store_reg( R_EAX, Rn );
nkeynes@417
  2601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2602
:}
nkeynes@359
  2603
STC SGR, Rn {:  
nkeynes@671
  2604
    COUNT_INST(I_STC);
nkeynes@386
  2605
    check_priv();
nkeynes@359
  2606
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2607
    store_reg( R_EAX, Rn );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2609
:}
nkeynes@359
  2610
STC DBR, Rn {:  
nkeynes@671
  2611
    COUNT_INST(I_STC);
nkeynes@386
  2612
    check_priv();
nkeynes@359
  2613
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2614
    store_reg( R_EAX, Rn );
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
:}
nkeynes@374
  2617
STC Rm_BANK, Rn {:
nkeynes@671
  2618
    COUNT_INST(I_STC);
nkeynes@386
  2619
    check_priv();
nkeynes@374
  2620
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2621
    store_reg( R_EAX, Rn );
nkeynes@417
  2622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2623
:}
nkeynes@374
  2624
STC.L SR, @-Rn {:
nkeynes@671
  2625
    COUNT_INST(I_STCSRM);
nkeynes@586
  2626
    check_priv();
nkeynes@586
  2627
    load_reg( R_EAX, Rn );
nkeynes@586
  2628
    check_walign32( R_EAX );
nkeynes@586
  2629
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2630
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  2631
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@395
  2632
    call_func0( sh4_read_sr );
nkeynes@926
  2633
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@926
  2634
    MOV_esp8_r32( 0, R_EAX );
nkeynes@586
  2635
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@926
  2636
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2637
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2638
:}
nkeynes@359
  2639
STC.L VBR, @-Rn {:  
nkeynes@671
  2640
    COUNT_INST(I_STCM);
nkeynes@586
  2641
    check_priv();
nkeynes@586
  2642
    load_reg( R_EAX, Rn );
nkeynes@586
  2643
    check_walign32( R_EAX );
nkeynes@586
  2644
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2645
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2646
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2647
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2648
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2649
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2650
:}
nkeynes@359
  2651
STC.L SSR, @-Rn {:  
nkeynes@671
  2652
    COUNT_INST(I_STCM);
nkeynes@586
  2653
    check_priv();
nkeynes@586
  2654
    load_reg( R_EAX, Rn );
nkeynes@586
  2655
    check_walign32( R_EAX );
nkeynes@586
  2656
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2657
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2658
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2659
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2660
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2661
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2662
:}
nkeynes@416
  2663
STC.L SPC, @-Rn {:
nkeynes@671
  2664
    COUNT_INST(I_STCM);
nkeynes@586
  2665
    check_priv();
nkeynes@586
  2666
    load_reg( R_EAX, Rn );
nkeynes@586
  2667
    check_walign32( R_EAX );
nkeynes@586
  2668
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2669
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2670
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2671
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2672
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2674
:}
nkeynes@359
  2675
STC.L SGR, @-Rn {:  
nkeynes@671
  2676
    COUNT_INST(I_STCM);
nkeynes@586
  2677
    check_priv();
nkeynes@586
  2678
    load_reg( R_EAX, Rn );
nkeynes@586
  2679
    check_walign32( R_EAX );
nkeynes@586
  2680
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2681
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2682
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2683
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2684
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2686
:}
nkeynes@359
  2687
STC.L DBR, @-Rn {:  
nkeynes@671
  2688
    COUNT_INST(I_STCM);
nkeynes@586
  2689
    check_priv();
nkeynes@586
  2690
    load_reg( R_EAX, Rn );
nkeynes@586
  2691
    check_walign32( R_EAX );
nkeynes@586
  2692
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2693
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2694
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2695
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2696
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2697
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2698
:}
nkeynes@374
  2699
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2700
    COUNT_INST(I_STCM);
nkeynes@586
  2701
    check_priv();
nkeynes@586
  2702
    load_reg( R_EAX, Rn );
nkeynes@586
  2703
    check_walign32( R_EAX );
nkeynes@586
  2704
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2705
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2706
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2707
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2708
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2709
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2710
:}
nkeynes@359
  2711
STC.L GBR, @-Rn {:  
nkeynes@671
  2712
    COUNT_INST(I_STCM);
nkeynes@586
  2713
    load_reg( R_EAX, Rn );
nkeynes@586
  2714
    check_walign32( R_EAX );
nkeynes@586
  2715
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2716
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2717
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2718
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2719
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2720
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2721
:}
nkeynes@359
  2722
STS FPSCR, Rn {:  
nkeynes@673
  2723
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2724
    check_fpuen();
nkeynes@359
  2725
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2726
    store_reg( R_EAX, Rn );
nkeynes@359
  2727
:}
nkeynes@359
  2728
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2729
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2730
    check_fpuen();
nkeynes@586
  2731
    load_reg( R_EAX, Rn );
nkeynes@586
  2732
    check_walign32( R_EAX );
nkeynes@586
  2733
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2734
    MMU_TRANSLATE_WRITE( R_EAX );