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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 593:6c710c7c6835
prev591:7b9612fd2395
next596:dfc0c93d882e
author nkeynes
date Thu Jan 17 21:26:58 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix block overruns from long epilogues
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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    uint32_t recovery_posn;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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void sh4_x86_add_recovery( uint32_t pc )
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{
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    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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    xlat_recovery_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
nkeynes@586
   338
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   339
/**
nkeynes@586
   340
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   341
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   342
 */
nkeynes@586
   343
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   344
nkeynes@586
   345
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   346
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   347
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   348
nkeynes@590
   349
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   350
nkeynes@539
   351
/****** Import appropriate calling conventions ******/
nkeynes@539
   352
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   353
#include "sh4/ia64abi.h"
nkeynes@539
   354
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   355
#ifdef APPLE_BUILD
nkeynes@539
   356
#include "sh4/ia32mac.h"
nkeynes@539
   357
#else
nkeynes@539
   358
#include "sh4/ia32abi.h"
nkeynes@539
   359
#endif
nkeynes@539
   360
#endif
nkeynes@539
   361
nkeynes@593
   362
uint32_t sh4_translate_end_block_size()
nkeynes@593
   363
{
nkeynes@593
   364
    return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@593
   365
}
nkeynes@593
   366
nkeynes@593
   367
nkeynes@590
   368
/**
nkeynes@590
   369
 * Embed a breakpoint into the generated code
nkeynes@590
   370
 */
nkeynes@586
   371
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   372
{
nkeynes@591
   373
    load_imm32( R_EAX, pc );
nkeynes@591
   374
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   375
}
nkeynes@590
   376
nkeynes@590
   377
/**
nkeynes@590
   378
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@590
   379
 * can't translate (mainly page-crossing delay slots at the moment).
nkeynes@590
   380
 * Caller is responsible for setting new_pc.
nkeynes@590
   381
 */
nkeynes@590
   382
void sh4_emulator_exit( sh4vma_t endpc )
nkeynes@590
   383
{
nkeynes@590
   384
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   385
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   386
    
nkeynes@590
   387
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@590
   388
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   389
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   390
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   391
nkeynes@590
   392
    call_func0( sh4_execute_instruction );    
nkeynes@590
   393
    load_imm32( R_EAX, R_PC );
nkeynes@590
   394
    if( sh4_x86.tlb_on ) {
nkeynes@590
   395
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   396
    } else {
nkeynes@590
   397
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   398
    }
nkeynes@590
   399
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@590
   400
    POP_r32(R_EBP);
nkeynes@590
   401
    RET();
nkeynes@590
   402
} 
nkeynes@539
   403
nkeynes@359
   404
/**
nkeynes@359
   405
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   406
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   407
 * 
nkeynes@586
   408
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   409
 *
nkeynes@359
   410
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   411
 * (eg a branch or 
nkeynes@359
   412
 */
nkeynes@590
   413
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   414
{
nkeynes@388
   415
    uint32_t ir;
nkeynes@586
   416
    /* Read instruction from icache */
nkeynes@586
   417
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   418
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   419
    
nkeynes@586
   420
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   421
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   422
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   423
	 * almost certainly in a delay slot.
nkeynes@586
   424
	 *
nkeynes@586
   425
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   426
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   427
	 * small repairs to cope with the different environment).
nkeynes@586
   428
	 */
nkeynes@586
   429
nkeynes@586
   430
    if( !sh4_x86.in_delay_slot ) {
nkeynes@586
   431
	sh4_x86_add_recovery(pc);
nkeynes@388
   432
    }
nkeynes@359
   433
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   434
            case 0x0:
nkeynes@359
   435
                switch( ir&0xF ) {
nkeynes@359
   436
                    case 0x2:
nkeynes@359
   437
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   438
                            case 0x0:
nkeynes@359
   439
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   440
                                    case 0x0:
nkeynes@359
   441
                                        { /* STC SR, Rn */
nkeynes@359
   442
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   443
                                        check_priv();
nkeynes@374
   444
                                        call_func0(sh4_read_sr);
nkeynes@368
   445
                                        store_reg( R_EAX, Rn );
nkeynes@417
   446
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   447
                                        }
nkeynes@359
   448
                                        break;
nkeynes@359
   449
                                    case 0x1:
nkeynes@359
   450
                                        { /* STC GBR, Rn */
nkeynes@359
   451
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   452
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   453
                                        store_reg( R_EAX, Rn );
nkeynes@359
   454
                                        }
nkeynes@359
   455
                                        break;
nkeynes@359
   456
                                    case 0x2:
nkeynes@359
   457
                                        { /* STC VBR, Rn */
nkeynes@359
   458
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   459
                                        check_priv();
nkeynes@359
   460
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   461
                                        store_reg( R_EAX, Rn );
nkeynes@417
   462
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   463
                                        }
nkeynes@359
   464
                                        break;
nkeynes@359
   465
                                    case 0x3:
nkeynes@359
   466
                                        { /* STC SSR, Rn */
nkeynes@359
   467
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   468
                                        check_priv();
nkeynes@359
   469
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   470
                                        store_reg( R_EAX, Rn );
nkeynes@417
   471
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   472
                                        }
nkeynes@359
   473
                                        break;
nkeynes@359
   474
                                    case 0x4:
nkeynes@359
   475
                                        { /* STC SPC, Rn */
nkeynes@359
   476
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   477
                                        check_priv();
nkeynes@359
   478
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   479
                                        store_reg( R_EAX, Rn );
nkeynes@417
   480
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   481
                                        }
nkeynes@359
   482
                                        break;
nkeynes@359
   483
                                    default:
nkeynes@359
   484
                                        UNDEF();
nkeynes@359
   485
                                        break;
nkeynes@359
   486
                                }
nkeynes@359
   487
                                break;
nkeynes@359
   488
                            case 0x1:
nkeynes@359
   489
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   490
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   491
                                check_priv();
nkeynes@374
   492
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   493
                                store_reg( R_EAX, Rn );
nkeynes@417
   494
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   495
                                }
nkeynes@359
   496
                                break;
nkeynes@359
   497
                        }
nkeynes@359
   498
                        break;
nkeynes@359
   499
                    case 0x3:
nkeynes@359
   500
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   501
                            case 0x0:
nkeynes@359
   502
                                { /* BSRF Rn */
nkeynes@359
   503
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   504
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   505
                            	SLOTILLEGAL();
nkeynes@374
   506
                                } else {
nkeynes@590
   507
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   508
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   509
                            	store_spreg( R_EAX, R_PR );
nkeynes@590
   510
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   511
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   512
                            
nkeynes@417
   513
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   514
                            	sh4_translate_instruction( pc + 2 );
nkeynes@590
   515
                            	exit_block_newpcset(pc+2);
nkeynes@409
   516
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   517
                            	return 4;
nkeynes@374
   518
                                }
nkeynes@359
   519
                                }
nkeynes@359
   520
                                break;
nkeynes@359
   521
                            case 0x2:
nkeynes@359
   522
                                { /* BRAF Rn */
nkeynes@359
   523
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   524
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   525
                            	SLOTILLEGAL();
nkeynes@374
   526
                                } else {
nkeynes@590
   527
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   528
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   529
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   530
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   531
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   532
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   533
                            	sh4_translate_instruction( pc + 2 );
nkeynes@590
   534
                            	exit_block_newpcset(pc+2);
nkeynes@409
   535
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   536
                            	return 4;
nkeynes@374
   537
                                }
nkeynes@359
   538
                                }
nkeynes@359
   539
                                break;
nkeynes@359
   540
                            case 0x8:
nkeynes@359
   541
                                { /* PREF @Rn */
nkeynes@359
   542
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   543
                                load_reg( R_EAX, Rn );
nkeynes@532
   544
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   545
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   546
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
   547
                                JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
   548
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
   549
                                TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
   550
                                JE_exc(-1);
nkeynes@380
   551
                                JMP_TARGET(end);
nkeynes@417
   552
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   553
                                }
nkeynes@359
   554
                                break;
nkeynes@359
   555
                            case 0x9:
nkeynes@359
   556
                                { /* OCBI @Rn */
nkeynes@359
   557
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   558
                                }
nkeynes@359
   559
                                break;
nkeynes@359
   560
                            case 0xA:
nkeynes@359
   561
                                { /* OCBP @Rn */
nkeynes@359
   562
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   563
                                }
nkeynes@359
   564
                                break;
nkeynes@359
   565
                            case 0xB:
nkeynes@359
   566
                                { /* OCBWB @Rn */
nkeynes@359
   567
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   568
                                }
nkeynes@359
   569
                                break;
nkeynes@359
   570
                            case 0xC:
nkeynes@359
   571
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   572
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
   573
                                load_reg( R_EAX, Rn );
nkeynes@586
   574
                                check_walign32( R_EAX );
nkeynes@586
   575
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   576
                                load_reg( R_EDX, 0 );
nkeynes@586
   577
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   578
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   579
                                }
nkeynes@359
   580
                                break;
nkeynes@359
   581
                            default:
nkeynes@359
   582
                                UNDEF();
nkeynes@359
   583
                                break;
nkeynes@359
   584
                        }
nkeynes@359
   585
                        break;
nkeynes@359
   586
                    case 0x4:
nkeynes@359
   587
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   588
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   589
                        load_reg( R_EAX, 0 );
nkeynes@359
   590
                        load_reg( R_ECX, Rn );
nkeynes@586
   591
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   592
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   593
                        load_reg( R_EDX, Rm );
nkeynes@586
   594
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   595
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   596
                        }
nkeynes@359
   597
                        break;
nkeynes@359
   598
                    case 0x5:
nkeynes@359
   599
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   600
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   601
                        load_reg( R_EAX, 0 );
nkeynes@361
   602
                        load_reg( R_ECX, Rn );
nkeynes@586
   603
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   604
                        check_walign16( R_EAX );
nkeynes@586
   605
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   606
                        load_reg( R_EDX, Rm );
nkeynes@586
   607
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   608
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   609
                        }
nkeynes@359
   610
                        break;
nkeynes@359
   611
                    case 0x6:
nkeynes@359
   612
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   613
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   614
                        load_reg( R_EAX, 0 );
nkeynes@361
   615
                        load_reg( R_ECX, Rn );
nkeynes@586
   616
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   617
                        check_walign32( R_EAX );
nkeynes@586
   618
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   619
                        load_reg( R_EDX, Rm );
nkeynes@586
   620
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   621
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   622
                        }
nkeynes@359
   623
                        break;
nkeynes@359
   624
                    case 0x7:
nkeynes@359
   625
                        { /* MUL.L Rm, Rn */
nkeynes@359
   626
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   627
                        load_reg( R_EAX, Rm );
nkeynes@361
   628
                        load_reg( R_ECX, Rn );
nkeynes@361
   629
                        MUL_r32( R_ECX );
nkeynes@361
   630
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   631
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   632
                        }
nkeynes@359
   633
                        break;
nkeynes@359
   634
                    case 0x8:
nkeynes@359
   635
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   636
                            case 0x0:
nkeynes@359
   637
                                { /* CLRT */
nkeynes@374
   638
                                CLC();
nkeynes@374
   639
                                SETC_t();
nkeynes@417
   640
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   641
                                }
nkeynes@359
   642
                                break;
nkeynes@359
   643
                            case 0x1:
nkeynes@359
   644
                                { /* SETT */
nkeynes@374
   645
                                STC();
nkeynes@374
   646
                                SETC_t();
nkeynes@417
   647
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   648
                                }
nkeynes@359
   649
                                break;
nkeynes@359
   650
                            case 0x2:
nkeynes@359
   651
                                { /* CLRMAC */
nkeynes@374
   652
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   653
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   654
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   655
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   656
                                }
nkeynes@359
   657
                                break;
nkeynes@359
   658
                            case 0x3:
nkeynes@359
   659
                                { /* LDTLB */
nkeynes@553
   660
                                call_func0( MMU_ldtlb );
nkeynes@359
   661
                                }
nkeynes@359
   662
                                break;
nkeynes@359
   663
                            case 0x4:
nkeynes@359
   664
                                { /* CLRS */
nkeynes@374
   665
                                CLC();
nkeynes@374
   666
                                SETC_sh4r(R_S);
nkeynes@417
   667
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   668
                                }
nkeynes@359
   669
                                break;
nkeynes@359
   670
                            case 0x5:
nkeynes@359
   671
                                { /* SETS */
nkeynes@374
   672
                                STC();
nkeynes@374
   673
                                SETC_sh4r(R_S);
nkeynes@417
   674
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   675
                                }
nkeynes@359
   676
                                break;
nkeynes@359
   677
                            default:
nkeynes@359
   678
                                UNDEF();
nkeynes@359
   679
                                break;
nkeynes@359
   680
                        }
nkeynes@359
   681
                        break;
nkeynes@359
   682
                    case 0x9:
nkeynes@359
   683
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   684
                            case 0x0:
nkeynes@359
   685
                                { /* NOP */
nkeynes@359
   686
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   687
                                }
nkeynes@359
   688
                                break;
nkeynes@359
   689
                            case 0x1:
nkeynes@359
   690
                                { /* DIV0U */
nkeynes@361
   691
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   692
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   693
                                store_spreg( R_EAX, R_M );
nkeynes@361
   694
                                store_spreg( R_EAX, R_T );
nkeynes@417
   695
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   696
                                }
nkeynes@359
   697
                                break;
nkeynes@359
   698
                            case 0x2:
nkeynes@359
   699
                                { /* MOVT Rn */
nkeynes@359
   700
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   701
                                load_spreg( R_EAX, R_T );
nkeynes@359
   702
                                store_reg( R_EAX, Rn );
nkeynes@359
   703
                                }
nkeynes@359
   704
                                break;
nkeynes@359
   705
                            default:
nkeynes@359
   706
                                UNDEF();
nkeynes@359
   707
                                break;
nkeynes@359
   708
                        }
nkeynes@359
   709
                        break;
nkeynes@359
   710
                    case 0xA:
nkeynes@359
   711
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   712
                            case 0x0:
nkeynes@359
   713
                                { /* STS MACH, Rn */
nkeynes@359
   714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   715
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   716
                                store_reg( R_EAX, Rn );
nkeynes@359
   717
                                }
nkeynes@359
   718
                                break;
nkeynes@359
   719
                            case 0x1:
nkeynes@359
   720
                                { /* STS MACL, Rn */
nkeynes@359
   721
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   722
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   723
                                store_reg( R_EAX, Rn );
nkeynes@359
   724
                                }
nkeynes@359
   725
                                break;
nkeynes@359
   726
                            case 0x2:
nkeynes@359
   727
                                { /* STS PR, Rn */
nkeynes@359
   728
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   729
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   730
                                store_reg( R_EAX, Rn );
nkeynes@359
   731
                                }
nkeynes@359
   732
                                break;
nkeynes@359
   733
                            case 0x3:
nkeynes@359
   734
                                { /* STC SGR, Rn */
nkeynes@359
   735
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   736
                                check_priv();
nkeynes@359
   737
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   738
                                store_reg( R_EAX, Rn );
nkeynes@417
   739
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   740
                                }
nkeynes@359
   741
                                break;
nkeynes@359
   742
                            case 0x5:
nkeynes@359
   743
                                { /* STS FPUL, Rn */
nkeynes@359
   744
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   745
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   746
                                store_reg( R_EAX, Rn );
nkeynes@359
   747
                                }
nkeynes@359
   748
                                break;
nkeynes@359
   749
                            case 0x6:
nkeynes@359
   750
                                { /* STS FPSCR, Rn */
nkeynes@359
   751
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   752
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   753
                                store_reg( R_EAX, Rn );
nkeynes@359
   754
                                }
nkeynes@359
   755
                                break;
nkeynes@359
   756
                            case 0xF:
nkeynes@359
   757
                                { /* STC DBR, Rn */
nkeynes@359
   758
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   759
                                check_priv();
nkeynes@359
   760
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   761
                                store_reg( R_EAX, Rn );
nkeynes@417
   762
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   763
                                }
nkeynes@359
   764
                                break;
nkeynes@359
   765
                            default:
nkeynes@359
   766
                                UNDEF();
nkeynes@359
   767
                                break;
nkeynes@359
   768
                        }
nkeynes@359
   769
                        break;
nkeynes@359
   770
                    case 0xB:
nkeynes@359
   771
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   772
                            case 0x0:
nkeynes@359
   773
                                { /* RTS */
nkeynes@374
   774
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   775
                            	SLOTILLEGAL();
nkeynes@374
   776
                                } else {
nkeynes@408
   777
                            	load_spreg( R_ECX, R_PR );
nkeynes@590
   778
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
   779
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
   780
                            	sh4_translate_instruction(pc+2);
nkeynes@590
   781
                            	exit_block_newpcset(pc+2);
nkeynes@409
   782
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   783
                            	return 4;
nkeynes@374
   784
                                }
nkeynes@359
   785
                                }
nkeynes@359
   786
                                break;
nkeynes@359
   787
                            case 0x1:
nkeynes@359
   788
                                { /* SLEEP */
nkeynes@388
   789
                                check_priv();
nkeynes@388
   790
                                call_func0( sh4_sleep );
nkeynes@417
   791
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
   792
                                sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
   793
                                return 2;
nkeynes@359
   794
                                }
nkeynes@359
   795
                                break;
nkeynes@359
   796
                            case 0x2:
nkeynes@359
   797
                                { /* RTE */
nkeynes@374
   798
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   799
                            	SLOTILLEGAL();
nkeynes@374
   800
                                } else {
nkeynes@408
   801
                            	check_priv();
nkeynes@408
   802
                            	load_spreg( R_ECX, R_SPC );
nkeynes@590
   803
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
   804
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   805
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
   806
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
   807
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   808
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   809
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   810
                            	sh4_translate_instruction(pc+2);
nkeynes@590
   811
                            	exit_block_newpcset(pc+2);
nkeynes@409
   812
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   813
                            	return 4;
nkeynes@374
   814
                                }
nkeynes@359
   815
                                }
nkeynes@359
   816
                                break;
nkeynes@359
   817
                            default:
nkeynes@359
   818
                                UNDEF();
nkeynes@359
   819
                                break;
nkeynes@359
   820
                        }
nkeynes@359
   821
                        break;
nkeynes@359
   822
                    case 0xC:
nkeynes@359
   823
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   824
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   825
                        load_reg( R_EAX, 0 );
nkeynes@359
   826
                        load_reg( R_ECX, Rm );
nkeynes@586
   827
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   828
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
   829
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   830
                        store_reg( R_EAX, Rn );
nkeynes@417
   831
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   832
                        }
nkeynes@359
   833
                        break;
nkeynes@359
   834
                    case 0xD:
nkeynes@359
   835
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   836
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   837
                        load_reg( R_EAX, 0 );
nkeynes@361
   838
                        load_reg( R_ECX, Rm );
nkeynes@586
   839
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   840
                        check_ralign16( R_EAX );
nkeynes@586
   841
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   842
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   843
                        store_reg( R_EAX, Rn );
nkeynes@417
   844
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   845
                        }
nkeynes@359
   846
                        break;
nkeynes@359
   847
                    case 0xE:
nkeynes@359
   848
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   849
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   850
                        load_reg( R_EAX, 0 );
nkeynes@361
   851
                        load_reg( R_ECX, Rm );
nkeynes@586
   852
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   853
                        check_ralign32( R_EAX );
nkeynes@586
   854
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   855
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   856
                        store_reg( R_EAX, Rn );
nkeynes@417
   857
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   858
                        }
nkeynes@359
   859
                        break;
nkeynes@359
   860
                    case 0xF:
nkeynes@359
   861
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   862
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   863
                        if( Rm == Rn ) {
nkeynes@586
   864
                    	load_reg( R_EAX, Rm );
nkeynes@586
   865
                    	check_ralign32( R_EAX );
nkeynes@586
   866
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   867
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   868
                    	load_reg( R_EAX, Rn );
nkeynes@586
   869
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@586
   870
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   871
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   872
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   873
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
   874
                        } else {
nkeynes@586
   875
                    	load_reg( R_EAX, Rm );
nkeynes@586
   876
                    	check_ralign32( R_EAX );
nkeynes@586
   877
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   878
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   879
                    	load_reg( R_EAX, Rn );
nkeynes@586
   880
                    	check_ralign32( R_EAX );
nkeynes@586
   881
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   882
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   883
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   884
                        }
nkeynes@586
   885
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   886
                        POP_r32( R_ECX );
nkeynes@586
   887
                        PUSH_r32( R_EAX );
nkeynes@386
   888
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   889
                        POP_realigned_r32( R_ECX );
nkeynes@586
   890
                    
nkeynes@386
   891
                        IMUL_r32( R_ECX );
nkeynes@386
   892
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   893
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   894
                    
nkeynes@386
   895
                        load_spreg( R_ECX, R_S );
nkeynes@386
   896
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   897
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   898
                        call_func0( signsat48 );
nkeynes@386
   899
                        JMP_TARGET( nosat );
nkeynes@417
   900
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   901
                        }
nkeynes@359
   902
                        break;
nkeynes@359
   903
                    default:
nkeynes@359
   904
                        UNDEF();
nkeynes@359
   905
                        break;
nkeynes@359
   906
                }
nkeynes@359
   907
                break;
nkeynes@359
   908
            case 0x1:
nkeynes@359
   909
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   910
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
   911
                load_reg( R_EAX, Rn );
nkeynes@586
   912
                ADD_imm32_r32( disp, R_EAX );
nkeynes@586
   913
                check_walign32( R_EAX );
nkeynes@586
   914
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   915
                load_reg( R_EDX, Rm );
nkeynes@586
   916
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   917
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   918
                }
nkeynes@359
   919
                break;
nkeynes@359
   920
            case 0x2:
nkeynes@359
   921
                switch( ir&0xF ) {
nkeynes@359
   922
                    case 0x0:
nkeynes@359
   923
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   924
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   925
                        load_reg( R_EAX, Rn );
nkeynes@586
   926
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   927
                        load_reg( R_EDX, Rm );
nkeynes@586
   928
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   929
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   930
                        }
nkeynes@359
   931
                        break;
nkeynes@359
   932
                    case 0x1:
nkeynes@359
   933
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   934
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   935
                        load_reg( R_EAX, Rn );
nkeynes@586
   936
                        check_walign16( R_EAX );
nkeynes@586
   937
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
   938
                        load_reg( R_EDX, Rm );
nkeynes@586
   939
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   940
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
                        }
nkeynes@359
   942
                        break;
nkeynes@359
   943
                    case 0x2:
nkeynes@359
   944
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   945
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   946
                        load_reg( R_EAX, Rn );
nkeynes@586
   947
                        check_walign32(R_EAX);
nkeynes@586
   948
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   949
                        load_reg( R_EDX, Rm );
nkeynes@586
   950
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   951
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   952
                        }
nkeynes@359
   953
                        break;
nkeynes@359
   954
                    case 0x4:
nkeynes@359
   955
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   956
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   957
                        load_reg( R_EAX, Rn );
nkeynes@586
   958
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
   959
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   960
                        load_reg( R_EDX, Rm );
nkeynes@586
   961
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
   962
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   963
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   964
                        }
nkeynes@359
   965
                        break;
nkeynes@359
   966
                    case 0x5:
nkeynes@359
   967
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   968
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   969
                        load_reg( R_EAX, Rn );
nkeynes@586
   970
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
   971
                        check_walign16( R_EAX );
nkeynes@586
   972
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   973
                        load_reg( R_EDX, Rm );
nkeynes@586
   974
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
   975
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   976
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   977
                        }
nkeynes@359
   978
                        break;
nkeynes@359
   979
                    case 0x6:
nkeynes@359
   980
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   981
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   982
                        load_reg( R_EAX, Rn );
nkeynes@586
   983
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
   984
                        check_walign32( R_EAX );
nkeynes@586
   985
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   986
                        load_reg( R_EDX, Rm );
nkeynes@586
   987
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
   988
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   989
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   990
                        }
nkeynes@359
   991
                        break;
nkeynes@359
   992
                    case 0x7:
nkeynes@359
   993
                        { /* DIV0S Rm, Rn */
nkeynes@359
   994
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   995
                        load_reg( R_EAX, Rm );
nkeynes@386
   996
                        load_reg( R_ECX, Rn );
nkeynes@361
   997
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   998
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   999
                        store_spreg( R_EAX, R_M );
nkeynes@361
  1000
                        store_spreg( R_ECX, R_Q );
nkeynes@361
  1001
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1002
                        SETNE_t();
nkeynes@417
  1003
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
  1004
                        }
nkeynes@359
  1005
                        break;
nkeynes@359
  1006
                    case 0x8:
nkeynes@359
  1007
                        { /* TST Rm, Rn */
nkeynes@359
  1008
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1009
                        load_reg( R_EAX, Rm );
nkeynes@361
  1010
                        load_reg( R_ECX, Rn );
nkeynes@361
  1011
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1012
                        SETE_t();
nkeynes@417
  1013
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1014
                        }
nkeynes@359
  1015
                        break;
nkeynes@359
  1016
                    case 0x9:
nkeynes@359
  1017
                        { /* AND Rm, Rn */
nkeynes@359
  1018
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1019
                        load_reg( R_EAX, Rm );
nkeynes@359
  1020
                        load_reg( R_ECX, Rn );
nkeynes@359
  1021
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1022
                        store_reg( R_ECX, Rn );
nkeynes@417
  1023
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1024
                        }
nkeynes@359
  1025
                        break;
nkeynes@359
  1026
                    case 0xA:
nkeynes@359
  1027
                        { /* XOR Rm, Rn */
nkeynes@359
  1028
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1029
                        load_reg( R_EAX, Rm );
nkeynes@359
  1030
                        load_reg( R_ECX, Rn );
nkeynes@359
  1031
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1032
                        store_reg( R_ECX, Rn );
nkeynes@417
  1033
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1034
                        }
nkeynes@359
  1035
                        break;
nkeynes@359
  1036
                    case 0xB:
nkeynes@359
  1037
                        { /* OR Rm, Rn */
nkeynes@359
  1038
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1039
                        load_reg( R_EAX, Rm );
nkeynes@359
  1040
                        load_reg( R_ECX, Rn );
nkeynes@359
  1041
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1042
                        store_reg( R_ECX, Rn );
nkeynes@417
  1043
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1044
                        }
nkeynes@359
  1045
                        break;
nkeynes@359
  1046
                    case 0xC:
nkeynes@359
  1047
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1048
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1049
                        load_reg( R_EAX, Rm );
nkeynes@368
  1050
                        load_reg( R_ECX, Rn );
nkeynes@368
  1051
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1052
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1053
                        JE_rel8(13, target1);
nkeynes@368
  1054
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1055
                        JE_rel8(9, target2);
nkeynes@368
  1056
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1057
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1058
                        JE_rel8(2, target3);
nkeynes@368
  1059
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1060
                        JMP_TARGET(target1);
nkeynes@380
  1061
                        JMP_TARGET(target2);
nkeynes@380
  1062
                        JMP_TARGET(target3);
nkeynes@368
  1063
                        SETE_t();
nkeynes@417
  1064
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1065
                        }
nkeynes@359
  1066
                        break;
nkeynes@359
  1067
                    case 0xD:
nkeynes@359
  1068
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1069
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1070
                        load_reg( R_EAX, Rm );
nkeynes@394
  1071
                        load_reg( R_ECX, Rn );
nkeynes@394
  1072
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1073
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1074
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1075
                        store_reg( R_ECX, Rn );
nkeynes@417
  1076
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1077
                        }
nkeynes@359
  1078
                        break;
nkeynes@359
  1079
                    case 0xE:
nkeynes@359
  1080
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1081
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1082
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1083
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1084
                        MUL_r32( R_ECX );
nkeynes@374
  1085
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1086
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1087
                        }
nkeynes@359
  1088
                        break;
nkeynes@359
  1089
                    case 0xF:
nkeynes@359
  1090
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1091
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1092
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1093
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1094
                        MUL_r32( R_ECX );
nkeynes@374
  1095
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1096
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1097
                        }
nkeynes@359
  1098
                        break;
nkeynes@359
  1099
                    default:
nkeynes@359
  1100
                        UNDEF();
nkeynes@359
  1101
                        break;
nkeynes@359
  1102
                }
nkeynes@359
  1103
                break;
nkeynes@359
  1104
            case 0x3:
nkeynes@359
  1105
                switch( ir&0xF ) {
nkeynes@359
  1106
                    case 0x0:
nkeynes@359
  1107
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1108
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1109
                        load_reg( R_EAX, Rm );
nkeynes@359
  1110
                        load_reg( R_ECX, Rn );
nkeynes@359
  1111
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1112
                        SETE_t();
nkeynes@417
  1113
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1114
                        }
nkeynes@359
  1115
                        break;
nkeynes@359
  1116
                    case 0x2:
nkeynes@359
  1117
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1118
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1119
                        load_reg( R_EAX, Rm );
nkeynes@359
  1120
                        load_reg( R_ECX, Rn );
nkeynes@359
  1121
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1122
                        SETAE_t();
nkeynes@417
  1123
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1124
                        }
nkeynes@359
  1125
                        break;
nkeynes@359
  1126
                    case 0x3:
nkeynes@359
  1127
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1128
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1129
                        load_reg( R_EAX, Rm );
nkeynes@359
  1130
                        load_reg( R_ECX, Rn );
nkeynes@359
  1131
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1132
                        SETGE_t();
nkeynes@417
  1133
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1134
                        }
nkeynes@359
  1135
                        break;
nkeynes@359
  1136
                    case 0x4:
nkeynes@359
  1137
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1138
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1139
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1140
                        load_reg( R_EAX, Rn );
nkeynes@417
  1141
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1142
                    	LDC_t();
nkeynes@417
  1143
                        }
nkeynes@386
  1144
                        RCL1_r32( R_EAX );
nkeynes@386
  1145
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1146
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1147
                        JE_rel8(5, mqequal);
nkeynes@386
  1148
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1149
                        JMP_rel8(3, end);
nkeynes@380
  1150
                        JMP_TARGET(mqequal);
nkeynes@386
  1151
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1152
                        JMP_TARGET(end);
nkeynes@386
  1153
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1154
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1155
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1156
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1157
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1158
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1159
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1160
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1161
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1162
                        }
nkeynes@359
  1163
                        break;
nkeynes@359
  1164
                    case 0x5:
nkeynes@359
  1165
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1166
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1167
                        load_reg( R_EAX, Rm );
nkeynes@361
  1168
                        load_reg( R_ECX, Rn );
nkeynes@361
  1169
                        MUL_r32(R_ECX);
nkeynes@361
  1170
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1171
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1172
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1173
                        }
nkeynes@359
  1174
                        break;
nkeynes@359
  1175
                    case 0x6:
nkeynes@359
  1176
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1177
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1178
                        load_reg( R_EAX, Rm );
nkeynes@359
  1179
                        load_reg( R_ECX, Rn );
nkeynes@359
  1180
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1181
                        SETA_t();
nkeynes@417
  1182
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1183
                        }
nkeynes@359
  1184
                        break;
nkeynes@359
  1185
                    case 0x7:
nkeynes@359
  1186
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1187
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1188
                        load_reg( R_EAX, Rm );
nkeynes@359
  1189
                        load_reg( R_ECX, Rn );
nkeynes@359
  1190
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1191
                        SETG_t();
nkeynes@417
  1192
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1193
                        }
nkeynes@359
  1194
                        break;
nkeynes@359
  1195
                    case 0x8:
nkeynes@359
  1196
                        { /* SUB Rm, Rn */
nkeynes@359
  1197
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1198
                        load_reg( R_EAX, Rm );
nkeynes@359
  1199
                        load_reg( R_ECX, Rn );
nkeynes@359
  1200
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1201
                        store_reg( R_ECX, Rn );
nkeynes@417
  1202
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1203
                        }
nkeynes@359
  1204
                        break;
nkeynes@359
  1205
                    case 0xA:
nkeynes@359
  1206
                        { /* SUBC Rm, Rn */
nkeynes@359
  1207
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1208
                        load_reg( R_EAX, Rm );
nkeynes@359
  1209
                        load_reg( R_ECX, Rn );
nkeynes@417
  1210
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1211
                    	LDC_t();
nkeynes@417
  1212
                        }
nkeynes@359
  1213
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1214
                        store_reg( R_ECX, Rn );
nkeynes@394
  1215
                        SETC_t();
nkeynes@417
  1216
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1217
                        }
nkeynes@359
  1218
                        break;
nkeynes@359
  1219
                    case 0xB:
nkeynes@359
  1220
                        { /* SUBV Rm, Rn */
nkeynes@359
  1221
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1222
                        load_reg( R_EAX, Rm );
nkeynes@359
  1223
                        load_reg( R_ECX, Rn );
nkeynes@359
  1224
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1225
                        store_reg( R_ECX, Rn );
nkeynes@359
  1226
                        SETO_t();
nkeynes@417
  1227
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1228
                        }
nkeynes@359
  1229
                        break;
nkeynes@359
  1230
                    case 0xC:
nkeynes@359
  1231
                        { /* ADD Rm, Rn */
nkeynes@359
  1232
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1233
                        load_reg( R_EAX, Rm );
nkeynes@359
  1234
                        load_reg( R_ECX, Rn );
nkeynes@359
  1235
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1236
                        store_reg( R_ECX, Rn );
nkeynes@417
  1237
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1238
                        }
nkeynes@359
  1239
                        break;
nkeynes@359
  1240
                    case 0xD:
nkeynes@359
  1241
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1242
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1243
                        load_reg( R_EAX, Rm );
nkeynes@361
  1244
                        load_reg( R_ECX, Rn );
nkeynes@361
  1245
                        IMUL_r32(R_ECX);
nkeynes@361
  1246
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1247
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1248
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1249
                        }
nkeynes@359
  1250
                        break;
nkeynes@359
  1251
                    case 0xE:
nkeynes@359
  1252
                        { /* ADDC Rm, Rn */
nkeynes@359
  1253
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1254
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1255
                    	LDC_t();
nkeynes@417
  1256
                        }
nkeynes@359
  1257
                        load_reg( R_EAX, Rm );
nkeynes@359
  1258
                        load_reg( R_ECX, Rn );
nkeynes@359
  1259
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1260
                        store_reg( R_ECX, Rn );
nkeynes@359
  1261
                        SETC_t();
nkeynes@417
  1262
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1263
                        }
nkeynes@359
  1264
                        break;
nkeynes@359
  1265
                    case 0xF:
nkeynes@359
  1266
                        { /* ADDV Rm, Rn */
nkeynes@359
  1267
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1268
                        load_reg( R_EAX, Rm );
nkeynes@359
  1269
                        load_reg( R_ECX, Rn );
nkeynes@359
  1270
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1271
                        store_reg( R_ECX, Rn );
nkeynes@359
  1272
                        SETO_t();
nkeynes@417
  1273
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1274
                        }
nkeynes@359
  1275
                        break;
nkeynes@359
  1276
                    default:
nkeynes@359
  1277
                        UNDEF();
nkeynes@359
  1278
                        break;
nkeynes@359
  1279
                }
nkeynes@359
  1280
                break;
nkeynes@359
  1281
            case 0x4:
nkeynes@359
  1282
                switch( ir&0xF ) {
nkeynes@359
  1283
                    case 0x0:
nkeynes@359
  1284
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1285
                            case 0x0:
nkeynes@359
  1286
                                { /* SHLL Rn */
nkeynes@359
  1287
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1288
                                load_reg( R_EAX, Rn );
nkeynes@359
  1289
                                SHL1_r32( R_EAX );
nkeynes@397
  1290
                                SETC_t();
nkeynes@359
  1291
                                store_reg( R_EAX, Rn );
nkeynes@417
  1292
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1293
                                }
nkeynes@359
  1294
                                break;
nkeynes@359
  1295
                            case 0x1:
nkeynes@359
  1296
                                { /* DT Rn */
nkeynes@359
  1297
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1298
                                load_reg( R_EAX, Rn );
nkeynes@386
  1299
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1300
                                store_reg( R_EAX, Rn );
nkeynes@359
  1301
                                SETE_t();
nkeynes@417
  1302
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1303
                                }
nkeynes@359
  1304
                                break;
nkeynes@359
  1305
                            case 0x2:
nkeynes@359
  1306
                                { /* SHAL Rn */
nkeynes@359
  1307
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1308
                                load_reg( R_EAX, Rn );
nkeynes@359
  1309
                                SHL1_r32( R_EAX );
nkeynes@397
  1310
                                SETC_t();
nkeynes@359
  1311
                                store_reg( R_EAX, Rn );
nkeynes@417
  1312
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1313
                                }
nkeynes@359
  1314
                                break;
nkeynes@359
  1315
                            default:
nkeynes@359
  1316
                                UNDEF();
nkeynes@359
  1317
                                break;
nkeynes@359
  1318
                        }
nkeynes@359
  1319
                        break;
nkeynes@359
  1320
                    case 0x1:
nkeynes@359
  1321
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1322
                            case 0x0:
nkeynes@359
  1323
                                { /* SHLR Rn */
nkeynes@359
  1324
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1325
                                load_reg( R_EAX, Rn );
nkeynes@359
  1326
                                SHR1_r32( R_EAX );
nkeynes@397
  1327
                                SETC_t();
nkeynes@359
  1328
                                store_reg( R_EAX, Rn );
nkeynes@417
  1329
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1330
                                }
nkeynes@359
  1331
                                break;
nkeynes@359
  1332
                            case 0x1:
nkeynes@359
  1333
                                { /* CMP/PZ Rn */
nkeynes@359
  1334
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1335
                                load_reg( R_EAX, Rn );
nkeynes@359
  1336
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1337
                                SETGE_t();
nkeynes@417
  1338
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1339
                                }
nkeynes@359
  1340
                                break;
nkeynes@359
  1341
                            case 0x2:
nkeynes@359
  1342
                                { /* SHAR Rn */
nkeynes@359
  1343
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1344
                                load_reg( R_EAX, Rn );
nkeynes@359
  1345
                                SAR1_r32( R_EAX );
nkeynes@397
  1346
                                SETC_t();
nkeynes@359
  1347
                                store_reg( R_EAX, Rn );
nkeynes@417
  1348
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1349
                                }
nkeynes@359
  1350
                                break;
nkeynes@359
  1351
                            default:
nkeynes@359
  1352
                                UNDEF();
nkeynes@359
  1353
                                break;
nkeynes@359
  1354
                        }
nkeynes@359
  1355
                        break;
nkeynes@359
  1356
                    case 0x2:
nkeynes@359
  1357
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1358
                            case 0x0:
nkeynes@359
  1359
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1360
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1361
                                load_reg( R_EAX, Rn );
nkeynes@586
  1362
                                check_walign32( R_EAX );
nkeynes@586
  1363
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1364
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1365
                                load_spreg( R_EDX, R_MACH );
nkeynes@586
  1366
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1367
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1368
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1369
                                }
nkeynes@359
  1370
                                break;
nkeynes@359
  1371
                            case 0x1:
nkeynes@359
  1372
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1373
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1374
                                load_reg( R_EAX, Rn );
nkeynes@586
  1375
                                check_walign32( R_EAX );
nkeynes@586
  1376
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1377
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1378
                                load_spreg( R_EDX, R_MACL );
nkeynes@586
  1379
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1380
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1381
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1382
                                }
nkeynes@359
  1383
                                break;
nkeynes@359
  1384
                            case 0x2:
nkeynes@359
  1385
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1386
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1387
                                load_reg( R_EAX, Rn );
nkeynes@586
  1388
                                check_walign32( R_EAX );
nkeynes@586
  1389
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1390
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1391
                                load_spreg( R_EDX, R_PR );
nkeynes@586
  1392
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1393
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1394
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1395
                                }
nkeynes@359
  1396
                                break;
nkeynes@359
  1397
                            case 0x3:
nkeynes@359
  1398
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1399
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1400
                                check_priv();
nkeynes@586
  1401
                                load_reg( R_EAX, Rn );
nkeynes@586
  1402
                                check_walign32( R_EAX );
nkeynes@586
  1403
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1404
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1405
                                load_spreg( R_EDX, R_SGR );
nkeynes@586
  1406
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1407
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1408
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1409
                                }
nkeynes@359
  1410
                                break;
nkeynes@359
  1411
                            case 0x5:
nkeynes@359
  1412
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1413
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1414
                                load_reg( R_EAX, Rn );
nkeynes@586
  1415
                                check_walign32( R_EAX );
nkeynes@586
  1416
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1417
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1418
                                load_spreg( R_EDX, R_FPUL );
nkeynes@586
  1419
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1420
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1421
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1422
                                }
nkeynes@359
  1423
                                break;
nkeynes@359
  1424
                            case 0x6:
nkeynes@359
  1425
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1426
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1427
                                load_reg( R_EAX, Rn );
nkeynes@586
  1428
                                check_walign32( R_EAX );
nkeynes@586
  1429
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1430
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1431
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  1432
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1433
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1434
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1435
                                }
nkeynes@359
  1436
                                break;
nkeynes@359
  1437
                            case 0xF:
nkeynes@359
  1438
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1439
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1440
                                check_priv();
nkeynes@586
  1441
                                load_reg( R_EAX, Rn );
nkeynes@586
  1442
                                check_walign32( R_EAX );
nkeynes@586
  1443
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1444
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1445
                                load_spreg( R_EDX, R_DBR );
nkeynes@586
  1446
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1447
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1448
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1449
                                }
nkeynes@359
  1450
                                break;
nkeynes@359
  1451
                            default:
nkeynes@359
  1452
                                UNDEF();
nkeynes@359
  1453
                                break;
nkeynes@359
  1454
                        }
nkeynes@359
  1455
                        break;
nkeynes@359
  1456
                    case 0x3:
nkeynes@359
  1457
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1458
                            case 0x0:
nkeynes@359
  1459
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1460
                                    case 0x0:
nkeynes@359
  1461
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1462
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1463
                                        check_priv();
nkeynes@586
  1464
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1465
                                        check_walign32( R_EAX );
nkeynes@586
  1466
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1467
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1468
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1469
                                        call_func0( sh4_read_sr );
nkeynes@586
  1470
                                        POP_realigned_r32( R_ECX );
nkeynes@586
  1471
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1472
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1473
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1474
                                        }
nkeynes@359
  1475
                                        break;
nkeynes@359
  1476
                                    case 0x1:
nkeynes@359
  1477
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1478
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1479
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1480
                                        check_walign32( R_EAX );
nkeynes@586
  1481
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1482
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1483
                                        load_spreg( R_EDX, R_GBR );
nkeynes@586
  1484
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1485
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1486
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1487
                                        }
nkeynes@359
  1488
                                        break;
nkeynes@359
  1489
                                    case 0x2:
nkeynes@359
  1490
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1491
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1492
                                        check_priv();
nkeynes@586
  1493
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1494
                                        check_walign32( R_EAX );
nkeynes@586
  1495
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1496
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1497
                                        load_spreg( R_EDX, R_VBR );
nkeynes@586
  1498
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1499
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1500
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1501
                                        }
nkeynes@359
  1502
                                        break;
nkeynes@359
  1503
                                    case 0x3:
nkeynes@359
  1504
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1505
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1506
                                        check_priv();
nkeynes@586
  1507
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1508
                                        check_walign32( R_EAX );
nkeynes@586
  1509
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1510
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1511
                                        load_spreg( R_EDX, R_SSR );
nkeynes@586
  1512
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1513
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1514
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1515
                                        }
nkeynes@359
  1516
                                        break;
nkeynes@359
  1517
                                    case 0x4:
nkeynes@359
  1518
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1519
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1520
                                        check_priv();
nkeynes@586
  1521
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1522
                                        check_walign32( R_EAX );
nkeynes@586
  1523
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1524
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1525
                                        load_spreg( R_EDX, R_SPC );
nkeynes@586
  1526
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1527
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1528
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1529
                                        }
nkeynes@359
  1530
                                        break;
nkeynes@359
  1531
                                    default:
nkeynes@359
  1532
                                        UNDEF();
nkeynes@359
  1533
                                        break;
nkeynes@359
  1534
                                }
nkeynes@359
  1535
                                break;
nkeynes@359
  1536
                            case 0x1:
nkeynes@359
  1537
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1538
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1539
                                check_priv();
nkeynes@586
  1540
                                load_reg( R_EAX, Rn );
nkeynes@586
  1541
                                check_walign32( R_EAX );
nkeynes@586
  1542
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1543
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1544
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  1545
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1546
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1547
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1548
                                }
nkeynes@359
  1549
                                break;
nkeynes@359
  1550
                        }
nkeynes@359
  1551
                        break;
nkeynes@359
  1552
                    case 0x4:
nkeynes@359
  1553
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1554
                            case 0x0:
nkeynes@359
  1555
                                { /* ROTL Rn */
nkeynes@359
  1556
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1557
                                load_reg( R_EAX, Rn );
nkeynes@359
  1558
                                ROL1_r32( R_EAX );
nkeynes@359
  1559
                                store_reg( R_EAX, Rn );
nkeynes@359
  1560
                                SETC_t();
nkeynes@417
  1561
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1562
                                }
nkeynes@359
  1563
                                break;
nkeynes@359
  1564
                            case 0x2:
nkeynes@359
  1565
                                { /* ROTCL Rn */
nkeynes@359
  1566
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1567
                                load_reg( R_EAX, Rn );
nkeynes@417
  1568
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1569
                            	LDC_t();
nkeynes@417
  1570
                                }
nkeynes@359
  1571
                                RCL1_r32( R_EAX );
nkeynes@359
  1572
                                store_reg( R_EAX, Rn );
nkeynes@359
  1573
                                SETC_t();
nkeynes@417
  1574
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1575
                                }
nkeynes@359
  1576
                                break;
nkeynes@359
  1577
                            default:
nkeynes@359
  1578
                                UNDEF();
nkeynes@359
  1579
                                break;
nkeynes@359
  1580
                        }
nkeynes@359
  1581
                        break;
nkeynes@359
  1582
                    case 0x5:
nkeynes@359
  1583
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1584
                            case 0x0:
nkeynes@359
  1585
                                { /* ROTR Rn */
nkeynes@359
  1586
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1587
                                load_reg( R_EAX, Rn );
nkeynes@359
  1588
                                ROR1_r32( R_EAX );
nkeynes@359
  1589
                                store_reg( R_EAX, Rn );
nkeynes@359
  1590
                                SETC_t();
nkeynes@417
  1591
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1592
                                }
nkeynes@359
  1593
                                break;
nkeynes@359
  1594
                            case 0x1:
nkeynes@359
  1595
                                { /* CMP/PL Rn */
nkeynes@359
  1596
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1597
                                load_reg( R_EAX, Rn );
nkeynes@359
  1598
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1599
                                SETG_t();
nkeynes@417
  1600
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1601
                                }
nkeynes@359
  1602
                                break;
nkeynes@359
  1603
                            case 0x2:
nkeynes@359
  1604
                                { /* ROTCR Rn */
nkeynes@359
  1605
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1606
                                load_reg( R_EAX, Rn );
nkeynes@417
  1607
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1608
                            	LDC_t();
nkeynes@417
  1609
                                }
nkeynes@359
  1610
                                RCR1_r32( R_EAX );
nkeynes@359
  1611
                                store_reg( R_EAX, Rn );
nkeynes@359
  1612
                                SETC_t();
nkeynes@417
  1613
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1614
                                }
nkeynes@359
  1615
                                break;
nkeynes@359
  1616
                            default:
nkeynes@359
  1617
                                UNDEF();
nkeynes@359
  1618
                                break;
nkeynes@359
  1619
                        }
nkeynes@359
  1620
                        break;
nkeynes@359
  1621
                    case 0x6:
nkeynes@359
  1622
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1623
                            case 0x0:
nkeynes@359
  1624
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1625
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1626
                                load_reg( R_EAX, Rm );
nkeynes@395
  1627
                                check_ralign32( R_EAX );
nkeynes@586
  1628
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1629
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1630
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1631
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1632
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1633
                                }
nkeynes@359
  1634
                                break;
nkeynes@359
  1635
                            case 0x1:
nkeynes@359
  1636
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1637
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1638
                                load_reg( R_EAX, Rm );
nkeynes@395
  1639
                                check_ralign32( R_EAX );
nkeynes@586
  1640
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1641
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1642
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1643
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1644
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1645
                                }
nkeynes@359
  1646
                                break;
nkeynes@359
  1647
                            case 0x2:
nkeynes@359
  1648
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1649
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1650
                                load_reg( R_EAX, Rm );
nkeynes@395
  1651
                                check_ralign32( R_EAX );
nkeynes@586
  1652
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1653
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1654
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1655
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1656
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1657
                                }
nkeynes@359
  1658
                                break;
nkeynes@359
  1659
                            case 0x3:
nkeynes@359
  1660
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1661
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1662
                                check_priv();
nkeynes@359
  1663
                                load_reg( R_EAX, Rm );
nkeynes@395
  1664
                                check_ralign32( R_EAX );
nkeynes@586
  1665
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1666
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1667
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1668
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1669
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1670
                                }
nkeynes@359
  1671
                                break;
nkeynes@359
  1672
                            case 0x5:
nkeynes@359
  1673
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1674
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1675
                                load_reg( R_EAX, Rm );
nkeynes@395
  1676
                                check_ralign32( R_EAX );
nkeynes@586
  1677
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1678
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1679
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1680
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1681
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1682
                                }
nkeynes@359
  1683
                                break;
nkeynes@359
  1684
                            case 0x6:
nkeynes@359
  1685
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1686
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1687
                                load_reg( R_EAX, Rm );
nkeynes@395
  1688
                                check_ralign32( R_EAX );
nkeynes@586
  1689
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1690
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1691
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1692
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1693
                                update_fr_bank( R_EAX );
nkeynes@417
  1694
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1695
                                }
nkeynes@359
  1696
                                break;
nkeynes@359
  1697
                            case 0xF:
nkeynes@359
  1698
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1699
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1700
                                check_priv();
nkeynes@359
  1701
                                load_reg( R_EAX, Rm );
nkeynes@395
  1702
                                check_ralign32( R_EAX );
nkeynes@586
  1703
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1704
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1705
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1706
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1707
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1708
                                }
nkeynes@359
  1709
                                break;
nkeynes@359
  1710
                            default:
nkeynes@359
  1711
                                UNDEF();
nkeynes@359
  1712
                                break;
nkeynes@359
  1713
                        }
nkeynes@359
  1714
                        break;
nkeynes@359
  1715
                    case 0x7:
nkeynes@359
  1716
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1717
                            case 0x0:
nkeynes@359
  1718
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1719
                                    case 0x0:
nkeynes@359
  1720
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1721
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1722
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1723
                                    	SLOTILLEGAL();
nkeynes@386
  1724
                                        } else {
nkeynes@586
  1725
                                    	check_priv();
nkeynes@386
  1726
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1727
                                    	check_ralign32( R_EAX );
nkeynes@586
  1728
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1729
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1730
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1731
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1732
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1733
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1734
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1735
                                        }
nkeynes@359
  1736
                                        }
nkeynes@359
  1737
                                        break;
nkeynes@359
  1738
                                    case 0x1:
nkeynes@359
  1739
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1740
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1741
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1742
                                        check_ralign32( R_EAX );
nkeynes@586
  1743
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1744
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1745
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1746
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1747
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1748
                                        }
nkeynes@359
  1749
                                        break;
nkeynes@359
  1750
                                    case 0x2:
nkeynes@359
  1751
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1752
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1753
                                        check_priv();
nkeynes@359
  1754
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1755
                                        check_ralign32( R_EAX );
nkeynes@586
  1756
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1757
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1758
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1759
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1760
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1761
                                        }
nkeynes@359
  1762
                                        break;
nkeynes@359
  1763
                                    case 0x3:
nkeynes@359
  1764
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1765
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1766
                                        check_priv();
nkeynes@359
  1767
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1768
                                        check_ralign32( R_EAX );
nkeynes@586
  1769
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1770
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1771
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1772
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1773
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1774
                                        }
nkeynes@359
  1775
                                        break;
nkeynes@359
  1776
                                    case 0x4:
nkeynes@359
  1777
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1778
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1779
                                        check_priv();
nkeynes@359
  1780
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1781
                                        check_ralign32( R_EAX );
nkeynes@586
  1782
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1783
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1784
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1785
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1786
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1787
                                        }
nkeynes@359
  1788
                                        break;
nkeynes@359
  1789
                                    default:
nkeynes@359
  1790
                                        UNDEF();
nkeynes@359
  1791
                                        break;
nkeynes@359
  1792
                                }
nkeynes@359
  1793
                                break;
nkeynes@359
  1794
                            case 0x1:
nkeynes@359
  1795
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1796
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1797
                                check_priv();
nkeynes@374
  1798
                                load_reg( R_EAX, Rm );
nkeynes@395
  1799
                                check_ralign32( R_EAX );
nkeynes@586
  1800
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1801
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1802
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1803
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1804
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1805
                                }
nkeynes@359
  1806
                                break;
nkeynes@359
  1807
                        }
nkeynes@359
  1808
                        break;
nkeynes@359
  1809
                    case 0x8:
nkeynes@359
  1810
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1811
                            case 0x0:
nkeynes@359
  1812
                                { /* SHLL2 Rn */
nkeynes@359
  1813
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1814
                                load_reg( R_EAX, Rn );
nkeynes@359
  1815
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1816
                                store_reg( R_EAX, Rn );
nkeynes@417
  1817
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1818
                                }
nkeynes@359
  1819
                                break;
nkeynes@359
  1820
                            case 0x1:
nkeynes@359
  1821
                                { /* SHLL8 Rn */
nkeynes@359
  1822
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1823
                                load_reg( R_EAX, Rn );
nkeynes@359
  1824
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1825
                                store_reg( R_EAX, Rn );
nkeynes@417
  1826
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1827
                                }
nkeynes@359
  1828
                                break;
nkeynes@359
  1829
                            case 0x2:
nkeynes@359
  1830
                                { /* SHLL16 Rn */
nkeynes@359
  1831
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1832
                                load_reg( R_EAX, Rn );
nkeynes@359
  1833
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1834
                                store_reg( R_EAX, Rn );
nkeynes@417
  1835
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1836
                                }
nkeynes@359
  1837
                                break;
nkeynes@359
  1838
                            default:
nkeynes@359
  1839
                                UNDEF();
nkeynes@359
  1840
                                break;
nkeynes@359
  1841
                        }
nkeynes@359
  1842
                        break;
nkeynes@359
  1843
                    case 0x9:
nkeynes@359
  1844
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1845
                            case 0x0:
nkeynes@359
  1846
                                { /* SHLR2 Rn */
nkeynes@359
  1847
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1848
                                load_reg( R_EAX, Rn );
nkeynes@359
  1849
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1850
                                store_reg( R_EAX, Rn );
nkeynes@417
  1851
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1852
                                }
nkeynes@359
  1853
                                break;
nkeynes@359
  1854
                            case 0x1:
nkeynes@359
  1855
                                { /* SHLR8 Rn */
nkeynes@359
  1856
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1857
                                load_reg( R_EAX, Rn );
nkeynes@359
  1858
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1859
                                store_reg( R_EAX, Rn );
nkeynes@417
  1860
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1861
                                }
nkeynes@359
  1862
                                break;
nkeynes@359
  1863
                            case 0x2:
nkeynes@359
  1864
                                { /* SHLR16 Rn */
nkeynes@359
  1865
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1866
                                load_reg( R_EAX, Rn );
nkeynes@359
  1867
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1868
                                store_reg( R_EAX, Rn );
nkeynes@417
  1869
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1870
                                }
nkeynes@359
  1871
                                break;
nkeynes@359
  1872
                            default:
nkeynes@359
  1873
                                UNDEF();
nkeynes@359
  1874
                                break;
nkeynes@359
  1875
                        }
nkeynes@359
  1876
                        break;
nkeynes@359
  1877
                    case 0xA:
nkeynes@359
  1878
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1879
                            case 0x0:
nkeynes@359
  1880
                                { /* LDS Rm, MACH */
nkeynes@359
  1881
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1882
                                load_reg( R_EAX, Rm );
nkeynes@359
  1883
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1884
                                }
nkeynes@359
  1885
                                break;
nkeynes@359
  1886
                            case 0x1:
nkeynes@359
  1887
                                { /* LDS Rm, MACL */
nkeynes@359
  1888
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1889
                                load_reg( R_EAX, Rm );
nkeynes@359
  1890
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1891
                                }
nkeynes@359
  1892
                                break;
nkeynes@359
  1893
                            case 0x2:
nkeynes@359
  1894
                                { /* LDS Rm, PR */
nkeynes@359
  1895
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1896
                                load_reg( R_EAX, Rm );
nkeynes@359
  1897
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1898
                                }
nkeynes@359
  1899
                                break;
nkeynes@359
  1900
                            case 0x3:
nkeynes@359
  1901
                                { /* LDC Rm, SGR */
nkeynes@359
  1902
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1903
                                check_priv();
nkeynes@359
  1904
                                load_reg( R_EAX, Rm );
nkeynes@359
  1905
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1906
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1907
                                }
nkeynes@359
  1908
                                break;
nkeynes@359
  1909
                            case 0x5:
nkeynes@359
  1910
                                { /* LDS Rm, FPUL */
nkeynes@359
  1911
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1912
                                load_reg( R_EAX, Rm );
nkeynes@359
  1913
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1914
                                }
nkeynes@359
  1915
                                break;
nkeynes@359
  1916
                            case 0x6:
nkeynes@359
  1917
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1918
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1919
                                load_reg( R_EAX, Rm );
nkeynes@359
  1920
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1921
                                update_fr_bank( R_EAX );
nkeynes@417
  1922
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1923
                                }
nkeynes@359
  1924
                                break;
nkeynes@359
  1925
                            case 0xF:
nkeynes@359
  1926
                                { /* LDC Rm, DBR */
nkeynes@359
  1927
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1928
                                check_priv();
nkeynes@359
  1929
                                load_reg( R_EAX, Rm );
nkeynes@359
  1930
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1931
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1932
                                }
nkeynes@359
  1933
                                break;
nkeynes@359
  1934
                            default:
nkeynes@359
  1935
                                UNDEF();
nkeynes@359
  1936
                                break;
nkeynes@359
  1937
                        }
nkeynes@359
  1938
                        break;
nkeynes@359
  1939
                    case 0xB:
nkeynes@359
  1940
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1941
                            case 0x0:
nkeynes@359
  1942
                                { /* JSR @Rn */
nkeynes@359
  1943
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1944
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1945
                            	SLOTILLEGAL();
nkeynes@374
  1946
                                } else {
nkeynes@590
  1947
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
  1948
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1949
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1950
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1951
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@526
  1952
                            	sh4_translate_instruction(pc+2);
nkeynes@590
  1953
                            	exit_block_newpcset(pc+2);
nkeynes@409
  1954
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1955
                            	return 4;
nkeynes@374
  1956
                                }
nkeynes@359
  1957
                                }
nkeynes@359
  1958
                                break;
nkeynes@359
  1959
                            case 0x1:
nkeynes@359
  1960
                                { /* TAS.B @Rn */
nkeynes@359
  1961
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1962
                                load_reg( R_EAX, Rn );
nkeynes@586
  1963
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1964
                                PUSH_realigned_r32( R_EAX );
nkeynes@586
  1965
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1966
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1967
                                SETE_t();
nkeynes@361
  1968
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1969
                                POP_realigned_r32( R_ECX );
nkeynes@361
  1970
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1971
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1972
                                }
nkeynes@359
  1973
                                break;
nkeynes@359
  1974
                            case 0x2:
nkeynes@359
  1975
                                { /* JMP @Rn */
nkeynes@359
  1976
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1977
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1978
                            	SLOTILLEGAL();
nkeynes@374
  1979
                                } else {
nkeynes@408
  1980
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1981
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1982
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1983
                            	sh4_translate_instruction(pc+2);
nkeynes@590
  1984
                            	exit_block_newpcset(pc+2);
nkeynes@409
  1985
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1986
                            	return 4;
nkeynes@374
  1987
                                }
nkeynes@359
  1988
                                }
nkeynes@359
  1989
                                break;
nkeynes@359
  1990
                            default:
nkeynes@359
  1991
                                UNDEF();
nkeynes@359
  1992
                                break;
nkeynes@359
  1993
                        }
nkeynes@359
  1994
                        break;
nkeynes@359
  1995
                    case 0xC:
nkeynes@359
  1996
                        { /* SHAD Rm, Rn */
nkeynes@359
  1997
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1998
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1999
                        load_reg( R_EAX, Rn );
nkeynes@361
  2000
                        load_reg( R_ECX, Rm );
nkeynes@361
  2001
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2002
                        JGE_rel8(16, doshl);
nkeynes@361
  2003
                                        
nkeynes@361
  2004
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  2005
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2006
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  2007
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  2008
                        JMP_rel8(10, end);          // 2
nkeynes@386
  2009
                    
nkeynes@386
  2010
                        JMP_TARGET(emptysar);
nkeynes@386
  2011
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  2012
                        JMP_rel8(5, end2);
nkeynes@386
  2013
                    
nkeynes@380
  2014
                        JMP_TARGET(doshl);
nkeynes@361
  2015
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2016
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2017
                        JMP_TARGET(end);
nkeynes@386
  2018
                        JMP_TARGET(end2);
nkeynes@361
  2019
                        store_reg( R_EAX, Rn );
nkeynes@417
  2020
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2021
                        }
nkeynes@359
  2022
                        break;
nkeynes@359
  2023
                    case 0xD:
nkeynes@359
  2024
                        { /* SHLD Rm, Rn */
nkeynes@359
  2025
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2026
                        load_reg( R_EAX, Rn );
nkeynes@368
  2027
                        load_reg( R_ECX, Rm );
nkeynes@386
  2028
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2029
                        JGE_rel8(15, doshl);
nkeynes@368
  2030
                    
nkeynes@386
  2031
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2032
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2033
                        JE_rel8( 4, emptyshr );
nkeynes@386
  2034
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  2035
                        JMP_rel8(9, end);          // 2
nkeynes@386
  2036
                    
nkeynes@386
  2037
                        JMP_TARGET(emptyshr);
nkeynes@386
  2038
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  2039
                        JMP_rel8(5, end2);
nkeynes@386
  2040
                    
nkeynes@386
  2041
                        JMP_TARGET(doshl);
nkeynes@386
  2042
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2043
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2044
                        JMP_TARGET(end);
nkeynes@386
  2045
                        JMP_TARGET(end2);
nkeynes@368
  2046
                        store_reg( R_EAX, Rn );
nkeynes@417
  2047
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2048
                        }
nkeynes@359
  2049
                        break;
nkeynes@359
  2050
                    case 0xE:
nkeynes@359
  2051
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2052
                            case 0x0:
nkeynes@359
  2053
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2054
                                    case 0x0:
nkeynes@359
  2055
                                        { /* LDC Rm, SR */
nkeynes@359
  2056
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2057
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2058
                                    	SLOTILLEGAL();
nkeynes@386
  2059
                                        } else {
nkeynes@386
  2060
                                    	check_priv();
nkeynes@386
  2061
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2062
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2063
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2064
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2065
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2066
                                        }
nkeynes@359
  2067
                                        }
nkeynes@359
  2068
                                        break;
nkeynes@359
  2069
                                    case 0x1:
nkeynes@359
  2070
                                        { /* LDC Rm, GBR */
nkeynes@359
  2071
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2072
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2073
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2074
                                        }
nkeynes@359
  2075
                                        break;
nkeynes@359
  2076
                                    case 0x2:
nkeynes@359
  2077
                                        { /* LDC Rm, VBR */
nkeynes@359
  2078
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2079
                                        check_priv();
nkeynes@359
  2080
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2081
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2082
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2083
                                        }
nkeynes@359
  2084
                                        break;
nkeynes@359
  2085
                                    case 0x3:
nkeynes@359
  2086
                                        { /* LDC Rm, SSR */
nkeynes@359
  2087
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2088
                                        check_priv();
nkeynes@359
  2089
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2090
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2091
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2092
                                        }
nkeynes@359
  2093
                                        break;
nkeynes@359
  2094
                                    case 0x4:
nkeynes@359
  2095
                                        { /* LDC Rm, SPC */
nkeynes@359
  2096
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2097
                                        check_priv();
nkeynes@359
  2098
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2099
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2100
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2101
                                        }
nkeynes@359
  2102
                                        break;
nkeynes@359
  2103
                                    default:
nkeynes@359
  2104
                                        UNDEF();
nkeynes@359
  2105
                                        break;
nkeynes@359
  2106
                                }
nkeynes@359
  2107
                                break;
nkeynes@359
  2108
                            case 0x1:
nkeynes@359
  2109
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2110
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2111
                                check_priv();
nkeynes@374
  2112
                                load_reg( R_EAX, Rm );
nkeynes@374
  2113
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2114
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2115
                                }
nkeynes@359
  2116
                                break;
nkeynes@359
  2117
                        }
nkeynes@359
  2118
                        break;
nkeynes@359
  2119
                    case 0xF:
nkeynes@359
  2120
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2121
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2122
                        if( Rm == Rn ) {
nkeynes@586
  2123
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2124
                    	check_ralign16( R_EAX );
nkeynes@586
  2125
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2126
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2127
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2128
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@586
  2129
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2130
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2131
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  2132
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
  2133
                        } else {
nkeynes@586
  2134
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2135
                    	check_ralign16( R_EAX );
nkeynes@586
  2136
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2137
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2138
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2139
                    	check_ralign16( R_EAX );
nkeynes@586
  2140
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2141
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
  2142
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2143
                        }
nkeynes@586
  2144
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2145
                        POP_r32( R_ECX );
nkeynes@586
  2146
                        PUSH_r32( R_EAX );
nkeynes@386
  2147
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2148
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2149
                        IMUL_r32( R_ECX );
nkeynes@386
  2150
                    
nkeynes@386
  2151
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2152
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2153
                        JE_rel8( 47, nosat );
nkeynes@386
  2154
                    
nkeynes@386
  2155
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2156
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2157
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2158
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2159
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2160
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2161
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2162
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2163
                    
nkeynes@386
  2164
                        JMP_TARGET(positive);
nkeynes@386
  2165
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2166
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2167
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2168
                    
nkeynes@386
  2169
                        JMP_TARGET(nosat);
nkeynes@386
  2170
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2171
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2172
                        JMP_TARGET(end);
nkeynes@386
  2173
                        JMP_TARGET(end2);
nkeynes@386
  2174
                        JMP_TARGET(end3);
nkeynes@417
  2175
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2176
                        }
nkeynes@359
  2177
                        break;
nkeynes@359
  2178
                }
nkeynes@359
  2179
                break;
nkeynes@359
  2180
            case 0x5:
nkeynes@359
  2181
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2182
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
  2183
                load_reg( R_EAX, Rm );
nkeynes@586
  2184
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  2185
                check_ralign32( R_EAX );
nkeynes@586
  2186
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2187
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2188
                store_reg( R_EAX, Rn );
nkeynes@417
  2189
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2190
                }
nkeynes@359
  2191
                break;
nkeynes@359
  2192
            case 0x6:
nkeynes@359
  2193
                switch( ir&0xF ) {
nkeynes@359
  2194
                    case 0x0:
nkeynes@359
  2195
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2196
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2197
                        load_reg( R_EAX, Rm );
nkeynes@586
  2198
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2199
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2200
                        store_reg( R_EAX, Rn );
nkeynes@417
  2201
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2202
                        }
nkeynes@359
  2203
                        break;
nkeynes@359
  2204
                    case 0x1:
nkeynes@359
  2205
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2206
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2207
                        load_reg( R_EAX, Rm );
nkeynes@586
  2208
                        check_ralign16( R_EAX );
nkeynes@586
  2209
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2210
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2211
                        store_reg( R_EAX, Rn );
nkeynes@417
  2212
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2213
                        }
nkeynes@359
  2214
                        break;
nkeynes@359
  2215
                    case 0x2:
nkeynes@359
  2216
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2217
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2218
                        load_reg( R_EAX, Rm );
nkeynes@586
  2219
                        check_ralign32( R_EAX );
nkeynes@586
  2220
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2221
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2222
                        store_reg( R_EAX, Rn );
nkeynes@417
  2223
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2224
                        }
nkeynes@359
  2225
                        break;
nkeynes@359
  2226
                    case 0x3:
nkeynes@359
  2227
                        { /* MOV Rm, Rn */
nkeynes@359
  2228
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2229
                        load_reg( R_EAX, Rm );
nkeynes@359
  2230
                        store_reg( R_EAX, Rn );
nkeynes@359
  2231
                        }
nkeynes@359
  2232
                        break;
nkeynes@359
  2233
                    case 0x4:
nkeynes@359
  2234
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2235
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2236
                        load_reg( R_EAX, Rm );
nkeynes@586
  2237
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2238
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  2239
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2240
                        store_reg( R_EAX, Rn );
nkeynes@417
  2241
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2242
                        }
nkeynes@359
  2243
                        break;
nkeynes@359
  2244
                    case 0x5:
nkeynes@359
  2245
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2246
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2247
                        load_reg( R_EAX, Rm );
nkeynes@374
  2248
                        check_ralign16( R_EAX );
nkeynes@586
  2249
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2250
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2251
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2252
                        store_reg( R_EAX, Rn );
nkeynes@417
  2253
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2254
                        }
nkeynes@359
  2255
                        break;
nkeynes@359
  2256
                    case 0x6:
nkeynes@359
  2257
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2258
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2259
                        load_reg( R_EAX, Rm );
nkeynes@386
  2260
                        check_ralign32( R_EAX );
nkeynes@586
  2261
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2262
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2263
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2264
                        store_reg( R_EAX, Rn );
nkeynes@417
  2265
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2266
                        }
nkeynes@359
  2267
                        break;
nkeynes@359
  2268
                    case 0x7:
nkeynes@359
  2269
                        { /* NOT Rm, Rn */
nkeynes@359
  2270
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2271
                        load_reg( R_EAX, Rm );
nkeynes@359
  2272
                        NOT_r32( R_EAX );
nkeynes@359
  2273
                        store_reg( R_EAX, Rn );
nkeynes@417
  2274
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2275
                        }
nkeynes@359
  2276
                        break;
nkeynes@359
  2277
                    case 0x8:
nkeynes@359
  2278
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2279
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2280
                        load_reg( R_EAX, Rm );
nkeynes@359
  2281
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2282
                        store_reg( R_EAX, Rn );
nkeynes@359
  2283
                        }
nkeynes@359
  2284
                        break;
nkeynes@359
  2285
                    case 0x9:
nkeynes@359
  2286
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2287
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2288
                        load_reg( R_EAX, Rm );
nkeynes@359
  2289
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2290
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2291
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2292
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2293
                        store_reg( R_ECX, Rn );
nkeynes@417
  2294
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2295
                        }
nkeynes@359
  2296
                        break;
nkeynes@359
  2297
                    case 0xA:
nkeynes@359
  2298
                        { /* NEGC Rm, Rn */
nkeynes@359
  2299
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2300
                        load_reg( R_EAX, Rm );
nkeynes@359
  2301
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2302
                        LDC_t();
nkeynes@359
  2303
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2304
                        store_reg( R_ECX, Rn );
nkeynes@359
  2305
                        SETC_t();
nkeynes@417
  2306
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2307
                        }
nkeynes@359
  2308
                        break;
nkeynes@359
  2309
                    case 0xB:
nkeynes@359
  2310
                        { /* NEG Rm, Rn */
nkeynes@359
  2311
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2312
                        load_reg( R_EAX, Rm );
nkeynes@359
  2313
                        NEG_r32( R_EAX );
nkeynes@359
  2314
                        store_reg( R_EAX, Rn );
nkeynes@417
  2315
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2316
                        }
nkeynes@359
  2317
                        break;
nkeynes@359
  2318
                    case 0xC:
nkeynes@359
  2319
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2320
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2321
                        load_reg( R_EAX, Rm );
nkeynes@361
  2322
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2323
                        store_reg( R_EAX, Rn );
nkeynes@359
  2324
                        }
nkeynes@359
  2325
                        break;
nkeynes@359
  2326
                    case 0xD:
nkeynes@359
  2327
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2328
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2329
                        load_reg( R_EAX, Rm );
nkeynes@361
  2330
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2331
                        store_reg( R_EAX, Rn );
nkeynes@359
  2332
                        }
nkeynes@359
  2333
                        break;
nkeynes@359
  2334
                    case 0xE:
nkeynes@359
  2335
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2336
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2337
                        load_reg( R_EAX, Rm );
nkeynes@359
  2338
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2339
                        store_reg( R_EAX, Rn );
nkeynes@359
  2340
                        }
nkeynes@359
  2341
                        break;
nkeynes@359
  2342
                    case 0xF:
nkeynes@359
  2343
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2344
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2345
                        load_reg( R_EAX, Rm );
nkeynes@361
  2346
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2347
                        store_reg( R_EAX, Rn );
nkeynes@359
  2348
                        }
nkeynes@359
  2349
                        break;
nkeynes@359
  2350
                }
nkeynes@359
  2351
                break;
nkeynes@359
  2352
            case 0x7:
nkeynes@359
  2353
                { /* ADD #imm, Rn */
nkeynes@359
  2354
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2355
                load_reg( R_EAX, Rn );
nkeynes@359
  2356
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2357
                store_reg( R_EAX, Rn );
nkeynes@417
  2358
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2359
                }
nkeynes@359
  2360
                break;
nkeynes@359
  2361
            case 0x8:
nkeynes@359
  2362
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2363
                    case 0x0:
nkeynes@359
  2364
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2365
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2366
                        load_reg( R_EAX, Rn );
nkeynes@586
  2367
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2368
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2369
                        load_reg( R_EDX, 0 );
nkeynes@586
  2370
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2371
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2372
                        }
nkeynes@359
  2373
                        break;
nkeynes@359
  2374
                    case 0x1:
nkeynes@359
  2375
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2376
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2377
                        load_reg( R_EAX, Rn );
nkeynes@586
  2378
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2379
                        check_walign16( R_EAX );
nkeynes@586
  2380
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2381
                        load_reg( R_EDX, 0 );
nkeynes@586
  2382
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2383
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2384
                        }
nkeynes@359
  2385
                        break;
nkeynes@359
  2386
                    case 0x4:
nkeynes@359
  2387
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2388
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2389
                        load_reg( R_EAX, Rm );
nkeynes@586
  2390
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2391
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2392
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2393
                        store_reg( R_EAX, 0 );
nkeynes@417
  2394
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2395
                        }
nkeynes@359
  2396
                        break;
nkeynes@359
  2397
                    case 0x5:
nkeynes@359
  2398
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2399
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2400
                        load_reg( R_EAX, Rm );
nkeynes@586
  2401
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2402
                        check_ralign16( R_EAX );
nkeynes@586
  2403
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2404
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2405
                        store_reg( R_EAX, 0 );
nkeynes@417
  2406
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2407
                        }
nkeynes@359
  2408
                        break;
nkeynes@359
  2409
                    case 0x8:
nkeynes@359
  2410
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2411
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2412
                        load_reg( R_EAX, 0 );
nkeynes@359
  2413
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2414
                        SETE_t();
nkeynes@417
  2415
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2416
                        }
nkeynes@359
  2417
                        break;
nkeynes@359
  2418
                    case 0x9:
nkeynes@359
  2419
                        { /* BT disp */
nkeynes@359
  2420
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2421
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2422
                    	SLOTILLEGAL();
nkeynes@374
  2423
                        } else {
nkeynes@586
  2424
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2425
                    	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2426
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2427
                    	JMP_TARGET(nottaken);
nkeynes@408
  2428
                    	return 2;
nkeynes@374
  2429
                        }
nkeynes@359
  2430
                        }
nkeynes@359
  2431
                        break;
nkeynes@359
  2432
                    case 0xB:
nkeynes@359
  2433
                        { /* BF disp */
nkeynes@359
  2434
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2435
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2436
                    	SLOTILLEGAL();
nkeynes@374
  2437
                        } else {
nkeynes@586
  2438
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2439
                    	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2440
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2441
                    	JMP_TARGET(nottaken);
nkeynes@408
  2442
                    	return 2;
nkeynes@374
  2443
                        }
nkeynes@359
  2444
                        }
nkeynes@359
  2445
                        break;
nkeynes@359
  2446
                    case 0xD:
nkeynes@359
  2447
                        { /* BT/S disp */
nkeynes@359
  2448
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2449
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2450
                    	SLOTILLEGAL();
nkeynes@374
  2451
                        } else {
nkeynes@590
  2452
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2453
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2454
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2455
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2456
                    	}
nkeynes@417
  2457
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2458
                    	sh4_translate_instruction(pc+2);
nkeynes@586
  2459
                    	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  2460
                    	// not taken
nkeynes@408
  2461
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2462
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2463
                    	return 4;
nkeynes@374
  2464
                        }
nkeynes@359
  2465
                        }
nkeynes@359
  2466
                        break;
nkeynes@359
  2467
                    case 0xF:
nkeynes@359
  2468
                        { /* BF/S disp */
nkeynes@359
  2469
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2470
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2471
                    	SLOTILLEGAL();
nkeynes@374
  2472
                        } else {
nkeynes@586
  2473
                    	sh4vma_t target = disp + pc + 4;
nkeynes@590
  2474
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2475
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2476
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2477
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2478
                    	}
nkeynes@417
  2479
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2480
                    	sh4_translate_instruction(pc+2);
nkeynes@586
  2481
                    	exit_block_rel( target, pc+4 );
nkeynes@408
  2482
                    	// not taken
nkeynes@408
  2483
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2484
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2485
                    	return 4;
nkeynes@374
  2486
                        }
nkeynes@359
  2487
                        }
nkeynes@359
  2488
                        break;
nkeynes@359
  2489
                    default:
nkeynes@359
  2490
                        UNDEF();
nkeynes@359
  2491
                        break;
nkeynes@359
  2492
                }
nkeynes@359
  2493
                break;
nkeynes@359
  2494
            case 0x9:
nkeynes@359
  2495
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2496
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2497
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2498
            	SLOTILLEGAL();
nkeynes@374
  2499
                } else {
nkeynes@586
  2500
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  2501
            	uint32_t target = pc + disp + 4;
nkeynes@586
  2502
            	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  2503
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  2504
            	    MOV_moff32_EAX( ptr );
nkeynes@586
  2505
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  2506
            	} else {
nkeynes@586
  2507
            	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  2508
            	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  2509
            	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2510
            	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2511
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  2512
            	}
nkeynes@374
  2513
            	store_reg( R_EAX, Rn );
nkeynes@374
  2514
                }
nkeynes@359
  2515
                }
nkeynes@359
  2516
                break;
nkeynes@359
  2517
            case 0xA:
nkeynes@359
  2518
                { /* BRA disp */
nkeynes@359
  2519
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2520
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2521
            	SLOTILLEGAL();
nkeynes@374
  2522
                } else {
nkeynes@590
  2523
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  2524
            	sh4_translate_instruction( pc + 2 );
nkeynes@586
  2525
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2526
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2527
            	return 4;
nkeynes@374
  2528
                }
nkeynes@359
  2529
                }
nkeynes@359
  2530
                break;
nkeynes@359
  2531
            case 0xB:
nkeynes@359
  2532
                { /* BSR disp */
nkeynes@359
  2533
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2534
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2535
            	SLOTILLEGAL();
nkeynes@374
  2536
                } else {
nkeynes@590
  2537
            	load_spreg( R_EAX, R_PC );
nkeynes@590
  2538
            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  2539
            	store_spreg( R_EAX, R_PR );
nkeynes@590
  2540
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  2541
            	sh4_translate_instruction( pc + 2 );
nkeynes@586
  2542
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2543
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2544
            	return 4;
nkeynes@374
  2545
                }
nkeynes@359
  2546
                }
nkeynes@359
  2547
                break;
nkeynes@359
  2548
            case 0xC:
nkeynes@359
  2549
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2550
                    case 0x0:
nkeynes@359
  2551
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2552
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2553
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2554
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2555
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2556
                        load_reg( R_EDX, 0 );
nkeynes@586
  2557
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2558
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2559
                        }
nkeynes@359
  2560
                        break;
nkeynes@359
  2561
                    case 0x1:
nkeynes@359
  2562
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2563
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2564
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2565
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2566
                        check_walign16( R_EAX );
nkeynes@586
  2567
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2568
                        load_reg( R_EDX, 0 );
nkeynes@586
  2569
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2570
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2571
                        }
nkeynes@359
  2572
                        break;
nkeynes@359
  2573
                    case 0x2:
nkeynes@359
  2574
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2575
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2576
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2577
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2578
                        check_walign32( R_EAX );
nkeynes@586
  2579
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2580
                        load_reg( R_EDX, 0 );
nkeynes@586
  2581
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2582
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2583
                        }
nkeynes@359
  2584
                        break;
nkeynes@359
  2585
                    case 0x3:
nkeynes@359
  2586
                        { /* TRAPA #imm */
nkeynes@359
  2587
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2588
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2589
                    	SLOTILLEGAL();
nkeynes@374
  2590
                        } else {
nkeynes@590
  2591
                    	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  2592
                    	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  2593
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2594
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2595
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2596
                    	exit_block_pcset(pc);
nkeynes@409
  2597
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2598
                    	return 2;
nkeynes@374
  2599
                        }
nkeynes@359
  2600
                        }
nkeynes@359
  2601
                        break;
nkeynes@359
  2602
                    case 0x4:
nkeynes@359
  2603
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2604
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2605
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2606
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2607
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2608
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2609
                        store_reg( R_EAX, 0 );
nkeynes@417
  2610
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2611
                        }
nkeynes@359
  2612
                        break;
nkeynes@359
  2613
                    case 0x5:
nkeynes@359
  2614
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2615
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2616
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2617
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2618
                        check_ralign16( R_EAX );
nkeynes@586
  2619
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2620
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2621
                        store_reg( R_EAX, 0 );
nkeynes@417
  2622
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2623
                        }
nkeynes@359
  2624
                        break;
nkeynes@359
  2625
                    case 0x6:
nkeynes@359
  2626
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2627
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2628
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2629
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2630
                        check_ralign32( R_EAX );
nkeynes@586
  2631
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2632
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2633
                        store_reg( R_EAX, 0 );
nkeynes@417
  2634
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2635
                        }
nkeynes@359
  2636
                        break;
nkeynes@359
  2637
                    case 0x7:
nkeynes@359
  2638
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2639
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2640
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2641
                    	SLOTILLEGAL();
nkeynes@374
  2642
                        } else {
nkeynes@586
  2643
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  2644
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2645
                    	store_reg( R_ECX, 0 );
nkeynes@586
  2646
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2647
                        }
nkeynes@359
  2648
                        }
nkeynes@359
  2649
                        break;
nkeynes@359
  2650
                    case 0x8:
nkeynes@359
  2651
                        { /* TST #imm, R0 */
nkeynes@359
  2652
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2653
                        load_reg( R_EAX, 0 );
nkeynes@368
  2654
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2655
                        SETE_t();
nkeynes@417
  2656
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2657
                        }
nkeynes@359
  2658
                        break;
nkeynes@359
  2659
                    case 0x9:
nkeynes@359
  2660
                        { /* AND #imm, R0 */
nkeynes@359
  2661
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2662
                        load_reg( R_EAX, 0 );
nkeynes@359
  2663
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2664
                        store_reg( R_EAX, 0 );
nkeynes@417
  2665
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2666
                        }
nkeynes@359
  2667
                        break;
nkeynes@359
  2668
                    case 0xA:
nkeynes@359
  2669
                        { /* XOR #imm, R0 */
nkeynes@359
  2670
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2671
                        load_reg( R_EAX, 0 );
nkeynes@359
  2672
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2673
                        store_reg( R_EAX, 0 );
nkeynes@417
  2674
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2675
                        }
nkeynes@359
  2676
                        break;
nkeynes@359
  2677
                    case 0xB:
nkeynes@359
  2678
                        { /* OR #imm, R0 */
nkeynes@359
  2679
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2680
                        load_reg( R_EAX, 0 );
nkeynes@359
  2681
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2682
                        store_reg( R_EAX, 0 );
nkeynes@417
  2683
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2684
                        }
nkeynes@359
  2685
                        break;
nkeynes@359
  2686
                    case 0xC:
nkeynes@359
  2687
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2688
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2689
                        load_reg( R_EAX, 0);
nkeynes@368
  2690
                        load_reg( R_ECX, R_GBR);
nkeynes@586
  2691
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2692
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2693
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  2694
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2695
                        SETE_t();
nkeynes@417
  2696
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2697
                        }
nkeynes@359
  2698
                        break;
nkeynes@359
  2699
                    case 0xD:
nkeynes@359
  2700
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2701
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2702
                        load_reg( R_EAX, 0 );
nkeynes@359
  2703
                        load_spreg( R_ECX, R_GBR );
nkeynes@586
  2704
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2705
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2706
                        PUSH_realigned_r32(R_EAX);
nkeynes@586
  2707
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
  2708
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2709
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2710
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2711
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2712
                        }
nkeynes@359
  2713
                        break;
nkeynes@359
  2714
                    case 0xE:
nkeynes@359
  2715
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2716
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2717
                        load_reg( R_EAX, 0 );
nkeynes@359
  2718
                        load_spreg( R_ECX, R_GBR );
nkeynes@586
  2719
                        ADD_r32_r32( R_ECX, R_EAX );