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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 593:6c710c7c6835
prev591:7b9612fd2395
next596:dfc0c93d882e
author nkeynes
date Thu Jan 17 21:26:58 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix block overruns from long epilogues
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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    uint32_t recovery_posn;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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void sh4_x86_add_recovery( uint32_t pc )
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{
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    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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    xlat_recovery_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
nkeynes@586
   338
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   339
/**
nkeynes@586
   340
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   341
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   342
 */
nkeynes@586
   343
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   344
nkeynes@586
   345
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   346
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   347
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   348
nkeynes@590
   349
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   350
nkeynes@539
   351
/****** Import appropriate calling conventions ******/
nkeynes@539
   352
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   353
#include "sh4/ia64abi.h"
nkeynes@539
   354
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   355
#ifdef APPLE_BUILD
nkeynes@539
   356
#include "sh4/ia32mac.h"
nkeynes@539
   357
#else
nkeynes@539
   358
#include "sh4/ia32abi.h"
nkeynes@539
   359
#endif
nkeynes@539
   360
#endif
nkeynes@539
   361
nkeynes@593
   362
uint32_t sh4_translate_end_block_size()
nkeynes@593
   363
{
nkeynes@593
   364
    return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@593
   365
}
nkeynes@593
   366
nkeynes@593
   367
nkeynes@590
   368
/**
nkeynes@590
   369
 * Embed a breakpoint into the generated code
nkeynes@590
   370
 */
nkeynes@586
   371
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   372
{
nkeynes@591
   373
    load_imm32( R_EAX, pc );
nkeynes@591
   374
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   375
}
nkeynes@590
   376
nkeynes@590
   377
/**
nkeynes@590
   378
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@590
   379
 * can't translate (mainly page-crossing delay slots at the moment).
nkeynes@590
   380
 * Caller is responsible for setting new_pc.
nkeynes@590
   381
 */
nkeynes@590
   382
void sh4_emulator_exit( sh4vma_t endpc )
nkeynes@590
   383
{
nkeynes@590
   384
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   385
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   386
    
nkeynes@590
   387
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@590
   388
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   389
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   390
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   391
nkeynes@590
   392
    call_func0( sh4_execute_instruction );    
nkeynes@590
   393
    load_imm32( R_EAX, R_PC );
nkeynes@590
   394
    if( sh4_x86.tlb_on ) {
nkeynes@590
   395
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   396
    } else {
nkeynes@590
   397
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   398
    }
nkeynes@590
   399
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@590
   400
    POP_r32(R_EBP);
nkeynes@590
   401
    RET();
nkeynes@590
   402
} 
nkeynes@539
   403
nkeynes@359
   404
/**
nkeynes@359
   405
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   406
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   407
 * 
nkeynes@586
   408
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   409
 *
nkeynes@359
   410
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   411
 * (eg a branch or 
nkeynes@359
   412
 */
nkeynes@590
   413
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   414
{
nkeynes@388
   415
    uint32_t ir;
nkeynes@586
   416
    /* Read instruction from icache */
nkeynes@586
   417
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   418
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   419
    
nkeynes@586
   420
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   421
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   422
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   423
	 * almost certainly in a delay slot.
nkeynes@586
   424
	 *
nkeynes@586
   425
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   426
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   427
	 * small repairs to cope with the different environment).
nkeynes@586
   428
	 */
nkeynes@586
   429
nkeynes@586
   430
    if( !sh4_x86.in_delay_slot ) {
nkeynes@586
   431
	sh4_x86_add_recovery(pc);
nkeynes@388
   432
    }
nkeynes@359
   433
%%
nkeynes@359
   434
/* ALU operations */
nkeynes@359
   435
ADD Rm, Rn {:
nkeynes@359
   436
    load_reg( R_EAX, Rm );
nkeynes@359
   437
    load_reg( R_ECX, Rn );
nkeynes@359
   438
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   439
    store_reg( R_ECX, Rn );
nkeynes@417
   440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   441
:}
nkeynes@359
   442
ADD #imm, Rn {:  
nkeynes@359
   443
    load_reg( R_EAX, Rn );
nkeynes@359
   444
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   445
    store_reg( R_EAX, Rn );
nkeynes@417
   446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   447
:}
nkeynes@359
   448
ADDC Rm, Rn {:
nkeynes@417
   449
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   450
	LDC_t();
nkeynes@417
   451
    }
nkeynes@359
   452
    load_reg( R_EAX, Rm );
nkeynes@359
   453
    load_reg( R_ECX, Rn );
nkeynes@359
   454
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   455
    store_reg( R_ECX, Rn );
nkeynes@359
   456
    SETC_t();
nkeynes@417
   457
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   458
:}
nkeynes@359
   459
ADDV Rm, Rn {:
nkeynes@359
   460
    load_reg( R_EAX, Rm );
nkeynes@359
   461
    load_reg( R_ECX, Rn );
nkeynes@359
   462
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   463
    store_reg( R_ECX, Rn );
nkeynes@359
   464
    SETO_t();
nkeynes@417
   465
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   466
:}
nkeynes@359
   467
AND Rm, Rn {:
nkeynes@359
   468
    load_reg( R_EAX, Rm );
nkeynes@359
   469
    load_reg( R_ECX, Rn );
nkeynes@359
   470
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   471
    store_reg( R_ECX, Rn );
nkeynes@417
   472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   473
:}
nkeynes@359
   474
AND #imm, R0 {:  
nkeynes@359
   475
    load_reg( R_EAX, 0 );
nkeynes@359
   476
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   477
    store_reg( R_EAX, 0 );
nkeynes@417
   478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   479
:}
nkeynes@359
   480
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   481
    load_reg( R_EAX, 0 );
nkeynes@359
   482
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   483
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   484
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   485
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   486
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   487
    POP_realigned_r32(R_ECX);
nkeynes@386
   488
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   489
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   490
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   491
:}
nkeynes@359
   492
CMP/EQ Rm, Rn {:  
nkeynes@359
   493
    load_reg( R_EAX, Rm );
nkeynes@359
   494
    load_reg( R_ECX, Rn );
nkeynes@359
   495
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   496
    SETE_t();
nkeynes@417
   497
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   498
:}
nkeynes@359
   499
CMP/EQ #imm, R0 {:  
nkeynes@359
   500
    load_reg( R_EAX, 0 );
nkeynes@359
   501
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   502
    SETE_t();
nkeynes@417
   503
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   504
:}
nkeynes@359
   505
CMP/GE Rm, Rn {:  
nkeynes@359
   506
    load_reg( R_EAX, Rm );
nkeynes@359
   507
    load_reg( R_ECX, Rn );
nkeynes@359
   508
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   509
    SETGE_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/GT Rm, Rn {: 
nkeynes@359
   513
    load_reg( R_EAX, Rm );
nkeynes@359
   514
    load_reg( R_ECX, Rn );
nkeynes@359
   515
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   516
    SETG_t();
nkeynes@417
   517
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   518
:}
nkeynes@359
   519
CMP/HI Rm, Rn {:  
nkeynes@359
   520
    load_reg( R_EAX, Rm );
nkeynes@359
   521
    load_reg( R_ECX, Rn );
nkeynes@359
   522
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   523
    SETA_t();
nkeynes@417
   524
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   525
:}
nkeynes@359
   526
CMP/HS Rm, Rn {: 
nkeynes@359
   527
    load_reg( R_EAX, Rm );
nkeynes@359
   528
    load_reg( R_ECX, Rn );
nkeynes@359
   529
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   530
    SETAE_t();
nkeynes@417
   531
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   532
 :}
nkeynes@359
   533
CMP/PL Rn {: 
nkeynes@359
   534
    load_reg( R_EAX, Rn );
nkeynes@359
   535
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   536
    SETG_t();
nkeynes@417
   537
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   538
:}
nkeynes@359
   539
CMP/PZ Rn {:  
nkeynes@359
   540
    load_reg( R_EAX, Rn );
nkeynes@359
   541
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   542
    SETGE_t();
nkeynes@417
   543
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   544
:}
nkeynes@361
   545
CMP/STR Rm, Rn {:  
nkeynes@368
   546
    load_reg( R_EAX, Rm );
nkeynes@368
   547
    load_reg( R_ECX, Rn );
nkeynes@368
   548
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   549
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   550
    JE_rel8(13, target1);
nkeynes@368
   551
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   552
    JE_rel8(9, target2);
nkeynes@368
   553
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   554
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   555
    JE_rel8(2, target3);
nkeynes@368
   556
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   557
    JMP_TARGET(target1);
nkeynes@380
   558
    JMP_TARGET(target2);
nkeynes@380
   559
    JMP_TARGET(target3);
nkeynes@368
   560
    SETE_t();
nkeynes@417
   561
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   562
:}
nkeynes@361
   563
DIV0S Rm, Rn {:
nkeynes@361
   564
    load_reg( R_EAX, Rm );
nkeynes@386
   565
    load_reg( R_ECX, Rn );
nkeynes@361
   566
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   567
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   568
    store_spreg( R_EAX, R_M );
nkeynes@361
   569
    store_spreg( R_ECX, R_Q );
nkeynes@361
   570
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   571
    SETNE_t();
nkeynes@417
   572
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   573
:}
nkeynes@361
   574
DIV0U {:  
nkeynes@361
   575
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   576
    store_spreg( R_EAX, R_Q );
nkeynes@361
   577
    store_spreg( R_EAX, R_M );
nkeynes@361
   578
    store_spreg( R_EAX, R_T );
nkeynes@417
   579
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   580
:}
nkeynes@386
   581
DIV1 Rm, Rn {:
nkeynes@386
   582
    load_spreg( R_ECX, R_M );
nkeynes@386
   583
    load_reg( R_EAX, Rn );
nkeynes@417
   584
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   585
	LDC_t();
nkeynes@417
   586
    }
nkeynes@386
   587
    RCL1_r32( R_EAX );
nkeynes@386
   588
    SETC_r8( R_DL ); // Q'
nkeynes@386
   589
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   590
    JE_rel8(5, mqequal);
nkeynes@386
   591
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   592
    JMP_rel8(3, end);
nkeynes@380
   593
    JMP_TARGET(mqequal);
nkeynes@386
   594
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   595
    JMP_TARGET(end);
nkeynes@386
   596
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   597
    SETC_r8(R_AL); // tmp1
nkeynes@386
   598
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   599
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   600
    store_spreg( R_ECX, R_Q );
nkeynes@386
   601
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   602
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   603
    store_spreg( R_EAX, R_T );
nkeynes@417
   604
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   605
:}
nkeynes@361
   606
DMULS.L Rm, Rn {:  
nkeynes@361
   607
    load_reg( R_EAX, Rm );
nkeynes@361
   608
    load_reg( R_ECX, Rn );
nkeynes@361
   609
    IMUL_r32(R_ECX);
nkeynes@361
   610
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   611
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   613
:}
nkeynes@361
   614
DMULU.L Rm, Rn {:  
nkeynes@361
   615
    load_reg( R_EAX, Rm );
nkeynes@361
   616
    load_reg( R_ECX, Rn );
nkeynes@361
   617
    MUL_r32(R_ECX);
nkeynes@361
   618
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   619
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   620
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   621
:}
nkeynes@359
   622
DT Rn {:  
nkeynes@359
   623
    load_reg( R_EAX, Rn );
nkeynes@382
   624
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   625
    store_reg( R_EAX, Rn );
nkeynes@359
   626
    SETE_t();
nkeynes@417
   627
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   628
:}
nkeynes@359
   629
EXTS.B Rm, Rn {:  
nkeynes@359
   630
    load_reg( R_EAX, Rm );
nkeynes@359
   631
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   632
    store_reg( R_EAX, Rn );
nkeynes@359
   633
:}
nkeynes@361
   634
EXTS.W Rm, Rn {:  
nkeynes@361
   635
    load_reg( R_EAX, Rm );
nkeynes@361
   636
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   637
    store_reg( R_EAX, Rn );
nkeynes@361
   638
:}
nkeynes@361
   639
EXTU.B Rm, Rn {:  
nkeynes@361
   640
    load_reg( R_EAX, Rm );
nkeynes@361
   641
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   642
    store_reg( R_EAX, Rn );
nkeynes@361
   643
:}
nkeynes@361
   644
EXTU.W Rm, Rn {:  
nkeynes@361
   645
    load_reg( R_EAX, Rm );
nkeynes@361
   646
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   647
    store_reg( R_EAX, Rn );
nkeynes@361
   648
:}
nkeynes@586
   649
MAC.L @Rm+, @Rn+ {:
nkeynes@586
   650
    if( Rm == Rn ) {
nkeynes@586
   651
	load_reg( R_EAX, Rm );
nkeynes@586
   652
	check_ralign32( R_EAX );
nkeynes@586
   653
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   654
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   655
	load_reg( R_EAX, Rn );
nkeynes@586
   656
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@586
   657
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   658
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   659
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   660
	// adding a page-boundary check to skip the second translation
nkeynes@586
   661
    } else {
nkeynes@586
   662
	load_reg( R_EAX, Rm );
nkeynes@586
   663
	check_ralign32( R_EAX );
nkeynes@586
   664
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   665
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   666
	load_reg( R_EAX, Rn );
nkeynes@586
   667
	check_ralign32( R_EAX );
nkeynes@586
   668
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   669
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   670
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   671
    }
nkeynes@586
   672
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   673
    POP_r32( R_ECX );
nkeynes@586
   674
    PUSH_r32( R_EAX );
nkeynes@386
   675
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   676
    POP_realigned_r32( R_ECX );
nkeynes@586
   677
nkeynes@386
   678
    IMUL_r32( R_ECX );
nkeynes@386
   679
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   680
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   681
nkeynes@386
   682
    load_spreg( R_ECX, R_S );
nkeynes@386
   683
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   684
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   685
    call_func0( signsat48 );
nkeynes@386
   686
    JMP_TARGET( nosat );
nkeynes@417
   687
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   688
:}
nkeynes@386
   689
MAC.W @Rm+, @Rn+ {:  
nkeynes@586
   690
    if( Rm == Rn ) {
nkeynes@586
   691
	load_reg( R_EAX, Rm );
nkeynes@586
   692
	check_ralign16( R_EAX );
nkeynes@586
   693
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   694
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   695
	load_reg( R_EAX, Rn );
nkeynes@586
   696
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@586
   697
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   698
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   699
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   700
	// adding a page-boundary check to skip the second translation
nkeynes@586
   701
    } else {
nkeynes@586
   702
	load_reg( R_EAX, Rm );
nkeynes@586
   703
	check_ralign16( R_EAX );
nkeynes@586
   704
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   705
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   706
	load_reg( R_EAX, Rn );
nkeynes@586
   707
	check_ralign16( R_EAX );
nkeynes@586
   708
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   709
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   710
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   711
    }
nkeynes@586
   712
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   713
    POP_r32( R_ECX );
nkeynes@586
   714
    PUSH_r32( R_EAX );
nkeynes@386
   715
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   716
    POP_realigned_r32( R_ECX );
nkeynes@386
   717
    IMUL_r32( R_ECX );
nkeynes@386
   718
nkeynes@386
   719
    load_spreg( R_ECX, R_S );
nkeynes@386
   720
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   721
    JE_rel8( 47, nosat );
nkeynes@386
   722
nkeynes@386
   723
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   724
    JNO_rel8( 51, end );            // 2
nkeynes@386
   725
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   726
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   727
    JS_rel8( 13, positive );        // 2
nkeynes@386
   728
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   729
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   730
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   731
nkeynes@386
   732
    JMP_TARGET(positive);
nkeynes@386
   733
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   734
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   735
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   736
nkeynes@386
   737
    JMP_TARGET(nosat);
nkeynes@386
   738
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   739
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   740
    JMP_TARGET(end);
nkeynes@386
   741
    JMP_TARGET(end2);
nkeynes@386
   742
    JMP_TARGET(end3);
nkeynes@417
   743
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   744
:}
nkeynes@359
   745
MOVT Rn {:  
nkeynes@359
   746
    load_spreg( R_EAX, R_T );
nkeynes@359
   747
    store_reg( R_EAX, Rn );
nkeynes@359
   748
:}
nkeynes@361
   749
MUL.L Rm, Rn {:  
nkeynes@361
   750
    load_reg( R_EAX, Rm );
nkeynes@361
   751
    load_reg( R_ECX, Rn );
nkeynes@361
   752
    MUL_r32( R_ECX );
nkeynes@361
   753
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   754
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   755
:}
nkeynes@374
   756
MULS.W Rm, Rn {:
nkeynes@374
   757
    load_reg16s( R_EAX, Rm );
nkeynes@374
   758
    load_reg16s( R_ECX, Rn );
nkeynes@374
   759
    MUL_r32( R_ECX );
nkeynes@374
   760
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   761
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   762
:}
nkeynes@374
   763
MULU.W Rm, Rn {:  
nkeynes@374
   764
    load_reg16u( R_EAX, Rm );
nkeynes@374
   765
    load_reg16u( R_ECX, Rn );
nkeynes@374
   766
    MUL_r32( R_ECX );
nkeynes@374
   767
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   768
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   769
:}
nkeynes@359
   770
NEG Rm, Rn {:
nkeynes@359
   771
    load_reg( R_EAX, Rm );
nkeynes@359
   772
    NEG_r32( R_EAX );
nkeynes@359
   773
    store_reg( R_EAX, Rn );
nkeynes@417
   774
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   775
:}
nkeynes@359
   776
NEGC Rm, Rn {:  
nkeynes@359
   777
    load_reg( R_EAX, Rm );
nkeynes@359
   778
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   779
    LDC_t();
nkeynes@359
   780
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   781
    store_reg( R_ECX, Rn );
nkeynes@359
   782
    SETC_t();
nkeynes@417
   783
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   784
:}
nkeynes@359
   785
NOT Rm, Rn {:  
nkeynes@359
   786
    load_reg( R_EAX, Rm );
nkeynes@359
   787
    NOT_r32( R_EAX );
nkeynes@359
   788
    store_reg( R_EAX, Rn );
nkeynes@417
   789
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   790
:}
nkeynes@359
   791
OR Rm, Rn {:  
nkeynes@359
   792
    load_reg( R_EAX, Rm );
nkeynes@359
   793
    load_reg( R_ECX, Rn );
nkeynes@359
   794
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   795
    store_reg( R_ECX, Rn );
nkeynes@417
   796
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   797
:}
nkeynes@359
   798
OR #imm, R0 {:
nkeynes@359
   799
    load_reg( R_EAX, 0 );
nkeynes@359
   800
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   801
    store_reg( R_EAX, 0 );
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   803
:}
nkeynes@374
   804
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   805
    load_reg( R_EAX, 0 );
nkeynes@374
   806
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   807
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   808
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   809
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   810
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   811
    POP_realigned_r32(R_ECX);
nkeynes@386
   812
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   813
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   814
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   815
:}
nkeynes@359
   816
ROTCL Rn {:
nkeynes@359
   817
    load_reg( R_EAX, Rn );
nkeynes@417
   818
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   819
	LDC_t();
nkeynes@417
   820
    }
nkeynes@359
   821
    RCL1_r32( R_EAX );
nkeynes@359
   822
    store_reg( R_EAX, Rn );
nkeynes@359
   823
    SETC_t();
nkeynes@417
   824
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   825
:}
nkeynes@359
   826
ROTCR Rn {:  
nkeynes@359
   827
    load_reg( R_EAX, Rn );
nkeynes@417
   828
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   829
	LDC_t();
nkeynes@417
   830
    }
nkeynes@359
   831
    RCR1_r32( R_EAX );
nkeynes@359
   832
    store_reg( R_EAX, Rn );
nkeynes@359
   833
    SETC_t();
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   835
:}
nkeynes@359
   836
ROTL Rn {:  
nkeynes@359
   837
    load_reg( R_EAX, Rn );
nkeynes@359
   838
    ROL1_r32( R_EAX );
nkeynes@359
   839
    store_reg( R_EAX, Rn );
nkeynes@359
   840
    SETC_t();
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   842
:}
nkeynes@359
   843
ROTR Rn {:  
nkeynes@359
   844
    load_reg( R_EAX, Rn );
nkeynes@359
   845
    ROR1_r32( R_EAX );
nkeynes@359
   846
    store_reg( R_EAX, Rn );
nkeynes@359
   847
    SETC_t();
nkeynes@417
   848
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   849
:}
nkeynes@359
   850
SHAD Rm, Rn {:
nkeynes@359
   851
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   852
    load_reg( R_EAX, Rn );
nkeynes@361
   853
    load_reg( R_ECX, Rm );
nkeynes@361
   854
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   855
    JGE_rel8(16, doshl);
nkeynes@361
   856
                    
nkeynes@361
   857
    NEG_r32( R_ECX );      // 2
nkeynes@361
   858
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   859
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   860
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   861
    JMP_rel8(10, end);          // 2
nkeynes@386
   862
nkeynes@386
   863
    JMP_TARGET(emptysar);
nkeynes@386
   864
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   865
    JMP_rel8(5, end2);
nkeynes@382
   866
nkeynes@380
   867
    JMP_TARGET(doshl);
nkeynes@361
   868
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   869
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   870
    JMP_TARGET(end);
nkeynes@386
   871
    JMP_TARGET(end2);
nkeynes@361
   872
    store_reg( R_EAX, Rn );
nkeynes@417
   873
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   874
:}
nkeynes@359
   875
SHLD Rm, Rn {:  
nkeynes@368
   876
    load_reg( R_EAX, Rn );
nkeynes@368
   877
    load_reg( R_ECX, Rm );
nkeynes@382
   878
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   879
    JGE_rel8(15, doshl);
nkeynes@368
   880
nkeynes@382
   881
    NEG_r32( R_ECX );      // 2
nkeynes@382
   882
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   883
    JE_rel8( 4, emptyshr );
nkeynes@382
   884
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   885
    JMP_rel8(9, end);          // 2
nkeynes@386
   886
nkeynes@386
   887
    JMP_TARGET(emptyshr);
nkeynes@386
   888
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   889
    JMP_rel8(5, end2);
nkeynes@382
   890
nkeynes@382
   891
    JMP_TARGET(doshl);
nkeynes@382
   892
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   893
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   894
    JMP_TARGET(end);
nkeynes@386
   895
    JMP_TARGET(end2);
nkeynes@368
   896
    store_reg( R_EAX, Rn );
nkeynes@417
   897
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   898
:}
nkeynes@359
   899
SHAL Rn {: 
nkeynes@359
   900
    load_reg( R_EAX, Rn );
nkeynes@359
   901
    SHL1_r32( R_EAX );
nkeynes@397
   902
    SETC_t();
nkeynes@359
   903
    store_reg( R_EAX, Rn );
nkeynes@417
   904
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   905
:}
nkeynes@359
   906
SHAR Rn {:  
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@359
   908
    SAR1_r32( R_EAX );
nkeynes@397
   909
    SETC_t();
nkeynes@359
   910
    store_reg( R_EAX, Rn );
nkeynes@417
   911
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   912
:}
nkeynes@359
   913
SHLL Rn {:  
nkeynes@359
   914
    load_reg( R_EAX, Rn );
nkeynes@359
   915
    SHL1_r32( R_EAX );
nkeynes@397
   916
    SETC_t();
nkeynes@359
   917
    store_reg( R_EAX, Rn );
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   919
:}
nkeynes@359
   920
SHLL2 Rn {:
nkeynes@359
   921
    load_reg( R_EAX, Rn );
nkeynes@359
   922
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   923
    store_reg( R_EAX, Rn );
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   925
:}
nkeynes@359
   926
SHLL8 Rn {:  
nkeynes@359
   927
    load_reg( R_EAX, Rn );
nkeynes@359
   928
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   929
    store_reg( R_EAX, Rn );
nkeynes@417
   930
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   931
:}
nkeynes@359
   932
SHLL16 Rn {:  
nkeynes@359
   933
    load_reg( R_EAX, Rn );
nkeynes@359
   934
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   935
    store_reg( R_EAX, Rn );
nkeynes@417
   936
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   937
:}
nkeynes@359
   938
SHLR Rn {:  
nkeynes@359
   939
    load_reg( R_EAX, Rn );
nkeynes@359
   940
    SHR1_r32( R_EAX );
nkeynes@397
   941
    SETC_t();
nkeynes@359
   942
    store_reg( R_EAX, Rn );
nkeynes@417
   943
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   944
:}
nkeynes@359
   945
SHLR2 Rn {:  
nkeynes@359
   946
    load_reg( R_EAX, Rn );
nkeynes@359
   947
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@417
   949
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   950
:}
nkeynes@359
   951
SHLR8 Rn {:  
nkeynes@359
   952
    load_reg( R_EAX, Rn );
nkeynes@359
   953
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@417
   955
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   956
:}
nkeynes@359
   957
SHLR16 Rn {:  
nkeynes@359
   958
    load_reg( R_EAX, Rn );
nkeynes@359
   959
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   960
    store_reg( R_EAX, Rn );
nkeynes@417
   961
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   962
:}
nkeynes@359
   963
SUB Rm, Rn {:  
nkeynes@359
   964
    load_reg( R_EAX, Rm );
nkeynes@359
   965
    load_reg( R_ECX, Rn );
nkeynes@359
   966
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   967
    store_reg( R_ECX, Rn );
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   969
:}
nkeynes@359
   970
SUBC Rm, Rn {:  
nkeynes@359
   971
    load_reg( R_EAX, Rm );
nkeynes@359
   972
    load_reg( R_ECX, Rn );
nkeynes@417
   973
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   974
	LDC_t();
nkeynes@417
   975
    }
nkeynes@359
   976
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   977
    store_reg( R_ECX, Rn );
nkeynes@394
   978
    SETC_t();
nkeynes@417
   979
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   980
:}
nkeynes@359
   981
SUBV Rm, Rn {:  
nkeynes@359
   982
    load_reg( R_EAX, Rm );
nkeynes@359
   983
    load_reg( R_ECX, Rn );
nkeynes@359
   984
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   985
    store_reg( R_ECX, Rn );
nkeynes@359
   986
    SETO_t();
nkeynes@417
   987
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   988
:}
nkeynes@359
   989
SWAP.B Rm, Rn {:  
nkeynes@359
   990
    load_reg( R_EAX, Rm );
nkeynes@359
   991
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   992
    store_reg( R_EAX, Rn );
nkeynes@359
   993
:}
nkeynes@359
   994
SWAP.W Rm, Rn {:  
nkeynes@359
   995
    load_reg( R_EAX, Rm );
nkeynes@359
   996
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   997
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   998
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   999
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1000
    store_reg( R_ECX, Rn );
nkeynes@417
  1001
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1002
:}
nkeynes@361
  1003
TAS.B @Rn {:  
nkeynes@586
  1004
    load_reg( R_EAX, Rn );
nkeynes@586
  1005
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1006
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1007
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1008
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1009
    SETE_t();
nkeynes@361
  1010
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1011
    POP_realigned_r32( R_ECX );
nkeynes@361
  1012
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1013
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1014
:}
nkeynes@361
  1015
TST Rm, Rn {:  
nkeynes@361
  1016
    load_reg( R_EAX, Rm );
nkeynes@361
  1017
    load_reg( R_ECX, Rn );
nkeynes@361
  1018
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1019
    SETE_t();
nkeynes@417
  1020
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1021
:}
nkeynes@368
  1022
TST #imm, R0 {:  
nkeynes@368
  1023
    load_reg( R_EAX, 0 );
nkeynes@368
  1024
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1025
    SETE_t();
nkeynes@417
  1026
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1027
:}
nkeynes@368
  1028
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1029
    load_reg( R_EAX, 0);
nkeynes@368
  1030
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1031
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1032
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1033
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1034
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1035
    SETE_t();
nkeynes@417
  1036
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1037
:}
nkeynes@359
  1038
XOR Rm, Rn {:  
nkeynes@359
  1039
    load_reg( R_EAX, Rm );
nkeynes@359
  1040
    load_reg( R_ECX, Rn );
nkeynes@359
  1041
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1042
    store_reg( R_ECX, Rn );
nkeynes@417
  1043
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1044
:}
nkeynes@359
  1045
XOR #imm, R0 {:  
nkeynes@359
  1046
    load_reg( R_EAX, 0 );
nkeynes@359
  1047
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1048
    store_reg( R_EAX, 0 );
nkeynes@417
  1049
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1050
:}
nkeynes@359
  1051
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1052
    load_reg( R_EAX, 0 );
nkeynes@359
  1053
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1054
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1055
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1056
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1057
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1058
    POP_realigned_r32(R_ECX);
nkeynes@359
  1059
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1060
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1061
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1062
:}
nkeynes@361
  1063
XTRCT Rm, Rn {:
nkeynes@361
  1064
    load_reg( R_EAX, Rm );
nkeynes@394
  1065
    load_reg( R_ECX, Rn );
nkeynes@394
  1066
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1067
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1068
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1069
    store_reg( R_ECX, Rn );
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
:}
nkeynes@359
  1072
nkeynes@359
  1073
/* Data move instructions */
nkeynes@359
  1074
MOV Rm, Rn {:  
nkeynes@359
  1075
    load_reg( R_EAX, Rm );
nkeynes@359
  1076
    store_reg( R_EAX, Rn );
nkeynes@359
  1077
:}
nkeynes@359
  1078
MOV #imm, Rn {:  
nkeynes@359
  1079
    load_imm32( R_EAX, imm );
nkeynes@359
  1080
    store_reg( R_EAX, Rn );
nkeynes@359
  1081
:}
nkeynes@359
  1082
MOV.B Rm, @Rn {:  
nkeynes@586
  1083
    load_reg( R_EAX, Rn );
nkeynes@586
  1084
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1085
    load_reg( R_EDX, Rm );
nkeynes@586
  1086
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1087
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1088
:}
nkeynes@359
  1089
MOV.B Rm, @-Rn {:  
nkeynes@586
  1090
    load_reg( R_EAX, Rn );
nkeynes@586
  1091
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1092
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1093
    load_reg( R_EDX, Rm );
nkeynes@586
  1094
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1095
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1097
:}
nkeynes@359
  1098
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1099
    load_reg( R_EAX, 0 );
nkeynes@359
  1100
    load_reg( R_ECX, Rn );
nkeynes@586
  1101
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1102
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1103
    load_reg( R_EDX, Rm );
nkeynes@586
  1104
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1106
:}
nkeynes@359
  1107
MOV.B R0, @(disp, GBR) {:  
nkeynes@586
  1108
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1109
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1110
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1111
    load_reg( R_EDX, 0 );
nkeynes@586
  1112
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1113
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1114
:}
nkeynes@359
  1115
MOV.B R0, @(disp, Rn) {:  
nkeynes@586
  1116
    load_reg( R_EAX, Rn );
nkeynes@586
  1117
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1118
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1119
    load_reg( R_EDX, 0 );
nkeynes@586
  1120
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1121
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1122
:}
nkeynes@359
  1123
MOV.B @Rm, Rn {:  
nkeynes@586
  1124
    load_reg( R_EAX, Rm );
nkeynes@586
  1125
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1126
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1127
    store_reg( R_EAX, Rn );
nkeynes@417
  1128
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1129
:}
nkeynes@359
  1130
MOV.B @Rm+, Rn {:  
nkeynes@586
  1131
    load_reg( R_EAX, Rm );
nkeynes@586
  1132
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1133
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1134
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1135
    store_reg( R_EAX, Rn );
nkeynes@417
  1136
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1137
:}
nkeynes@359
  1138
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1139
    load_reg( R_EAX, 0 );
nkeynes@359
  1140
    load_reg( R_ECX, Rm );
nkeynes@586
  1141
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1142
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1143
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1144
    store_reg( R_EAX, Rn );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B @(disp, GBR), R0 {:  
nkeynes@586
  1148
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1149
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1150
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1151
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1152
    store_reg( R_EAX, 0 );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1154
:}
nkeynes@359
  1155
MOV.B @(disp, Rm), R0 {:  
nkeynes@586
  1156
    load_reg( R_EAX, Rm );
nkeynes@586
  1157
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1158
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1159
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1160
    store_reg( R_EAX, 0 );
nkeynes@417
  1161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1162
:}
nkeynes@374
  1163
MOV.L Rm, @Rn {:
nkeynes@586
  1164
    load_reg( R_EAX, Rn );
nkeynes@586
  1165
    check_walign32(R_EAX);
nkeynes@586
  1166
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1167
    load_reg( R_EDX, Rm );
nkeynes@586
  1168
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1169
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1170
:}
nkeynes@361
  1171
MOV.L Rm, @-Rn {:  
nkeynes@586
  1172
    load_reg( R_EAX, Rn );
nkeynes@586
  1173
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1174
    check_walign32( R_EAX );
nkeynes@586
  1175
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1176
    load_reg( R_EDX, Rm );
nkeynes@586
  1177
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1178
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1179
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1180
:}
nkeynes@361
  1181
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1182
    load_reg( R_EAX, 0 );
nkeynes@361
  1183
    load_reg( R_ECX, Rn );
nkeynes@586
  1184
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1185
    check_walign32( R_EAX );
nkeynes@586
  1186
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1187
    load_reg( R_EDX, Rm );
nkeynes@586
  1188
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1189
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1190
:}
nkeynes@361
  1191
MOV.L R0, @(disp, GBR) {:  
nkeynes@586
  1192
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1193
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1194
    check_walign32( R_EAX );
nkeynes@586
  1195
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1196
    load_reg( R_EDX, 0 );
nkeynes@586
  1197
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1199
:}
nkeynes@361
  1200
MOV.L Rm, @(disp, Rn) {:  
nkeynes@586
  1201
    load_reg( R_EAX, Rn );
nkeynes@586
  1202
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1203
    check_walign32( R_EAX );
nkeynes@586
  1204
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1205
    load_reg( R_EDX, Rm );
nkeynes@586
  1206
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1208
:}
nkeynes@361
  1209
MOV.L @Rm, Rn {:  
nkeynes@586
  1210
    load_reg( R_EAX, Rm );
nkeynes@586
  1211
    check_ralign32( R_EAX );
nkeynes@586
  1212
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1213
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1214
    store_reg( R_EAX, Rn );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1216
:}
nkeynes@361
  1217
MOV.L @Rm+, Rn {:  
nkeynes@361
  1218
    load_reg( R_EAX, Rm );
nkeynes@382
  1219
    check_ralign32( R_EAX );
nkeynes@586
  1220
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1221
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1222
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1223
    store_reg( R_EAX, Rn );
nkeynes@417
  1224
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1225
:}
nkeynes@361
  1226
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1227
    load_reg( R_EAX, 0 );
nkeynes@361
  1228
    load_reg( R_ECX, Rm );
nkeynes@586
  1229
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1230
    check_ralign32( R_EAX );
nkeynes@586
  1231
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1232
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1233
    store_reg( R_EAX, Rn );
nkeynes@417
  1234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1235
:}
nkeynes@361
  1236
MOV.L @(disp, GBR), R0 {:
nkeynes@586
  1237
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1238
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1239
    check_ralign32( R_EAX );
nkeynes@586
  1240
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1241
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1242
    store_reg( R_EAX, 0 );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1246
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1247
	SLOTILLEGAL();
nkeynes@374
  1248
    } else {
nkeynes@388
  1249
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1250
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1251
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1252
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1253
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1254
nkeynes@586
  1255
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1256
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1257
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1258
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1259
	    // behaviour though.
nkeynes@586
  1260
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1261
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1262
	} else {
nkeynes@586
  1263
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1264
	    // different virtual address than the translation was done with,
nkeynes@586
  1265
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1266
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1267
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1268
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1269
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1270
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1271
	}
nkeynes@382
  1272
	store_reg( R_EAX, Rn );
nkeynes@374
  1273
    }
nkeynes@361
  1274
:}
nkeynes@361
  1275
MOV.L @(disp, Rm), Rn {:  
nkeynes@586
  1276
    load_reg( R_EAX, Rm );
nkeynes@586
  1277
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1278
    check_ralign32( R_EAX );
nkeynes@586
  1279
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1280
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1281
    store_reg( R_EAX, Rn );
nkeynes@417
  1282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1283
:}
nkeynes@361
  1284
MOV.W Rm, @Rn {:  
nkeynes@586
  1285
    load_reg( R_EAX, Rn );
nkeynes@586
  1286
    check_walign16( R_EAX );
nkeynes@586
  1287
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1288
    load_reg( R_EDX, Rm );
nkeynes@586
  1289
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1290
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1291
:}
nkeynes@361
  1292
MOV.W Rm, @-Rn {:  
nkeynes@586
  1293
    load_reg( R_EAX, Rn );
nkeynes@586
  1294
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1295
    check_walign16( R_EAX );
nkeynes@586
  1296
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1297
    load_reg( R_EDX, Rm );
nkeynes@586
  1298
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1299
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1301
:}
nkeynes@361
  1302
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1303
    load_reg( R_EAX, 0 );
nkeynes@361
  1304
    load_reg( R_ECX, Rn );
nkeynes@586
  1305
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1306
    check_walign16( R_EAX );
nkeynes@586
  1307
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1308
    load_reg( R_EDX, Rm );
nkeynes@586
  1309
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1311
:}
nkeynes@361
  1312
MOV.W R0, @(disp, GBR) {:  
nkeynes@586
  1313
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1314
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1315
    check_walign16( R_EAX );
nkeynes@586
  1316
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1317
    load_reg( R_EDX, 0 );
nkeynes@586
  1318
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1320
:}
nkeynes@361
  1321
MOV.W R0, @(disp, Rn) {:  
nkeynes@586
  1322
    load_reg( R_EAX, Rn );
nkeynes@586
  1323
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1324
    check_walign16( R_EAX );
nkeynes@586
  1325
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1326
    load_reg( R_EDX, 0 );
nkeynes@586
  1327
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1328
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1329
:}
nkeynes@361
  1330
MOV.W @Rm, Rn {:  
nkeynes@586
  1331
    load_reg( R_EAX, Rm );
nkeynes@586
  1332
    check_ralign16( R_EAX );
nkeynes@586
  1333
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1334
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1335
    store_reg( R_EAX, Rn );
nkeynes@417
  1336
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1337
:}
nkeynes@361
  1338
MOV.W @Rm+, Rn {:  
nkeynes@361
  1339
    load_reg( R_EAX, Rm );
nkeynes@374
  1340
    check_ralign16( R_EAX );
nkeynes@586
  1341
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1342
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1343
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1344
    store_reg( R_EAX, Rn );
nkeynes@417
  1345
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1346
:}
nkeynes@361
  1347
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1348
    load_reg( R_EAX, 0 );
nkeynes@361
  1349
    load_reg( R_ECX, Rm );
nkeynes@586
  1350
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1351
    check_ralign16( R_EAX );
nkeynes@586
  1352
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1353
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1354
    store_reg( R_EAX, Rn );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1356
:}
nkeynes@361
  1357
MOV.W @(disp, GBR), R0 {:  
nkeynes@586
  1358
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1359
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1360
    check_ralign16( R_EAX );
nkeynes@586
  1361
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1362
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1363
    store_reg( R_EAX, 0 );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1365
:}
nkeynes@361
  1366
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1367
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1368
	SLOTILLEGAL();
nkeynes@374
  1369
    } else {
nkeynes@586
  1370
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1371
	uint32_t target = pc + disp + 4;
nkeynes@586
  1372
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1373
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1374
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1375
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1376
	} else {
nkeynes@586
  1377
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1378
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1379
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1380
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1381
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1382
	}
nkeynes@374
  1383
	store_reg( R_EAX, Rn );
nkeynes@374
  1384
    }
nkeynes@361
  1385
:}
nkeynes@361
  1386
MOV.W @(disp, Rm), R0 {:  
nkeynes@586
  1387
    load_reg( R_EAX, Rm );
nkeynes@586
  1388
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1389
    check_ralign16( R_EAX );
nkeynes@586
  1390
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1391
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1392
    store_reg( R_EAX, 0 );
nkeynes@417
  1393
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1394
:}
nkeynes@361
  1395
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1396
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1397
	SLOTILLEGAL();
nkeynes@374
  1398
    } else {
nkeynes@586
  1399
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1400
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1401
	store_reg( R_ECX, 0 );
nkeynes@586
  1402
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1403
    }
nkeynes@361
  1404
:}
nkeynes@361
  1405
MOVCA.L R0, @Rn {:  
nkeynes@586
  1406
    load_reg( R_EAX, Rn );
nkeynes@586
  1407
    check_walign32( R_EAX );
nkeynes@586
  1408
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1409
    load_reg( R_EDX, 0 );
nkeynes@586
  1410
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1412
:}
nkeynes@359
  1413
nkeynes@359
  1414
/* Control transfer instructions */
nkeynes@374
  1415
BF disp {:
nkeynes@374
  1416
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1417
	SLOTILLEGAL();
nkeynes@374
  1418
    } else {
nkeynes@586
  1419
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1420
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1421
	exit_block_rel(target, pc+2 );
nkeynes@380
  1422
	JMP_TARGET(nottaken);
nkeynes@408
  1423
	return 2;
nkeynes@374
  1424
    }
nkeynes@374
  1425
:}
nkeynes@374
  1426
BF/S disp {:
nkeynes@374
  1427
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1428
	SLOTILLEGAL();
nkeynes@374
  1429
    } else {
nkeynes@586
  1430
	sh4vma_t target = disp + pc + 4;
nkeynes@590
  1431
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1432
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1433
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1434
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1435
	}
nkeynes@417
  1436
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1437
	sh4_translate_instruction(pc+2);
nkeynes@586
  1438
	exit_block_rel( target, pc+4 );
nkeynes@408
  1439
	// not taken
nkeynes@408
  1440
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1441
	sh4_translate_instruction(pc+2);
nkeynes@408
  1442
	return 4;
nkeynes@374
  1443
    }
nkeynes@374
  1444
:}
nkeynes@374
  1445
BRA disp {:  
nkeynes@374
  1446
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1447
	SLOTILLEGAL();
nkeynes@374
  1448
    } else {
nkeynes@590
  1449
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1450
	sh4_translate_instruction( pc + 2 );
nkeynes@586
  1451
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1452
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1453
	return 4;
nkeynes@374
  1454
    }
nkeynes@374
  1455
:}
nkeynes@374
  1456
BRAF Rn {:  
nkeynes@374
  1457
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1458
	SLOTILLEGAL();
nkeynes@374
  1459
    } else {
nkeynes@590
  1460
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1461
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1462
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1463
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1464
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1465
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1466
	sh4_translate_instruction( pc + 2 );
nkeynes@590
  1467
	exit_block_newpcset(pc+2);
nkeynes@409
  1468
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1469
	return 4;
nkeynes@374
  1470
    }
nkeynes@374
  1471
:}
nkeynes@374
  1472
BSR disp {:  
nkeynes@374
  1473
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1474
	SLOTILLEGAL();
nkeynes@374
  1475
    } else {
nkeynes@590
  1476
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1477
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1478
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1479
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1480
	sh4_translate_instruction( pc + 2 );
nkeynes@586
  1481
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1482
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1483
	return 4;
nkeynes@374
  1484
    }
nkeynes@374
  1485
:}
nkeynes@374
  1486
BSRF Rn {:  
nkeynes@374
  1487
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1488
	SLOTILLEGAL();
nkeynes@374
  1489
    } else {
nkeynes@590
  1490
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1491
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1492
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1493
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1494
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1495
nkeynes@417
  1496
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1497
	sh4_translate_instruction( pc + 2 );
nkeynes@590
  1498
	exit_block_newpcset(pc+2);
nkeynes@409
  1499
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1500
	return 4;
nkeynes@374
  1501
    }
nkeynes@374
  1502
:}
nkeynes@374
  1503
BT disp {:
nkeynes@374
  1504
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1505
	SLOTILLEGAL();
nkeynes@374
  1506
    } else {
nkeynes@586
  1507
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1508
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1509
	exit_block_rel(target, pc+2 );
nkeynes@380
  1510
	JMP_TARGET(nottaken);
nkeynes@408
  1511
	return 2;
nkeynes@374
  1512
    }
nkeynes@374
  1513
:}
nkeynes@374
  1514
BT/S disp {:
nkeynes@374
  1515
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1516
	SLOTILLEGAL();
nkeynes@374
  1517
    } else {
nkeynes@590
  1518
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1519
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1520
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1521
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1522
	}
nkeynes@417
  1523
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1524
	sh4_translate_instruction(pc+2);
nkeynes@586
  1525
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  1526
	// not taken
nkeynes@408
  1527
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1528
	sh4_translate_instruction(pc+2);
nkeynes@408
  1529
	return 4;
nkeynes@374
  1530
    }
nkeynes@374
  1531
:}
nkeynes@374
  1532
JMP @Rn {:  
nkeynes@374
  1533
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1534
	SLOTILLEGAL();
nkeynes@374
  1535
    } else {
nkeynes@408
  1536
	load_reg( R_ECX, Rn );
nkeynes@590
  1537
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1538
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1539
	sh4_translate_instruction(pc+2);
nkeynes@590
  1540
	exit_block_newpcset(pc+2);
nkeynes@409
  1541
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1542
	return 4;
nkeynes@374
  1543
    }
nkeynes@374
  1544
:}
nkeynes@374
  1545
JSR @Rn {:  
nkeynes@374
  1546
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1547
	SLOTILLEGAL();
nkeynes@374
  1548
    } else {
nkeynes@590
  1549
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1550
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1551
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1552
	load_reg( R_ECX, Rn );
nkeynes@590
  1553
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@526
  1554
	sh4_translate_instruction(pc+2);
nkeynes@590
  1555
	exit_block_newpcset(pc+2);
nkeynes@409
  1556
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1557
	return 4;
nkeynes@374
  1558
    }
nkeynes@374
  1559
:}
nkeynes@374
  1560
RTE {:  
nkeynes@374
  1561
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1562
	SLOTILLEGAL();
nkeynes@374
  1563
    } else {
nkeynes@408
  1564
	check_priv();
nkeynes@408
  1565
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1566
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1567
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1568
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1569
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1570
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1571
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1572
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1573
	sh4_translate_instruction(pc+2);
nkeynes@590
  1574
	exit_block_newpcset(pc+2);
nkeynes@409
  1575
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1576
	return 4;
nkeynes@374
  1577
    }
nkeynes@374
  1578
:}
nkeynes@374
  1579
RTS {:  
nkeynes@374
  1580
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1581
	SLOTILLEGAL();
nkeynes@374
  1582
    } else {
nkeynes@408
  1583
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1584
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1585
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@526
  1586
	sh4_translate_instruction(pc+2);
nkeynes@590
  1587
	exit_block_newpcset(pc+2);
nkeynes@409
  1588
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1589
	return 4;
nkeynes@374
  1590
    }
nkeynes@374
  1591
:}
nkeynes@374
  1592
TRAPA #imm {:  
nkeynes@374
  1593
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1594
	SLOTILLEGAL();
nkeynes@374
  1595
    } else {
nkeynes@590
  1596
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1597
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1598
	load_imm32( R_EAX, imm );
nkeynes@527
  1599
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1600
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1601
	exit_block_pcset(pc);
nkeynes@409
  1602
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1603
	return 2;
nkeynes@374
  1604
    }
nkeynes@374
  1605
:}
nkeynes@374
  1606
UNDEF {:  
nkeynes@374
  1607
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1608
	SLOTILLEGAL();
nkeynes@374
  1609
    } else {
nkeynes@586
  1610
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1611
	return 2;
nkeynes@374
  1612
    }
nkeynes@368
  1613
:}
nkeynes@374
  1614
nkeynes@374
  1615
CLRMAC {:  
nkeynes@374
  1616
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1617
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1618
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1620
:}
nkeynes@374
  1621
CLRS {:
nkeynes@374
  1622
    CLC();
nkeynes@374
  1623
    SETC_sh4r(R_S);
nkeynes@417
  1624
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1625
:}
nkeynes@374
  1626
CLRT {:  
nkeynes@374
  1627
    CLC();
nkeynes@374
  1628
    SETC_t();
nkeynes@417
  1629
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1630
:}
nkeynes@374
  1631
SETS {:  
nkeynes@374
  1632
    STC();
nkeynes@374
  1633
    SETC_sh4r(R_S);
nkeynes@417
  1634
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1635
:}
nkeynes@374
  1636
SETT {:  
nkeynes@374
  1637
    STC();
nkeynes@374
  1638
    SETC_t();
nkeynes@417
  1639
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1640
:}
nkeynes@359
  1641
nkeynes@375
  1642
/* Floating point moves */
nkeynes@375
  1643
FMOV FRm, FRn {:  
nkeynes@375
  1644
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1645
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1646
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1647
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1648
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1649
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1650
     */
nkeynes@377
  1651
    check_fpuen();
nkeynes@375
  1652
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1653
    load_fr_bank( R_EDX );
nkeynes@375
  1654
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1655
    JNE_rel8(8, doublesize);
nkeynes@375
  1656
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1657
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1658
    if( FRm&1 ) {
nkeynes@386
  1659
	JMP_rel8(24, end);
nkeynes@380
  1660
	JMP_TARGET(doublesize);
nkeynes@375
  1661
	load_xf_bank( R_ECX ); 
nkeynes@375
  1662
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1663
	if( FRn&1 ) {
nkeynes@375
  1664
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1665
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1666
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1667
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1668
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1669
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1670
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1671
	}
nkeynes@380
  1672
	JMP_TARGET(end);
nkeynes@375
  1673
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1674
	if( FRn&1 ) {
nkeynes@386
  1675
	    JMP_rel8(24, end);
nkeynes@375
  1676
	    load_xf_bank( R_ECX );
nkeynes@375
  1677
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1678
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1679
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1680
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1681
	    JMP_TARGET(end);
nkeynes@375
  1682
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1683
	    JMP_rel8(12, end);
nkeynes@375
  1684
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1685
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1686
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1687
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1688
	    JMP_TARGET(end);
nkeynes@375
  1689
	}
nkeynes@375
  1690
    }
nkeynes@417
  1691
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1692
:}
nkeynes@416
  1693
FMOV FRm, @Rn {: 
nkeynes@586
  1694
    check_fpuen();
nkeynes@586
  1695
    load_reg( R_EAX, Rn );
nkeynes@586
  1696
    check_walign32( R_EAX );
nkeynes@586
  1697
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1698
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1699
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1700
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1701
    load_fr_bank( R_EDX );
nkeynes@586
  1702
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1703
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1704
    if( FRm&1 ) {
nkeynes@527
  1705
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1706
	JMP_TARGET(doublesize);
nkeynes@416
  1707
	load_xf_bank( R_EDX );
nkeynes@586
  1708
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1709
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1710
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1711
	JMP_TARGET(end);
nkeynes@375
  1712
    } else {
nkeynes@527
  1713
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1714
	JMP_TARGET(doublesize);
nkeynes@416
  1715
	load_fr_bank( R_EDX );
nkeynes@586
  1716
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1717
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1718
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1719
	JMP_TARGET(end);
nkeynes@375
  1720
    }
nkeynes@417
  1721
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1722
:}
nkeynes@375
  1723
FMOV @Rm, FRn {:  
nkeynes@586
  1724
    check_fpuen();
nkeynes@586
  1725
    load_reg( R_EAX, Rm );
nkeynes@586
  1726
    check_ralign32( R_EAX );
nkeynes@586
  1727
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1728
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1729
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1730
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1731
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1732
    load_fr_bank( R_EDX );
nkeynes@416
  1733
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1734
    if( FRn&1 ) {
nkeynes@527
  1735
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1736
	JMP_TARGET(doublesize);
nkeynes@586
  1737
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1738
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1739
	load_xf_bank( R_EDX );
nkeynes@586
  1740
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1741
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1742
	JMP_TARGET(end);
nkeynes@375
  1743
    } else {
nkeynes@527
  1744
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1745
	JMP_TARGET(doublesize);
nkeynes@586
  1746
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1747
	load_fr_bank( R_EDX );
nkeynes@586
  1748
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1749
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1750
	JMP_TARGET(end);
nkeynes@375
  1751
    }
nkeynes@417
  1752
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1753
:}
nkeynes@377
  1754
FMOV FRm, @-Rn {:  
nkeynes@586
  1755
    check_fpuen();
nkeynes@586
  1756
    load_reg( R_EAX, Rn );
nkeynes@586
  1757
    check_walign32( R_EAX );
nkeynes@416
  1758
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1759
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1760
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@586
  1761
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1762
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1763
    load_fr_bank( R_EDX );
nkeynes@586
  1764
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1765
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@586
  1766
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1767
    if( FRm&1 ) {
nkeynes@586
  1768
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1769
	JMP_TARGET(doublesize);
nkeynes@586
  1770
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1771
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1772
	load_xf_bank( R_EDX );
nkeynes@586
  1773
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1774
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1775
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1776
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1777
	JMP_TARGET(end);
nkeynes@377
  1778
    } else {
nkeynes@586
  1779
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1780
	JMP_TARGET(doublesize);
nkeynes@586
  1781
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1782
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1783
	load_fr_bank( R_EDX );
nkeynes@586
  1784
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1785
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1786
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1787
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1788
	JMP_TARGET(end);
nkeynes@377
  1789
    }
nkeynes@417
  1790
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1791
:}
nkeynes@416
  1792
FMOV @Rm+, FRn {:
nkeynes@586
  1793
    check_fpuen();
nkeynes@586
  1794
    load_reg( R_EAX, Rm );
nkeynes@586
  1795
    check_ralign32( R_EAX );
nkeynes@586
  1796
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1797
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1798
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1799
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1800
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1801
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1802
    load_fr_bank( R_EDX );
nkeynes@416
  1803
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1804
    if( FRn&1 ) {
nkeynes@586
  1805
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1806
	JMP_TARGET(doublesize);
nkeynes@586
  1807
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1808
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1809
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1810
	load_xf_bank( R_EDX );
nkeynes@586
  1811
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1812
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1813
	JMP_TARGET(end);
nkeynes@377
  1814
    } else {
nkeynes@586
  1815
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@586
  1816
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1817
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1818
	load_fr_bank( R_EDX );
nkeynes@586
  1819
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1820
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1821
	JMP_TARGET(end);
nkeynes@377
  1822
    }
nkeynes@417
  1823
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1824
:}
nkeynes@377
  1825
FMOV FRm, @(R0, Rn) {:  
nkeynes@586
  1826
    check_fpuen();
nkeynes@586
  1827
    load_reg( R_EAX, Rn );
nkeynes@586
  1828
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1829
    check_walign32( R_EAX );
nkeynes@586
  1830
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1831
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1832
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1833
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1834
    load_fr_bank( R_EDX );
nkeynes@586
  1835
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1836
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1837
    if( FRm&1 ) {
nkeynes@527
  1838
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1839
	JMP_TARGET(doublesize);
nkeynes@416
  1840
	load_xf_bank( R_EDX );
nkeynes@586
  1841
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1842
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1843
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1844
	JMP_TARGET(end);
nkeynes@377
  1845
    } else {
nkeynes@527
  1846
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1847
	JMP_TARGET(doublesize);
nkeynes@416
  1848
	load_fr_bank( R_EDX );
nkeynes@586
  1849
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1850
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1851
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1852
	JMP_TARGET(end);
nkeynes@377
  1853
    }
nkeynes@417
  1854
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1855
:}
nkeynes@377
  1856
FMOV @(R0, Rm), FRn {:  
nkeynes@586
  1857
    check_fpuen();
nkeynes@586
  1858
    load_reg( R_EAX, Rm );
nkeynes@586
  1859
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1860
    check_ralign32( R_EAX );
nkeynes@586
  1861
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1862
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1863
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1864
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1865
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1866
    load_fr_bank( R_EDX );
nkeynes@416
  1867
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1868
    if( FRn&1 ) {
nkeynes@527
  1869
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1870
	JMP_TARGET(doublesize);
nkeynes@586
  1871
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1872
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1873
	load_xf_bank( R_EDX );
nkeynes@586
  1874
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1875
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1876
	JMP_TARGET(end);
nkeynes@377
  1877
    } else {
nkeynes@527
  1878
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1879
	JMP_TARGET(doublesize);
nkeynes@586
  1880
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1881
	load_fr_bank( R_EDX );
nkeynes@586
  1882
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1883
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1884
	JMP_TARGET(end);
nkeynes@377
  1885
    }
nkeynes@417
  1886
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1887
:}
nkeynes@377
  1888
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1889
    check_fpuen();
nkeynes@377
  1890
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1891
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1892
    JNE_rel8(8, end);
nkeynes@377
  1893
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1894
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1895
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1896
    JMP_TARGET(end);
nkeynes@417
  1897
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1898
:}
nkeynes@377
  1899
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1900
    check_fpuen();
nkeynes@377
  1901
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1902
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1903
    JNE_rel8(11, end);
nkeynes@377
  1904
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1905
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1906
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1907
    JMP_TARGET(end);
nkeynes@417
  1908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1909
:}
nkeynes@377
  1910
nkeynes@377
  1911
FLOAT FPUL, FRn {:  
nkeynes@377
  1912
    check_fpuen();
nkeynes@377
  1913
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1914
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1915
    FILD_sh4r(R_FPUL);
nkeynes@377
  1916
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1917
    JNE_rel8(5, doubleprec);
nkeynes@377
  1918
    pop_fr( R_EDX, FRn );
nkeynes@380
  1919
    JMP_rel8(3, end);
nkeynes@380
  1920
    JMP_TARGET(doubleprec);
nkeynes@377
  1921
    pop_dr( R_EDX, FRn );
nkeynes@380
  1922
    JMP_TARGET(end);
nkeynes@417
  1923
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1924
:}
nkeynes@377
  1925
FTRC FRm, FPUL {:  
nkeynes@377
  1926
    check_fpuen();
nkeynes@388
  1927
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1928
    load_fr_bank( R_EDX );
nkeynes@388
  1929
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1930
    JNE_rel8(5, doubleprec);
nkeynes@388
  1931
    push_fr( R_EDX, FRm );
nkeynes@388
  1932
    JMP_rel8(3, doop);
nkeynes@388
  1933
    JMP_TARGET(doubleprec);
nkeynes@388
  1934
    push_dr( R_EDX, FRm );
nkeynes@388
  1935
    JMP_TARGET( doop );
nkeynes@388
  1936
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1937
    FILD_r32ind( R_ECX );
nkeynes@388
  1938
    FCOMIP_st(1);
nkeynes@394
  1939
    JNA_rel8( 32, sat );
nkeynes@388
  1940
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1941
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1942
    FCOMIP_st(1);                   // 2
nkeynes@394
  1943
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1944
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1945
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1946
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1947
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1948
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1949
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1950
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1951
nkeynes@388
  1952
    JMP_TARGET(sat);
nkeynes@388
  1953
    JMP_TARGET(sat2);
nkeynes@388
  1954
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1955
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1956
    FPOP_st();
nkeynes@388
  1957
    JMP_TARGET(end);
nkeynes@417
  1958
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1959
:}
nkeynes@377
  1960
FLDS FRm, FPUL {:  
nkeynes@377
  1961
    check_fpuen();
nkeynes@377
  1962
    load_fr_bank( R_ECX );
nkeynes@377
  1963
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1964
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1965
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1966
:}
nkeynes@377
  1967
FSTS FPUL, FRn {:  
nkeynes@377
  1968
    check_fpuen();
nkeynes@377
  1969
    load_fr_bank( R_ECX );
nkeynes@377
  1970
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1971
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1972
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1973
:}
nkeynes@377
  1974
FCNVDS FRm, FPUL {:  
nkeynes@377
  1975
    check_fpuen();
nkeynes@377
  1976
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1977
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1978
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1979
    load_fr_bank( R_ECX );
nkeynes@377
  1980
    push_dr( R_ECX, FRm );
nkeynes@377
  1981
    pop_fpul();
nkeynes@380
  1982
    JMP_TARGET(end);
nkeynes@417
  1983
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1984
:}
nkeynes@377
  1985
FCNVSD FPUL, FRn {:  
nkeynes@377
  1986
    check_fpuen();
nkeynes@377
  1987
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1988
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1989
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1990
    load_fr_bank( R_ECX );
nkeynes@377
  1991
    push_fpul();
nkeynes@377
  1992
    pop_dr( R_ECX, FRn );
nkeynes@380
  1993
    JMP_TARGET(end);
nkeynes@417
  1994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1995
:}
nkeynes@375
  1996
nkeynes@359
  1997
/* Floating point instructions */
nkeynes@374
  1998
FABS FRn {:  
nkeynes@377
  1999
    check_fpuen();
nkeynes@374
  2000
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2001
    load_fr_bank( R_EDX );
nkeynes@374
  2002
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2003
    JNE_rel8(10, doubleprec);
nkeynes@374
  2004
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  2005
    FABS_st0(); // 2
nkeynes@374
  2006
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2007
    JMP_rel8(8,end); // 2
nkeynes@380
  2008
    JMP_TARGET(doubleprec);
nkeynes@374
  2009
    push_dr(R_EDX, FRn);
nkeynes@374
  2010
    FABS_st0();
nkeynes@374
  2011
    pop_dr(R_EDX, FRn);
nkeynes@380
  2012
    JMP_TARGET(end);
nkeynes@417
  2013
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2014
:}
nkeynes@377
  2015
FADD FRm, FRn {:  
nkeynes@377
  2016
    check_fpuen();
nkeynes@375
  2017
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2018
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2019
    load_fr_bank( R_EDX );
nkeynes@380
  2020
    JNE_rel8(13,doubleprec);
nkeynes@377
  2021
    push_fr(R_EDX, FRm);
nkeynes@377
  2022
    push_fr(R_EDX, FRn);
nkeynes@377
  2023
    FADDP_st(1);
nkeynes@377
  2024
    pop_fr(R_EDX, FRn);
nkeynes@380
  2025
    JMP_rel8(11,end);
nkeynes@380
  2026
    JMP_TARGET(doubleprec);
nkeynes@377
  2027
    push_dr(R_EDX, FRm);
nkeynes@377
  2028
    push_dr(R_EDX, FRn);
nkeynes@377
  2029
    FADDP_st(1);
nkeynes@377
  2030
    pop_dr(R_EDX, FRn);
nkeynes@380
  2031
    JMP_TARGET(end);
nkeynes@417
  2032
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2033
:}
nkeynes@377
  2034
FDIV FRm, FRn {:  
nkeynes@377
  2035
    check_fpuen();
nkeynes@375
  2036
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2037
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2038
    load_fr_bank( R_EDX );
nkeynes@380
  2039
    JNE_rel8(13, doubleprec);
nkeynes@377
  2040
    push_fr(R_EDX, FRn);
nkeynes@377
  2041
    push_fr(R_EDX, FRm);
nkeynes@377
  2042
    FDIVP_st(1);
nkeynes@377
  2043
    pop_fr(R_EDX, FRn);
nkeynes@380
  2044
    JMP_rel8(11, end);
nkeynes@380
  2045
    JMP_TARGET(doubleprec);
nkeynes@377
  2046
    push_dr(R_EDX, FRn);
nkeynes@377
  2047
    push_dr(R_EDX, FRm);
nkeynes@377
  2048
    FDIVP_st(1);
nkeynes@377
  2049
    pop_dr(R_EDX, FRn);
nkeynes@380
  2050
    JMP_TARGET(end);
nkeynes@417
  2051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2052
:}
nkeynes@375
  2053
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2054
    check_fpuen();
nkeynes@375
  2055
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2056
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2057
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2058
    JNE_rel8(18, doubleprec);
nkeynes@375
  2059
    push_fr( R_EDX, 0 );
nkeynes@375
  2060
    push_fr( R_EDX, FRm );
nkeynes@375
  2061
    FMULP_st(1);
nkeynes@375
  2062
    push_fr( R_EDX, FRn );
nkeynes@375
  2063
    FADDP_st(1);
nkeynes@375
  2064
    pop_fr( R_EDX, FRn );
nkeynes@380
  2065
    JMP_rel8(16, end);
nkeynes@380
  2066
    JMP_TARGET(doubleprec);
nkeynes@375
  2067
    push_dr( R_EDX, 0 );
nkeynes@375
  2068
    push_dr( R_EDX, FRm );
nkeynes@375
  2069
    FMULP_st(1);
nkeynes@375
  2070
    push_dr( R_EDX, FRn );
nkeynes@375
  2071
    FADDP_st(1);
nkeynes@375
  2072
    pop_dr( R_EDX, FRn );
nkeynes@380
  2073
    JMP_TARGET(end);
nkeynes@417
  2074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2075
:}
nkeynes@375
  2076
nkeynes@377
  2077
FMUL FRm, FRn {:  
nkeynes@377
  2078
    check_fpuen();
nkeynes@377
  2079
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2080
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2081
    load_fr_bank( R_EDX );
nkeynes@380
  2082
    JNE_rel8(13, doubleprec);
nkeynes@377
  2083
    push_fr(R_EDX, FRm);
nkeynes@377
  2084
    push_fr(R_EDX, FRn);
nkeynes@377
  2085
    FMULP_st(1);
nkeynes@377
  2086
    pop_fr(R_EDX, FRn);
nkeynes@380
  2087
    JMP_rel8(11, end);
nkeynes@380
  2088
    JMP_TARGET(doubleprec);
nkeynes@377
  2089
    push_dr(R_EDX, FRm);
nkeynes@377
  2090
    push_dr(R_EDX, FRn);
nkeynes@377
  2091
    FMULP_st(1);
nkeynes@377
  2092
    pop_dr(R_EDX, FRn);
nkeynes@380
  2093
    JMP_TARGET(end);
nkeynes@417
  2094
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2095
:}
nkeynes@377
  2096
FNEG FRn {:  
nkeynes@377
  2097
    check_fpuen();
nkeynes@377
  2098
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2099
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2100
    load_fr_bank( R_EDX );
nkeynes@380
  2101
    JNE_rel8(10, doubleprec);
nkeynes@377
  2102
    push_fr(R_EDX, FRn);
nkeynes@377
  2103
    FCHS_st0();
nkeynes@377
  2104
    pop_fr(R_EDX, FRn);
nkeynes@380
  2105
    JMP_rel8(8, end);
nkeynes@380
  2106
    JMP_TARGET(doubleprec);
nkeynes@377
  2107
    push_dr(R_EDX, FRn);
nkeynes@377
  2108
    FCHS_st0();
nkeynes@377
  2109
    pop_dr(R_EDX, FRn);
nkeynes@380
  2110
    JMP_TARGET(end);
nkeynes@417
  2111
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2112
:}
nkeynes@377
  2113
FSRRA FRn {:  
nkeynes@377
  2114
    check_fpuen();
nkeynes@377
  2115
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2116
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2117
    load_fr_bank( R_EDX );
nkeynes@380
  2118
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2119
    FLD1_st0();
nkeynes@377
  2120
    push_fr(R_EDX, FRn);
nkeynes@377
  2121
    FSQRT_st0();
nkeynes@377
  2122
    FDIVP_st(1);
nkeynes@377
  2123
    pop_fr(R_EDX, FRn);
nkeynes@380
  2124
    JMP_TARGET(end);
nkeynes@417
  2125
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2126
:}
nkeynes@377
  2127
FSQRT FRn {:  
nkeynes@377
  2128
    check_fpuen();
nkeynes@377
  2129
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2130
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2131
    load_fr_bank( R_EDX );
nkeynes@380
  2132
    JNE_rel8(10, doubleprec);
nkeynes@377
  2133
    push_fr(R_EDX, FRn);
nkeynes@377
  2134
    FSQRT_st0();
nkeynes@377
  2135
    pop_fr(R_EDX, FRn);
nkeynes@380
  2136
    JMP_rel8(8, end);
nkeynes@380
  2137
    JMP_TARGET(doubleprec);
nkeynes@377
  2138
    push_dr(R_EDX, FRn);
nkeynes@377
  2139
    FSQRT_st0();
nkeynes@377
  2140
    pop_dr(R_EDX, FRn);
nkeynes@380
  2141
    JMP_TARGET(end);
nkeynes@417
  2142
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2143
:}
nkeynes@377
  2144
FSUB FRm, FRn {:  
nkeynes@377
  2145
    check_fpuen();
nkeynes@377
  2146
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2147
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2148
    load_fr_bank( R_EDX );
nkeynes@380
  2149
    JNE_rel8(13, doubleprec);
nkeynes@377
  2150
    push_fr(R_EDX, FRn);
nkeynes@377
  2151
    push_fr(R_EDX, FRm);
nkeynes@388
  2152
    FSUBP_st(1);
nkeynes@377
  2153
    pop_fr(R_EDX, FRn);
nkeynes@380
  2154
    JMP_rel8(11, end);
nkeynes@380
  2155
    JMP_TARGET(doubleprec);
nkeynes@377
  2156
    push_dr(R_EDX, FRn);
nkeynes@377
  2157
    push_dr(R_EDX, FRm);
nkeynes@388
  2158
    FSUBP_st(1);
nkeynes@377
  2159
    pop_dr(R_EDX, FRn);
nkeynes@380
  2160
    JMP_TARGET(end);
nkeynes@417
  2161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2162
:}
nkeynes@377
  2163
nkeynes@377
  2164
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2165
    check_fpuen();
nkeynes@377
  2166
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2167
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2168
    load_fr_bank( R_EDX );
nkeynes@380
  2169
    JNE_rel8(8, doubleprec);
nkeynes@377
  2170
    push_fr(R_EDX, FRm);
nkeynes@377
  2171
    push_fr(R_EDX, FRn);
nkeynes@380
  2172
    JMP_rel8(6, end);
nkeynes@380
  2173
    JMP_TARGET(doubleprec);
nkeynes@377
  2174
    push_dr(R_EDX, FRm);
nkeynes@377
  2175
    push_dr(R_EDX, FRn);
nkeynes@382
  2176
    JMP_TARGET(end);
nkeynes@377
  2177
    FCOMIP_st(1);
nkeynes@377
  2178
    SETE_t();
nkeynes@377
  2179
    FPOP_st();
nkeynes@417
  2180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2181
:}
nkeynes@377
  2182
FCMP/GT FRm, FRn {:  
nkeynes@377
  2183
    check_fpuen();
nkeynes@377
  2184
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2185
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2186
    load_fr_bank( R_EDX );
nkeynes@380
  2187
    JNE_rel8(8, doubleprec);
nkeynes@377
  2188
    push_fr(R_EDX, FRm);
nkeynes@377
  2189
    push_fr(R_EDX, FRn);
nkeynes@380
  2190
    JMP_rel8(6, end);
nkeynes@380
  2191
    JMP_TARGET(doubleprec);
nkeynes@377
  2192
    push_dr(R_EDX, FRm);
nkeynes@377
  2193
    push_dr(R_EDX, FRn);
nkeynes@380
  2194
    JMP_TARGET(end);
nkeynes@377
  2195
    FCOMIP_st(1);
nkeynes@377
  2196
    SETA_t();
nkeynes@377
  2197
    FPOP_st();
nkeynes@417
  2198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2199
:}
nkeynes@377
  2200
nkeynes@377
  2201
FSCA FPUL, FRn {:  
nkeynes@377
  2202
    check_fpuen();
nkeynes@388
  2203
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2204
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2205
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2206
    load_fr_bank( R_ECX );
nkeynes@388
  2207
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2208
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2209
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2210
    JMP_TARGET(doubleprec);
nkeynes@417
  2211
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2212
:}
nkeynes@377
  2213
FIPR FVm, FVn {:  
nkeynes@377
  2214
    check_fpuen();
nkeynes@388
  2215
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2216
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2217
    JNE_rel8(44, doubleprec);
nkeynes@388
  2218
    
nkeynes@388
  2219
    load_fr_bank( R_ECX );
nkeynes@388
  2220
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2221
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2222
    FMULP_st(1);
nkeynes@388
  2223
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2224
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2225
    FMULP_st(1);
nkeynes@388
  2226
    FADDP_st(1);
nkeynes@388
  2227
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2228
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2229
    FMULP_st(1);
nkeynes@388
  2230
    FADDP_st(1);
nkeynes@388
  2231
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2232
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2233
    FMULP_st(1);
nkeynes@388
  2234
    FADDP_st(1);
nkeynes@388
  2235
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2236
    JMP_TARGET(doubleprec);
nkeynes@417
  2237
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2238
:}
nkeynes@377
  2239
FTRV XMTRX, FVn {:  
nkeynes@377
  2240
    check_fpuen();
nkeynes@388
  2241
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2242
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2243
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2244
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2245
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2246
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2247
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2248
    JMP_TARGET(doubleprec);
nkeynes@417
  2249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2250
:}
nkeynes@377
  2251
nkeynes@377
  2252
FRCHG {:  
nkeynes@377
  2253
    check_fpuen();
nkeynes@377
  2254
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2255
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2256
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2257
    update_fr_bank( R_ECX );
nkeynes@417
  2258
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2259
:}
nkeynes@377
  2260
FSCHG {:  
nkeynes@377
  2261
    check_fpuen();
nkeynes@377
  2262
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2263
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2264
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2265
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2266
:}
nkeynes@359
  2267
nkeynes@359
  2268
/* Processor control instructions */
nkeynes@368
  2269
LDC Rm, SR {:
nkeynes@386
  2270
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2271
	SLOTILLEGAL();
nkeynes@386
  2272
    } else {
nkeynes@386
  2273
	check_priv();
nkeynes@386
  2274
	load_reg( R_EAX, Rm );
nkeynes@386
  2275
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2276
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2277
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2278
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2279
    }
nkeynes@368
  2280
:}
nkeynes@359
  2281
LDC Rm, GBR {: 
nkeynes@359
  2282
    load_reg( R_EAX, Rm );
nkeynes@359
  2283
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2284
:}
nkeynes@359
  2285
LDC Rm, VBR {:  
nkeynes@386
  2286
    check_priv();
nkeynes@359
  2287
    load_reg( R_EAX, Rm );
nkeynes@359
  2288
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC Rm, SSR {:  
nkeynes@386
  2292
    check_priv();
nkeynes@359
  2293
    load_reg( R_EAX, Rm );
nkeynes@359
  2294
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2296
:}
nkeynes@359
  2297
LDC Rm, SGR {:  
nkeynes@386
  2298
    check_priv();
nkeynes@359
  2299
    load_reg( R_EAX, Rm );
nkeynes@359
  2300
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2301
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2302
:}
nkeynes@359
  2303
LDC Rm, SPC {:  
nkeynes@386
  2304
    check_priv();
nkeynes@359
  2305
    load_reg( R_EAX, Rm );
nkeynes@359
  2306
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2307
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
:}
nkeynes@359
  2309
LDC Rm, DBR {:  
nkeynes@386
  2310
    check_priv();
nkeynes@359
  2311
    load_reg( R_EAX, Rm );
nkeynes@359
  2312
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2314
:}
nkeynes@374
  2315
LDC Rm, Rn_BANK {:  
nkeynes@386
  2316
    check_priv();
nkeynes@374
  2317
    load_reg( R_EAX, Rm );
nkeynes@374
  2318
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2320
:}
nkeynes@359
  2321
LDC.L @Rm+, GBR {:  
nkeynes@359
  2322
    load_reg( R_EAX, Rm );
nkeynes@395
  2323
    check_ralign32( R_EAX );
nkeynes@586
  2324
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2325
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2326
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2327
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2328
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2329
:}
nkeynes@368
  2330
LDC.L @Rm+, SR {:
nkeynes@386
  2331
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2332
	SLOTILLEGAL();
nkeynes@386
  2333
    } else {
nkeynes@586
  2334
	check_priv();
nkeynes@386
  2335
	load_reg( R_EAX, Rm );
nkeynes@395
  2336
	check_ralign32( R_EAX );
nkeynes@586
  2337
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2338
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2339
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2340
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2341
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2342
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2343
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2344
    }
nkeynes@359
  2345
:}
nkeynes@359
  2346
LDC.L @Rm+, VBR {:  
nkeynes@586
  2347
    check_priv();
nkeynes@359
  2348
    load_reg( R_EAX, Rm );
nkeynes@395
  2349
    check_ralign32( R_EAX );
nkeynes@586
  2350
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2351
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2352
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2353
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2355
:}
nkeynes@359
  2356
LDC.L @Rm+, SSR {:
nkeynes@586
  2357
    check_priv();
nkeynes@359
  2358
    load_reg( R_EAX, Rm );
nkeynes@416
  2359
    check_ralign32( R_EAX );
nkeynes@586
  2360
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2361
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2362
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2363
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2365
:}
nkeynes@359
  2366
LDC.L @Rm+, SGR {:  
nkeynes@586
  2367
    check_priv();
nkeynes@359
  2368
    load_reg( R_EAX, Rm );
nkeynes@395
  2369
    check_ralign32( R_EAX );
nkeynes@586
  2370
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2371
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2372
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2373
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2374
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2375
:}
nkeynes@359
  2376
LDC.L @Rm+, SPC {:  
nkeynes@586
  2377
    check_priv();
nkeynes@359
  2378
    load_reg( R_EAX, Rm );
nkeynes@395
  2379
    check_ralign32( R_EAX );
nkeynes@586
  2380
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2381
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2382
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2383
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2385
:}
nkeynes@359
  2386
LDC.L @Rm+, DBR {:  
nkeynes@586
  2387
    check_priv();
nkeynes@359
  2388
    load_reg( R_EAX, Rm );
nkeynes@395
  2389
    check_ralign32( R_EAX );
nkeynes@586
  2390
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2391
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2392
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2393
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2395
:}
nkeynes@359
  2396
LDC.L @Rm+, Rn_BANK {:  
nkeynes@586
  2397
    check_priv();
nkeynes@374
  2398
    load_reg( R_EAX, Rm );
nkeynes@395
  2399
    check_ralign32( R_EAX );
nkeynes@586
  2400
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2401
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2402
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2403
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2405
:}
nkeynes@359
  2406
LDS Rm, FPSCR {:  
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@359
  2408
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2409
    update_fr_bank( R_EAX );
nkeynes@417
  2410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2411
:}
nkeynes@359
  2412
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2413
    load_reg( R_EAX, Rm );
nkeynes@395
  2414
    check_ralign32( R_EAX );
nkeynes@586
  2415
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2416
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2417
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2418
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2419
    update_fr_bank( R_EAX );
nkeynes@417
  2420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2421
:}
nkeynes@359
  2422
LDS Rm, FPUL {:  
nkeynes@359
  2423
    load_reg( R_EAX, Rm );
nkeynes@359
  2424
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2425
:}
nkeynes@359
  2426
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2427
    load_reg( R_EAX, Rm );
nkeynes@395
  2428
    check_ralign32( R_EAX );
nkeynes@586
  2429
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2430
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2431
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2432
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2433
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2434
:}
nkeynes@359
  2435
LDS Rm, MACH {: 
nkeynes@359
  2436
    load_reg( R_EAX, Rm );
nkeynes@359
  2437
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2438
:}
nkeynes@359
  2439
LDS.L @Rm+, MACH {:  
nkeynes@359
  2440
    load_reg( R_EAX, Rm );
nkeynes@395
  2441
    check_ralign32( R_EAX );
nkeynes@586
  2442
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2443
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2444
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2445
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2447
:}
nkeynes@359
  2448
LDS Rm, MACL {:  
nkeynes@359
  2449
    load_reg( R_EAX, Rm );
nkeynes@359
  2450
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2451
:}
nkeynes@359
  2452
LDS.L @Rm+, MACL {:  
nkeynes@359
  2453
    load_reg( R_EAX, Rm );
nkeynes@395
  2454
    check_ralign32( R_EAX );
nkeynes@586
  2455
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2456
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2457
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2458
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2459
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2460
:}
nkeynes@359
  2461
LDS Rm, PR {:  
nkeynes@359
  2462
    load_reg( R_EAX, Rm );
nkeynes@359
  2463
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2464
:}
nkeynes@359
  2465
LDS.L @Rm+, PR {:  
nkeynes@359
  2466
    load_reg( R_EAX, Rm );
nkeynes@395
  2467
    check_ralign32( R_EAX );
nkeynes@586
  2468
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2469
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2470
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2471
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2473
:}
nkeynes@550
  2474
LDTLB {:  
nkeynes@553
  2475
    call_func0( MMU_ldtlb );
nkeynes@550
  2476
:}
nkeynes@359
  2477
OCBI @Rn {:  :}
nkeynes@359
  2478
OCBP @Rn {:  :}
nkeynes@359
  2479
OCBWB @Rn {:  :}
nkeynes@374
  2480
PREF @Rn {:
nkeynes@374
  2481
    load_reg( R_EAX, Rn );
nkeynes@532
  2482
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2483
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2484
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
  2485
    JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
  2486
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2487
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2488
    JE_exc(-1);
nkeynes@380
  2489
    JMP_TARGET(end);
nkeynes@417
  2490
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2491
:}
nkeynes@388
  2492
SLEEP {: 
nkeynes@388
  2493
    check_priv();
nkeynes@388
  2494
    call_func0( sh4_sleep );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2496
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2497
    return 2;
nkeynes@388
  2498
:}
nkeynes@386
  2499
STC SR, Rn {:
nkeynes@386
  2500
    check_priv();
nkeynes@386
  2501
    call_func0(sh4_read_sr);
nkeynes@386
  2502
    store_reg( R_EAX, Rn );
nkeynes@417
  2503
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2504
:}
nkeynes@359
  2505
STC GBR, Rn {:  
nkeynes@359
  2506
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2507
    store_reg( R_EAX, Rn );
nkeynes@359
  2508
:}
nkeynes@359
  2509
STC VBR, Rn {:  
nkeynes@386
  2510
    check_priv();
nkeynes@359
  2511
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2512
    store_reg( R_EAX, Rn );
nkeynes@417
  2513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2514
:}
nkeynes@359
  2515
STC SSR, Rn {:  
nkeynes@386
  2516
    check_priv();
nkeynes@359
  2517
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2518
    store_reg( R_EAX, Rn );
nkeynes@417
  2519
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2520
:}
nkeynes@359
  2521
STC SPC, Rn {:  
nkeynes@386
  2522
    check_priv();
nkeynes@359
  2523
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2524
    store_reg( R_EAX, Rn );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
STC SGR, Rn {:  
nkeynes@386
  2528
    check_priv();
nkeynes@359
  2529
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2530
    store_reg( R_EAX, Rn );
nkeynes@417
  2531
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2532
:}
nkeynes@359
  2533
STC DBR, Rn {:  
nkeynes@386
  2534
    check_priv();
nkeynes@359
  2535
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2536
    store_reg( R_EAX, Rn );
nkeynes@417
  2537
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2538
:}
nkeynes@374
  2539
STC Rm_BANK, Rn {:
nkeynes@386
  2540
    check_priv();
nkeynes@374
  2541
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2542
    store_reg( R_EAX, Rn );
nkeynes@417
  2543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2544
:}
nkeynes@374
  2545
STC.L SR, @-Rn {:
nkeynes@586
  2546
    check_priv();
nkeynes@586
  2547
    load_reg( R_EAX, Rn );
nkeynes@586
  2548
    check_walign32( R_EAX );
nkeynes@586
  2549
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2550
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2551
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2552
    call_func0( sh4_read_sr );
nkeynes@586
  2553
    POP_realigned_r32( R_ECX );
nkeynes@586
  2554
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2555
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2556
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2557
:}
nkeynes@359
  2558
STC.L VBR, @-Rn {:  
nkeynes@586
  2559
    check_priv();
nkeynes@586
  2560
    load_reg( R_EAX, Rn );
nkeynes@586
  2561
    check_walign32( R_EAX );
nkeynes@586
  2562
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2563
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2564
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2565
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2566
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2567
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2568
:}
nkeynes@359
  2569
STC.L SSR, @-Rn {:  
nkeynes@586
  2570
    check_priv();
nkeynes@586
  2571
    load_reg( R_EAX, Rn );
nkeynes@586
  2572
    check_walign32( R_EAX );
nkeynes@586
  2573
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2574
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2575
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2576
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2577
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2579
:}
nkeynes@416
  2580
STC.L SPC, @-Rn {:
nkeynes@586
  2581
    check_priv();
nkeynes@586
  2582
    load_reg( R_EAX, Rn );
nkeynes@586
  2583
    check_walign32( R_EAX );
nkeynes@586
  2584
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2585
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2586
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2587
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2588
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2589
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2590
:}
nkeynes@359
  2591
STC.L SGR, @-Rn {:  
nkeynes@586
  2592
    check_priv();
nkeynes@586
  2593
    load_reg( R_EAX, Rn );
nkeynes@586
  2594
    check_walign32( R_EAX );
nkeynes@586
  2595
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2596
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2597
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2598
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2599
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2600
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2601
:}
nkeynes@359
  2602
STC.L DBR, @-Rn {:  
nkeynes@586
  2603
    check_priv();
nkeynes@586
  2604
    load_reg( R_EAX, Rn );
nkeynes@586
  2605
    check_walign32( R_EAX );
nkeynes@586
  2606
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2607
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2608
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2609
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2610
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2612
:}
nkeynes@374
  2613
STC.L Rm_BANK, @-Rn {:  
nkeynes@586
  2614
    check_priv();
nkeynes@586
  2615
    load_reg( R_EAX, Rn );
nkeynes@586
  2616
    check_walign32( R_EAX );
nkeynes@586
  2617
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2618
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2619
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2620
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2621
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2623
:}
nkeynes@359
  2624
STC.L GBR, @-Rn {:  
nkeynes@586
  2625
    load_reg( R_EAX, Rn );
nkeynes@586
  2626
    check_walign32( R_EAX );
nkeynes@586
  2627
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2628
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2629
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2630
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2631
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2632
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2633
:}
nkeynes@359
  2634
STS FPSCR, Rn {:  
nkeynes@359
  2635
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2636
    store_reg( R_EAX, Rn );
nkeynes@359
  2637
:}
nkeynes@359
  2638
STS.L FPSCR, @-Rn {:  
nkeynes@586
  2639
    load_reg( R_EAX, Rn );
nkeynes@586
  2640
    check_walign32( R_EAX );
nkeynes@586
  2641
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2642
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2643
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2644
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2645
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2646
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2647
:}
nkeynes@359
  2648
STS FPUL, Rn {:  
nkeynes@359
  2649
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2650
    store_reg( R_EAX, Rn );
nkeynes@359
  2651
:}
nkeynes@359
  2652
STS.L FPUL, @-Rn {:  
nkeynes@586
  2653
    load_reg( R_EAX, Rn );
nkeynes@586
  2654
    check_walign32( R_EAX );
nkeynes@586
  2655
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2656
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2657
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2658
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2659
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2660
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2661
:}
nkeynes@359
  2662
STS MACH, Rn {:  
nkeynes@359
  2663
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2664
    store_reg( R_EAX, Rn );
nkeynes@359
  2665
:}
nkeynes@359
  2666
STS.L MACH, @-Rn {:  
nkeynes@586
  2667
    load_reg( R_EAX, Rn );
nkeynes@586
  2668
    check_walign32( R_EAX );
nkeynes@586
  2669
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2670
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2671
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2672
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2673
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2674
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2675
:}
nkeynes@359
  2676
STS MACL, Rn {:  
nkeynes@359
  2677
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2678
    store_reg( R_EAX, Rn );
nkeynes@359
  2679
:}
nkeynes@359
  2680
STS.L MACL, @-Rn {:  
nkeynes@586
  2681
    load_reg( R_EAX, Rn );
nkeynes@586
  2682
    check_walign32( R_EAX );
nkeynes@586
  2683
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2684
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2685
    load_spreg( R_EDX, R_MACL );
nkeynes@586
  2686
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2687
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2688
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2689
:}
nkeynes@359
  2690
STS PR, Rn {:  
nkeynes@359
  2691
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2692
    store_reg( R_EAX, Rn );
nkeynes@359
  2693
:}
nkeynes@359
  2694
STS.L PR, @-Rn {:  
nkeynes@586
  2695
    load_reg( R_EAX, Rn );
nkeynes@586
  2696
    check_walign32( R_EAX );
nkeynes@586
  2697
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2698
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2699
    load_spreg( R_EDX, R_PR );
nkeynes@586
  2700
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2701
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2702
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2703
:}
nkeynes@359
  2704
nkeynes@359
  2705
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2706
%%
nkeynes@590
  2707
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359
  2708
    return 0;
nkeynes@359
  2709
}
.