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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 939:6f2302afeb89
prev937:81b0c79d9788
next941:c67574ed4355
author nkeynes
date Sat Jan 03 03:30:26 2009 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change MMU work-in-progress
* Move SDRAM out into separate sdram.c
* Move all page-table management into mmu.c
* Convert UTLB management to use the new page-tables
* Rip out all calls to mmu_vma_to_phys_* and replace with direct access
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "sh4/mmu.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            JMP_exc(EXC_SLOT_ILLEGAL); \
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        } else { \
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            JMP_exc(EXC_ILLEGAL ); \
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        } \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
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 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
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 */
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#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
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        call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
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#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
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        call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); } 
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#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
nkeynes@939
   307
#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
nkeynes@368
   308
nkeynes@937
   309
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   310
nkeynes@539
   311
/****** Import appropriate calling conventions ******/
nkeynes@675
   312
#if SIZEOF_VOID_P == 8
nkeynes@539
   313
#include "sh4/ia64abi.h"
nkeynes@675
   314
#else /* 32-bit system */
nkeynes@539
   315
#include "sh4/ia32abi.h"
nkeynes@539
   316
#endif
nkeynes@539
   317
nkeynes@901
   318
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   319
{
nkeynes@927
   320
    enter_block();
nkeynes@901
   321
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   322
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   323
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   324
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   325
    sh4_x86.block_start_pc = pc;
nkeynes@939
   326
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   328
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   329
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   330
}
nkeynes@901
   331
nkeynes@901
   332
nkeynes@593
   333
uint32_t sh4_translate_end_block_size()
nkeynes@593
   334
{
nkeynes@596
   335
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   336
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   337
    } else {
nkeynes@901
   338
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   339
    }
nkeynes@593
   340
}
nkeynes@593
   341
nkeynes@593
   342
nkeynes@590
   343
/**
nkeynes@590
   344
 * Embed a breakpoint into the generated code
nkeynes@590
   345
 */
nkeynes@586
   346
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   347
{
nkeynes@591
   348
    load_imm32( R_EAX, pc );
nkeynes@591
   349
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   351
}
nkeynes@590
   352
nkeynes@601
   353
nkeynes@601
   354
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   355
nkeynes@590
   356
/**
nkeynes@590
   357
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   358
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   359
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   360
 *
nkeynes@601
   361
 * Performs:
nkeynes@601
   362
 *   Set PC = endpc
nkeynes@601
   363
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   364
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   365
 *   Call sh4_execute_instruction
nkeynes@601
   366
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   367
 */
nkeynes@601
   368
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   369
{
nkeynes@590
   370
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   371
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   372
    
nkeynes@601
   373
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   374
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   375
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   376
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   377
nkeynes@590
   378
    call_func0( sh4_execute_instruction );    
nkeynes@601
   379
    load_spreg( R_EAX, R_PC );
nkeynes@590
   380
    if( sh4_x86.tlb_on ) {
nkeynes@590
   381
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   382
    } else {
nkeynes@590
   383
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   384
    }
nkeynes@926
   385
    exit_block();
nkeynes@590
   386
} 
nkeynes@539
   387
nkeynes@359
   388
/**
nkeynes@359
   389
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   390
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   391
 * 
nkeynes@586
   392
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   393
 *
nkeynes@359
   394
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   395
 * (eg a branch or 
nkeynes@359
   396
 */
nkeynes@590
   397
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   398
{
nkeynes@388
   399
    uint32_t ir;
nkeynes@586
   400
    /* Read instruction from icache */
nkeynes@586
   401
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   402
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   403
    
nkeynes@586
   404
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   405
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   406
    }
nkeynes@359
   407
%%
nkeynes@359
   408
/* ALU operations */
nkeynes@359
   409
ADD Rm, Rn {:
nkeynes@671
   410
    COUNT_INST(I_ADD);
nkeynes@359
   411
    load_reg( R_EAX, Rm );
nkeynes@359
   412
    load_reg( R_ECX, Rn );
nkeynes@359
   413
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   414
    store_reg( R_ECX, Rn );
nkeynes@417
   415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   416
:}
nkeynes@359
   417
ADD #imm, Rn {:  
nkeynes@671
   418
    COUNT_INST(I_ADDI);
nkeynes@939
   419
    ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   421
:}
nkeynes@359
   422
ADDC Rm, Rn {:
nkeynes@671
   423
    COUNT_INST(I_ADDC);
nkeynes@417
   424
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   425
        LDC_t();
nkeynes@417
   426
    }
nkeynes@359
   427
    load_reg( R_EAX, Rm );
nkeynes@359
   428
    load_reg( R_ECX, Rn );
nkeynes@359
   429
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   430
    store_reg( R_ECX, Rn );
nkeynes@359
   431
    SETC_t();
nkeynes@417
   432
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   433
:}
nkeynes@359
   434
ADDV Rm, Rn {:
nkeynes@671
   435
    COUNT_INST(I_ADDV);
nkeynes@359
   436
    load_reg( R_EAX, Rm );
nkeynes@359
   437
    load_reg( R_ECX, Rn );
nkeynes@359
   438
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   439
    store_reg( R_ECX, Rn );
nkeynes@359
   440
    SETO_t();
nkeynes@417
   441
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   442
:}
nkeynes@359
   443
AND Rm, Rn {:
nkeynes@671
   444
    COUNT_INST(I_AND);
nkeynes@359
   445
    load_reg( R_EAX, Rm );
nkeynes@359
   446
    load_reg( R_ECX, Rn );
nkeynes@359
   447
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   448
    store_reg( R_ECX, Rn );
nkeynes@417
   449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   450
:}
nkeynes@359
   451
AND #imm, R0 {:  
nkeynes@671
   452
    COUNT_INST(I_ANDI);
nkeynes@359
   453
    load_reg( R_EAX, 0 );
nkeynes@359
   454
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   455
    store_reg( R_EAX, 0 );
nkeynes@417
   456
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   457
:}
nkeynes@359
   458
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   459
    COUNT_INST(I_ANDB);
nkeynes@359
   460
    load_reg( R_EAX, 0 );
nkeynes@939
   461
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
   462
    MOV_r32_esp8(R_EAX, 0);
nkeynes@930
   463
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@930
   464
    MOV_esp8_r32(0, R_EAX);
nkeynes@905
   465
    AND_imm32_r32(imm, R_EDX );
nkeynes@930
   466
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   467
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   468
:}
nkeynes@359
   469
CMP/EQ Rm, Rn {:  
nkeynes@671
   470
    COUNT_INST(I_CMPEQ);
nkeynes@359
   471
    load_reg( R_EAX, Rm );
nkeynes@359
   472
    load_reg( R_ECX, Rn );
nkeynes@359
   473
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   474
    SETE_t();
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   476
:}
nkeynes@359
   477
CMP/EQ #imm, R0 {:  
nkeynes@671
   478
    COUNT_INST(I_CMPEQI);
nkeynes@359
   479
    load_reg( R_EAX, 0 );
nkeynes@359
   480
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   481
    SETE_t();
nkeynes@417
   482
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   483
:}
nkeynes@359
   484
CMP/GE Rm, Rn {:  
nkeynes@671
   485
    COUNT_INST(I_CMPGE);
nkeynes@359
   486
    load_reg( R_EAX, Rm );
nkeynes@359
   487
    load_reg( R_ECX, Rn );
nkeynes@359
   488
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   489
    SETGE_t();
nkeynes@417
   490
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   491
:}
nkeynes@359
   492
CMP/GT Rm, Rn {: 
nkeynes@671
   493
    COUNT_INST(I_CMPGT);
nkeynes@359
   494
    load_reg( R_EAX, Rm );
nkeynes@359
   495
    load_reg( R_ECX, Rn );
nkeynes@359
   496
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   497
    SETG_t();
nkeynes@417
   498
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/HI Rm, Rn {:  
nkeynes@671
   501
    COUNT_INST(I_CMPHI);
nkeynes@359
   502
    load_reg( R_EAX, Rm );
nkeynes@359
   503
    load_reg( R_ECX, Rn );
nkeynes@359
   504
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   505
    SETA_t();
nkeynes@417
   506
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   507
:}
nkeynes@359
   508
CMP/HS Rm, Rn {: 
nkeynes@671
   509
    COUNT_INST(I_CMPHS);
nkeynes@359
   510
    load_reg( R_EAX, Rm );
nkeynes@359
   511
    load_reg( R_ECX, Rn );
nkeynes@359
   512
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   513
    SETAE_t();
nkeynes@417
   514
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   515
 :}
nkeynes@359
   516
CMP/PL Rn {: 
nkeynes@671
   517
    COUNT_INST(I_CMPPL);
nkeynes@359
   518
    load_reg( R_EAX, Rn );
nkeynes@359
   519
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   520
    SETG_t();
nkeynes@417
   521
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   522
:}
nkeynes@359
   523
CMP/PZ Rn {:  
nkeynes@671
   524
    COUNT_INST(I_CMPPZ);
nkeynes@359
   525
    load_reg( R_EAX, Rn );
nkeynes@359
   526
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   527
    SETGE_t();
nkeynes@417
   528
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   529
:}
nkeynes@361
   530
CMP/STR Rm, Rn {:  
nkeynes@671
   531
    COUNT_INST(I_CMPSTR);
nkeynes@368
   532
    load_reg( R_EAX, Rm );
nkeynes@368
   533
    load_reg( R_ECX, Rn );
nkeynes@368
   534
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   535
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   536
    JE_rel8(target1);
nkeynes@669
   537
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   538
    JE_rel8(target2);
nkeynes@669
   539
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   540
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   541
    JE_rel8(target3);
nkeynes@669
   542
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   543
    JMP_TARGET(target1);
nkeynes@380
   544
    JMP_TARGET(target2);
nkeynes@380
   545
    JMP_TARGET(target3);
nkeynes@368
   546
    SETE_t();
nkeynes@417
   547
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   548
:}
nkeynes@361
   549
DIV0S Rm, Rn {:
nkeynes@671
   550
    COUNT_INST(I_DIV0S);
nkeynes@361
   551
    load_reg( R_EAX, Rm );
nkeynes@386
   552
    load_reg( R_ECX, Rn );
nkeynes@361
   553
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   554
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   555
    store_spreg( R_EAX, R_M );
nkeynes@361
   556
    store_spreg( R_ECX, R_Q );
nkeynes@361
   557
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   558
    SETNE_t();
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   560
:}
nkeynes@361
   561
DIV0U {:  
nkeynes@671
   562
    COUNT_INST(I_DIV0U);
nkeynes@361
   563
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   564
    store_spreg( R_EAX, R_Q );
nkeynes@361
   565
    store_spreg( R_EAX, R_M );
nkeynes@361
   566
    store_spreg( R_EAX, R_T );
nkeynes@417
   567
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   568
:}
nkeynes@386
   569
DIV1 Rm, Rn {:
nkeynes@671
   570
    COUNT_INST(I_DIV1);
nkeynes@386
   571
    load_spreg( R_ECX, R_M );
nkeynes@386
   572
    load_reg( R_EAX, Rn );
nkeynes@417
   573
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   574
	LDC_t();
nkeynes@417
   575
    }
nkeynes@386
   576
    RCL1_r32( R_EAX );
nkeynes@386
   577
    SETC_r8( R_DL ); // Q'
nkeynes@386
   578
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   579
    JE_rel8(mqequal);
nkeynes@386
   580
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   581
    JMP_rel8(end);
nkeynes@380
   582
    JMP_TARGET(mqequal);
nkeynes@386
   583
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   584
    JMP_TARGET(end);
nkeynes@386
   585
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   586
    SETC_r8(R_AL); // tmp1
nkeynes@386
   587
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   588
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   589
    store_spreg( R_ECX, R_Q );
nkeynes@386
   590
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   591
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   592
    store_spreg( R_EAX, R_T );
nkeynes@417
   593
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   594
:}
nkeynes@361
   595
DMULS.L Rm, Rn {:  
nkeynes@671
   596
    COUNT_INST(I_DMULS);
nkeynes@361
   597
    load_reg( R_EAX, Rm );
nkeynes@361
   598
    load_reg( R_ECX, Rn );
nkeynes@361
   599
    IMUL_r32(R_ECX);
nkeynes@361
   600
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   601
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   603
:}
nkeynes@361
   604
DMULU.L Rm, Rn {:  
nkeynes@671
   605
    COUNT_INST(I_DMULU);
nkeynes@361
   606
    load_reg( R_EAX, Rm );
nkeynes@361
   607
    load_reg( R_ECX, Rn );
nkeynes@361
   608
    MUL_r32(R_ECX);
nkeynes@361
   609
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   610
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   612
:}
nkeynes@359
   613
DT Rn {:  
nkeynes@671
   614
    COUNT_INST(I_DT);
nkeynes@359
   615
    load_reg( R_EAX, Rn );
nkeynes@382
   616
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   617
    store_reg( R_EAX, Rn );
nkeynes@359
   618
    SETE_t();
nkeynes@417
   619
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   620
:}
nkeynes@359
   621
EXTS.B Rm, Rn {:  
nkeynes@671
   622
    COUNT_INST(I_EXTSB);
nkeynes@359
   623
    load_reg( R_EAX, Rm );
nkeynes@359
   624
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   625
    store_reg( R_EAX, Rn );
nkeynes@359
   626
:}
nkeynes@361
   627
EXTS.W Rm, Rn {:  
nkeynes@671
   628
    COUNT_INST(I_EXTSW);
nkeynes@361
   629
    load_reg( R_EAX, Rm );
nkeynes@361
   630
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   631
    store_reg( R_EAX, Rn );
nkeynes@361
   632
:}
nkeynes@361
   633
EXTU.B Rm, Rn {:  
nkeynes@671
   634
    COUNT_INST(I_EXTUB);
nkeynes@361
   635
    load_reg( R_EAX, Rm );
nkeynes@361
   636
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   637
    store_reg( R_EAX, Rn );
nkeynes@361
   638
:}
nkeynes@361
   639
EXTU.W Rm, Rn {:  
nkeynes@671
   640
    COUNT_INST(I_EXTUW);
nkeynes@361
   641
    load_reg( R_EAX, Rm );
nkeynes@361
   642
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   643
    store_reg( R_EAX, Rn );
nkeynes@361
   644
:}
nkeynes@586
   645
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   646
    COUNT_INST(I_MACL);
nkeynes@586
   647
    if( Rm == Rn ) {
nkeynes@586
   648
	load_reg( R_EAX, Rm );
nkeynes@586
   649
	check_ralign32( R_EAX );
nkeynes@939
   650
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   651
	MOV_r32_esp8(R_EAX, 0);
nkeynes@939
   652
	load_reg( R_EAX, Rm );
nkeynes@939
   653
	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
   654
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
   655
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   656
    } else {
nkeynes@586
   657
	load_reg( R_EAX, Rm );
nkeynes@586
   658
	check_ralign32( R_EAX );
nkeynes@939
   659
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   660
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   661
	load_reg( R_EAX, Rn );
nkeynes@926
   662
	check_ralign32( R_EAX );
nkeynes@939
   663
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   664
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   665
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   666
    }
nkeynes@939
   667
    
nkeynes@939
   668
    IMUL_esp8( 0 );
nkeynes@386
   669
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   670
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   671
nkeynes@386
   672
    load_spreg( R_ECX, R_S );
nkeynes@386
   673
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   674
    JE_rel8( nosat );
nkeynes@386
   675
    call_func0( signsat48 );
nkeynes@386
   676
    JMP_TARGET( nosat );
nkeynes@417
   677
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   678
:}
nkeynes@386
   679
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   680
    COUNT_INST(I_MACW);
nkeynes@586
   681
    if( Rm == Rn ) {
nkeynes@586
   682
	load_reg( R_EAX, Rm );
nkeynes@586
   683
	check_ralign16( R_EAX );
nkeynes@939
   684
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   685
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@939
   686
	load_reg( R_EAX, Rm );
nkeynes@939
   687
	LEA_r32disp8_r32( R_EAX, 2, R_EAX );
nkeynes@939
   688
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   689
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   690
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   691
	// adding a page-boundary check to skip the second translation
nkeynes@586
   692
    } else {
nkeynes@586
   693
	load_reg( R_EAX, Rm );
nkeynes@586
   694
	check_ralign16( R_EAX );
nkeynes@939
   695
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   696
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   697
	load_reg( R_EAX, Rn );
nkeynes@926
   698
	check_ralign16( R_EAX );
nkeynes@939
   699
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   700
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   701
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   702
    }
nkeynes@939
   703
    IMUL_esp8( 0 );
nkeynes@386
   704
    load_spreg( R_ECX, R_S );
nkeynes@386
   705
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   706
    JE_rel8( nosat );
nkeynes@386
   707
nkeynes@386
   708
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   709
    JNO_rel8( end );            // 2
nkeynes@386
   710
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   711
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   712
    JS_rel8( positive );        // 2
nkeynes@386
   713
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   714
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   715
    JMP_rel8(end2);           // 2
nkeynes@386
   716
nkeynes@386
   717
    JMP_TARGET(positive);
nkeynes@386
   718
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   719
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   720
    JMP_rel8(end3);            // 2
nkeynes@386
   721
nkeynes@386
   722
    JMP_TARGET(nosat);
nkeynes@386
   723
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   724
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   725
    JMP_TARGET(end);
nkeynes@386
   726
    JMP_TARGET(end2);
nkeynes@386
   727
    JMP_TARGET(end3);
nkeynes@417
   728
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   729
:}
nkeynes@359
   730
MOVT Rn {:  
nkeynes@671
   731
    COUNT_INST(I_MOVT);
nkeynes@359
   732
    load_spreg( R_EAX, R_T );
nkeynes@359
   733
    store_reg( R_EAX, Rn );
nkeynes@359
   734
:}
nkeynes@361
   735
MUL.L Rm, Rn {:  
nkeynes@671
   736
    COUNT_INST(I_MULL);
nkeynes@361
   737
    load_reg( R_EAX, Rm );
nkeynes@361
   738
    load_reg( R_ECX, Rn );
nkeynes@361
   739
    MUL_r32( R_ECX );
nkeynes@361
   740
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   741
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   742
:}
nkeynes@374
   743
MULS.W Rm, Rn {:
nkeynes@671
   744
    COUNT_INST(I_MULSW);
nkeynes@374
   745
    load_reg16s( R_EAX, Rm );
nkeynes@374
   746
    load_reg16s( R_ECX, Rn );
nkeynes@374
   747
    MUL_r32( R_ECX );
nkeynes@374
   748
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   749
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   750
:}
nkeynes@374
   751
MULU.W Rm, Rn {:  
nkeynes@671
   752
    COUNT_INST(I_MULUW);
nkeynes@374
   753
    load_reg16u( R_EAX, Rm );
nkeynes@374
   754
    load_reg16u( R_ECX, Rn );
nkeynes@374
   755
    MUL_r32( R_ECX );
nkeynes@374
   756
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   758
:}
nkeynes@359
   759
NEG Rm, Rn {:
nkeynes@671
   760
    COUNT_INST(I_NEG);
nkeynes@359
   761
    load_reg( R_EAX, Rm );
nkeynes@359
   762
    NEG_r32( R_EAX );
nkeynes@359
   763
    store_reg( R_EAX, Rn );
nkeynes@417
   764
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   765
:}
nkeynes@359
   766
NEGC Rm, Rn {:  
nkeynes@671
   767
    COUNT_INST(I_NEGC);
nkeynes@359
   768
    load_reg( R_EAX, Rm );
nkeynes@359
   769
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   770
    LDC_t();
nkeynes@359
   771
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   772
    store_reg( R_ECX, Rn );
nkeynes@359
   773
    SETC_t();
nkeynes@417
   774
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   775
:}
nkeynes@359
   776
NOT Rm, Rn {:  
nkeynes@671
   777
    COUNT_INST(I_NOT);
nkeynes@359
   778
    load_reg( R_EAX, Rm );
nkeynes@359
   779
    NOT_r32( R_EAX );
nkeynes@359
   780
    store_reg( R_EAX, Rn );
nkeynes@417
   781
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   782
:}
nkeynes@359
   783
OR Rm, Rn {:  
nkeynes@671
   784
    COUNT_INST(I_OR);
nkeynes@359
   785
    load_reg( R_EAX, Rm );
nkeynes@359
   786
    load_reg( R_ECX, Rn );
nkeynes@359
   787
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   788
    store_reg( R_ECX, Rn );
nkeynes@417
   789
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   790
:}
nkeynes@359
   791
OR #imm, R0 {:
nkeynes@671
   792
    COUNT_INST(I_ORI);
nkeynes@359
   793
    load_reg( R_EAX, 0 );
nkeynes@359
   794
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   795
    store_reg( R_EAX, 0 );
nkeynes@417
   796
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   797
:}
nkeynes@374
   798
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   799
    COUNT_INST(I_ORB);
nkeynes@374
   800
    load_reg( R_EAX, 0 );
nkeynes@939
   801
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
   802
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
   803
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@930
   804
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
   805
    OR_imm32_r32(imm, R_EDX );
nkeynes@930
   806
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   807
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   808
:}
nkeynes@359
   809
ROTCL Rn {:
nkeynes@671
   810
    COUNT_INST(I_ROTCL);
nkeynes@359
   811
    load_reg( R_EAX, Rn );
nkeynes@417
   812
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   813
	LDC_t();
nkeynes@417
   814
    }
nkeynes@359
   815
    RCL1_r32( R_EAX );
nkeynes@359
   816
    store_reg( R_EAX, Rn );
nkeynes@359
   817
    SETC_t();
nkeynes@417
   818
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   819
:}
nkeynes@359
   820
ROTCR Rn {:  
nkeynes@671
   821
    COUNT_INST(I_ROTCR);
nkeynes@359
   822
    load_reg( R_EAX, Rn );
nkeynes@417
   823
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   824
	LDC_t();
nkeynes@417
   825
    }
nkeynes@359
   826
    RCR1_r32( R_EAX );
nkeynes@359
   827
    store_reg( R_EAX, Rn );
nkeynes@359
   828
    SETC_t();
nkeynes@417
   829
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   830
:}
nkeynes@359
   831
ROTL Rn {:  
nkeynes@671
   832
    COUNT_INST(I_ROTL);
nkeynes@359
   833
    load_reg( R_EAX, Rn );
nkeynes@359
   834
    ROL1_r32( R_EAX );
nkeynes@359
   835
    store_reg( R_EAX, Rn );
nkeynes@359
   836
    SETC_t();
nkeynes@417
   837
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   838
:}
nkeynes@359
   839
ROTR Rn {:  
nkeynes@671
   840
    COUNT_INST(I_ROTR);
nkeynes@359
   841
    load_reg( R_EAX, Rn );
nkeynes@359
   842
    ROR1_r32( R_EAX );
nkeynes@359
   843
    store_reg( R_EAX, Rn );
nkeynes@359
   844
    SETC_t();
nkeynes@417
   845
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   846
:}
nkeynes@359
   847
SHAD Rm, Rn {:
nkeynes@671
   848
    COUNT_INST(I_SHAD);
nkeynes@359
   849
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   850
    load_reg( R_EAX, Rn );
nkeynes@361
   851
    load_reg( R_ECX, Rm );
nkeynes@361
   852
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   853
    JGE_rel8(doshl);
nkeynes@361
   854
                    
nkeynes@361
   855
    NEG_r32( R_ECX );      // 2
nkeynes@361
   856
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   857
    JE_rel8(emptysar);     // 2
nkeynes@361
   858
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   859
    JMP_rel8(end);          // 2
nkeynes@386
   860
nkeynes@386
   861
    JMP_TARGET(emptysar);
nkeynes@386
   862
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   863
    JMP_rel8(end2);
nkeynes@382
   864
nkeynes@380
   865
    JMP_TARGET(doshl);
nkeynes@361
   866
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   867
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   868
    JMP_TARGET(end);
nkeynes@386
   869
    JMP_TARGET(end2);
nkeynes@361
   870
    store_reg( R_EAX, Rn );
nkeynes@417
   871
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   872
:}
nkeynes@359
   873
SHLD Rm, Rn {:  
nkeynes@671
   874
    COUNT_INST(I_SHLD);
nkeynes@368
   875
    load_reg( R_EAX, Rn );
nkeynes@368
   876
    load_reg( R_ECX, Rm );
nkeynes@382
   877
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   878
    JGE_rel8(doshl);
nkeynes@368
   879
nkeynes@382
   880
    NEG_r32( R_ECX );      // 2
nkeynes@382
   881
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   882
    JE_rel8(emptyshr );
nkeynes@382
   883
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   884
    JMP_rel8(end);          // 2
nkeynes@386
   885
nkeynes@386
   886
    JMP_TARGET(emptyshr);
nkeynes@386
   887
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   888
    JMP_rel8(end2);
nkeynes@382
   889
nkeynes@382
   890
    JMP_TARGET(doshl);
nkeynes@382
   891
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   892
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   893
    JMP_TARGET(end);
nkeynes@386
   894
    JMP_TARGET(end2);
nkeynes@368
   895
    store_reg( R_EAX, Rn );
nkeynes@417
   896
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   897
:}
nkeynes@359
   898
SHAL Rn {: 
nkeynes@671
   899
    COUNT_INST(I_SHAL);
nkeynes@359
   900
    load_reg( R_EAX, Rn );
nkeynes@359
   901
    SHL1_r32( R_EAX );
nkeynes@397
   902
    SETC_t();
nkeynes@359
   903
    store_reg( R_EAX, Rn );
nkeynes@417
   904
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   905
:}
nkeynes@359
   906
SHAR Rn {:  
nkeynes@671
   907
    COUNT_INST(I_SHAR);
nkeynes@359
   908
    load_reg( R_EAX, Rn );
nkeynes@359
   909
    SAR1_r32( R_EAX );
nkeynes@397
   910
    SETC_t();
nkeynes@359
   911
    store_reg( R_EAX, Rn );
nkeynes@417
   912
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   913
:}
nkeynes@359
   914
SHLL Rn {:  
nkeynes@671
   915
    COUNT_INST(I_SHLL);
nkeynes@359
   916
    load_reg( R_EAX, Rn );
nkeynes@359
   917
    SHL1_r32( R_EAX );
nkeynes@397
   918
    SETC_t();
nkeynes@359
   919
    store_reg( R_EAX, Rn );
nkeynes@417
   920
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   921
:}
nkeynes@359
   922
SHLL2 Rn {:
nkeynes@671
   923
    COUNT_INST(I_SHLL);
nkeynes@359
   924
    load_reg( R_EAX, Rn );
nkeynes@359
   925
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   926
    store_reg( R_EAX, Rn );
nkeynes@417
   927
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   928
:}
nkeynes@359
   929
SHLL8 Rn {:  
nkeynes@671
   930
    COUNT_INST(I_SHLL);
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@417
   934
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   935
:}
nkeynes@359
   936
SHLL16 Rn {:  
nkeynes@671
   937
    COUNT_INST(I_SHLL);
nkeynes@359
   938
    load_reg( R_EAX, Rn );
nkeynes@359
   939
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   940
    store_reg( R_EAX, Rn );
nkeynes@417
   941
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   942
:}
nkeynes@359
   943
SHLR Rn {:  
nkeynes@671
   944
    COUNT_INST(I_SHLR);
nkeynes@359
   945
    load_reg( R_EAX, Rn );
nkeynes@359
   946
    SHR1_r32( R_EAX );
nkeynes@397
   947
    SETC_t();
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@417
   949
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   950
:}
nkeynes@359
   951
SHLR2 Rn {:  
nkeynes@671
   952
    COUNT_INST(I_SHLR);
nkeynes@359
   953
    load_reg( R_EAX, Rn );
nkeynes@359
   954
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   955
    store_reg( R_EAX, Rn );
nkeynes@417
   956
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   957
:}
nkeynes@359
   958
SHLR8 Rn {:  
nkeynes@671
   959
    COUNT_INST(I_SHLR);
nkeynes@359
   960
    load_reg( R_EAX, Rn );
nkeynes@359
   961
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   962
    store_reg( R_EAX, Rn );
nkeynes@417
   963
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   964
:}
nkeynes@359
   965
SHLR16 Rn {:  
nkeynes@671
   966
    COUNT_INST(I_SHLR);
nkeynes@359
   967
    load_reg( R_EAX, Rn );
nkeynes@359
   968
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   969
    store_reg( R_EAX, Rn );
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
:}
nkeynes@359
   972
SUB Rm, Rn {:  
nkeynes@671
   973
    COUNT_INST(I_SUB);
nkeynes@359
   974
    load_reg( R_EAX, Rm );
nkeynes@359
   975
    load_reg( R_ECX, Rn );
nkeynes@359
   976
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   977
    store_reg( R_ECX, Rn );
nkeynes@417
   978
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   979
:}
nkeynes@359
   980
SUBC Rm, Rn {:  
nkeynes@671
   981
    COUNT_INST(I_SUBC);
nkeynes@359
   982
    load_reg( R_EAX, Rm );
nkeynes@359
   983
    load_reg( R_ECX, Rn );
nkeynes@417
   984
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   985
	LDC_t();
nkeynes@417
   986
    }
nkeynes@359
   987
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   988
    store_reg( R_ECX, Rn );
nkeynes@394
   989
    SETC_t();
nkeynes@417
   990
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   991
:}
nkeynes@359
   992
SUBV Rm, Rn {:  
nkeynes@671
   993
    COUNT_INST(I_SUBV);
nkeynes@359
   994
    load_reg( R_EAX, Rm );
nkeynes@359
   995
    load_reg( R_ECX, Rn );
nkeynes@359
   996
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   997
    store_reg( R_ECX, Rn );
nkeynes@359
   998
    SETO_t();
nkeynes@417
   999
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1000
:}
nkeynes@359
  1001
SWAP.B Rm, Rn {:  
nkeynes@671
  1002
    COUNT_INST(I_SWAPB);
nkeynes@359
  1003
    load_reg( R_EAX, Rm );
nkeynes@601
  1004
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1005
    store_reg( R_EAX, Rn );
nkeynes@359
  1006
:}
nkeynes@359
  1007
SWAP.W Rm, Rn {:  
nkeynes@671
  1008
    COUNT_INST(I_SWAPB);
nkeynes@359
  1009
    load_reg( R_EAX, Rm );
nkeynes@359
  1010
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1011
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1012
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1013
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1014
    store_reg( R_ECX, Rn );
nkeynes@417
  1015
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1016
:}
nkeynes@361
  1017
TAS.B @Rn {:  
nkeynes@671
  1018
    COUNT_INST(I_TASB);
nkeynes@586
  1019
    load_reg( R_EAX, Rn );
nkeynes@930
  1020
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
  1021
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1022
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1023
    SETE_t();
nkeynes@905
  1024
    OR_imm8_r8( 0x80, R_DL );
nkeynes@930
  1025
    MOV_esp8_r32( 0, R_EAX );
nkeynes@930
  1026
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1027
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1028
:}
nkeynes@361
  1029
TST Rm, Rn {:  
nkeynes@671
  1030
    COUNT_INST(I_TST);
nkeynes@361
  1031
    load_reg( R_EAX, Rm );
nkeynes@361
  1032
    load_reg( R_ECX, Rn );
nkeynes@361
  1033
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1034
    SETE_t();
nkeynes@417
  1035
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1036
:}
nkeynes@368
  1037
TST #imm, R0 {:  
nkeynes@671
  1038
    COUNT_INST(I_TSTI);
nkeynes@368
  1039
    load_reg( R_EAX, 0 );
nkeynes@368
  1040
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1041
    SETE_t();
nkeynes@417
  1042
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1043
:}
nkeynes@368
  1044
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1045
    COUNT_INST(I_TSTB);
nkeynes@368
  1046
    load_reg( R_EAX, 0);
nkeynes@939
  1047
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
  1048
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1049
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1050
    SETE_t();
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1052
:}
nkeynes@359
  1053
XOR Rm, Rn {:  
nkeynes@671
  1054
    COUNT_INST(I_XOR);
nkeynes@359
  1055
    load_reg( R_EAX, Rm );
nkeynes@359
  1056
    load_reg( R_ECX, Rn );
nkeynes@359
  1057
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1058
    store_reg( R_ECX, Rn );
nkeynes@417
  1059
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1060
:}
nkeynes@359
  1061
XOR #imm, R0 {:  
nkeynes@671
  1062
    COUNT_INST(I_XORI);
nkeynes@359
  1063
    load_reg( R_EAX, 0 );
nkeynes@359
  1064
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1065
    store_reg( R_EAX, 0 );
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1067
:}
nkeynes@359
  1068
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1069
    COUNT_INST(I_XORB);
nkeynes@359
  1070
    load_reg( R_EAX, 0 );
nkeynes@939
  1071
    ADD_sh4r_r32( R_GBR, R_EAX ); 
nkeynes@930
  1072
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
  1073
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@930
  1074
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1075
    XOR_imm32_r32( imm, R_EDX );
nkeynes@930
  1076
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1077
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1078
:}
nkeynes@361
  1079
XTRCT Rm, Rn {:
nkeynes@671
  1080
    COUNT_INST(I_XTRCT);
nkeynes@361
  1081
    load_reg( R_EAX, Rm );
nkeynes@394
  1082
    load_reg( R_ECX, Rn );
nkeynes@394
  1083
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1084
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1085
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1086
    store_reg( R_ECX, Rn );
nkeynes@417
  1087
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1088
:}
nkeynes@359
  1089
nkeynes@359
  1090
/* Data move instructions */
nkeynes@359
  1091
MOV Rm, Rn {:  
nkeynes@671
  1092
    COUNT_INST(I_MOV);
nkeynes@359
  1093
    load_reg( R_EAX, Rm );
nkeynes@359
  1094
    store_reg( R_EAX, Rn );
nkeynes@359
  1095
:}
nkeynes@359
  1096
MOV #imm, Rn {:  
nkeynes@671
  1097
    COUNT_INST(I_MOVI);
nkeynes@359
  1098
    load_imm32( R_EAX, imm );
nkeynes@359
  1099
    store_reg( R_EAX, Rn );
nkeynes@359
  1100
:}
nkeynes@359
  1101
MOV.B Rm, @Rn {:  
nkeynes@671
  1102
    COUNT_INST(I_MOVB);
nkeynes@586
  1103
    load_reg( R_EAX, Rn );
nkeynes@930
  1104
    load_reg( R_EDX, Rm );
nkeynes@930
  1105
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV.B Rm, @-Rn {:  
nkeynes@671
  1109
    COUNT_INST(I_MOVB);
nkeynes@586
  1110
    load_reg( R_EAX, Rn );
nkeynes@939
  1111
    LEA_r32disp8_r32( R_EAX, -1, R_EAX );
nkeynes@930
  1112
    load_reg( R_EDX, Rm );
nkeynes@939
  1113
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@586
  1114
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1116
:}
nkeynes@359
  1117
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1118
    COUNT_INST(I_MOVB);
nkeynes@359
  1119
    load_reg( R_EAX, 0 );
nkeynes@939
  1120
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@930
  1121
    load_reg( R_EDX, Rm );
nkeynes@930
  1122
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1124
:}
nkeynes@359
  1125
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1126
    COUNT_INST(I_MOVB);
nkeynes@586
  1127
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1128
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1129
    load_reg( R_EDX, 0 );
nkeynes@930
  1130
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1131
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1132
:}
nkeynes@359
  1133
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1134
    COUNT_INST(I_MOVB);
nkeynes@586
  1135
    load_reg( R_EAX, Rn );
nkeynes@586
  1136
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1137
    load_reg( R_EDX, 0 );
nkeynes@930
  1138
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1139
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1140
:}
nkeynes@359
  1141
MOV.B @Rm, Rn {:  
nkeynes@671
  1142
    COUNT_INST(I_MOVB);
nkeynes@586
  1143
    load_reg( R_EAX, Rm );
nkeynes@930
  1144
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1145
    store_reg( R_EAX, Rn );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
:}
nkeynes@359
  1148
MOV.B @Rm+, Rn {:  
nkeynes@671
  1149
    COUNT_INST(I_MOVB);
nkeynes@586
  1150
    load_reg( R_EAX, Rm );
nkeynes@930
  1151
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@939
  1152
    if( Rm != Rn ) {
nkeynes@939
  1153
    	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1154
    }
nkeynes@359
  1155
    store_reg( R_EAX, Rn );
nkeynes@417
  1156
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1157
:}
nkeynes@359
  1158
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1159
    COUNT_INST(I_MOVB);
nkeynes@359
  1160
    load_reg( R_EAX, 0 );
nkeynes@939
  1161
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@930
  1162
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1163
    store_reg( R_EAX, Rn );
nkeynes@417
  1164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1165
:}
nkeynes@359
  1166
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1167
    COUNT_INST(I_MOVB);
nkeynes@586
  1168
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1169
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1170
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1171
    store_reg( R_EAX, 0 );
nkeynes@417
  1172
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1173
:}
nkeynes@359
  1174
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1175
    COUNT_INST(I_MOVB);
nkeynes@586
  1176
    load_reg( R_EAX, Rm );
nkeynes@586
  1177
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1178
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1179
    store_reg( R_EAX, 0 );
nkeynes@417
  1180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1181
:}
nkeynes@374
  1182
MOV.L Rm, @Rn {:
nkeynes@671
  1183
    COUNT_INST(I_MOVL);
nkeynes@586
  1184
    load_reg( R_EAX, Rn );
nkeynes@586
  1185
    check_walign32(R_EAX);
nkeynes@930
  1186
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@930
  1187
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@930
  1188
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@930
  1189
    JNE_rel8( notsq );
nkeynes@930
  1190
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@930
  1191
    load_reg( R_EDX, Rm );
nkeynes@930
  1192
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@930
  1193
    JMP_rel8(end);
nkeynes@930
  1194
    JMP_TARGET(notsq);
nkeynes@930
  1195
    load_reg( R_EDX, Rm );
nkeynes@930
  1196
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@930
  1197
    JMP_TARGET(end);
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1199
:}
nkeynes@361
  1200
MOV.L Rm, @-Rn {:  
nkeynes@671
  1201
    COUNT_INST(I_MOVL);
nkeynes@586
  1202
    load_reg( R_EAX, Rn );
nkeynes@586
  1203
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1204
    check_walign32( R_EAX );
nkeynes@930
  1205
    load_reg( R_EDX, Rm );
nkeynes@939
  1206
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  1207
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1209
:}
nkeynes@361
  1210
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1211
    COUNT_INST(I_MOVL);
nkeynes@361
  1212
    load_reg( R_EAX, 0 );
nkeynes@939
  1213
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1214
    check_walign32( R_EAX );
nkeynes@930
  1215
    load_reg( R_EDX, Rm );
nkeynes@930
  1216
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1218
:}
nkeynes@361
  1219
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1220
    COUNT_INST(I_MOVL);
nkeynes@586
  1221
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1222
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1223
    check_walign32( R_EAX );
nkeynes@930
  1224
    load_reg( R_EDX, 0 );
nkeynes@930
  1225
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1226
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1227
:}
nkeynes@361
  1228
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1229
    COUNT_INST(I_MOVL);
nkeynes@586
  1230
    load_reg( R_EAX, Rn );
nkeynes@586
  1231
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1232
    check_walign32( R_EAX );
nkeynes@930
  1233
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@930
  1234
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@930
  1235
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@930
  1236
    JNE_rel8( notsq );
nkeynes@930
  1237
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@930
  1238
    load_reg( R_EDX, Rm );
nkeynes@930
  1239
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@930
  1240
    JMP_rel8(end);
nkeynes@930
  1241
    JMP_TARGET(notsq);
nkeynes@930
  1242
    load_reg( R_EDX, Rm );
nkeynes@930
  1243
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@930
  1244
    JMP_TARGET(end);
nkeynes@417
  1245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1246
:}
nkeynes@361
  1247
MOV.L @Rm, Rn {:  
nkeynes@671
  1248
    COUNT_INST(I_MOVL);
nkeynes@586
  1249
    load_reg( R_EAX, Rm );
nkeynes@586
  1250
    check_ralign32( R_EAX );
nkeynes@930
  1251
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1252
    store_reg( R_EAX, Rn );
nkeynes@417
  1253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.L @Rm+, Rn {:  
nkeynes@671
  1256
    COUNT_INST(I_MOVL);
nkeynes@361
  1257
    load_reg( R_EAX, Rm );
nkeynes@382
  1258
    check_ralign32( R_EAX );
nkeynes@930
  1259
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1260
    if( Rm != Rn ) {
nkeynes@939
  1261
    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1262
    }
nkeynes@361
  1263
    store_reg( R_EAX, Rn );
nkeynes@417
  1264
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1265
:}
nkeynes@361
  1266
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1267
    COUNT_INST(I_MOVL);
nkeynes@361
  1268
    load_reg( R_EAX, 0 );
nkeynes@939
  1269
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1270
    check_ralign32( R_EAX );
nkeynes@930
  1271
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1272
    store_reg( R_EAX, Rn );
nkeynes@417
  1273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1274
:}
nkeynes@361
  1275
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1276
    COUNT_INST(I_MOVL);
nkeynes@586
  1277
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1278
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1279
    check_ralign32( R_EAX );
nkeynes@930
  1280
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1281
    store_reg( R_EAX, 0 );
nkeynes@417
  1282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1283
:}
nkeynes@361
  1284
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1285
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1286
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1287
	SLOTILLEGAL();
nkeynes@374
  1288
    } else {
nkeynes@388
  1289
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1290
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1291
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1292
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1293
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1294
nkeynes@586
  1295
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1296
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1297
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1298
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1299
	    // behaviour though.
nkeynes@586
  1300
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1301
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1302
	} else {
nkeynes@586
  1303
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1304
	    // different virtual address than the translation was done with,
nkeynes@586
  1305
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1306
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1307
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@930
  1308
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1309
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1310
	}
nkeynes@382
  1311
	store_reg( R_EAX, Rn );
nkeynes@374
  1312
    }
nkeynes@361
  1313
:}
nkeynes@361
  1314
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1315
    COUNT_INST(I_MOVL);
nkeynes@586
  1316
    load_reg( R_EAX, Rm );
nkeynes@586
  1317
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1318
    check_ralign32( R_EAX );
nkeynes@930
  1319
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1320
    store_reg( R_EAX, Rn );
nkeynes@417
  1321
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1322
:}
nkeynes@361
  1323
MOV.W Rm, @Rn {:  
nkeynes@671
  1324
    COUNT_INST(I_MOVW);
nkeynes@586
  1325
    load_reg( R_EAX, Rn );
nkeynes@586
  1326
    check_walign16( R_EAX );
nkeynes@930
  1327
    load_reg( R_EDX, Rm );
nkeynes@930
  1328
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1329
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1330
:}
nkeynes@361
  1331
MOV.W Rm, @-Rn {:  
nkeynes@671
  1332
    COUNT_INST(I_MOVW);
nkeynes@586
  1333
    load_reg( R_EAX, Rn );
nkeynes@586
  1334
    check_walign16( R_EAX );
nkeynes@939
  1335
    LEA_r32disp8_r32( R_EAX, -2, R_EAX );
nkeynes@930
  1336
    load_reg( R_EDX, Rm );
nkeynes@939
  1337
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@586
  1338
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1340
:}
nkeynes@361
  1341
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1342
    COUNT_INST(I_MOVW);
nkeynes@361
  1343
    load_reg( R_EAX, 0 );
nkeynes@939
  1344
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1345
    check_walign16( R_EAX );
nkeynes@930
  1346
    load_reg( R_EDX, Rm );
nkeynes@930
  1347
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1348
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1349
:}
nkeynes@361
  1350
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1351
    COUNT_INST(I_MOVW);
nkeynes@586
  1352
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1353
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1354
    check_walign16( R_EAX );
nkeynes@930
  1355
    load_reg( R_EDX, 0 );
nkeynes@930
  1356
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1357
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1358
:}
nkeynes@361
  1359
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1360
    COUNT_INST(I_MOVW);
nkeynes@586
  1361
    load_reg( R_EAX, Rn );
nkeynes@586
  1362
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1363
    check_walign16( R_EAX );
nkeynes@930
  1364
    load_reg( R_EDX, 0 );
nkeynes@930
  1365
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1366
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1367
:}
nkeynes@361
  1368
MOV.W @Rm, Rn {:  
nkeynes@671
  1369
    COUNT_INST(I_MOVW);
nkeynes@586
  1370
    load_reg( R_EAX, Rm );
nkeynes@586
  1371
    check_ralign16( R_EAX );
nkeynes@930
  1372
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1373
    store_reg( R_EAX, Rn );
nkeynes@417
  1374
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1375
:}
nkeynes@361
  1376
MOV.W @Rm+, Rn {:  
nkeynes@671
  1377
    COUNT_INST(I_MOVW);
nkeynes@361
  1378
    load_reg( R_EAX, Rm );
nkeynes@374
  1379
    check_ralign16( R_EAX );
nkeynes@930
  1380
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@939
  1381
    if( Rm != Rn ) {
nkeynes@939
  1382
        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1383
    }
nkeynes@361
  1384
    store_reg( R_EAX, Rn );
nkeynes@417
  1385
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1386
:}
nkeynes@361
  1387
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1388
    COUNT_INST(I_MOVW);
nkeynes@361
  1389
    load_reg( R_EAX, 0 );
nkeynes@939
  1390
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1391
    check_ralign16( R_EAX );
nkeynes@930
  1392
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1393
    store_reg( R_EAX, Rn );
nkeynes@417
  1394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1395
:}
nkeynes@361
  1396
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1397
    COUNT_INST(I_MOVW);
nkeynes@586
  1398
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1399
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1400
    check_ralign16( R_EAX );
nkeynes@930
  1401
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1402
    store_reg( R_EAX, 0 );
nkeynes@417
  1403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1404
:}
nkeynes@361
  1405
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1406
    COUNT_INST(I_MOVW);
nkeynes@374
  1407
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1408
	SLOTILLEGAL();
nkeynes@374
  1409
    } else {
nkeynes@586
  1410
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1411
	uint32_t target = pc + disp + 4;
nkeynes@586
  1412
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1413
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1414
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1415
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1416
	} else {
nkeynes@586
  1417
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1418
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1419
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1420
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1421
	}
nkeynes@374
  1422
	store_reg( R_EAX, Rn );
nkeynes@374
  1423
    }
nkeynes@361
  1424
:}
nkeynes@361
  1425
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1426
    COUNT_INST(I_MOVW);
nkeynes@586
  1427
    load_reg( R_EAX, Rm );
nkeynes@586
  1428
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1429
    check_ralign16( R_EAX );
nkeynes@930
  1430
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1431
    store_reg( R_EAX, 0 );
nkeynes@417
  1432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1435
    COUNT_INST(I_MOVA);
nkeynes@374
  1436
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1437
	SLOTILLEGAL();
nkeynes@374
  1438
    } else {
nkeynes@586
  1439
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1440
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1441
	store_reg( R_ECX, 0 );
nkeynes@586
  1442
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1443
    }
nkeynes@361
  1444
:}
nkeynes@361
  1445
MOVCA.L R0, @Rn {:  
nkeynes@671
  1446
    COUNT_INST(I_MOVCA);
nkeynes@586
  1447
    load_reg( R_EAX, Rn );
nkeynes@586
  1448
    check_walign32( R_EAX );
nkeynes@930
  1449
    load_reg( R_EDX, 0 );
nkeynes@930
  1450
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1452
:}
nkeynes@359
  1453
nkeynes@359
  1454
/* Control transfer instructions */
nkeynes@374
  1455
BF disp {:
nkeynes@671
  1456
    COUNT_INST(I_BF);
nkeynes@374
  1457
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1458
	SLOTILLEGAL();
nkeynes@374
  1459
    } else {
nkeynes@586
  1460
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1461
	JT_rel8( nottaken );
nkeynes@586
  1462
	exit_block_rel(target, pc+2 );
nkeynes@380
  1463
	JMP_TARGET(nottaken);
nkeynes@408
  1464
	return 2;
nkeynes@374
  1465
    }
nkeynes@374
  1466
:}
nkeynes@374
  1467
BF/S disp {:
nkeynes@671
  1468
    COUNT_INST(I_BFS);
nkeynes@374
  1469
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1470
	SLOTILLEGAL();
nkeynes@374
  1471
    } else {
nkeynes@590
  1472
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1473
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1474
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1475
	    JT_rel8(nottaken);
nkeynes@601
  1476
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1477
	    JMP_TARGET(nottaken);
nkeynes@601
  1478
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1479
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1480
	    exit_block_emu(pc+2);
nkeynes@601
  1481
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1482
	    return 2;
nkeynes@601
  1483
	} else {
nkeynes@601
  1484
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1485
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1486
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1487
	    }
nkeynes@601
  1488
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1489
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1490
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1491
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1492
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1493
	    
nkeynes@601
  1494
	    // not taken
nkeynes@601
  1495
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1496
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1497
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1498
	    return 4;
nkeynes@417
  1499
	}
nkeynes@374
  1500
    }
nkeynes@374
  1501
:}
nkeynes@374
  1502
BRA disp {:  
nkeynes@671
  1503
    COUNT_INST(I_BRA);
nkeynes@374
  1504
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1505
	SLOTILLEGAL();
nkeynes@374
  1506
    } else {
nkeynes@590
  1507
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1508
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1509
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1510
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1511
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1512
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1513
	    exit_block_emu(pc+2);
nkeynes@601
  1514
	    return 2;
nkeynes@601
  1515
	} else {
nkeynes@601
  1516
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1517
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1518
	    return 4;
nkeynes@601
  1519
	}
nkeynes@374
  1520
    }
nkeynes@374
  1521
:}
nkeynes@374
  1522
BRAF Rn {:  
nkeynes@671
  1523
    COUNT_INST(I_BRAF);
nkeynes@374
  1524
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1525
	SLOTILLEGAL();
nkeynes@374
  1526
    } else {
nkeynes@590
  1527
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1528
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1529
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1530
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1531
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1532
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1533
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1534
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1535
	    exit_block_emu(pc+2);
nkeynes@601
  1536
	    return 2;
nkeynes@601
  1537
	} else {
nkeynes@601
  1538
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1539
	    exit_block_newpcset(pc+2);
nkeynes@601
  1540
	    return 4;
nkeynes@601
  1541
	}
nkeynes@374
  1542
    }
nkeynes@374
  1543
:}
nkeynes@374
  1544
BSR disp {:  
nkeynes@671
  1545
    COUNT_INST(I_BSR);
nkeynes@374
  1546
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1547
	SLOTILLEGAL();
nkeynes@374
  1548
    } else {
nkeynes@590
  1549
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1550
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1551
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1552
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1553
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1554
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1555
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1556
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1557
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1558
	    exit_block_emu(pc+2);
nkeynes@601
  1559
	    return 2;
nkeynes@601
  1560
	} else {
nkeynes@601
  1561
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1562
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1563
	    return 4;
nkeynes@601
  1564
	}
nkeynes@374
  1565
    }
nkeynes@374
  1566
:}
nkeynes@374
  1567
BSRF Rn {:  
nkeynes@671
  1568
    COUNT_INST(I_BSRF);
nkeynes@374
  1569
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1570
	SLOTILLEGAL();
nkeynes@374
  1571
    } else {
nkeynes@590
  1572
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1573
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1574
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1575
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1576
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1577
nkeynes@601
  1578
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1579
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1580
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1581
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1582
	    exit_block_emu(pc+2);
nkeynes@601
  1583
	    return 2;
nkeynes@601
  1584
	} else {
nkeynes@601
  1585
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1586
	    exit_block_newpcset(pc+2);
nkeynes@601
  1587
	    return 4;
nkeynes@601
  1588
	}
nkeynes@374
  1589
    }
nkeynes@374
  1590
:}
nkeynes@374
  1591
BT disp {:
nkeynes@671
  1592
    COUNT_INST(I_BT);
nkeynes@374
  1593
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1594
	SLOTILLEGAL();
nkeynes@374
  1595
    } else {
nkeynes@586
  1596
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1597
	JF_rel8( nottaken );
nkeynes@586
  1598
	exit_block_rel(target, pc+2 );
nkeynes@380
  1599
	JMP_TARGET(nottaken);
nkeynes@408
  1600
	return 2;
nkeynes@374
  1601
    }
nkeynes@374
  1602
:}
nkeynes@374
  1603
BT/S disp {:
nkeynes@671
  1604
    COUNT_INST(I_BTS);
nkeynes@374
  1605
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1606
	SLOTILLEGAL();
nkeynes@374
  1607
    } else {
nkeynes@590
  1608
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1609
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1610
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1611
	    JF_rel8(nottaken);
nkeynes@601
  1612
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1613
	    JMP_TARGET(nottaken);
nkeynes@601
  1614
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1615
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1616
	    exit_block_emu(pc+2);
nkeynes@601
  1617
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1618
	    return 2;
nkeynes@601
  1619
	} else {
nkeynes@601
  1620
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1621
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1622
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1623
	    }
nkeynes@601
  1624
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1625
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1626
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1627
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1628
	    // not taken
nkeynes@601
  1629
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1630
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1631
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1632
	    return 4;
nkeynes@417
  1633
	}
nkeynes@374
  1634
    }
nkeynes@374
  1635
:}
nkeynes@374
  1636
JMP @Rn {:  
nkeynes@671
  1637
    COUNT_INST(I_JMP);
nkeynes@374
  1638
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1639
	SLOTILLEGAL();
nkeynes@374
  1640
    } else {
nkeynes@408
  1641
	load_reg( R_ECX, Rn );
nkeynes@590
  1642
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1643
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1644
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1645
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1646
	    exit_block_emu(pc+2);
nkeynes@601
  1647
	    return 2;
nkeynes@601
  1648
	} else {
nkeynes@601
  1649
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1650
	    exit_block_newpcset(pc+2);
nkeynes@601
  1651
	    return 4;
nkeynes@601
  1652
	}
nkeynes@374
  1653
    }
nkeynes@374
  1654
:}
nkeynes@374
  1655
JSR @Rn {:  
nkeynes@671
  1656
    COUNT_INST(I_JSR);
nkeynes@374
  1657
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1658
	SLOTILLEGAL();
nkeynes@374
  1659
    } else {
nkeynes@590
  1660
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1661
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1662
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1663
	load_reg( R_ECX, Rn );
nkeynes@590
  1664
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1665
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1666
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1667
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1668
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1669
	    exit_block_emu(pc+2);
nkeynes@601
  1670
	    return 2;
nkeynes@601
  1671
	} else {
nkeynes@601
  1672
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1673
	    exit_block_newpcset(pc+2);
nkeynes@601
  1674
	    return 4;
nkeynes@601
  1675
	}
nkeynes@374
  1676
    }
nkeynes@374
  1677
:}
nkeynes@374
  1678
RTE {:  
nkeynes@671
  1679
    COUNT_INST(I_RTE);
nkeynes@374
  1680
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1681
	SLOTILLEGAL();
nkeynes@374
  1682
    } else {
nkeynes@408
  1683
	check_priv();
nkeynes@408
  1684
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1685
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1686
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1687
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1688
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1689
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1690
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1691
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1692
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1693
	    exit_block_emu(pc+2);
nkeynes@601
  1694
	    return 2;
nkeynes@601
  1695
	} else {
nkeynes@601
  1696
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1697
	    exit_block_newpcset(pc+2);
nkeynes@601
  1698
	    return 4;
nkeynes@601
  1699
	}
nkeynes@374
  1700
    }
nkeynes@374
  1701
:}
nkeynes@374
  1702
RTS {:  
nkeynes@671
  1703
    COUNT_INST(I_RTS);
nkeynes@374
  1704
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1705
	SLOTILLEGAL();
nkeynes@374
  1706
    } else {
nkeynes@408
  1707
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1708
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1709
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1710
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1711
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1712
	    exit_block_emu(pc+2);
nkeynes@601
  1713
	    return 2;
nkeynes@601
  1714
	} else {
nkeynes@601
  1715
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1716
	    exit_block_newpcset(pc+2);
nkeynes@601
  1717
	    return 4;
nkeynes@601
  1718
	}
nkeynes@374
  1719
    }
nkeynes@374
  1720
:}
nkeynes@374
  1721
TRAPA #imm {:  
nkeynes@671
  1722
    COUNT_INST(I_TRAPA);
nkeynes@374
  1723
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1724
	SLOTILLEGAL();
nkeynes@374
  1725
    } else {
nkeynes@590
  1726
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1727
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1728
	load_imm32( R_EAX, imm );
nkeynes@527
  1729
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1730
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1731
	exit_block_pcset(pc);
nkeynes@409
  1732
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1733
	return 2;
nkeynes@374
  1734
    }
nkeynes@374
  1735
:}
nkeynes@374
  1736
UNDEF {:  
nkeynes@671
  1737
    COUNT_INST(I_UNDEF);
nkeynes@374
  1738
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1739
	SLOTILLEGAL();
nkeynes@374
  1740
    } else {
nkeynes@586
  1741
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1742
	return 2;
nkeynes@374
  1743
    }
nkeynes@368
  1744
:}
nkeynes@374
  1745
nkeynes@374
  1746
CLRMAC {:  
nkeynes@671
  1747
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1748
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1749
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1750
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1751
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1752
:}
nkeynes@374
  1753
CLRS {:
nkeynes@671
  1754
    COUNT_INST(I_CLRS);
nkeynes@374
  1755
    CLC();
nkeynes@374
  1756
    SETC_sh4r(R_S);
nkeynes@872
  1757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1758
:}
nkeynes@374
  1759
CLRT {:  
nkeynes@671
  1760
    COUNT_INST(I_CLRT);
nkeynes@374
  1761
    CLC();
nkeynes@374
  1762
    SETC_t();
nkeynes@417
  1763
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1764
:}
nkeynes@374
  1765
SETS {:  
nkeynes@671
  1766
    COUNT_INST(I_SETS);
nkeynes@374
  1767
    STC();
nkeynes@374
  1768
    SETC_sh4r(R_S);
nkeynes@872
  1769
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1770
:}
nkeynes@374
  1771
SETT {:  
nkeynes@671
  1772
    COUNT_INST(I_SETT);
nkeynes@374
  1773
    STC();
nkeynes@374
  1774
    SETC_t();
nkeynes@417
  1775
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1776
:}
nkeynes@359
  1777
nkeynes@375
  1778
/* Floating point moves */
nkeynes@375
  1779
FMOV FRm, FRn {:  
nkeynes@671
  1780
    COUNT_INST(I_FMOV1);
nkeynes@377
  1781
    check_fpuen();
nkeynes@901
  1782
    if( sh4_x86.double_size ) {
nkeynes@901
  1783
        load_dr0( R_EAX, FRm );
nkeynes@901
  1784
        load_dr1( R_ECX, FRm );
nkeynes@901
  1785
        store_dr0( R_EAX, FRn );
nkeynes@901
  1786
        store_dr1( R_ECX, FRn );
nkeynes@901
  1787
    } else {
nkeynes@901
  1788
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1789
        store_fr( R_EAX, FRn );
nkeynes@901
  1790
    }
nkeynes@375
  1791
:}
nkeynes@416
  1792
FMOV FRm, @Rn {: 
nkeynes@671
  1793
    COUNT_INST(I_FMOV2);
nkeynes@586
  1794
    check_fpuen();
nkeynes@586
  1795
    load_reg( R_EAX, Rn );
nkeynes@901
  1796
    if( sh4_x86.double_size ) {
nkeynes@901
  1797
        check_walign64( R_EAX );
nkeynes@930
  1798
        load_dr0( R_EDX, FRm );
nkeynes@939
  1799
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1800
        load_reg( R_EAX, Rn );
nkeynes@939
  1801
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1802
        load_dr1( R_EDX, FRm );
nkeynes@939
  1803
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1804
    } else {
nkeynes@901
  1805
        check_walign32( R_EAX );
nkeynes@930
  1806
        load_fr( R_EDX, FRm );
nkeynes@930
  1807
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1808
    }
nkeynes@417
  1809
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1810
:}
nkeynes@375
  1811
FMOV @Rm, FRn {:  
nkeynes@671
  1812
    COUNT_INST(I_FMOV5);
nkeynes@586
  1813
    check_fpuen();
nkeynes@586
  1814
    load_reg( R_EAX, Rm );
nkeynes@901
  1815
    if( sh4_x86.double_size ) {
nkeynes@901
  1816
        check_ralign64( R_EAX );
nkeynes@939
  1817
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1818
        store_dr0( R_EAX, FRn );
nkeynes@939
  1819
        load_reg( R_EAX, Rm );
nkeynes@939
  1820
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1821
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1822
        store_dr1( R_EAX, FRn );
nkeynes@901
  1823
    } else {
nkeynes@901
  1824
        check_ralign32( R_EAX );
nkeynes@930
  1825
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1826
        store_fr( R_EAX, FRn );
nkeynes@901
  1827
    }
nkeynes@417
  1828
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1829
:}
nkeynes@377
  1830
FMOV FRm, @-Rn {:  
nkeynes@671
  1831
    COUNT_INST(I_FMOV3);
nkeynes@586
  1832
    check_fpuen();
nkeynes@586
  1833
    load_reg( R_EAX, Rn );
nkeynes@901
  1834
    if( sh4_x86.double_size ) {
nkeynes@901
  1835
        check_walign64( R_EAX );
nkeynes@939
  1836
        LEA_r32disp8_r32( R_EAX, -8, R_EAX );
nkeynes@930
  1837
        load_dr0( R_EDX, FRm );
nkeynes@939
  1838
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1839
        load_reg( R_EAX, Rn );
nkeynes@939
  1840
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@939
  1841
        load_dr1( R_EDX, FRm );
nkeynes@939
  1842
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1843
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1844
    } else {
nkeynes@901
  1845
        check_walign32( R_EAX );
nkeynes@939
  1846
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@930
  1847
        load_fr( R_EDX, FRm );
nkeynes@939
  1848
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1849
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1850
    }
nkeynes@417
  1851
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1852
:}
nkeynes@416
  1853
FMOV @Rm+, FRn {:
nkeynes@671
  1854
    COUNT_INST(I_FMOV6);
nkeynes@586
  1855
    check_fpuen();
nkeynes@586
  1856
    load_reg( R_EAX, Rm );
nkeynes@901
  1857
    if( sh4_x86.double_size ) {
nkeynes@901
  1858
        check_ralign64( R_EAX );
nkeynes@939
  1859
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1860
        store_dr0( R_EAX, FRn );
nkeynes@939
  1861
        load_reg( R_EAX, Rm );
nkeynes@939
  1862
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1863
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1864
        store_dr1( R_EAX, FRn );
nkeynes@901
  1865
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1866
    } else {
nkeynes@901
  1867
        check_ralign32( R_EAX );
nkeynes@930
  1868
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1869
        store_fr( R_EAX, FRn );
nkeynes@939
  1870
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1871
    }
nkeynes@417
  1872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1873
:}
nkeynes@377
  1874
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1875
    COUNT_INST(I_FMOV4);
nkeynes@586
  1876
    check_fpuen();
nkeynes@586
  1877
    load_reg( R_EAX, Rn );
nkeynes@586
  1878
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1879
    if( sh4_x86.double_size ) {
nkeynes@901
  1880
        check_walign64( R_EAX );
nkeynes@930
  1881
        load_dr0( R_EDX, FRm );
nkeynes@939
  1882
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1883
        load_reg( R_EAX, Rn );
nkeynes@939
  1884
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@939
  1885
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1886
        load_dr1( R_EDX, FRm );
nkeynes@939
  1887
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1888
    } else {
nkeynes@901
  1889
        check_walign32( R_EAX );
nkeynes@930
  1890
        load_fr( R_EDX, FRm );
nkeynes@930
  1891
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1892
    }
nkeynes@417
  1893
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1894
:}
nkeynes@377
  1895
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1896
    COUNT_INST(I_FMOV7);
nkeynes@586
  1897
    check_fpuen();
nkeynes@586
  1898
    load_reg( R_EAX, Rm );
nkeynes@586
  1899
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1900
    if( sh4_x86.double_size ) {
nkeynes@901
  1901
        check_ralign64( R_EAX );
nkeynes@939
  1902
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1903
        store_dr0( R_EAX, FRn );
nkeynes@939
  1904
        load_reg( R_EAX, Rm );
nkeynes@939
  1905
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@939
  1906
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1907
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1908
        store_dr1( R_EAX, FRn );
nkeynes@901
  1909
    } else {
nkeynes@901
  1910
        check_ralign32( R_EAX );
nkeynes@930
  1911
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1912
        store_fr( R_EAX, FRn );
nkeynes@901
  1913
    }
nkeynes@417
  1914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1915
:}
nkeynes@377
  1916
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1917
    COUNT_INST(I_FLDI0);
nkeynes@377
  1918
    check_fpuen();
nkeynes@901
  1919
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1920
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1921
        store_fr( R_EAX, FRn );
nkeynes@901
  1922
    }
nkeynes@417
  1923
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1924
:}
nkeynes@377
  1925
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1926
    COUNT_INST(I_FLDI1);
nkeynes@377
  1927
    check_fpuen();
nkeynes@901
  1928
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1929
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1930
        store_fr( R_EAX, FRn );
nkeynes@901
  1931
    }
nkeynes@377
  1932
:}
nkeynes@377
  1933
nkeynes@377
  1934
FLOAT FPUL, FRn {:  
nkeynes@671
  1935
    COUNT_INST(I_FLOAT);
nkeynes@377
  1936
    check_fpuen();
nkeynes@377
  1937
    FILD_sh4r(R_FPUL);
nkeynes@901
  1938
    if( sh4_x86.double_prec ) {
nkeynes@901
  1939
        pop_dr( FRn );
nkeynes@901
  1940
    } else {
nkeynes@901
  1941
        pop_fr( FRn );
nkeynes@901
  1942
    }
nkeynes@377
  1943
:}
nkeynes@377
  1944
FTRC FRm, FPUL {:  
nkeynes@671
  1945
    COUNT_INST(I_FTRC);
nkeynes@377
  1946
    check_fpuen();
nkeynes@901
  1947
    if( sh4_x86.double_prec ) {
nkeynes@901
  1948
        push_dr( FRm );
nkeynes@901
  1949
    } else {
nkeynes@901
  1950
        push_fr( FRm );
nkeynes@901
  1951
    }
nkeynes@789
  1952
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1953
    FILD_r32ind( R_ECX );
nkeynes@388
  1954
    FCOMIP_st(1);
nkeynes@669
  1955
    JNA_rel8( sat );
nkeynes@789
  1956
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  1957
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1958
    FCOMIP_st(1);                   // 2
nkeynes@669
  1959
    JAE_rel8( sat2 );            // 2
nkeynes@789
  1960
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  1961
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  1962
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  1963
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1964
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1965
    FLDCW_r32ind( R_EAX );
nkeynes@669
  1966
    JMP_rel8(end);             // 2
nkeynes@388
  1967
nkeynes@388
  1968
    JMP_TARGET(sat);
nkeynes@388
  1969
    JMP_TARGET(sat2);
nkeynes@388
  1970
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1971
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1972
    FPOP_st();
nkeynes@388
  1973
    JMP_TARGET(end);
nkeynes@417
  1974
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1975
:}
nkeynes@377
  1976
FLDS FRm, FPUL {:  
nkeynes@671
  1977
    COUNT_INST(I_FLDS);
nkeynes@377
  1978
    check_fpuen();
nkeynes@669
  1979
    load_fr( R_EAX, FRm );
nkeynes@377
  1980
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1981
:}
nkeynes@377
  1982
FSTS FPUL, FRn {:  
nkeynes@671
  1983
    COUNT_INST(I_FSTS);
nkeynes@377
  1984
    check_fpuen();
nkeynes@377
  1985
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  1986
    store_fr( R_EAX, FRn );
nkeynes@377
  1987
:}
nkeynes@377
  1988
FCNVDS FRm, FPUL {:  
nkeynes@671
  1989
    COUNT_INST(I_FCNVDS);
nkeynes@377
  1990
    check_fpuen();
nkeynes@901
  1991
    if( sh4_x86.double_prec ) {
nkeynes@901
  1992
        push_dr( FRm );
nkeynes@901
  1993
        pop_fpul();
nkeynes@901
  1994
    }
nkeynes@377
  1995
:}
nkeynes@377
  1996
FCNVSD FPUL, FRn {:  
nkeynes@671
  1997
    COUNT_INST(I_FCNVSD);
nkeynes@377
  1998
    check_fpuen();
nkeynes@901
  1999
    if( sh4_x86.double_prec ) {
nkeynes@901
  2000
        push_fpul();
nkeynes@901
  2001
        pop_dr( FRn );
nkeynes@901
  2002
    }
nkeynes@377
  2003
:}
nkeynes@375
  2004
nkeynes@359
  2005
/* Floating point instructions */
nkeynes@374
  2006
FABS FRn {:  
nkeynes@671
  2007
    COUNT_INST(I_FABS);
nkeynes@377
  2008
    check_fpuen();
nkeynes@901
  2009
    if( sh4_x86.double_prec ) {
nkeynes@901
  2010
        push_dr(FRn);
nkeynes@901
  2011
        FABS_st0();
nkeynes@901
  2012
        pop_dr(FRn);
nkeynes@901
  2013
    } else {
nkeynes@901
  2014
        push_fr(FRn);
nkeynes@901
  2015
        FABS_st0();
nkeynes@901
  2016
        pop_fr(FRn);
nkeynes@901
  2017
    }
nkeynes@374
  2018
:}
nkeynes@377
  2019
FADD FRm, FRn {:  
nkeynes@671
  2020
    COUNT_INST(I_FADD);
nkeynes@377
  2021
    check_fpuen();
nkeynes@901
  2022
    if( sh4_x86.double_prec ) {
nkeynes@901
  2023
        push_dr(FRm);
nkeynes@901
  2024
        push_dr(FRn);
nkeynes@901
  2025
        FADDP_st(1);
nkeynes@901
  2026
        pop_dr(FRn);
nkeynes@901
  2027
    } else {
nkeynes@901
  2028
        push_fr(FRm);
nkeynes@901
  2029
        push_fr(FRn);
nkeynes@901
  2030
        FADDP_st(1);
nkeynes@901
  2031
        pop_fr(FRn);
nkeynes@901
  2032
    }
nkeynes@375
  2033
:}
nkeynes@377
  2034
FDIV FRm, FRn {:  
nkeynes@671
  2035
    COUNT_INST(I_FDIV);
nkeynes@377
  2036
    check_fpuen();
nkeynes@901
  2037
    if( sh4_x86.double_prec ) {
nkeynes@901
  2038
        push_dr(FRn);
nkeynes@901
  2039
        push_dr(FRm);
nkeynes@901
  2040
        FDIVP_st(1);
nkeynes@901
  2041
        pop_dr(FRn);
nkeynes@901
  2042
    } else {
nkeynes@901
  2043
        push_fr(FRn);
nkeynes@901
  2044
        push_fr(FRm);
nkeynes@901
  2045
        FDIVP_st(1);
nkeynes@901
  2046
        pop_fr(FRn);
nkeynes@901
  2047
    }
nkeynes@375
  2048
:}
nkeynes@375
  2049
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2050
    COUNT_INST(I_FMAC);
nkeynes@377
  2051
    check_fpuen();
nkeynes@901
  2052
    if( sh4_x86.double_prec ) {
nkeynes@901
  2053
        push_dr( 0 );
nkeynes@901
  2054
        push_dr( FRm );
nkeynes@901
  2055
        FMULP_st(1);
nkeynes@901
  2056
        push_dr( FRn );
nkeynes@901
  2057
        FADDP_st(1);
nkeynes@901
  2058
        pop_dr( FRn );
nkeynes@901
  2059
    } else {
nkeynes@901
  2060
        push_fr( 0 );
nkeynes@901
  2061
        push_fr( FRm );
nkeynes@901
  2062
        FMULP_st(1);
nkeynes@901
  2063
        push_fr( FRn );
nkeynes@901
  2064
        FADDP_st(1);
nkeynes@901
  2065
        pop_fr( FRn );
nkeynes@901
  2066
    }
nkeynes@375
  2067
:}
nkeynes@375
  2068
nkeynes@377
  2069
FMUL FRm, FRn {:  
nkeynes@671
  2070
    COUNT_INST(I_FMUL);
nkeynes@377
  2071
    check_fpuen();
nkeynes@901
  2072
    if( sh4_x86.double_prec ) {
nkeynes@901
  2073
        push_dr(FRm);
nkeynes@901
  2074
        push_dr(FRn);
nkeynes@901
  2075
        FMULP_st(1);
nkeynes@901
  2076
        pop_dr(FRn);
nkeynes@901
  2077
    } else {
nkeynes@901
  2078
        push_fr(FRm);
nkeynes@901
  2079
        push_fr(FRn);
nkeynes@901
  2080
        FMULP_st(1);
nkeynes@901
  2081
        pop_fr(FRn);
nkeynes@901
  2082
    }
nkeynes@377
  2083
:}
nkeynes@377
  2084
FNEG FRn {:  
nkeynes@671
  2085
    COUNT_INST(I_FNEG);
nkeynes@377
  2086
    check_fpuen();
nkeynes@901
  2087
    if( sh4_x86.double_prec ) {
nkeynes@901
  2088
        push_dr(FRn);
nkeynes@901
  2089
        FCHS_st0();
nkeynes@901
  2090
        pop_dr(FRn);
nkeynes@901
  2091
    } else {
nkeynes@901
  2092
        push_fr(FRn);
nkeynes@901
  2093
        FCHS_st0();
nkeynes@901
  2094
        pop_fr(FRn);
nkeynes@901
  2095
    }
nkeynes@377
  2096
:}
nkeynes@377
  2097
FSRRA FRn {:  
nkeynes@671
  2098
    COUNT_INST(I_FSRRA);
nkeynes@377
  2099
    check_fpuen();
nkeynes@901
  2100
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2101
        FLD1_st0();
nkeynes@901
  2102
        push_fr(FRn);
nkeynes@901
  2103
        FSQRT_st0();
nkeynes@901
  2104
        FDIVP_st(1);
nkeynes@901
  2105
        pop_fr(FRn);
nkeynes@901
  2106
    }
nkeynes@377
  2107
:}
nkeynes@377
  2108
FSQRT FRn {:  
nkeynes@671
  2109
    COUNT_INST(I_FSQRT);
nkeynes@377
  2110
    check_fpuen();
nkeynes@901
  2111
    if( sh4_x86.double_prec ) {
nkeynes@901
  2112
        push_dr(FRn);
nkeynes@901
  2113
        FSQRT_st0();
nkeynes@901
  2114
        pop_dr(FRn);
nkeynes@901
  2115
    } else {
nkeynes@901
  2116
        push_fr(FRn);
nkeynes@901
  2117
        FSQRT_st0();
nkeynes@901
  2118
        pop_fr(FRn);
nkeynes@901
  2119
    }
nkeynes@377
  2120
:}
nkeynes@377
  2121
FSUB FRm, FRn {:  
nkeynes@671
  2122
    COUNT_INST(I_FSUB);
nkeynes@377
  2123
    check_fpuen();
nkeynes@901
  2124
    if( sh4_x86.double_prec ) {
nkeynes@901
  2125
        push_dr(FRn);
nkeynes@901
  2126
        push_dr(FRm);
nkeynes@901
  2127
        FSUBP_st(1);
nkeynes@901
  2128
        pop_dr(FRn);
nkeynes@901
  2129
    } else {
nkeynes@901
  2130
        push_fr(FRn);
nkeynes@901
  2131
        push_fr(FRm);
nkeynes@901
  2132
        FSUBP_st(1);
nkeynes@901
  2133
        pop_fr(FRn);
nkeynes@901
  2134
    }
nkeynes@377
  2135
:}
nkeynes@377
  2136
nkeynes@377
  2137
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2138
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2139
    check_fpuen();
nkeynes@901
  2140
    if( sh4_x86.double_prec ) {
nkeynes@901
  2141
        push_dr(FRm);
nkeynes@901
  2142
        push_dr(FRn);
nkeynes@901
  2143
    } else {
nkeynes@901
  2144
        push_fr(FRm);
nkeynes@901
  2145
        push_fr(FRn);
nkeynes@901
  2146
    }
nkeynes@377
  2147
    FCOMIP_st(1);
nkeynes@377
  2148
    SETE_t();
nkeynes@377
  2149
    FPOP_st();
nkeynes@901
  2150
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2151
:}
nkeynes@377
  2152
FCMP/GT FRm, FRn {:  
nkeynes@671
  2153
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2154
    check_fpuen();
nkeynes@901
  2155
    if( sh4_x86.double_prec ) {
nkeynes@901
  2156
        push_dr(FRm);
nkeynes@901
  2157
        push_dr(FRn);
nkeynes@901
  2158
    } else {
nkeynes@901
  2159
        push_fr(FRm);
nkeynes@901
  2160
        push_fr(FRn);
nkeynes@901
  2161
    }
nkeynes@377
  2162
    FCOMIP_st(1);
nkeynes@377
  2163
    SETA_t();
nkeynes@377
  2164
    FPOP_st();
nkeynes@901
  2165
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2166
:}
nkeynes@377
  2167
nkeynes@377
  2168
FSCA FPUL, FRn {:  
nkeynes@671
  2169
    COUNT_INST(I_FSCA);
nkeynes@377
  2170
    check_fpuen();
nkeynes@901
  2171
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2172
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2173
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2174
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2175
    }
nkeynes@417
  2176
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2177
:}
nkeynes@377
  2178
FIPR FVm, FVn {:  
nkeynes@671
  2179
    COUNT_INST(I_FIPR);
nkeynes@377
  2180
    check_fpuen();
nkeynes@901
  2181
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2182
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2183
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2184
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2185
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2186
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2187
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2188
        } else {
nkeynes@904
  2189
            push_fr( FVm<<2 );
nkeynes@903
  2190
            push_fr( FVn<<2 );
nkeynes@903
  2191
            FMULP_st(1);
nkeynes@903
  2192
            push_fr( (FVm<<2)+1);
nkeynes@903
  2193
            push_fr( (FVn<<2)+1);
nkeynes@903
  2194
            FMULP_st(1);
nkeynes@903
  2195
            FADDP_st(1);
nkeynes@903
  2196
            push_fr( (FVm<<2)+2);
nkeynes@903
  2197
            push_fr( (FVn<<2)+2);
nkeynes@903
  2198
            FMULP_st(1);
nkeynes@903
  2199
            FADDP_st(1);
nkeynes@903
  2200
            push_fr( (FVm<<2)+3);
nkeynes@903
  2201
            push_fr( (FVn<<2)+3);
nkeynes@903
  2202
            FMULP_st(1);
nkeynes@903
  2203
            FADDP_st(1);
nkeynes@903
  2204
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2205
        }
nkeynes@901
  2206
    }
nkeynes@377
  2207
:}
nkeynes@377
  2208
FTRV XMTRX, FVn {:  
nkeynes@671
  2209
    COUNT_INST(I_FTRV);
nkeynes@377
  2210
    check_fpuen();
nkeynes@901
  2211
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2212
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2213
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2214
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2215
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2216
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2217
nkeynes@903
  2218
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2219
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2220
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2221
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2222
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2223
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2224
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2225
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2226
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2227
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2228
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2229
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2230
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2231
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2232
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2233
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2234
        } else {
nkeynes@903
  2235
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2236
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2237
        }
nkeynes@901
  2238
    }
nkeynes@417
  2239
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2240
:}
nkeynes@377
  2241
nkeynes@377
  2242
FRCHG {:  
nkeynes@671
  2243
    COUNT_INST(I_FRCHG);
nkeynes@377
  2244
    check_fpuen();
nkeynes@936
  2245
    XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );
nkeynes@669
  2246
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2248
:}
nkeynes@377
  2249
FSCHG {:  
nkeynes@671
  2250
    COUNT_INST(I_FSCHG);
nkeynes@377
  2251
    check_fpuen();
nkeynes@936
  2252
    XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);
nkeynes@936
  2253
    XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2255
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2256
:}
nkeynes@359
  2257
nkeynes@359
  2258
/* Processor control instructions */
nkeynes@368
  2259
LDC Rm, SR {:
nkeynes@671
  2260
    COUNT_INST(I_LDCSR);
nkeynes@386
  2261
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2262
	SLOTILLEGAL();
nkeynes@386
  2263
    } else {
nkeynes@386
  2264
	check_priv();
nkeynes@386
  2265
	load_reg( R_EAX, Rm );
nkeynes@386
  2266
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2267
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2268
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2269
	return 2;
nkeynes@386
  2270
    }
nkeynes@368
  2271
:}
nkeynes@359
  2272
LDC Rm, GBR {: 
nkeynes@671
  2273
    COUNT_INST(I_LDC);
nkeynes@359
  2274
    load_reg( R_EAX, Rm );
nkeynes@359
  2275
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2276
:}
nkeynes@359
  2277
LDC Rm, VBR {:  
nkeynes@671
  2278
    COUNT_INST(I_LDC);
nkeynes@386
  2279
    check_priv();
nkeynes@359
  2280
    load_reg( R_EAX, Rm );
nkeynes@359
  2281
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2283
:}
nkeynes@359
  2284
LDC Rm, SSR {:  
nkeynes@671
  2285
    COUNT_INST(I_LDC);
nkeynes@386
  2286
    check_priv();
nkeynes@359
  2287
    load_reg( R_EAX, Rm );
nkeynes@359
  2288
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC Rm, SGR {:  
nkeynes@671
  2292
    COUNT_INST(I_LDC);
nkeynes@386
  2293
    check_priv();
nkeynes@359
  2294
    load_reg( R_EAX, Rm );
nkeynes@359
  2295
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2296
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2297
:}
nkeynes@359
  2298
LDC Rm, SPC {:  
nkeynes@671
  2299
    COUNT_INST(I_LDC);
nkeynes@386
  2300
    check_priv();
nkeynes@359
  2301
    load_reg( R_EAX, Rm );
nkeynes@359
  2302
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2304
:}
nkeynes@359
  2305
LDC Rm, DBR {:  
nkeynes@671
  2306
    COUNT_INST(I_LDC);
nkeynes@386
  2307
    check_priv();
nkeynes@359
  2308
    load_reg( R_EAX, Rm );
nkeynes@359
  2309
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2311
:}
nkeynes@374
  2312
LDC Rm, Rn_BANK {:  
nkeynes@671
  2313
    COUNT_INST(I_LDC);
nkeynes@386
  2314
    check_priv();
nkeynes@374
  2315
    load_reg( R_EAX, Rm );
nkeynes@374
  2316
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2318
:}
nkeynes@359
  2319
LDC.L @Rm+, GBR {:  
nkeynes@671
  2320
    COUNT_INST(I_LDCM);
nkeynes@359
  2321
    load_reg( R_EAX, Rm );
nkeynes@395
  2322
    check_ralign32( R_EAX );
nkeynes@939
  2323
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2324
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2325
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2326
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2327
:}
nkeynes@368
  2328
LDC.L @Rm+, SR {:
nkeynes@671
  2329
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2330
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2331
	SLOTILLEGAL();
nkeynes@386
  2332
    } else {
nkeynes@586
  2333
	check_priv();
nkeynes@386
  2334
	load_reg( R_EAX, Rm );
nkeynes@395
  2335
	check_ralign32( R_EAX );
nkeynes@939
  2336
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2337
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
  2338
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2339
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2340
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2341
	return 2;
nkeynes@386
  2342
    }
nkeynes@359
  2343
:}
nkeynes@359
  2344
LDC.L @Rm+, VBR {:  
nkeynes@671
  2345
    COUNT_INST(I_LDCM);
nkeynes@586
  2346
    check_priv();
nkeynes@359
  2347
    load_reg( R_EAX, Rm );
nkeynes@395
  2348
    check_ralign32( R_EAX );
nkeynes@939
  2349
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2350
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2351
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2352
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2353
:}
nkeynes@359
  2354
LDC.L @Rm+, SSR {:
nkeynes@671
  2355
    COUNT_INST(I_LDCM);
nkeynes@586
  2356
    check_priv();
nkeynes@359
  2357
    load_reg( R_EAX, Rm );
nkeynes@416
  2358
    check_ralign32( R_EAX );
nkeynes@939
  2359
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2360
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2361
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2363
:}
nkeynes@359
  2364
LDC.L @Rm+, SGR {:  
nkeynes@671
  2365
    COUNT_INST(I_LDCM);
nkeynes@586
  2366
    check_priv();
nkeynes@359
  2367
    load_reg( R_EAX, Rm );
nkeynes@395
  2368
    check_ralign32( R_EAX );
nkeynes@939
  2369
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2370
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2371
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2373
:}
nkeynes@359
  2374
LDC.L @Rm+, SPC {:  
nkeynes@671
  2375
    COUNT_INST(I_LDCM);
nkeynes@586
  2376
    check_priv();
nkeynes@359
  2377
    load_reg( R_EAX, Rm );
nkeynes@395
  2378
    check_ralign32( R_EAX );
nkeynes@939
  2379
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2380
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2381
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2382
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2383
:}
nkeynes@359
  2384
LDC.L @Rm+, DBR {:  
nkeynes@671
  2385
    COUNT_INST(I_LDCM);
nkeynes@586
  2386
    check_priv();
nkeynes@359
  2387
    load_reg( R_EAX, Rm );
nkeynes@395
  2388
    check_ralign32( R_EAX );
nkeynes@939
  2389
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2390
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2391
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2393
:}
nkeynes@359
  2394
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2395
    COUNT_INST(I_LDCM);
nkeynes@586
  2396
    check_priv();
nkeynes@374
  2397
    load_reg( R_EAX, Rm );
nkeynes@395
  2398
    check_ralign32( R_EAX );
nkeynes@939
  2399
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2400
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@374
  2401
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2403
:}
nkeynes@626
  2404
LDS Rm, FPSCR {:
nkeynes@673
  2405
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2406
    check_fpuen();
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@669
  2408
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2409
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2410
    return 2;
nkeynes@359
  2411
:}
nkeynes@359
  2412
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2413
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2414
    check_fpuen();
nkeynes@359
  2415
    load_reg( R_EAX, Rm );
nkeynes@395
  2416
    check_ralign32( R_EAX );
nkeynes@939
  2417
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2418
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@669
  2419
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2421
    return 2;
nkeynes@359
  2422
:}
nkeynes@359
  2423
LDS Rm, FPUL {:  
nkeynes@671
  2424
    COUNT_INST(I_LDS);
nkeynes@626
  2425
    check_fpuen();
nkeynes@359
  2426
    load_reg( R_EAX, Rm );
nkeynes@359
  2427
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2428
:}
nkeynes@359
  2429
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2430
    COUNT_INST(I_LDSM);
nkeynes@626
  2431
    check_fpuen();
nkeynes@359
  2432
    load_reg( R_EAX, Rm );
nkeynes@395
  2433
    check_ralign32( R_EAX );
nkeynes@939
  2434
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2435
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2436
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2437
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2438
:}
nkeynes@359
  2439
LDS Rm, MACH {: 
nkeynes@671
  2440
    COUNT_INST(I_LDS);
nkeynes@359
  2441
    load_reg( R_EAX, Rm );
nkeynes@359
  2442
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2443
:}
nkeynes@359
  2444
LDS.L @Rm+, MACH {:  
nkeynes@671
  2445
    COUNT_INST(I_LDSM);
nkeynes@359
  2446
    load_reg( R_EAX, Rm );
nkeynes@395
  2447
    check_ralign32( R_EAX );
nkeynes@939
  2448
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2449
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2450
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2452
:}
nkeynes@359
  2453
LDS Rm, MACL {:  
nkeynes@671
  2454
    COUNT_INST(I_LDS);
nkeynes@359
  2455
    load_reg( R_EAX, Rm );
nkeynes@359
  2456
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2457
:}
nkeynes@359
  2458
LDS.L @Rm+, MACL {:  
nkeynes@671
  2459
    COUNT_INST(I_LDSM);
nkeynes@359
  2460
    load_reg( R_EAX, Rm );
nkeynes@395
  2461
    check_ralign32( R_EAX );
nkeynes@939
  2462
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2463
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2464
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2465
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2466
:}
nkeynes@359
  2467
LDS Rm, PR {:  
nkeynes@671
  2468
    COUNT_INST(I_LDS);
nkeynes@359
  2469
    load_reg( R_EAX, Rm );
nkeynes@359
  2470
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2471
:}
nkeynes@359
  2472
LDS.L @Rm+, PR {:  
nkeynes@671
  2473
    COUNT_INST(I_LDSM);
nkeynes@359
  2474
    load_reg( R_EAX, Rm );
nkeynes@395
  2475
    check_ralign32( R_EAX );
nkeynes@939
  2476
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2477
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2478
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2480
:}
nkeynes@550
  2481
LDTLB {:  
nkeynes@671
  2482
    COUNT_INST(I_LDTLB);
nkeynes@553
  2483
    call_func0( MMU_ldtlb );
nkeynes@875
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2485
:}
nkeynes@671
  2486
OCBI @Rn {:
nkeynes@671
  2487
    COUNT_INST(I_OCBI);
nkeynes@671
  2488
:}
nkeynes@671
  2489
OCBP @Rn {:
nkeynes@671
  2490
    COUNT_INST(I_OCBP);
nkeynes@671
  2491
:}
nkeynes@671
  2492
OCBWB @Rn {:
nkeynes@671
  2493
    COUNT_INST(I_OCBWB);
nkeynes@671
  2494
:}
nkeynes@374
  2495
PREF @Rn {:
nkeynes@671
  2496
    COUNT_INST(I_PREF);
nkeynes@374
  2497
    load_reg( R_EAX, Rn );
nkeynes@532
  2498
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2499
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2500
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2501
    JNE_rel8(end);
nkeynes@911
  2502
    if( sh4_x86.tlb_on ) {
nkeynes@911
  2503
    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
nkeynes@911
  2504
        TEST_r32_r32( R_EAX, R_EAX );
nkeynes@911
  2505
        JE_exc(-1);
nkeynes@911
  2506
    } else {
nkeynes@911
  2507
    	call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@911
  2508
   	}
nkeynes@380
  2509
    JMP_TARGET(end);
nkeynes@417
  2510
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2511
:}
nkeynes@388
  2512
SLEEP {: 
nkeynes@671
  2513
    COUNT_INST(I_SLEEP);
nkeynes@388
  2514
    check_priv();
nkeynes@388
  2515
    call_func0( sh4_sleep );
nkeynes@417
  2516
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2517
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2518
    return 2;
nkeynes@388
  2519
:}
nkeynes@386
  2520
STC SR, Rn {:
nkeynes@671
  2521
    COUNT_INST(I_STCSR);
nkeynes@386
  2522
    check_priv();
nkeynes@386
  2523
    call_func0(sh4_read_sr);
nkeynes@386
  2524
    store_reg( R_EAX, Rn );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
STC GBR, Rn {:  
nkeynes@671
  2528
    COUNT_INST(I_STC);
nkeynes@359
  2529
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2530
    store_reg( R_EAX, Rn );
nkeynes@359
  2531
:}
nkeynes@359
  2532
STC VBR, Rn {:  
nkeynes@671
  2533
    COUNT_INST(I_STC);
nkeynes@386
  2534
    check_priv();
nkeynes@359
  2535
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2536
    store_reg( R_EAX, Rn );
nkeynes@417
  2537
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2538
:}
nkeynes@359
  2539
STC SSR, Rn {:  
nkeynes@671
  2540
    COUNT_INST(I_STC);
nkeynes@386
  2541
    check_priv();
nkeynes@359
  2542
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2543
    store_reg( R_EAX, Rn );
nkeynes@417
  2544
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2545
:}
nkeynes@359
  2546
STC SPC, Rn {:  
nkeynes@671
  2547
    COUNT_INST(I_STC);
nkeynes@386
  2548
    check_priv();
nkeynes@359
  2549
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2550
    store_reg( R_EAX, Rn );
nkeynes@417
  2551
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2552
:}
nkeynes@359
  2553
STC SGR, Rn {:  
nkeynes@671
  2554
    COUNT_INST(I_STC);
nkeynes@386
  2555
    check_priv();
nkeynes@359
  2556
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2557
    store_reg( R_EAX, Rn );
nkeynes@417
  2558
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2559
:}
nkeynes@359
  2560
STC DBR, Rn {:  
nkeynes@671
  2561
    COUNT_INST(I_STC);
nkeynes@386
  2562
    check_priv();
nkeynes@359
  2563
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2564
    store_reg( R_EAX, Rn );
nkeynes@417
  2565
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2566
:}
nkeynes@374
  2567
STC Rm_BANK, Rn {:
nkeynes@671
  2568
    COUNT_INST(I_STC);
nkeynes@386
  2569
    check_priv();
nkeynes@374
  2570
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2571
    store_reg( R_EAX, Rn );
nkeynes@417
  2572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2573
:}
nkeynes@374
  2574
STC.L SR, @-Rn {:
nkeynes@671
  2575
    COUNT_INST(I_STCSRM);
nkeynes@586
  2576
    check_priv();
nkeynes@939
  2577
    call_func0( sh4_read_sr );
nkeynes@939
  2578
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@586
  2579
    load_reg( R_EAX, Rn );
nkeynes@586
  2580
    check_walign32( R_EAX );
nkeynes@939
  2581
    LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@939
  2582
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2583
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2584
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2585
:}
nkeynes@359
  2586
STC.L VBR, @-Rn {:  
nkeynes@671
  2587
    COUNT_INST(I_STCM);
nkeynes@586
  2588
    check_priv();
nkeynes@586
  2589
    load_reg( R_EAX, Rn );
nkeynes@586
  2590
    check_walign32( R_EAX );
nkeynes@586
  2591
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2592
    load_spreg( R_EDX, R_VBR );
nkeynes@939
  2593
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2594
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2595
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2596
:}
nkeynes@359
  2597
STC.L SSR, @-Rn {:  
nkeynes@671
  2598
    COUNT_INST(I_STCM);
nkeynes@586
  2599
    check_priv();
nkeynes@586
  2600
    load_reg( R_EAX, Rn );
nkeynes@586
  2601
    check_walign32( R_EAX );
nkeynes@586
  2602
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2603
    load_spreg( R_EDX, R_SSR );
nkeynes@939
  2604
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2605
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2606
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2607
:}
nkeynes@416
  2608
STC.L SPC, @-Rn {:
nkeynes@671
  2609
    COUNT_INST(I_STCM);
nkeynes@586
  2610
    check_priv();
nkeynes@586
  2611
    load_reg( R_EAX, Rn );
nkeynes@586
  2612
    check_walign32( R_EAX );
nkeynes@586
  2613
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2614
    load_spreg( R_EDX, R_SPC );
nkeynes@939
  2615
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2616
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2617
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2618
:}
nkeynes@359
  2619
STC.L SGR, @-Rn {:  
nkeynes@671
  2620
    COUNT_INST(I_STCM);
nkeynes@586
  2621
    check_priv();
nkeynes@586
  2622
    load_reg( R_EAX, Rn );
nkeynes@586
  2623
    check_walign32( R_EAX );
nkeynes@586
  2624
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2625
    load_spreg( R_EDX, R_SGR );
nkeynes@939
  2626
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2627
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2628
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2629
:}
nkeynes@359
  2630
STC.L DBR, @-Rn {:  
nkeynes@671
  2631
    COUNT_INST(I_STCM);
nkeynes@586
  2632
    check_priv();
nkeynes@586
  2633
    load_reg( R_EAX, Rn );
nkeynes@586
  2634
    check_walign32( R_EAX );
nkeynes@586
  2635
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2636
    load_spreg( R_EDX, R_DBR );
nkeynes@939
  2637
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2638
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2639
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2640
:}
nkeynes@374
  2641
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2642
    COUNT_INST(I_STCM);
nkeynes@586
  2643
    check_priv();
nkeynes@586
  2644
    load_reg( R_EAX, Rn );
nkeynes@586
  2645
    check_walign32( R_EAX );
nkeynes@586
  2646
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2647
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@939
  2648
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2649
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2650
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2651
:}
nkeynes@359
  2652
STC.L GBR, @-Rn {:  
nkeynes@671
  2653
    COUNT_INST(I_STCM);
nkeynes@586
  2654
    load_reg( R_EAX, Rn );
nkeynes@586
  2655
    check_walign32( R_EAX );
nkeynes@586
  2656
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2657
    load_spreg( R_EDX, R_GBR );
nkeynes@939
  2658
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2659
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2660
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2661
:}
nkeynes@359
  2662
STS FPSCR, Rn {:  
nkeynes@673
  2663
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2664
    check_fpuen();
nkeynes@359
  2665
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2666
    store_reg( R_EAX, Rn );
nkeynes@359
  2667
:}
nkeynes@359
  2668
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2669
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2670
    check_fpuen();
nkeynes@586
  2671
    load_reg( R_EAX, Rn );
nkeynes@586
  2672
    check_walign32( R_EAX );
nkeynes@586
  2673
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2674
    load_spreg( R_EDX, R_FPSCR );
nkeynes@939
  2675
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2676
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2677
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2678
:}
nkeynes@359
  2679
STS FPUL, Rn {:  
nkeynes@671
  2680
    COUNT_INST(I_STS);
nkeynes@626
  2681
    check_fpuen();
nkeynes@359
  2682
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2683
    store_reg( R_EAX, Rn );
nkeynes@359
  2684
:}
nkeynes@359
  2685
STS.L FPUL, @-Rn {:  
nkeynes@671
  2686
    COUNT_INST(I_STSM);
nkeynes@626
  2687
    check_fpuen();
nkeynes@586
  2688
    load_reg( R_EAX, Rn );
nkeynes@586
  2689
    check_walign32( R_EAX );
nkeynes@586
  2690
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2691
    load_spreg( R_EDX, R_FPUL );
nkeynes@939
  2692
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2693
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2695
:}
nkeynes@359
  2696
STS MACH, Rn {:  
nkeynes@671
  2697
    COUNT_INST(I_STS);
nkeynes@359
  2698
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2699
    store_reg( R_EAX, Rn );
nkeynes@359
  2700
:}
nkeynes@359
  2701
STS.L MACH, @-Rn {:  
nkeynes@671
  2702
    COUNT_INST(I_STSM);
nkeynes@586
  2703
    load_reg( R_EAX, Rn );
nkeynes@586
  2704
    check_walign32( R_EAX );
nkeynes@586
  2705
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2706
    load_spreg( R_EDX, R_MACH );
nkeynes@939
  2707
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2708
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2709
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2710
:}
nkeynes@359
  2711
STS MACL, Rn {:  
nkeynes@671
  2712
    COUNT_INST(I_STS);
nkeynes@359
  2713
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2714
    store_reg( R_EAX, Rn );
nkeynes@359
  2715
:}
nkeynes@359
  2716
STS.L MACL, @-Rn {:  
nkeynes@671
  2717
    COUNT_INST(I_STSM);
nkeynes@586
  2718
    load_reg( R_EAX, Rn );
nkeynes@586
  2719
    check_walign32( R_EAX );
nkeynes@586
  2720
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2721
    load_spreg( R_EDX, R_MACL );
nkeynes@939
  2722
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2723
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2724
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2725
:}
nkeynes@359
  2726
STS PR, Rn {:  
nkeynes@671
  2727
    COUNT_INST(I_STS);
nkeynes@359
  2728
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2729
    store_reg( R_EAX, Rn );
nkeynes@359
  2730
:}
nkeynes@359
  2731
STS.L PR, @-Rn {:  
nkeynes@671
  2732
    COUNT_INST(I_STSM);
nkeynes@586
  2733
    load_reg( R_EAX, Rn );
nkeynes@586
  2734
    check_walign32( R_EAX );
nkeynes@586
  2735
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2736
    load_spreg( R_EDX, R_PR );
nkeynes@939
  2737
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2738
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2739
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2740
:}
nkeynes@359
  2741
nkeynes@671
  2742
NOP {: 
nkeynes@671
  2743
    COUNT_INST(