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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 386:6fb10951326a
prev381:aade6c9aca4d
next388:13bae2fb0373
author nkeynes
date Sun Sep 16 07:03:23 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Implement MAC.W, MAC.L and DIV1
Correct SHAD/SHLD
Fix privilege and slot illegal checks on LDC/STC opcodes
Fix various other small bugs
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.9 2007-09-16 07:03:23 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void signsat48( void )
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{
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    if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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	sh4r.mac = 0xFFFF800000000000LL;
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    else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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	sh4r.mac = 0x00007FFFFFFFFFFFLL;
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}
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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   322
}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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   333
    JNE_exit(EXIT_DATA_ADDR_WRITE);
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   334
}
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   335
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static inline void raise_exception( int exc )
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{
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    PUSH_imm32(exc);
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    call_func0(sh4_raise_exception);
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    ADD_imm8s_r32( 4, R_ESP );
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    sh4_x86.in_delay_slot = FALSE;
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   353
}
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   354
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   357
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   358
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   359
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   360
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   361
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   362
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   363
nkeynes@386
   364
#define RAISE_EXCEPTION( exc ) raise_exception(exc); return 1;
nkeynes@386
   365
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   366
nkeynes@368
   367
nkeynes@359
   368
nkeynes@359
   369
/**
nkeynes@359
   370
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   371
 * SI/DI as required
nkeynes@359
   372
 */
nkeynes@368
   373
void sh4_translate_begin_block() 
nkeynes@368
   374
{
nkeynes@368
   375
    PUSH_r32(R_EBP);
nkeynes@359
   376
    /* mov &sh4r, ebp */
nkeynes@359
   377
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   378
    PUSH_r32(R_EDI);
nkeynes@368
   379
    PUSH_r32(R_ESI);
nkeynes@380
   380
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   381
    
nkeynes@368
   382
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   383
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   384
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   385
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   386
}
nkeynes@359
   387
nkeynes@368
   388
/**
nkeynes@368
   389
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   390
 */
nkeynes@374
   391
void exit_block( )
nkeynes@368
   392
{
nkeynes@374
   393
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   394
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   395
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   396
    MUL_r32( R_ESI );
nkeynes@368
   397
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   398
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@381
   399
    load_imm32( R_EAX, 1 );
nkeynes@374
   400
    POP_r32(R_ESI);
nkeynes@374
   401
    POP_r32(R_EDI);
nkeynes@374
   402
    POP_r32(R_EBP);
nkeynes@368
   403
    RET();
nkeynes@359
   404
}
nkeynes@359
   405
nkeynes@359
   406
/**
nkeynes@359
   407
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   408
 */
nkeynes@359
   409
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   410
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   411
    // Normal termination - save PC, cycle count
nkeynes@374
   412
    exit_block( );
nkeynes@359
   413
nkeynes@368
   414
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   415
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   416
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@380
   417
    JMP_rel8( 33, target1 );
nkeynes@368
   418
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@380
   419
    JMP_rel8( 26, target2 );
nkeynes@368
   420
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@380
   421
    JMP_rel8( 19, target3 );
nkeynes@368
   422
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@380
   423
    JMP_rel8( 12, target4 );
nkeynes@368
   424
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@380
   425
    JMP_rel8( 5, target5 );
nkeynes@368
   426
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   427
    // target
nkeynes@380
   428
    JMP_TARGET(target1);
nkeynes@380
   429
    JMP_TARGET(target2);
nkeynes@380
   430
    JMP_TARGET(target3);
nkeynes@380
   431
    JMP_TARGET(target4);
nkeynes@380
   432
    JMP_TARGET(target5);
nkeynes@368
   433
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   434
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   435
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   436
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   437
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   438
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   439
    MUL_r32( R_ESI );
nkeynes@368
   440
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   441
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   442
nkeynes@368
   443
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   444
    CALL_r32( R_EAX ); // 2
nkeynes@386
   445
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@386
   446
    POP_r32(R_ESI);
nkeynes@386
   447
    POP_r32(R_EDI);
nkeynes@368
   448
    POP_r32(R_EBP);
nkeynes@368
   449
    RET();
nkeynes@368
   450
nkeynes@368
   451
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   452
}
nkeynes@359
   453
nkeynes@359
   454
/**
nkeynes@359
   455
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   456
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   457
 * 
nkeynes@359
   458
 *
nkeynes@359
   459
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   460
 * (eg a branch or 
nkeynes@359
   461
 */
nkeynes@359
   462
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   463
{
nkeynes@361
   464
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   465
    
nkeynes@359
   466
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   467
            case 0x0:
nkeynes@359
   468
                switch( ir&0xF ) {
nkeynes@359
   469
                    case 0x2:
nkeynes@359
   470
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   471
                            case 0x0:
nkeynes@359
   472
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   473
                                    case 0x0:
nkeynes@359
   474
                                        { /* STC SR, Rn */
nkeynes@359
   475
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   476
                                        check_priv();
nkeynes@374
   477
                                        call_func0(sh4_read_sr);
nkeynes@368
   478
                                        store_reg( R_EAX, Rn );
nkeynes@359
   479
                                        }
nkeynes@359
   480
                                        break;
nkeynes@359
   481
                                    case 0x1:
nkeynes@359
   482
                                        { /* STC GBR, Rn */
nkeynes@359
   483
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   484
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   485
                                        store_reg( R_EAX, Rn );
nkeynes@359
   486
                                        }
nkeynes@359
   487
                                        break;
nkeynes@359
   488
                                    case 0x2:
nkeynes@359
   489
                                        { /* STC VBR, Rn */
nkeynes@359
   490
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   491
                                        check_priv();
nkeynes@359
   492
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   493
                                        store_reg( R_EAX, Rn );
nkeynes@359
   494
                                        }
nkeynes@359
   495
                                        break;
nkeynes@359
   496
                                    case 0x3:
nkeynes@359
   497
                                        { /* STC SSR, Rn */
nkeynes@359
   498
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   499
                                        check_priv();
nkeynes@359
   500
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   501
                                        store_reg( R_EAX, Rn );
nkeynes@359
   502
                                        }
nkeynes@359
   503
                                        break;
nkeynes@359
   504
                                    case 0x4:
nkeynes@359
   505
                                        { /* STC SPC, Rn */
nkeynes@359
   506
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   507
                                        check_priv();
nkeynes@359
   508
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   509
                                        store_reg( R_EAX, Rn );
nkeynes@359
   510
                                        }
nkeynes@359
   511
                                        break;
nkeynes@359
   512
                                    default:
nkeynes@359
   513
                                        UNDEF();
nkeynes@359
   514
                                        break;
nkeynes@359
   515
                                }
nkeynes@359
   516
                                break;
nkeynes@359
   517
                            case 0x1:
nkeynes@359
   518
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   519
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   520
                                check_priv();
nkeynes@374
   521
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   522
                                store_reg( R_EAX, Rn );
nkeynes@359
   523
                                }
nkeynes@359
   524
                                break;
nkeynes@359
   525
                        }
nkeynes@359
   526
                        break;
nkeynes@359
   527
                    case 0x3:
nkeynes@359
   528
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   529
                            case 0x0:
nkeynes@359
   530
                                { /* BSRF Rn */
nkeynes@359
   531
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   532
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   533
                            	SLOTILLEGAL();
nkeynes@374
   534
                                } else {
nkeynes@374
   535
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
   536
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
   537
                            	load_reg( R_EDI, Rn );
nkeynes@374
   538
                            	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
   539
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   540
                            	return 0;
nkeynes@374
   541
                                }
nkeynes@359
   542
                                }
nkeynes@359
   543
                                break;
nkeynes@359
   544
                            case 0x2:
nkeynes@359
   545
                                { /* BRAF Rn */
nkeynes@359
   546
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   547
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   548
                            	SLOTILLEGAL();
nkeynes@374
   549
                                } else {
nkeynes@374
   550
                            	load_reg( R_EDI, Rn );
nkeynes@386
   551
                            	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
   552
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   553
                            	return 0;
nkeynes@374
   554
                                }
nkeynes@359
   555
                                }
nkeynes@359
   556
                                break;
nkeynes@359
   557
                            case 0x8:
nkeynes@359
   558
                                { /* PREF @Rn */
nkeynes@359
   559
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   560
                                load_reg( R_EAX, Rn );
nkeynes@374
   561
                                PUSH_r32( R_EAX );
nkeynes@374
   562
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   563
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
   564
                                JNE_rel8(7, end);
nkeynes@374
   565
                                call_func0( sh4_flush_store_queue );
nkeynes@380
   566
                                JMP_TARGET(end);
nkeynes@377
   567
                                ADD_imm8s_r32( 4, R_ESP );
nkeynes@359
   568
                                }
nkeynes@359
   569
                                break;
nkeynes@359
   570
                            case 0x9:
nkeynes@359
   571
                                { /* OCBI @Rn */
nkeynes@359
   572
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   573
                                }
nkeynes@359
   574
                                break;
nkeynes@359
   575
                            case 0xA:
nkeynes@359
   576
                                { /* OCBP @Rn */
nkeynes@359
   577
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   578
                                }
nkeynes@359
   579
                                break;
nkeynes@359
   580
                            case 0xB:
nkeynes@359
   581
                                { /* OCBWB @Rn */
nkeynes@359
   582
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   583
                                }
nkeynes@359
   584
                                break;
nkeynes@359
   585
                            case 0xC:
nkeynes@359
   586
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   587
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   588
                                load_reg( R_EAX, 0 );
nkeynes@361
   589
                                load_reg( R_ECX, Rn );
nkeynes@374
   590
                                check_walign32( R_ECX );
nkeynes@361
   591
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   592
                                }
nkeynes@359
   593
                                break;
nkeynes@359
   594
                            default:
nkeynes@359
   595
                                UNDEF();
nkeynes@359
   596
                                break;
nkeynes@359
   597
                        }
nkeynes@359
   598
                        break;
nkeynes@359
   599
                    case 0x4:
nkeynes@359
   600
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   601
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   602
                        load_reg( R_EAX, 0 );
nkeynes@359
   603
                        load_reg( R_ECX, Rn );
nkeynes@359
   604
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   605
                        load_reg( R_EAX, Rm );
nkeynes@359
   606
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   607
                        }
nkeynes@359
   608
                        break;
nkeynes@359
   609
                    case 0x5:
nkeynes@359
   610
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   611
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   612
                        load_reg( R_EAX, 0 );
nkeynes@361
   613
                        load_reg( R_ECX, Rn );
nkeynes@361
   614
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   615
                        check_walign16( R_ECX );
nkeynes@361
   616
                        load_reg( R_EAX, Rm );
nkeynes@361
   617
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   618
                        }
nkeynes@359
   619
                        break;
nkeynes@359
   620
                    case 0x6:
nkeynes@359
   621
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   622
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   623
                        load_reg( R_EAX, 0 );
nkeynes@361
   624
                        load_reg( R_ECX, Rn );
nkeynes@361
   625
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   626
                        check_walign32( R_ECX );
nkeynes@361
   627
                        load_reg( R_EAX, Rm );
nkeynes@361
   628
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   629
                        }
nkeynes@359
   630
                        break;
nkeynes@359
   631
                    case 0x7:
nkeynes@359
   632
                        { /* MUL.L Rm, Rn */
nkeynes@359
   633
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   634
                        load_reg( R_EAX, Rm );
nkeynes@361
   635
                        load_reg( R_ECX, Rn );
nkeynes@361
   636
                        MUL_r32( R_ECX );
nkeynes@361
   637
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   638
                        }
nkeynes@359
   639
                        break;
nkeynes@359
   640
                    case 0x8:
nkeynes@359
   641
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   642
                            case 0x0:
nkeynes@359
   643
                                { /* CLRT */
nkeynes@374
   644
                                CLC();
nkeynes@374
   645
                                SETC_t();
nkeynes@359
   646
                                }
nkeynes@359
   647
                                break;
nkeynes@359
   648
                            case 0x1:
nkeynes@359
   649
                                { /* SETT */
nkeynes@374
   650
                                STC();
nkeynes@374
   651
                                SETC_t();
nkeynes@359
   652
                                }
nkeynes@359
   653
                                break;
nkeynes@359
   654
                            case 0x2:
nkeynes@359
   655
                                { /* CLRMAC */
nkeynes@374
   656
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   657
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   658
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   659
                                }
nkeynes@359
   660
                                break;
nkeynes@359
   661
                            case 0x3:
nkeynes@359
   662
                                { /* LDTLB */
nkeynes@359
   663
                                }
nkeynes@359
   664
                                break;
nkeynes@359
   665
                            case 0x4:
nkeynes@359
   666
                                { /* CLRS */
nkeynes@374
   667
                                CLC();
nkeynes@374
   668
                                SETC_sh4r(R_S);
nkeynes@359
   669
                                }
nkeynes@359
   670
                                break;
nkeynes@359
   671
                            case 0x5:
nkeynes@359
   672
                                { /* SETS */
nkeynes@374
   673
                                STC();
nkeynes@374
   674
                                SETC_sh4r(R_S);
nkeynes@359
   675
                                }
nkeynes@359
   676
                                break;
nkeynes@359
   677
                            default:
nkeynes@359
   678
                                UNDEF();
nkeynes@359
   679
                                break;
nkeynes@359
   680
                        }
nkeynes@359
   681
                        break;
nkeynes@359
   682
                    case 0x9:
nkeynes@359
   683
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   684
                            case 0x0:
nkeynes@359
   685
                                { /* NOP */
nkeynes@359
   686
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   687
                                }
nkeynes@359
   688
                                break;
nkeynes@359
   689
                            case 0x1:
nkeynes@359
   690
                                { /* DIV0U */
nkeynes@361
   691
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   692
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   693
                                store_spreg( R_EAX, R_M );
nkeynes@361
   694
                                store_spreg( R_EAX, R_T );
nkeynes@359
   695
                                }
nkeynes@359
   696
                                break;
nkeynes@359
   697
                            case 0x2:
nkeynes@359
   698
                                { /* MOVT Rn */
nkeynes@359
   699
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   700
                                load_spreg( R_EAX, R_T );
nkeynes@359
   701
                                store_reg( R_EAX, Rn );
nkeynes@359
   702
                                }
nkeynes@359
   703
                                break;
nkeynes@359
   704
                            default:
nkeynes@359
   705
                                UNDEF();
nkeynes@359
   706
                                break;
nkeynes@359
   707
                        }
nkeynes@359
   708
                        break;
nkeynes@359
   709
                    case 0xA:
nkeynes@359
   710
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   711
                            case 0x0:
nkeynes@359
   712
                                { /* STS MACH, Rn */
nkeynes@359
   713
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   714
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   715
                                store_reg( R_EAX, Rn );
nkeynes@359
   716
                                }
nkeynes@359
   717
                                break;
nkeynes@359
   718
                            case 0x1:
nkeynes@359
   719
                                { /* STS MACL, Rn */
nkeynes@359
   720
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   721
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   722
                                store_reg( R_EAX, Rn );
nkeynes@359
   723
                                }
nkeynes@359
   724
                                break;
nkeynes@359
   725
                            case 0x2:
nkeynes@359
   726
                                { /* STS PR, Rn */
nkeynes@359
   727
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   728
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   729
                                store_reg( R_EAX, Rn );
nkeynes@359
   730
                                }
nkeynes@359
   731
                                break;
nkeynes@359
   732
                            case 0x3:
nkeynes@359
   733
                                { /* STC SGR, Rn */
nkeynes@359
   734
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   735
                                check_priv();
nkeynes@359
   736
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   737
                                store_reg( R_EAX, Rn );
nkeynes@359
   738
                                }
nkeynes@359
   739
                                break;
nkeynes@359
   740
                            case 0x5:
nkeynes@359
   741
                                { /* STS FPUL, Rn */
nkeynes@359
   742
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   743
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   744
                                store_reg( R_EAX, Rn );
nkeynes@359
   745
                                }
nkeynes@359
   746
                                break;
nkeynes@359
   747
                            case 0x6:
nkeynes@359
   748
                                { /* STS FPSCR, Rn */
nkeynes@359
   749
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   750
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   751
                                store_reg( R_EAX, Rn );
nkeynes@359
   752
                                }
nkeynes@359
   753
                                break;
nkeynes@359
   754
                            case 0xF:
nkeynes@359
   755
                                { /* STC DBR, Rn */
nkeynes@359
   756
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   757
                                check_priv();
nkeynes@359
   758
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   759
                                store_reg( R_EAX, Rn );
nkeynes@359
   760
                                }
nkeynes@359
   761
                                break;
nkeynes@359
   762
                            default:
nkeynes@359
   763
                                UNDEF();
nkeynes@359
   764
                                break;
nkeynes@359
   765
                        }
nkeynes@359
   766
                        break;
nkeynes@359
   767
                    case 0xB:
nkeynes@359
   768
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   769
                            case 0x0:
nkeynes@359
   770
                                { /* RTS */
nkeynes@374
   771
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   772
                            	SLOTILLEGAL();
nkeynes@374
   773
                                } else {
nkeynes@374
   774
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   775
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   776
                            	return 0;
nkeynes@374
   777
                                }
nkeynes@359
   778
                                }
nkeynes@359
   779
                                break;
nkeynes@359
   780
                            case 0x1:
nkeynes@359
   781
                                { /* SLEEP */
nkeynes@374
   782
                                /* TODO */
nkeynes@359
   783
                                }
nkeynes@359
   784
                                break;
nkeynes@359
   785
                            case 0x2:
nkeynes@359
   786
                                { /* RTE */
nkeynes@374
   787
                                check_priv();
nkeynes@374
   788
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   789
                            	SLOTILLEGAL();
nkeynes@374
   790
                                } else {
nkeynes@386
   791
                            	load_spreg( R_EDI, R_SPC );
nkeynes@374
   792
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   793
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   794
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   795
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   796
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
   797
                            	return 0;
nkeynes@374
   798
                                }
nkeynes@359
   799
                                }
nkeynes@359
   800
                                break;
nkeynes@359
   801
                            default:
nkeynes@359
   802
                                UNDEF();
nkeynes@359
   803
                                break;
nkeynes@359
   804
                        }
nkeynes@359
   805
                        break;
nkeynes@359
   806
                    case 0xC:
nkeynes@359
   807
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   808
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   809
                        load_reg( R_EAX, 0 );
nkeynes@359
   810
                        load_reg( R_ECX, Rm );
nkeynes@359
   811
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   812
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   813
                        store_reg( R_EAX, Rn );
nkeynes@359
   814
                        }
nkeynes@359
   815
                        break;
nkeynes@359
   816
                    case 0xD:
nkeynes@359
   817
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   818
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   819
                        load_reg( R_EAX, 0 );
nkeynes@361
   820
                        load_reg( R_ECX, Rm );
nkeynes@361
   821
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   822
                        check_ralign16( R_ECX );
nkeynes@361
   823
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   824
                        store_reg( R_EAX, Rn );
nkeynes@359
   825
                        }
nkeynes@359
   826
                        break;
nkeynes@359
   827
                    case 0xE:
nkeynes@359
   828
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   829
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   830
                        load_reg( R_EAX, 0 );
nkeynes@361
   831
                        load_reg( R_ECX, Rm );
nkeynes@361
   832
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   833
                        check_ralign32( R_ECX );
nkeynes@361
   834
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   835
                        store_reg( R_EAX, Rn );
nkeynes@359
   836
                        }
nkeynes@359
   837
                        break;
nkeynes@359
   838
                    case 0xF:
nkeynes@359
   839
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   840
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   841
                        load_reg( R_ECX, Rm );
nkeynes@386
   842
                        check_ralign32( R_ECX );
nkeynes@386
   843
                        load_reg( R_ECX, Rn );
nkeynes@386
   844
                        check_ralign32( R_ECX );
nkeynes@386
   845
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   846
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   847
                        PUSH_r32( R_EAX );
nkeynes@386
   848
                        load_reg( R_ECX, Rm );
nkeynes@386
   849
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   850
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   851
                        POP_r32( R_ECX );
nkeynes@386
   852
                        IMUL_r32( R_ECX );
nkeynes@386
   853
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   854
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   855
                    
nkeynes@386
   856
                        load_spreg( R_ECX, R_S );
nkeynes@386
   857
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   858
                        JE_rel8( 7, nosat );
nkeynes@386
   859
                        call_func0( signsat48 );
nkeynes@386
   860
                        JMP_TARGET( nosat );
nkeynes@359
   861
                        }
nkeynes@359
   862
                        break;
nkeynes@359
   863
                    default:
nkeynes@359
   864
                        UNDEF();
nkeynes@359
   865
                        break;
nkeynes@359
   866
                }
nkeynes@359
   867
                break;
nkeynes@359
   868
            case 0x1:
nkeynes@359
   869
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   870
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   871
                load_reg( R_ECX, Rn );
nkeynes@361
   872
                load_reg( R_EAX, Rm );
nkeynes@361
   873
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   874
                check_walign32( R_ECX );
nkeynes@361
   875
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   876
                }
nkeynes@359
   877
                break;
nkeynes@359
   878
            case 0x2:
nkeynes@359
   879
                switch( ir&0xF ) {
nkeynes@359
   880
                    case 0x0:
nkeynes@359
   881
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   882
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   883
                        load_reg( R_EAX, Rm );
nkeynes@359
   884
                        load_reg( R_ECX, Rn );
nkeynes@359
   885
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   886
                        }
nkeynes@359
   887
                        break;
nkeynes@359
   888
                    case 0x1:
nkeynes@359
   889
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   890
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   891
                        load_reg( R_ECX, Rn );
nkeynes@374
   892
                        check_walign16( R_ECX );
nkeynes@386
   893
                        load_reg( R_EAX, Rm );
nkeynes@386
   894
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   895
                        }
nkeynes@359
   896
                        break;
nkeynes@359
   897
                    case 0x2:
nkeynes@359
   898
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   899
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   900
                        load_reg( R_EAX, Rm );
nkeynes@361
   901
                        load_reg( R_ECX, Rn );
nkeynes@374
   902
                        check_walign32(R_ECX);
nkeynes@361
   903
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   904
                        }
nkeynes@359
   905
                        break;
nkeynes@359
   906
                    case 0x4:
nkeynes@359
   907
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   908
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   909
                        load_reg( R_EAX, Rm );
nkeynes@359
   910
                        load_reg( R_ECX, Rn );
nkeynes@386
   911
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   912
                        store_reg( R_ECX, Rn );
nkeynes@359
   913
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   914
                        }
nkeynes@359
   915
                        break;
nkeynes@359
   916
                    case 0x5:
nkeynes@359
   917
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   918
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   919
                        load_reg( R_ECX, Rn );
nkeynes@374
   920
                        check_walign16( R_ECX );
nkeynes@361
   921
                        load_reg( R_EAX, Rm );
nkeynes@361
   922
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
   923
                        store_reg( R_ECX, Rn );
nkeynes@361
   924
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   925
                        }
nkeynes@359
   926
                        break;
nkeynes@359
   927
                    case 0x6:
nkeynes@359
   928
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   929
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   930
                        load_reg( R_EAX, Rm );
nkeynes@361
   931
                        load_reg( R_ECX, Rn );
nkeynes@374
   932
                        check_walign32( R_ECX );
nkeynes@361
   933
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   934
                        store_reg( R_ECX, Rn );
nkeynes@361
   935
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   936
                        }
nkeynes@359
   937
                        break;
nkeynes@359
   938
                    case 0x7:
nkeynes@359
   939
                        { /* DIV0S Rm, Rn */
nkeynes@359
   940
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   941
                        load_reg( R_EAX, Rm );
nkeynes@386
   942
                        load_reg( R_ECX, Rn );
nkeynes@361
   943
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   944
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   945
                        store_spreg( R_EAX, R_M );
nkeynes@361
   946
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   947
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   948
                        SETNE_t();
nkeynes@359
   949
                        }
nkeynes@359
   950
                        break;
nkeynes@359
   951
                    case 0x8:
nkeynes@359
   952
                        { /* TST Rm, Rn */
nkeynes@359
   953
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   954
                        load_reg( R_EAX, Rm );
nkeynes@361
   955
                        load_reg( R_ECX, Rn );
nkeynes@361
   956
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   957
                        SETE_t();
nkeynes@359
   958
                        }
nkeynes@359
   959
                        break;
nkeynes@359
   960
                    case 0x9:
nkeynes@359
   961
                        { /* AND Rm, Rn */
nkeynes@359
   962
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   963
                        load_reg( R_EAX, Rm );
nkeynes@359
   964
                        load_reg( R_ECX, Rn );
nkeynes@359
   965
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   966
                        store_reg( R_ECX, Rn );
nkeynes@359
   967
                        }
nkeynes@359
   968
                        break;
nkeynes@359
   969
                    case 0xA:
nkeynes@359
   970
                        { /* XOR Rm, Rn */
nkeynes@359
   971
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   972
                        load_reg( R_EAX, Rm );
nkeynes@359
   973
                        load_reg( R_ECX, Rn );
nkeynes@359
   974
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   975
                        store_reg( R_ECX, Rn );
nkeynes@359
   976
                        }
nkeynes@359
   977
                        break;
nkeynes@359
   978
                    case 0xB:
nkeynes@359
   979
                        { /* OR Rm, Rn */
nkeynes@359
   980
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   981
                        load_reg( R_EAX, Rm );
nkeynes@359
   982
                        load_reg( R_ECX, Rn );
nkeynes@359
   983
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   984
                        store_reg( R_ECX, Rn );
nkeynes@359
   985
                        }
nkeynes@359
   986
                        break;
nkeynes@359
   987
                    case 0xC:
nkeynes@359
   988
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   989
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   990
                        load_reg( R_EAX, Rm );
nkeynes@368
   991
                        load_reg( R_ECX, Rn );
nkeynes@368
   992
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   993
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   994
                        JE_rel8(13, target1);
nkeynes@368
   995
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   996
                        JE_rel8(9, target2);
nkeynes@368
   997
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   998
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   999
                        JE_rel8(2, target3);
nkeynes@368
  1000
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1001
                        JMP_TARGET(target1);
nkeynes@380
  1002
                        JMP_TARGET(target2);
nkeynes@380
  1003
                        JMP_TARGET(target3);
nkeynes@368
  1004
                        SETE_t();
nkeynes@359
  1005
                        }
nkeynes@359
  1006
                        break;
nkeynes@359
  1007
                    case 0xD:
nkeynes@359
  1008
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1009
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1010
                        load_reg( R_EAX, Rm );
nkeynes@361
  1011
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1012
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
  1013
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
  1014
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1015
                        store_reg( R_ECX, Rn );
nkeynes@359
  1016
                        }
nkeynes@359
  1017
                        break;
nkeynes@359
  1018
                    case 0xE:
nkeynes@359
  1019
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1020
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1021
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1022
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1023
                        MUL_r32( R_ECX );
nkeynes@374
  1024
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1025
                        }
nkeynes@359
  1026
                        break;
nkeynes@359
  1027
                    case 0xF:
nkeynes@359
  1028
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1029
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1030
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1031
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1032
                        MUL_r32( R_ECX );
nkeynes@374
  1033
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1034
                        }
nkeynes@359
  1035
                        break;
nkeynes@359
  1036
                    default:
nkeynes@359
  1037
                        UNDEF();
nkeynes@359
  1038
                        break;
nkeynes@359
  1039
                }
nkeynes@359
  1040
                break;
nkeynes@359
  1041
            case 0x3:
nkeynes@359
  1042
                switch( ir&0xF ) {
nkeynes@359
  1043
                    case 0x0:
nkeynes@359
  1044
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1045
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1046
                        load_reg( R_EAX, Rm );
nkeynes@359
  1047
                        load_reg( R_ECX, Rn );
nkeynes@359
  1048
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1049
                        SETE_t();
nkeynes@359
  1050
                        }
nkeynes@359
  1051
                        break;
nkeynes@359
  1052
                    case 0x2:
nkeynes@359
  1053
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1054
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1055
                        load_reg( R_EAX, Rm );
nkeynes@359
  1056
                        load_reg( R_ECX, Rn );
nkeynes@359
  1057
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1058
                        SETAE_t();
nkeynes@359
  1059
                        }
nkeynes@359
  1060
                        break;
nkeynes@359
  1061
                    case 0x3:
nkeynes@359
  1062
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1063
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1064
                        load_reg( R_EAX, Rm );
nkeynes@359
  1065
                        load_reg( R_ECX, Rn );
nkeynes@359
  1066
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1067
                        SETGE_t();
nkeynes@359
  1068
                        }
nkeynes@359
  1069
                        break;
nkeynes@359
  1070
                    case 0x4:
nkeynes@359
  1071
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1072
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1073
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1074
                        load_reg( R_EAX, Rn );
nkeynes@374
  1075
                        LDC_t();
nkeynes@386
  1076
                        RCL1_r32( R_EAX );
nkeynes@386
  1077
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1078
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1079
                        JE_rel8(5, mqequal);
nkeynes@386
  1080
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1081
                        JMP_rel8(3, end);
nkeynes@380
  1082
                        JMP_TARGET(mqequal);
nkeynes@386
  1083
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1084
                        JMP_TARGET(end);
nkeynes@386
  1085
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1086
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1087
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1088
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1089
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1090
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1091
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1092
                        store_spreg( R_EAX, R_T );
nkeynes@359
  1093
                        }
nkeynes@359
  1094
                        break;
nkeynes@359
  1095
                    case 0x5:
nkeynes@359
  1096
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1097
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1098
                        load_reg( R_EAX, Rm );
nkeynes@361
  1099
                        load_reg( R_ECX, Rn );
nkeynes@361
  1100
                        MUL_r32(R_ECX);
nkeynes@361
  1101
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1102
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1103
                        }
nkeynes@359
  1104
                        break;
nkeynes@359
  1105
                    case 0x6:
nkeynes@359
  1106
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1107
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1108
                        load_reg( R_EAX, Rm );
nkeynes@359
  1109
                        load_reg( R_ECX, Rn );
nkeynes@359
  1110
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1111
                        SETA_t();
nkeynes@359
  1112
                        }
nkeynes@359
  1113
                        break;
nkeynes@359
  1114
                    case 0x7:
nkeynes@359
  1115
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1116
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1117
                        load_reg( R_EAX, Rm );
nkeynes@359
  1118
                        load_reg( R_ECX, Rn );
nkeynes@359
  1119
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1120
                        SETG_t();
nkeynes@359
  1121
                        }
nkeynes@359
  1122
                        break;
nkeynes@359
  1123
                    case 0x8:
nkeynes@359
  1124
                        { /* SUB Rm, Rn */
nkeynes@359
  1125
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1126
                        load_reg( R_EAX, Rm );
nkeynes@359
  1127
                        load_reg( R_ECX, Rn );
nkeynes@359
  1128
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1129
                        store_reg( R_ECX, Rn );
nkeynes@359
  1130
                        }
nkeynes@359
  1131
                        break;
nkeynes@359
  1132
                    case 0xA:
nkeynes@359
  1133
                        { /* SUBC Rm, Rn */
nkeynes@359
  1134
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1135
                        load_reg( R_EAX, Rm );
nkeynes@359
  1136
                        load_reg( R_ECX, Rn );
nkeynes@359
  1137
                        LDC_t();
nkeynes@359
  1138
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1139
                        store_reg( R_ECX, Rn );
nkeynes@359
  1140
                        }
nkeynes@359
  1141
                        break;
nkeynes@359
  1142
                    case 0xB:
nkeynes@359
  1143
                        { /* SUBV Rm, Rn */
nkeynes@359
  1144
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1145
                        load_reg( R_EAX, Rm );
nkeynes@359
  1146
                        load_reg( R_ECX, Rn );
nkeynes@359
  1147
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1148
                        store_reg( R_ECX, Rn );
nkeynes@359
  1149
                        SETO_t();
nkeynes@359
  1150
                        }
nkeynes@359
  1151
                        break;
nkeynes@359
  1152
                    case 0xC:
nkeynes@359
  1153
                        { /* ADD Rm, Rn */
nkeynes@359
  1154
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1155
                        load_reg( R_EAX, Rm );
nkeynes@359
  1156
                        load_reg( R_ECX, Rn );
nkeynes@359
  1157
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1158
                        store_reg( R_ECX, Rn );
nkeynes@359
  1159
                        }
nkeynes@359
  1160
                        break;
nkeynes@359
  1161
                    case 0xD:
nkeynes@359
  1162
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1163
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1164
                        load_reg( R_EAX, Rm );
nkeynes@361
  1165
                        load_reg( R_ECX, Rn );
nkeynes@361
  1166
                        IMUL_r32(R_ECX);
nkeynes@361
  1167
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1168
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1169
                        }
nkeynes@359
  1170
                        break;
nkeynes@359
  1171
                    case 0xE:
nkeynes@359
  1172
                        { /* ADDC Rm, Rn */
nkeynes@359
  1173
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1174
                        load_reg( R_EAX, Rm );
nkeynes@359
  1175
                        load_reg( R_ECX, Rn );
nkeynes@359
  1176
                        LDC_t();
nkeynes@359
  1177
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1178
                        store_reg( R_ECX, Rn );
nkeynes@359
  1179
                        SETC_t();
nkeynes@359
  1180
                        }
nkeynes@359
  1181
                        break;
nkeynes@359
  1182
                    case 0xF:
nkeynes@359
  1183
                        { /* ADDV Rm, Rn */
nkeynes@359
  1184
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1185
                        load_reg( R_EAX, Rm );
nkeynes@359
  1186
                        load_reg( R_ECX, Rn );
nkeynes@359
  1187
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1188
                        store_reg( R_ECX, Rn );
nkeynes@359
  1189
                        SETO_t();
nkeynes@359
  1190
                        }
nkeynes@359
  1191
                        break;
nkeynes@359
  1192
                    default:
nkeynes@359
  1193
                        UNDEF();
nkeynes@359
  1194
                        break;
nkeynes@359
  1195
                }
nkeynes@359
  1196
                break;
nkeynes@359
  1197
            case 0x4:
nkeynes@359
  1198
                switch( ir&0xF ) {
nkeynes@359
  1199
                    case 0x0:
nkeynes@359
  1200
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1201
                            case 0x0:
nkeynes@359
  1202
                                { /* SHLL Rn */
nkeynes@359
  1203
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1204
                                load_reg( R_EAX, Rn );
nkeynes@359
  1205
                                SHL1_r32( R_EAX );
nkeynes@359
  1206
                                store_reg( R_EAX, Rn );
nkeynes@359
  1207
                                }
nkeynes@359
  1208
                                break;
nkeynes@359
  1209
                            case 0x1:
nkeynes@359
  1210
                                { /* DT Rn */
nkeynes@359
  1211
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1212
                                load_reg( R_EAX, Rn );
nkeynes@386
  1213
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1214
                                store_reg( R_EAX, Rn );
nkeynes@359
  1215
                                SETE_t();
nkeynes@359
  1216
                                }
nkeynes@359
  1217
                                break;
nkeynes@359
  1218
                            case 0x2:
nkeynes@359
  1219
                                { /* SHAL Rn */
nkeynes@359
  1220
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1221
                                load_reg( R_EAX, Rn );
nkeynes@359
  1222
                                SHL1_r32( R_EAX );
nkeynes@359
  1223
                                store_reg( R_EAX, Rn );
nkeynes@359
  1224
                                }
nkeynes@359
  1225
                                break;
nkeynes@359
  1226
                            default:
nkeynes@359
  1227
                                UNDEF();
nkeynes@359
  1228
                                break;
nkeynes@359
  1229
                        }
nkeynes@359
  1230
                        break;
nkeynes@359
  1231
                    case 0x1:
nkeynes@359
  1232
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1233
                            case 0x0:
nkeynes@359
  1234
                                { /* SHLR Rn */
nkeynes@359
  1235
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1236
                                load_reg( R_EAX, Rn );
nkeynes@359
  1237
                                SHR1_r32( R_EAX );
nkeynes@359
  1238
                                store_reg( R_EAX, Rn );
nkeynes@359
  1239
                                }
nkeynes@359
  1240
                                break;
nkeynes@359
  1241
                            case 0x1:
nkeynes@359
  1242
                                { /* CMP/PZ Rn */
nkeynes@359
  1243
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1244
                                load_reg( R_EAX, Rn );
nkeynes@359
  1245
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1246
                                SETGE_t();
nkeynes@359
  1247
                                }
nkeynes@359
  1248
                                break;
nkeynes@359
  1249
                            case 0x2:
nkeynes@359
  1250
                                { /* SHAR Rn */
nkeynes@359
  1251
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1252
                                load_reg( R_EAX, Rn );
nkeynes@359
  1253
                                SAR1_r32( R_EAX );
nkeynes@359
  1254
                                store_reg( R_EAX, Rn );
nkeynes@359
  1255
                                }
nkeynes@359
  1256
                                break;
nkeynes@359
  1257
                            default:
nkeynes@359
  1258
                                UNDEF();
nkeynes@359
  1259
                                break;
nkeynes@359
  1260
                        }
nkeynes@359
  1261
                        break;
nkeynes@359
  1262
                    case 0x2:
nkeynes@359
  1263
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1264
                            case 0x0:
nkeynes@359
  1265
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1266
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1267
                                load_reg( R_ECX, Rn );
nkeynes@386
  1268
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1269
                                store_reg( R_ECX, Rn );
nkeynes@359
  1270
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1271
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1272
                                }
nkeynes@359
  1273
                                break;
nkeynes@359
  1274
                            case 0x1:
nkeynes@359
  1275
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1276
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1277
                                load_reg( R_ECX, Rn );
nkeynes@386
  1278
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1279
                                store_reg( R_ECX, Rn );
nkeynes@359
  1280
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1281
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1282
                                }
nkeynes@359
  1283
                                break;
nkeynes@359
  1284
                            case 0x2:
nkeynes@359
  1285
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1286
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1287
                                load_reg( R_ECX, Rn );
nkeynes@386
  1288
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1289
                                store_reg( R_ECX, Rn );
nkeynes@359
  1290
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1291
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1292
                                }
nkeynes@359
  1293
                                break;
nkeynes@359
  1294
                            case 0x3:
nkeynes@359
  1295
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1296
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1297
                                check_priv();
nkeynes@359
  1298
                                load_reg( R_ECX, Rn );
nkeynes@386
  1299
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1300
                                store_reg( R_ECX, Rn );
nkeynes@359
  1301
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1302
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1303
                                }
nkeynes@359
  1304
                                break;
nkeynes@359
  1305
                            case 0x5:
nkeynes@359
  1306
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1307
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1308
                                load_reg( R_ECX, Rn );
nkeynes@386
  1309
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1310
                                store_reg( R_ECX, Rn );
nkeynes@359
  1311
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1312
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1313
                                }
nkeynes@359
  1314
                                break;
nkeynes@359
  1315
                            case 0x6:
nkeynes@359
  1316
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1317
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1318
                                load_reg( R_ECX, Rn );
nkeynes@386
  1319
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1320
                                store_reg( R_ECX, Rn );
nkeynes@359
  1321
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1322
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1323
                                }
nkeynes@359
  1324
                                break;
nkeynes@359
  1325
                            case 0xF:
nkeynes@359
  1326
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1327
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1328
                                check_priv();
nkeynes@359
  1329
                                load_reg( R_ECX, Rn );
nkeynes@386
  1330
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1331
                                store_reg( R_ECX, Rn );
nkeynes@359
  1332
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1333
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1334
                                }
nkeynes@359
  1335
                                break;
nkeynes@359
  1336
                            default:
nkeynes@359
  1337
                                UNDEF();
nkeynes@359
  1338
                                break;
nkeynes@359
  1339
                        }
nkeynes@359
  1340
                        break;
nkeynes@359
  1341
                    case 0x3:
nkeynes@359
  1342
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1343
                            case 0x0:
nkeynes@359
  1344
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1345
                                    case 0x0:
nkeynes@359
  1346
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1347
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1348
                                        check_priv();
nkeynes@374
  1349
                                        load_reg( R_ECX, Rn );
nkeynes@386
  1350
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1351
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1352
                                        call_func0( sh4_read_sr );
nkeynes@374
  1353
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1354
                                        }
nkeynes@359
  1355
                                        break;
nkeynes@359
  1356
                                    case 0x1:
nkeynes@359
  1357
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1358
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1359
                                        load_reg( R_ECX, Rn );
nkeynes@386
  1360
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1361
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1362
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1363
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1364
                                        }
nkeynes@359
  1365
                                        break;
nkeynes@359
  1366
                                    case 0x2:
nkeynes@359
  1367
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1368
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1369
                                        check_priv();
nkeynes@359
  1370
                                        load_reg( R_ECX, Rn );
nkeynes@386
  1371
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1372
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1373
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1374
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1375
                                        }
nkeynes@359
  1376
                                        break;
nkeynes@359
  1377
                                    case 0x3:
nkeynes@359
  1378
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1379
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1380
                                        check_priv();
nkeynes@359
  1381
                                        load_reg( R_ECX, Rn );
nkeynes@386
  1382
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1383
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1384
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1385
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1386
                                        }
nkeynes@359
  1387
                                        break;
nkeynes@359
  1388
                                    case 0x4:
nkeynes@359
  1389
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1390
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1391
                                        check_priv();
nkeynes@359
  1392
                                        load_reg( R_ECX, Rn );
nkeynes@386
  1393
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1394
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1395
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1396
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1397
                                        }
nkeynes@359
  1398
                                        break;
nkeynes@359
  1399
                                    default:
nkeynes@359
  1400
                                        UNDEF();
nkeynes@359
  1401
                                        break;
nkeynes@359
  1402
                                }
nkeynes@359
  1403
                                break;
nkeynes@359
  1404
                            case 0x1:
nkeynes@359
  1405
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1406
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1407
                                check_priv();
nkeynes@374
  1408
                                load_reg( R_ECX, Rn );
nkeynes@386
  1409
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1410
                                store_reg( R_ECX, Rn );
nkeynes@374
  1411
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1412
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1413
                                }
nkeynes@359
  1414
                                break;
nkeynes@359
  1415
                        }
nkeynes@359
  1416
                        break;
nkeynes@359
  1417
                    case 0x4:
nkeynes@359
  1418
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1419
                            case 0x0:
nkeynes@359
  1420
                                { /* ROTL Rn */
nkeynes@359
  1421
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1422
                                load_reg( R_EAX, Rn );
nkeynes@359
  1423
                                ROL1_r32( R_EAX );
nkeynes@359
  1424
                                store_reg( R_EAX, Rn );
nkeynes@359
  1425
                                SETC_t();
nkeynes@359
  1426
                                }
nkeynes@359
  1427
                                break;
nkeynes@359
  1428
                            case 0x2:
nkeynes@359
  1429
                                { /* ROTCL Rn */
nkeynes@359
  1430
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1431
                                load_reg( R_EAX, Rn );
nkeynes@359
  1432
                                LDC_t();
nkeynes@359
  1433
                                RCL1_r32( R_EAX );
nkeynes@359
  1434
                                store_reg( R_EAX, Rn );
nkeynes@359
  1435
                                SETC_t();
nkeynes@359
  1436
                                }
nkeynes@359
  1437
                                break;
nkeynes@359
  1438
                            default:
nkeynes@359
  1439
                                UNDEF();
nkeynes@359
  1440
                                break;
nkeynes@359
  1441
                        }
nkeynes@359
  1442
                        break;
nkeynes@359
  1443
                    case 0x5:
nkeynes@359
  1444
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1445
                            case 0x0:
nkeynes@359
  1446
                                { /* ROTR Rn */
nkeynes@359
  1447
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1448
                                load_reg( R_EAX, Rn );
nkeynes@359
  1449
                                ROR1_r32( R_EAX );
nkeynes@359
  1450
                                store_reg( R_EAX, Rn );
nkeynes@359
  1451
                                SETC_t();
nkeynes@359
  1452
                                }
nkeynes@359
  1453
                                break;
nkeynes@359
  1454
                            case 0x1:
nkeynes@359
  1455
                                { /* CMP/PL Rn */
nkeynes@359
  1456
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1457
                                load_reg( R_EAX, Rn );
nkeynes@359
  1458
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1459
                                SETG_t();
nkeynes@359
  1460
                                }
nkeynes@359
  1461
                                break;
nkeynes@359
  1462
                            case 0x2:
nkeynes@359
  1463
                                { /* ROTCR Rn */
nkeynes@359
  1464
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1465
                                load_reg( R_EAX, Rn );
nkeynes@359
  1466
                                LDC_t();
nkeynes@359
  1467
                                RCR1_r32( R_EAX );
nkeynes@359
  1468
                                store_reg( R_EAX, Rn );
nkeynes@359
  1469
                                SETC_t();
nkeynes@359
  1470
                                }
nkeynes@359
  1471
                                break;
nkeynes@359
  1472
                            default:
nkeynes@359
  1473
                                UNDEF();
nkeynes@359
  1474
                                break;
nkeynes@359
  1475
                        }
nkeynes@359
  1476
                        break;
nkeynes@359
  1477
                    case 0x6:
nkeynes@359
  1478
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1479
                            case 0x0:
nkeynes@359
  1480
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1481
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1482
                                load_reg( R_EAX, Rm );
nkeynes@359
  1483
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1484
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1485
                                store_reg( R_EAX, Rm );
nkeynes@359
  1486
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1487
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1488
                                }
nkeynes@359
  1489
                                break;
nkeynes@359
  1490
                            case 0x1:
nkeynes@359
  1491
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1492
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1493
                                load_reg( R_EAX, Rm );
nkeynes@359
  1494
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1495
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1496
                                store_reg( R_EAX, Rm );
nkeynes@359
  1497
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1498
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1499
                                }
nkeynes@359
  1500
                                break;
nkeynes@359
  1501
                            case 0x2:
nkeynes@359
  1502
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1503
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1504
                                load_reg( R_EAX, Rm );
nkeynes@359
  1505
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1506
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1507
                                store_reg( R_EAX, Rm );
nkeynes@359
  1508
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1509
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1510
                                }
nkeynes@359
  1511
                                break;
nkeynes@359
  1512
                            case 0x3:
nkeynes@359
  1513
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1514
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1515
                                check_priv();
nkeynes@359
  1516
                                load_reg( R_EAX, Rm );
nkeynes@359
  1517
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1518
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1519
                                store_reg( R_EAX, Rm );
nkeynes@359
  1520
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1521
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1522
                                }
nkeynes@359
  1523
                                break;
nkeynes@359
  1524
                            case 0x5:
nkeynes@359
  1525
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1526
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1527
                                load_reg( R_EAX, Rm );
nkeynes@359
  1528
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1529
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1530
                                store_reg( R_EAX, Rm );
nkeynes@359
  1531
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1532
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1533
                                }
nkeynes@359
  1534
                                break;
nkeynes@359
  1535
                            case 0x6:
nkeynes@359
  1536
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1537
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1538
                                load_reg( R_EAX, Rm );
nkeynes@359
  1539
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1540
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1541
                                store_reg( R_EAX, Rm );
nkeynes@359
  1542
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1543
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1544
                                update_fr_bank( R_EAX );
nkeynes@359
  1545
                                }
nkeynes@359
  1546
                                break;
nkeynes@359
  1547
                            case 0xF:
nkeynes@359
  1548
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1549
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1550
                                check_priv();
nkeynes@359
  1551
                                load_reg( R_EAX, Rm );
nkeynes@359
  1552
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1553
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1554
                                store_reg( R_EAX, Rm );
nkeynes@359
  1555
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1556
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1557
                                }
nkeynes@359
  1558
                                break;
nkeynes@359
  1559
                            default:
nkeynes@359
  1560
                                UNDEF();
nkeynes@359
  1561
                                break;
nkeynes@359
  1562
                        }
nkeynes@359
  1563
                        break;
nkeynes@359
  1564
                    case 0x7:
nkeynes@359
  1565
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1566
                            case 0x0:
nkeynes@359
  1567
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1568
                                    case 0x0:
nkeynes@359
  1569
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1570
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1571
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1572
                                    	SLOTILLEGAL();
nkeynes@386
  1573
                                        } else {
nkeynes@386
  1574
                                    	check_priv();
nkeynes@386
  1575
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1576
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1577
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1578
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1579
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1580
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1581
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1582
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  1583
                                        }
nkeynes@359
  1584
                                        }
nkeynes@359
  1585
                                        break;
nkeynes@359
  1586
                                    case 0x1:
nkeynes@359
  1587
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1588
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1589
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1590
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1591
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1592
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1593
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1594
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1595
                                        }
nkeynes@359
  1596
                                        break;
nkeynes@359
  1597
                                    case 0x2:
nkeynes@359
  1598
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1599
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1600
                                        check_priv();
nkeynes@359
  1601
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1602
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1603
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1604
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1605
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1606
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1607
                                        }
nkeynes@359
  1608
                                        break;
nkeynes@359
  1609
                                    case 0x3:
nkeynes@359
  1610
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1611
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1612
                                        check_priv();
nkeynes@359
  1613
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1614
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1615
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1616
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1617
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1618
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1619
                                        }
nkeynes@359
  1620
                                        break;
nkeynes@359
  1621
                                    case 0x4:
nkeynes@359
  1622
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1623
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1624
                                        check_priv();
nkeynes@359
  1625
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1626
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1627
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1628
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1629
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1630
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1631
                                        }
nkeynes@359
  1632
                                        break;
nkeynes@359
  1633
                                    default:
nkeynes@359
  1634
                                        UNDEF();
nkeynes@359
  1635
                                        break;
nkeynes@359
  1636
                                }
nkeynes@359
  1637
                                break;
nkeynes@359
  1638
                            case 0x1:
nkeynes@359
  1639
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1640
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1641
                                check_priv();
nkeynes@374
  1642
                                load_reg( R_EAX, Rm );
nkeynes@374
  1643
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1644
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1645
                                store_reg( R_EAX, Rm );
nkeynes@374
  1646
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1647
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1648
                                }
nkeynes@359
  1649
                                break;
nkeynes@359
  1650
                        }
nkeynes@359
  1651
                        break;
nkeynes@359
  1652
                    case 0x8:
nkeynes@359
  1653
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1654
                            case 0x0:
nkeynes@359
  1655
                                { /* SHLL2 Rn */
nkeynes@359
  1656
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1657
                                load_reg( R_EAX, Rn );
nkeynes@359
  1658
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1659
                                store_reg( R_EAX, Rn );
nkeynes@359
  1660
                                }
nkeynes@359
  1661
                                break;
nkeynes@359
  1662
                            case 0x1:
nkeynes@359
  1663
                                { /* SHLL8 Rn */
nkeynes@359
  1664
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1665
                                load_reg( R_EAX, Rn );
nkeynes@359
  1666
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1667
                                store_reg( R_EAX, Rn );
nkeynes@359
  1668
                                }
nkeynes@359
  1669
                                break;
nkeynes@359
  1670
                            case 0x2:
nkeynes@359
  1671
                                { /* SHLL16 Rn */
nkeynes@359
  1672
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1673
                                load_reg( R_EAX, Rn );
nkeynes@359
  1674
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1675
                                store_reg( R_EAX, Rn );
nkeynes@359
  1676
                                }
nkeynes@359
  1677
                                break;
nkeynes@359
  1678
                            default:
nkeynes@359
  1679
                                UNDEF();
nkeynes@359
  1680
                                break;
nkeynes@359
  1681
                        }
nkeynes@359
  1682
                        break;
nkeynes@359
  1683
                    case 0x9:
nkeynes@359
  1684
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1685
                            case 0x0:
nkeynes@359
  1686
                                { /* SHLR2 Rn */
nkeynes@359
  1687
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1688
                                load_reg( R_EAX, Rn );
nkeynes@359
  1689
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1690
                                store_reg( R_EAX, Rn );
nkeynes@359
  1691
                                }
nkeynes@359
  1692
                                break;
nkeynes@359
  1693
                            case 0x1:
nkeynes@359
  1694
                                { /* SHLR8 Rn */
nkeynes@359
  1695
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1696
                                load_reg( R_EAX, Rn );
nkeynes@359
  1697
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1698
                                store_reg( R_EAX, Rn );
nkeynes@359
  1699
                                }
nkeynes@359
  1700
                                break;
nkeynes@359
  1701
                            case 0x2:
nkeynes@359
  1702
                                { /* SHLR16 Rn */
nkeynes@359
  1703
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1704
                                load_reg( R_EAX, Rn );
nkeynes@359
  1705
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1706
                                store_reg( R_EAX, Rn );
nkeynes@359
  1707
                                }
nkeynes@359
  1708
                                break;
nkeynes@359
  1709
                            default:
nkeynes@359
  1710
                                UNDEF();
nkeynes@359
  1711
                                break;
nkeynes@359
  1712
                        }
nkeynes@359
  1713
                        break;
nkeynes@359
  1714
                    case 0xA:
nkeynes@359
  1715
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1716
                            case 0x0:
nkeynes@359
  1717
                                { /* LDS Rm, MACH */
nkeynes@359
  1718
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1719
                                load_reg( R_EAX, Rm );
nkeynes@359
  1720
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1721
                                }
nkeynes@359
  1722
                                break;
nkeynes@359
  1723
                            case 0x1:
nkeynes@359
  1724
                                { /* LDS Rm, MACL */
nkeynes@359
  1725
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1726
                                load_reg( R_EAX, Rm );
nkeynes@359
  1727
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1728
                                }
nkeynes@359
  1729
                                break;
nkeynes@359
  1730
                            case 0x2:
nkeynes@359
  1731
                                { /* LDS Rm, PR */
nkeynes@359
  1732
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1733
                                load_reg( R_EAX, Rm );
nkeynes@359
  1734
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1735
                                }
nkeynes@359
  1736
                                break;
nkeynes@359
  1737
                            case 0x3:
nkeynes@359
  1738
                                { /* LDC Rm, SGR */
nkeynes@359
  1739
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1740
                                check_priv();
nkeynes@359
  1741
                                load_reg( R_EAX, Rm );
nkeynes@359
  1742
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1743
                                }
nkeynes@359
  1744
                                break;
nkeynes@359
  1745
                            case 0x5:
nkeynes@359
  1746
                                { /* LDS Rm, FPUL */
nkeynes@359
  1747
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1748
                                load_reg( R_EAX, Rm );
nkeynes@359
  1749
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1750
                                }
nkeynes@359
  1751
                                break;
nkeynes@359
  1752
                            case 0x6:
nkeynes@359
  1753
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1754
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1755
                                load_reg( R_EAX, Rm );
nkeynes@359
  1756
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1757
                                update_fr_bank( R_EAX );
nkeynes@359
  1758
                                }
nkeynes@359
  1759
                                break;
nkeynes@359
  1760
                            case 0xF:
nkeynes@359
  1761
                                { /* LDC Rm, DBR */
nkeynes@359
  1762
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1763
                                check_priv();
nkeynes@359
  1764
                                load_reg( R_EAX, Rm );
nkeynes@359
  1765
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1766
                                }
nkeynes@359
  1767
                                break;
nkeynes@359
  1768
                            default:
nkeynes@359
  1769
                                UNDEF();
nkeynes@359
  1770
                                break;
nkeynes@359
  1771
                        }
nkeynes@359
  1772
                        break;
nkeynes@359
  1773
                    case 0xB:
nkeynes@359
  1774
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1775
                            case 0x0:
nkeynes@359
  1776
                                { /* JSR @Rn */
nkeynes@359
  1777
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1778
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1779
                            	SLOTILLEGAL();
nkeynes@374
  1780
                                } else {
nkeynes@374
  1781
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1782
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
  1783
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1784
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1785
                            	return 0;
nkeynes@374
  1786
                                }
nkeynes@359
  1787
                                }
nkeynes@359
  1788
                                break;
nkeynes@359
  1789
                            case 0x1:
nkeynes@359
  1790
                                { /* TAS.B @Rn */
nkeynes@359
  1791
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1792
                                load_reg( R_ECX, Rn );
nkeynes@361
  1793
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1794
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1795
                                SETE_t();
nkeynes@361
  1796
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1797
                                load_reg( R_ECX, Rn );
nkeynes@361
  1798
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1799
                                }
nkeynes@359
  1800
                                break;
nkeynes@359
  1801
                            case 0x2:
nkeynes@359
  1802
                                { /* JMP @Rn */
nkeynes@359
  1803
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1804
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1805
                            	SLOTILLEGAL();
nkeynes@374
  1806
                                } else {
nkeynes@374
  1807
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1808
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1809
                            	return 0;
nkeynes@374
  1810
                                }
nkeynes@359
  1811
                                }
nkeynes@359
  1812
                                break;
nkeynes@359
  1813
                            default:
nkeynes@359
  1814
                                UNDEF();
nkeynes@359
  1815
                                break;
nkeynes@359
  1816
                        }
nkeynes@359
  1817
                        break;
nkeynes@359
  1818
                    case 0xC:
nkeynes@359
  1819
                        { /* SHAD Rm, Rn */
nkeynes@359
  1820
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1821
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1822
                        load_reg( R_EAX, Rn );
nkeynes@361
  1823
                        load_reg( R_ECX, Rm );
nkeynes@361
  1824
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1825
                        JGE_rel8(16, doshl);
nkeynes@361
  1826
                                        
nkeynes@361
  1827
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1828
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1829
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1830
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1831
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1832
                    
nkeynes@386
  1833
                        JMP_TARGET(emptysar);
nkeynes@386
  1834
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1835
                        JMP_rel8(5, end2);
nkeynes@386
  1836
                    
nkeynes@380
  1837
                        JMP_TARGET(doshl);
nkeynes@361
  1838
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1839
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1840
                        JMP_TARGET(end);
nkeynes@386
  1841
                        JMP_TARGET(end2);
nkeynes@361
  1842
                        store_reg( R_EAX, Rn );
nkeynes@359
  1843
                        }
nkeynes@359
  1844
                        break;
nkeynes@359
  1845
                    case 0xD:
nkeynes@359
  1846
                        { /* SHLD Rm, Rn */
nkeynes@359
  1847
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1848
                        load_reg( R_EAX, Rn );
nkeynes@368
  1849
                        load_reg( R_ECX, Rm );
nkeynes@386
  1850
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1851
                        JGE_rel8(15, doshl);
nkeynes@368
  1852
                    
nkeynes@386
  1853
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1854
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1855
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1856
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1857
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1858
                    
nkeynes@386
  1859
                        JMP_TARGET(emptyshr);
nkeynes@386
  1860
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1861
                        JMP_rel8(5, end2);
nkeynes@386
  1862
                    
nkeynes@386
  1863
                        JMP_TARGET(doshl);
nkeynes@386
  1864
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1865
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1866
                        JMP_TARGET(end);
nkeynes@386
  1867
                        JMP_TARGET(end2);
nkeynes@368
  1868
                        store_reg( R_EAX, Rn );
nkeynes@359
  1869
                        }
nkeynes@359
  1870
                        break;
nkeynes@359
  1871
                    case 0xE:
nkeynes@359
  1872
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1873
                            case 0x0:
nkeynes@359
  1874
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1875
                                    case 0x0:
nkeynes@359
  1876
                                        { /* LDC Rm, SR */
nkeynes@359
  1877
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1878
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1879
                                    	SLOTILLEGAL();
nkeynes@386
  1880
                                        } else {
nkeynes@386
  1881
                                    	check_priv();
nkeynes@386
  1882
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1883
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1884
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1885
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  1886
                                        }
nkeynes@359
  1887
                                        }
nkeynes@359
  1888
                                        break;
nkeynes@359
  1889
                                    case 0x1:
nkeynes@359
  1890
                                        { /* LDC Rm, GBR */
nkeynes@359
  1891
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1892
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1893
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1894
                                        }
nkeynes@359
  1895
                                        break;
nkeynes@359
  1896
                                    case 0x2:
nkeynes@359
  1897
                                        { /* LDC Rm, VBR */
nkeynes@359
  1898
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1899
                                        check_priv();
nkeynes@359
  1900
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1901
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1902
                                        }
nkeynes@359
  1903
                                        break;
nkeynes@359
  1904
                                    case 0x3:
nkeynes@359
  1905
                                        { /* LDC Rm, SSR */
nkeynes@359
  1906
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1907
                                        check_priv();
nkeynes@359
  1908
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1909
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1910
                                        }
nkeynes@359
  1911
                                        break;
nkeynes@359
  1912
                                    case 0x4:
nkeynes@359
  1913
                                        { /* LDC Rm, SPC */
nkeynes@359
  1914
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1915
                                        check_priv();
nkeynes@359
  1916
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1917
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1918
                                        }
nkeynes@359
  1919
                                        break;
nkeynes@359
  1920
                                    default:
nkeynes@359
  1921
                                        UNDEF();
nkeynes@359
  1922
                                        break;
nkeynes@359
  1923
                                }
nkeynes@359
  1924
                                break;
nkeynes@359
  1925
                            case 0x1:
nkeynes@359
  1926
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1927
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1928
                                check_priv();
nkeynes@374
  1929
                                load_reg( R_EAX, Rm );
nkeynes@374
  1930
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1931
                                }
nkeynes@359
  1932
                                break;
nkeynes@359
  1933
                        }
nkeynes@359
  1934
                        break;
nkeynes@359
  1935
                    case 0xF:
nkeynes@359
  1936
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1937
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1938
                        load_reg( R_ECX, Rm );
nkeynes@386
  1939
                        check_ralign16( R_ECX );
nkeynes@386
  1940
                        load_reg( R_ECX, Rn );
nkeynes@386
  1941
                        check_ralign16( R_ECX );
nkeynes@386
  1942
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  1943
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  1944
                        PUSH_r32( R_EAX );
nkeynes@386
  1945
                        load_reg( R_ECX, Rm );
nkeynes@386
  1946
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  1947
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  1948
                        POP_r32( R_ECX );
nkeynes@386
  1949
                        IMUL_r32( R_ECX );
nkeynes@386
  1950
                    
nkeynes@386
  1951
                        load_spreg( R_ECX, R_S );
nkeynes@386
  1952
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  1953
                        JE_rel8( 47, nosat );
nkeynes@386
  1954
                    
nkeynes@386
  1955
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  1956
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  1957
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  1958
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  1959
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  1960
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  1961
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  1962
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  1963
                    
nkeynes@386
  1964
                        JMP_TARGET(positive);
nkeynes@386
  1965
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  1966
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  1967
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  1968
                    
nkeynes@386
  1969
                        JMP_TARGET(nosat);
nkeynes@386
  1970
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  1971
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  1972
                        JMP_TARGET(end);
nkeynes@386
  1973
                        JMP_TARGET(end2);
nkeynes@386
  1974
                        JMP_TARGET(end3);
nkeynes@359
  1975
                        }
nkeynes@359
  1976
                        break;
nkeynes@359
  1977
                }
nkeynes@359
  1978
                break;
nkeynes@359
  1979
            case 0x5:
nkeynes@359
  1980
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1981
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1982
                load_reg( R_ECX, Rm );
nkeynes@361
  1983
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1984
                check_ralign32( R_ECX );
nkeynes@361
  1985
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1986
                store_reg( R_EAX, Rn );
nkeynes@359
  1987
                }
nkeynes@359
  1988
                break;
nkeynes@359
  1989
            case 0x6:
nkeynes@359
  1990
                switch( ir&0xF ) {
nkeynes@359
  1991
                    case 0x0:
nkeynes@359
  1992
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1993
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1994
                        load_reg( R_ECX, Rm );
nkeynes@359
  1995
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1996
                        store_reg( R_EAX, Rn );
nkeynes@359
  1997
                        }
nkeynes@359
  1998
                        break;
nkeynes@359
  1999
                    case 0x1:
nkeynes@359
  2000
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2001
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2002
                        load_reg( R_ECX, Rm );
nkeynes@374
  2003
                        check_ralign16( R_ECX );
nkeynes@361
  2004
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2005
                        store_reg( R_EAX, Rn );
nkeynes@359
  2006
                        }
nkeynes@359
  2007
                        break;
nkeynes@359
  2008
                    case 0x2:
nkeynes@359
  2009
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2010
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2011
                        load_reg( R_ECX, Rm );
nkeynes@374
  2012
                        check_ralign32( R_ECX );
nkeynes@361
  2013
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2014
                        store_reg( R_EAX, Rn );
nkeynes@359
  2015
                        }
nkeynes@359
  2016
                        break;
nkeynes@359
  2017
                    case 0x3:
nkeynes@359
  2018
                        { /* MOV Rm, Rn */
nkeynes@359
  2019
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2020
                        load_reg( R_EAX, Rm );
nkeynes@359
  2021
                        store_reg( R_EAX, Rn );
nkeynes@359
  2022
                        }
nkeynes@359
  2023
                        break;
nkeynes@359
  2024
                    case 0x4:
nkeynes@359
  2025
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2026
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2027
                        load_reg( R_ECX, Rm );
nkeynes@359
  2028
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2029
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2030
                        store_reg( R_EAX, Rm );
nkeynes@359
  2031
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2032
                        store_reg( R_EAX, Rn );
nkeynes@359
  2033
                        }
nkeynes@359
  2034
                        break;
nkeynes@359
  2035
                    case 0x5:
nkeynes@359
  2036
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2037
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2038
                        load_reg( R_EAX, Rm );
nkeynes@374
  2039
                        check_ralign16( R_EAX );
nkeynes@361
  2040
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2041
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2042
                        store_reg( R_EAX, Rm );
nkeynes@361
  2043
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2044
                        store_reg( R_EAX, Rn );
nkeynes@359
  2045
                        }
nkeynes@359
  2046
                        break;
nkeynes@359
  2047
                    case 0x6:
nkeynes@359
  2048
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2049
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2050
                        load_reg( R_EAX, Rm );
nkeynes@386
  2051
                        check_ralign32( R_EAX );
nkeynes@361
  2052
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2053
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2054
                        store_reg( R_EAX, Rm );
nkeynes@361
  2055
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2056
                        store_reg( R_EAX, Rn );
nkeynes@359
  2057
                        }
nkeynes@359
  2058
                        break;
nkeynes@359
  2059
                    case 0x7:
nkeynes@359
  2060
                        { /* NOT Rm, Rn */
nkeynes@359
  2061
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2062
                        load_reg( R_EAX, Rm );
nkeynes@359
  2063
                        NOT_r32( R_EAX );
nkeynes@359
  2064
                        store_reg( R_EAX, Rn );
nkeynes@359
  2065
                        }
nkeynes@359
  2066
                        break;
nkeynes@359
  2067
                    case 0x8:
nkeynes@359
  2068
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2069
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2070
                        load_reg( R_EAX, Rm );
nkeynes@359
  2071
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2072
                        store_reg( R_EAX, Rn );
nkeynes@359
  2073
                        }
nkeynes@359
  2074
                        break;
nkeynes@359
  2075
                    case 0x9:
nkeynes@359
  2076
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2077
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2078
                        load_reg( R_EAX, Rm );
nkeynes@359
  2079
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2080
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2081
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2082
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2083
                        store_reg( R_ECX, Rn );
nkeynes@359
  2084
                        }
nkeynes@359
  2085
                        break;
nkeynes@359
  2086
                    case 0xA:
nkeynes@359
  2087
                        { /* NEGC Rm, Rn */
nkeynes@359
  2088
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2089
                        load_reg( R_EAX, Rm );
nkeynes@359
  2090
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2091
                        LDC_t();
nkeynes@359
  2092
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2093
                        store_reg( R_ECX, Rn );
nkeynes@359
  2094
                        SETC_t();
nkeynes@359
  2095
                        }
nkeynes@359
  2096
                        break;
nkeynes@359
  2097
                    case 0xB:
nkeynes@359
  2098
                        { /* NEG Rm, Rn */
nkeynes@359
  2099
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2100
                        load_reg( R_EAX, Rm );
nkeynes@359
  2101
                        NEG_r32( R_EAX );
nkeynes@359
  2102
                        store_reg( R_EAX, Rn );
nkeynes@359
  2103
                        }
nkeynes@359
  2104
                        break;
nkeynes@359
  2105
                    case 0xC:
nkeynes@359
  2106
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2107
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2108
                        load_reg( R_EAX, Rm );
nkeynes@361
  2109
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2110
                        store_reg( R_EAX, Rn );
nkeynes@359
  2111
                        }
nkeynes@359
  2112
                        break;
nkeynes@359
  2113
                    case 0xD:
nkeynes@359
  2114
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2115
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2116
                        load_reg( R_EAX, Rm );
nkeynes@361
  2117
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2118
                        store_reg( R_EAX, Rn );
nkeynes@359
  2119
                        }
nkeynes@359
  2120
                        break;
nkeynes@359
  2121
                    case 0xE:
nkeynes@359
  2122
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2123
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2124
                        load_reg( R_EAX, Rm );
nkeynes@359
  2125
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2126
                        store_reg( R_EAX, Rn );
nkeynes@359
  2127
                        }
nkeynes@359
  2128
                        break;
nkeynes@359
  2129
                    case 0xF:
nkeynes@359
  2130
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2131
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2132
                        load_reg( R_EAX, Rm );
nkeynes@361
  2133
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2134
                        store_reg( R_EAX, Rn );
nkeynes@359
  2135
                        }
nkeynes@359
  2136
                        break;
nkeynes@359
  2137
                }
nkeynes@359
  2138
                break;
nkeynes@359
  2139
            case 0x7:
nkeynes@359
  2140
                { /* ADD #imm, Rn */
nkeynes@359
  2141
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2142
                load_reg( R_EAX, Rn );
nkeynes@359
  2143
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2144
                store_reg( R_EAX, Rn );
nkeynes@359
  2145
                }
nkeynes@359
  2146
                break;
nkeynes@359
  2147
            case 0x8:
nkeynes@359
  2148
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2149
                    case 0x0:
nkeynes@359
  2150
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2151
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2152
                        load_reg( R_EAX, 0 );
nkeynes@359
  2153
                        load_reg( R_ECX, Rn );
nkeynes@359
  2154
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2155
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2156
                        }
nkeynes@359
  2157
                        break;
nkeynes@359
  2158
                    case 0x1:
nkeynes@359
  2159
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2160
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2161
                        load_reg( R_ECX, Rn );
nkeynes@361
  2162
                        load_reg( R_EAX, 0 );
nkeynes@361
  2163
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2164
                        check_walign16( R_ECX );
nkeynes@361
  2165
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2166
                        }
nkeynes@359
  2167
                        break;
nkeynes@359
  2168
                    case 0x4:
nkeynes@359
  2169
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2170
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2171
                        load_reg( R_ECX, Rm );
nkeynes@359
  2172
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2173
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2174
                        store_reg( R_EAX, 0 );
nkeynes@359
  2175
                        }
nkeynes@359
  2176
                        break;
nkeynes@359
  2177
                    case 0x5:
nkeynes@359
  2178
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2179
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2180
                        load_reg( R_ECX, Rm );
nkeynes@361
  2181
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2182
                        check_ralign16( R_ECX );
nkeynes@361
  2183
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2184
                        store_reg( R_EAX, 0 );
nkeynes@359
  2185
                        }
nkeynes@359
  2186
                        break;
nkeynes@359
  2187
                    case 0x8:
nkeynes@359
  2188
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2189
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2190
                        load_reg( R_EAX, 0 );
nkeynes@359
  2191
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2192
                        SETE_t();
nkeynes@359
  2193
                        }
nkeynes@359
  2194
                        break;
nkeynes@359
  2195
                    case 0x9:
nkeynes@359
  2196
                        { /* BT disp */
nkeynes@359
  2197
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2198
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2199
                    	SLOTILLEGAL();
nkeynes@374
  2200
                        } else {
nkeynes@374
  2201
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2202
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2203
                    	JE_rel8( 5, nottaken );
nkeynes@374
  2204
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2205
                    	JMP_TARGET(nottaken);
nkeynes@374
  2206
                    	INC_r32(R_ESI);
nkeynes@374
  2207
                    	return 1;
nkeynes@374
  2208
                        }
nkeynes@359
  2209
                        }
nkeynes@359
  2210
                        break;
nkeynes@359
  2211
                    case 0xB:
nkeynes@359
  2212
                        { /* BF disp */
nkeynes@359
  2213
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2214
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2215
                    	SLOTILLEGAL();
nkeynes@374
  2216
                        } else {
nkeynes@374
  2217
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2218
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2219
                    	JNE_rel8( 5, nottaken );
nkeynes@374
  2220
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2221
                    	JMP_TARGET(nottaken);
nkeynes@374
  2222
                    	INC_r32(R_ESI);
nkeynes@374
  2223
                    	return 1;
nkeynes@374
  2224
                        }
nkeynes@359
  2225
                        }
nkeynes@359
  2226
                        break;
nkeynes@359
  2227
                    case 0xD:
nkeynes@359
  2228
                        { /* BT/S disp */
nkeynes@359
  2229
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2230
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2231
                    	SLOTILLEGAL();
nkeynes@374
  2232
                        } else {
nkeynes@386
  2233
                    	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  2234
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2235
                    	JE_rel8( 5, nottaken );
nkeynes@374
  2236
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2237
                    	JMP_TARGET(nottaken);
nkeynes@374
  2238
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2239
                    	return 0;
nkeynes@374
  2240
                        }
nkeynes@359
  2241
                        }
nkeynes@359
  2242
                        break;
nkeynes@359
  2243
                    case 0xF:
nkeynes@359
  2244
                        { /* BF/S disp */
nkeynes@359
  2245
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2246
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2247
                    	SLOTILLEGAL();
nkeynes@374
  2248
                        } else {
nkeynes@386
  2249
                    	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  2250
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2251
                    	JNE_rel8( 5, nottaken );
nkeynes@374
  2252
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2253
                    	JMP_TARGET(nottaken);
nkeynes@374
  2254
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2255
                    	return 0;
nkeynes@374
  2256
                        }
nkeynes@359
  2257
                        }
nkeynes@359
  2258
                        break;
nkeynes@359
  2259
                    default:
nkeynes@359
  2260
                        UNDEF();
nkeynes@359
  2261
                        break;
nkeynes@359
  2262
                }
nkeynes@359
  2263
                break;
nkeynes@359
  2264
            case 0x9:
nkeynes@359
  2265
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2266
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2267
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2268
            	SLOTILLEGAL();
nkeynes@374
  2269
                } else {
nkeynes@374
  2270
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2271
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2272
            	store_reg( R_EAX, Rn );
nkeynes@374
  2273
                }
nkeynes@359
  2274
                }
nkeynes@359
  2275
                break;
nkeynes@359
  2276
            case 0xA:
nkeynes@359
  2277
                { /* BRA disp */
nkeynes@359
  2278
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2279
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2280
            	SLOTILLEGAL();
nkeynes@374
  2281
                } else {
nkeynes@374
  2282
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2283
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2284
            	return 0;
nkeynes@374
  2285
                }
nkeynes@359
  2286
                }
nkeynes@359
  2287
                break;
nkeynes@359
  2288
            case 0xB:
nkeynes@359
  2289
                { /* BSR disp */
nkeynes@359
  2290
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2291
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2292
            	SLOTILLEGAL();
nkeynes@374
  2293
                } else {
nkeynes@374
  2294
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2295
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2296
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2297
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2298
            	return 0;
nkeynes@374
  2299
                }
nkeynes@359
  2300
                }
nkeynes@359
  2301
                break;
nkeynes@359
  2302
            case 0xC:
nkeynes@359
  2303
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2304
                    case 0x0:
nkeynes@359
  2305
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2306
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2307
                        load_reg( R_EAX, 0 );
nkeynes@359
  2308
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2309
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2310
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2311
                        }
nkeynes@359
  2312
                        break;
nkeynes@359
  2313
                    case 0x1:
nkeynes@359
  2314
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2315
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2316
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2317
                        load_reg( R_EAX, 0 );
nkeynes@361
  2318
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2319
                        check_walign16( R_ECX );
nkeynes@361
  2320
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2321
                        }
nkeynes@359
  2322
                        break;
nkeynes@359
  2323
                    case 0x2:
nkeynes@359
  2324
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2325
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2326
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2327
                        load_reg( R_EAX, 0 );
nkeynes@361
  2328
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2329
                        check_walign32( R_ECX );
nkeynes@361
  2330
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2331
                        }
nkeynes@359
  2332
                        break;
nkeynes@359
  2333
                    case 0x3:
nkeynes@359
  2334
                        { /* TRAPA #imm */
nkeynes@359
  2335
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2336
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2337
                    	SLOTILLEGAL();
nkeynes@374
  2338
                        } else {
nkeynes@374
  2339
                    	// TODO: Write TRA 
nkeynes@374
  2340
                    	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  2341
                        }
nkeynes@359
  2342
                        }
nkeynes@359
  2343
                        break;
nkeynes@359
  2344
                    case 0x4:
nkeynes@359
  2345
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2346
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2347
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2348
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2349
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2350
                        store_reg( R_EAX, 0 );
nkeynes@359
  2351
                        }
nkeynes@359
  2352
                        break;
nkeynes@359
  2353
                    case 0x5:
nkeynes@359
  2354
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2355
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2356
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2357
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2358
                        check_ralign16( R_ECX );
nkeynes@361
  2359
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2360
                        store_reg( R_EAX, 0 );
nkeynes@359
  2361
                        }
nkeynes@359
  2362
                        break;
nkeynes@359
  2363
                    case 0x6:
nkeynes@359
  2364
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2365
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2366
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2367
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2368
                        check_ralign32( R_ECX );
nkeynes@361
  2369
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2370
                        store_reg( R_EAX, 0 );
nkeynes@359
  2371
                        }
nkeynes@359
  2372
                        break;
nkeynes@359
  2373
                    case 0x7:
nkeynes@359
  2374
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2375
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2376
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2377
                    	SLOTILLEGAL();
nkeynes@374
  2378
                        } else {
nkeynes@374
  2379
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2380
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2381
                        }
nkeynes@359
  2382
                        }
nkeynes@359
  2383
                        break;
nkeynes@359
  2384
                    case 0x8:
nkeynes@359
  2385
                        { /* TST #imm, R0 */
nkeynes@359
  2386
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2387
                        load_reg( R_EAX, 0 );
nkeynes@368
  2388
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2389
                        SETE_t();
nkeynes@359
  2390
                        }
nkeynes@359
  2391
                        break;
nkeynes@359
  2392
                    case 0x9:
nkeynes@359
  2393
                        { /* AND #imm, R0 */
nkeynes@359
  2394
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2395
                        load_reg( R_EAX, 0 );
nkeynes@359
  2396
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2397
                        store_reg( R_EAX, 0 );
nkeynes@359
  2398
                        }
nkeynes@359
  2399
                        break;
nkeynes@359
  2400
                    case 0xA:
nkeynes@359
  2401
                        { /* XOR #imm, R0 */
nkeynes@359
  2402
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2403
                        load_reg( R_EAX, 0 );
nkeynes@359
  2404
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2405
                        store_reg( R_EAX, 0 );
nkeynes@359
  2406
                        }
nkeynes@359
  2407
                        break;
nkeynes@359
  2408
                    case 0xB:
nkeynes@359
  2409
                        { /* OR #imm, R0 */
nkeynes@359
  2410
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2411
                        load_reg( R_EAX, 0 );
nkeynes@359
  2412
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2413
                        store_reg( R_EAX, 0 );
nkeynes@359
  2414
                        }
nkeynes@359
  2415
                        break;
nkeynes@359
  2416
                    case 0xC:
nkeynes@359
  2417
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2418
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2419
                        load_reg( R_EAX, 0);
nkeynes@368
  2420
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2421
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2422
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  2423
                        TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  2424
                        SETE_t();
nkeynes@359
  2425
                        }
nkeynes@359
  2426
                        break;
nkeynes@359
  2427
                    case 0xD:
nkeynes@359
  2428
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2429
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2430
                        load_reg( R_EAX, 0 );
nkeynes@359
  2431
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2432
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2433
                        PUSH_r32(R_ECX);
nkeynes@386
  2434
                        call_func0(sh4_read_byte);
nkeynes@386
  2435
                        POP_r32(R_ECX);
nkeynes@386
  2436
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2437
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2438
                        }
nkeynes@359
  2439
                        break;
nkeynes@359
  2440
                    case 0xE:
nkeynes@359
  2441
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2442
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2443
                        load_reg( R_EAX, 0 );
nkeynes@359
  2444
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2445
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2446
                        PUSH_r32(R_ECX);
nkeynes@386
  2447
                        call_func0(sh4_read_byte);
nkeynes@386
  2448
                        POP_r32(R_ECX);
nkeynes@359
  2449
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2450
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2451
                        }
nkeynes@359
  2452
                        break;
nkeynes@359
  2453
                    case 0xF:
nkeynes@359
  2454
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2455
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2456
                        load_reg( R_EAX, 0 );
nkeynes@374
  2457
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2458
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2459
                        PUSH_r32(R_ECX);
nkeynes@386
  2460
                        call_func0(sh4_read_byte);
nkeynes@386
  2461
                        POP_r32(R_ECX);
nkeynes@386
  2462
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2463
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2464
                        }
nkeynes@359
  2465
                        break;
nkeynes@359
  2466
                }
nkeynes@359
  2467
                break;
nkeynes@359
  2468
            case 0xD:
nkeynes@359
  2469
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2470
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2471
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2472
            	SLOTILLEGAL();
nkeynes@374
  2473
                } else {
nkeynes@374
  2474
            	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2475
            	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2476
            	store_reg( R_EAX, Rn );
nkeynes@374
  2477
                }
nkeynes@359
  2478
                }
nkeynes@359
  2479
                break;
nkeynes@359
  2480
            case 0xE:
nkeynes@359
  2481
                { /* MOV #imm, Rn */
nkeynes@359
  2482
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2483
                load_imm32( R_EAX, imm );
nkeynes@359
  2484
                store_reg( R_EAX, Rn );
nkeynes@359
  2485
                }
nkeynes@359
  2486
                break;
nkeynes@359
  2487
            case 0xF:
nkeynes@359
  2488
                switch( ir&0xF ) {
nkeynes@359
  2489
                    case 0x0:
nkeynes@359
  2490
                        { /* FADD FRm, FRn */
nkeynes@359
  2491
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2492
                        check_fpuen();
nkeynes@377
  2493
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2494
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2495
                        load_fr_bank( R_EDX );
nkeynes@380
  2496
                        JNE_rel8(13,doubleprec);
nkeynes@377
  2497
                        push_fr(R_EDX, FRm);
nkeynes@377
  2498
                        push_fr(R_EDX, FRn);
nkeynes@377
  2499
                        FADDP_st(1);
nkeynes@377
  2500
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2501
                        JMP_rel8(11,end);
nkeynes@380
  2502
                        JMP_TARGET(doubleprec);
nkeynes@377
  2503
                        push_dr(R_EDX, FRm);
nkeynes@377
  2504
                        push_dr(R_EDX, FRn);
nkeynes@377
  2505
                        FADDP_st(1);
nkeynes@377
  2506
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2507
                        JMP_TARGET(end);
nkeynes@359
  2508
                        }
nkeynes@359
  2509
                        break;
nkeynes@359
  2510
                    case 0x1:
nkeynes@359
  2511
                        { /* FSUB FRm, FRn */
nkeynes@359
  2512
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2513
                        check_fpuen();
nkeynes@377
  2514
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2515
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2516
                        load_fr_bank( R_EDX );
nkeynes@380
  2517
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2518
                        push_fr(R_EDX, FRn);
nkeynes@377
  2519
                        push_fr(R_EDX, FRm);
nkeynes@377
  2520
                        FMULP_st(1);
nkeynes@377
  2521
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2522
                        JMP_rel8(11, end);
nkeynes@380
  2523
                        JMP_TARGET(doubleprec);
nkeynes@377
  2524
                        push_dr(R_EDX, FRn);
nkeynes@377
  2525
                        push_dr(R_EDX, FRm);
nkeynes@377
  2526
                        FMULP_st(1);
nkeynes@377
  2527
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2528
                        JMP_TARGET(end);
nkeynes@359
  2529
                        }
nkeynes@359
  2530
                        break;
nkeynes@359
  2531
                    case 0x2:
nkeynes@359
  2532
                        { /* FMUL FRm, FRn */
nkeynes@359
  2533
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2534
                        check_fpuen();
nkeynes@377
  2535
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2536
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2537
                        load_fr_bank( R_EDX );
nkeynes@380
  2538
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2539
                        push_fr(R_EDX, FRm);
nkeynes@377
  2540
                        push_fr(R_EDX, FRn);
nkeynes@377
  2541
                        FMULP_st(1);
nkeynes@377
  2542
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2543
                        JMP_rel8(11, end);
nkeynes@380
  2544
                        JMP_TARGET(doubleprec);
nkeynes@377
  2545
                        push_dr(R_EDX, FRm);
nkeynes@377
  2546
                        push_dr(R_EDX, FRn);
nkeynes@377
  2547
                        FMULP_st(1);
nkeynes@377
  2548
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2549
                        JMP_TARGET(end);
nkeynes@359
  2550
                        }
nkeynes@359
  2551
                        break;
nkeynes@359
  2552
                    case 0x3:
nkeynes@359
  2553
                        { /* FDIV FRm, FRn */
nkeynes@359
  2554
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2555
                        check_fpuen();
nkeynes@377
  2556
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2557
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2558
                        load_fr_bank( R_EDX );
nkeynes@380
  2559
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2560
                        push_fr(R_EDX, FRn);
nkeynes@377
  2561
                        push_fr(R_EDX, FRm);
nkeynes@377
  2562
                        FDIVP_st(1);
nkeynes@377
  2563
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2564
                        JMP_rel8(11, end);
nkeynes@380
  2565
                        JMP_TARGET(doubleprec);
nkeynes@377
  2566
                        push_dr(R_EDX, FRn);
nkeynes@377
  2567
                        push_dr(R_EDX, FRm);
nkeynes@377
  2568
                        FDIVP_st(1);
nkeynes@377
  2569
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2570
                        JMP_TARGET(end);
nkeynes@359
  2571
                        }
nkeynes@359
  2572
                        break;
nkeynes@359
  2573
                    case 0x4:
nkeynes@359
  2574
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2575
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2576
                        check_fpuen();
nkeynes@377
  2577
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2578
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2579
                        load_fr_bank( R_EDX );
nkeynes@380
  2580
                        JNE_rel8(8, doubleprec);
nkeynes@377
  2581
                        push_fr(R_EDX, FRm);
nkeynes@377
  2582
                        push_fr(R_EDX, FRn);
nkeynes@380
  2583
                        JMP_rel8(6, end);
nkeynes@380
  2584
                        JMP_TARGET(doubleprec);
nkeynes@377
  2585
                        push_dr(R_EDX, FRm);
nkeynes@377
  2586
                        push_dr(R_EDX, FRn);
nkeynes@386
  2587
                        JMP_TARGET(end);
nkeynes@377
  2588
                        FCOMIP_st(1);
nkeynes@377
  2589
                        SETE_t();
nkeynes@377
  2590
                        FPOP_st();
nkeynes@359
  2591
                        }
nkeynes@359
  2592
                        break;
nkeynes@359
  2593
                    case 0x5:
nkeynes@359
  2594
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2595
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2596
                        check_fpuen();
nkeynes@377
  2597
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2598
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2599
                        load_fr_bank( R_EDX );
nkeynes@380
  2600
                        JNE_rel8(8, doubleprec);
nkeynes@377
  2601
                        push_fr(R_EDX, FRm);
nkeynes@377
  2602
                        push_fr(R_EDX, FRn);
nkeynes@380
  2603
                        JMP_rel8(6, end);
nkeynes@380
  2604
                        JMP_TARGET(doubleprec);
nkeynes@377
  2605
                        push_dr(R_EDX, FRm);
nkeynes@377
  2606
                        push_dr(R_EDX, FRn);
nkeynes@380
  2607
                        JMP_TARGET(end);
nkeynes@377
  2608
                        FCOMIP_st(1);
nkeynes@377
  2609
                        SETA_t();
nkeynes@377
  2610
                        FPOP_st();
nkeynes@359
  2611
                        }
nkeynes@359
  2612
                        break;
nkeynes@359
  2613
                    case 0x6:
nkeynes@359
  2614
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2615
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2616
                        check_fpuen();
nkeynes@375
  2617
                        load_reg( R_EDX, Rm );
nkeynes@377
  2618
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@375
  2619
                        check_ralign32( R_EDX );
nkeynes@375
  2620
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2621
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2622
                        JNE_rel8(19, doublesize);
nkeynes@375
  2623
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2624
                        load_fr_bank( R_ECX );
nkeynes@375
  2625
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  2626
                        if( FRn&1 ) {
nkeynes@386
  2627
                    	JMP_rel8(48, end);
nkeynes@380
  2628
                    	JMP_TARGET(doublesize);
nkeynes@375
  2629
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  2630
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  2631
                    	load_xf_bank( R_ECX );
nkeynes@380
  2632
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2633
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2634
                    	JMP_TARGET(end);
nkeynes@375
  2635
                        } else {
nkeynes@380
  2636
                    	JMP_rel8(36, end);
nkeynes@380
  2637
                    	JMP_TARGET(doublesize);
nkeynes@375
  2638
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2639
                    	load_fr_bank( R_ECX );
nkeynes@380
  2640
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2641
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2642
                    	JMP_TARGET(end);
nkeynes@377
  2643
                        }
nkeynes@377
  2644
                        }
nkeynes@377
  2645
                        break;
nkeynes@377
  2646
                    case 0x7:
nkeynes@377
  2647
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@377
  2648
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2649
                        check_fpuen();
nkeynes@377
  2650
                        load_reg( R_EDX, Rn );
nkeynes@377
  2651
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  2652
                        check_walign32( R_EDX );
nkeynes@377
  2653
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2654
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2655
                        JNE_rel8(20, doublesize);
nkeynes@377
  2656
                        load_fr_bank( R_ECX );
nkeynes@377
  2657
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2658
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  2659
                        if( FRm&1 ) {
nkeynes@386
  2660
                    	JMP_rel8( 48, end );
nkeynes@380
  2661
                    	JMP_TARGET(doublesize);
nkeynes@377
  2662
                    	load_xf_bank( R_ECX );
nkeynes@380
  2663
                    	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  2664
                    	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  2665
                    	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  2666
                    	JMP_TARGET(end);
nkeynes@377
  2667
                        } else {
nkeynes@380
  2668
                    	JMP_rel8( 39, end );
nkeynes@380
  2669
                    	JMP_TARGET(doublesize);
nkeynes@377
  2670
                    	load_fr_bank( R_ECX );
nkeynes@380
  2671
                    	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  2672
                    	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  2673
                    	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  2674
                    	JMP_TARGET(end);
nkeynes@377
  2675
                        }
nkeynes@377
  2676
                        }
nkeynes@377
  2677
                        break;
nkeynes@377
  2678
                    case 0x8:
nkeynes@377
  2679
                        { /* FMOV @Rm, FRn */
nkeynes@377
  2680
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2681
                        check_fpuen();
nkeynes@377
  2682
                        load_reg( R_EDX, Rm );
nkeynes@377
  2683
                        check_ralign32( R_EDX );
nkeynes@377
  2684
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2685
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2686
                        JNE_rel8(19, doublesize);
nkeynes@377
  2687
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2688
                        load_fr_bank( R_ECX );
nkeynes@377
  2689
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  2690
                        if( FRn&1 ) {
nkeynes@386
  2691
                    	JMP_rel8(48, end);
nkeynes@380
  2692
                    	JMP_TARGET(doublesize);
nkeynes@377
  2693
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2694
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  2695
                    	load_xf_bank( R_ECX );
nkeynes@380
  2696
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2697
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2698
                    	JMP_TARGET(end);
nkeynes@377
  2699
                        } else {
nkeynes@380
  2700
                    	JMP_rel8(36, end);
nkeynes@380
  2701
                    	JMP_TARGET(doublesize);
nkeynes@377
  2702
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2703
                    	load_fr_bank( R_ECX );
nkeynes@380
  2704
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2705
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2706
                    	JMP_TARGET(end);
nkeynes@375
  2707
                        }
nkeynes@359
  2708
                        }
nkeynes@359
  2709
                        break;
nkeynes@359
  2710
                    case 0x9:
nkeynes@359
  2711
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  2712
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2713
                        check_fpuen();
nkeynes@377
  2714
                        load_reg( R_EDX, Rm );
nkeynes@377
  2715
                        check_ralign32( R_EDX );
nkeynes@377
  2716
                        MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  2717
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2718
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2719
                        JNE_rel8(25, doublesize);
nkeynes@377
  2720
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  2721
                        store_reg( R_EAX, Rm );