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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 386:6fb10951326a
prev382:fce3f4da92ab
next388:13bae2fb0373
author nkeynes
date Sun Sep 16 07:03:23 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Implement MAC.W, MAC.L and DIV1
Correct SHAD/SHLD
Fix privilege and slot illegal checks on LDC/STC opcodes
Fix various other small bugs
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.10 2007-09-16 07:03:23 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void signsat48( void )
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{
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    if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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	sh4r.mac = 0xFFFF800000000000LL;
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    else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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	sh4r.mac = 0x00007FFFFFFFFFFFLL;
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}
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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   322
}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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   333
    JNE_exit(EXIT_DATA_ADDR_WRITE);
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   334
}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static inline void raise_exception( int exc )
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{
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    PUSH_imm32(exc);
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    call_func0(sh4_raise_exception);
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    ADD_imm8s_r32( 4, R_ESP );
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    sh4_x86.in_delay_slot = FALSE;
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   353
}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   357
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   358
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   359
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   360
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   361
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   362
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   363
nkeynes@386
   364
#define RAISE_EXCEPTION( exc ) raise_exception(exc); return 1;
nkeynes@386
   365
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   366
nkeynes@368
   367
nkeynes@359
   368
nkeynes@359
   369
/**
nkeynes@359
   370
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   371
 * SI/DI as required
nkeynes@359
   372
 */
nkeynes@368
   373
void sh4_translate_begin_block() 
nkeynes@368
   374
{
nkeynes@368
   375
    PUSH_r32(R_EBP);
nkeynes@359
   376
    /* mov &sh4r, ebp */
nkeynes@359
   377
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   378
    PUSH_r32(R_EDI);
nkeynes@368
   379
    PUSH_r32(R_ESI);
nkeynes@380
   380
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   381
    
nkeynes@368
   382
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   383
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   384
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   385
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   386
}
nkeynes@359
   387
nkeynes@368
   388
/**
nkeynes@368
   389
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   390
 */
nkeynes@374
   391
void exit_block( )
nkeynes@368
   392
{
nkeynes@374
   393
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   394
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   395
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   396
    MUL_r32( R_ESI );
nkeynes@368
   397
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   398
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@381
   399
    load_imm32( R_EAX, 1 );
nkeynes@374
   400
    POP_r32(R_ESI);
nkeynes@374
   401
    POP_r32(R_EDI);
nkeynes@374
   402
    POP_r32(R_EBP);
nkeynes@368
   403
    RET();
nkeynes@359
   404
}
nkeynes@359
   405
nkeynes@359
   406
/**
nkeynes@359
   407
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   408
 */
nkeynes@359
   409
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   410
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   411
    // Normal termination - save PC, cycle count
nkeynes@374
   412
    exit_block( );
nkeynes@359
   413
nkeynes@368
   414
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   415
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   416
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@380
   417
    JMP_rel8( 33, target1 );
nkeynes@368
   418
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@380
   419
    JMP_rel8( 26, target2 );
nkeynes@368
   420
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@380
   421
    JMP_rel8( 19, target3 );
nkeynes@368
   422
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@380
   423
    JMP_rel8( 12, target4 );
nkeynes@368
   424
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@380
   425
    JMP_rel8( 5, target5 );
nkeynes@368
   426
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   427
    // target
nkeynes@380
   428
    JMP_TARGET(target1);
nkeynes@380
   429
    JMP_TARGET(target2);
nkeynes@380
   430
    JMP_TARGET(target3);
nkeynes@380
   431
    JMP_TARGET(target4);
nkeynes@380
   432
    JMP_TARGET(target5);
nkeynes@368
   433
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   434
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   435
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   436
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   437
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   438
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   439
    MUL_r32( R_ESI );
nkeynes@368
   440
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   441
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   442
nkeynes@368
   443
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   444
    CALL_r32( R_EAX ); // 2
nkeynes@382
   445
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@382
   446
    POP_r32(R_ESI);
nkeynes@382
   447
    POP_r32(R_EDI);
nkeynes@368
   448
    POP_r32(R_EBP);
nkeynes@368
   449
    RET();
nkeynes@368
   450
nkeynes@368
   451
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   452
}
nkeynes@359
   453
nkeynes@359
   454
/**
nkeynes@359
   455
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   456
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   457
 * 
nkeynes@359
   458
 *
nkeynes@359
   459
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   460
 * (eg a branch or 
nkeynes@359
   461
 */
nkeynes@359
   462
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   463
{
nkeynes@361
   464
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   465
    
nkeynes@359
   466
%%
nkeynes@359
   467
/* ALU operations */
nkeynes@359
   468
ADD Rm, Rn {:
nkeynes@359
   469
    load_reg( R_EAX, Rm );
nkeynes@359
   470
    load_reg( R_ECX, Rn );
nkeynes@359
   471
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   472
    store_reg( R_ECX, Rn );
nkeynes@359
   473
:}
nkeynes@359
   474
ADD #imm, Rn {:  
nkeynes@359
   475
    load_reg( R_EAX, Rn );
nkeynes@359
   476
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   477
    store_reg( R_EAX, Rn );
nkeynes@359
   478
:}
nkeynes@359
   479
ADDC Rm, Rn {:
nkeynes@359
   480
    load_reg( R_EAX, Rm );
nkeynes@359
   481
    load_reg( R_ECX, Rn );
nkeynes@359
   482
    LDC_t();
nkeynes@359
   483
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   484
    store_reg( R_ECX, Rn );
nkeynes@359
   485
    SETC_t();
nkeynes@359
   486
:}
nkeynes@359
   487
ADDV Rm, Rn {:
nkeynes@359
   488
    load_reg( R_EAX, Rm );
nkeynes@359
   489
    load_reg( R_ECX, Rn );
nkeynes@359
   490
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   491
    store_reg( R_ECX, Rn );
nkeynes@359
   492
    SETO_t();
nkeynes@359
   493
:}
nkeynes@359
   494
AND Rm, Rn {:
nkeynes@359
   495
    load_reg( R_EAX, Rm );
nkeynes@359
   496
    load_reg( R_ECX, Rn );
nkeynes@359
   497
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   498
    store_reg( R_ECX, Rn );
nkeynes@359
   499
:}
nkeynes@359
   500
AND #imm, R0 {:  
nkeynes@359
   501
    load_reg( R_EAX, 0 );
nkeynes@359
   502
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   503
    store_reg( R_EAX, 0 );
nkeynes@359
   504
:}
nkeynes@359
   505
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   506
    load_reg( R_EAX, 0 );
nkeynes@359
   507
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   508
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   509
    PUSH_r32(R_ECX);
nkeynes@386
   510
    call_func0(sh4_read_byte);
nkeynes@386
   511
    POP_r32(R_ECX);
nkeynes@386
   512
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   513
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   514
:}
nkeynes@359
   515
CMP/EQ Rm, Rn {:  
nkeynes@359
   516
    load_reg( R_EAX, Rm );
nkeynes@359
   517
    load_reg( R_ECX, Rn );
nkeynes@359
   518
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   519
    SETE_t();
nkeynes@359
   520
:}
nkeynes@359
   521
CMP/EQ #imm, R0 {:  
nkeynes@359
   522
    load_reg( R_EAX, 0 );
nkeynes@359
   523
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   524
    SETE_t();
nkeynes@359
   525
:}
nkeynes@359
   526
CMP/GE Rm, Rn {:  
nkeynes@359
   527
    load_reg( R_EAX, Rm );
nkeynes@359
   528
    load_reg( R_ECX, Rn );
nkeynes@359
   529
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   530
    SETGE_t();
nkeynes@359
   531
:}
nkeynes@359
   532
CMP/GT Rm, Rn {: 
nkeynes@359
   533
    load_reg( R_EAX, Rm );
nkeynes@359
   534
    load_reg( R_ECX, Rn );
nkeynes@359
   535
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   536
    SETG_t();
nkeynes@359
   537
:}
nkeynes@359
   538
CMP/HI Rm, Rn {:  
nkeynes@359
   539
    load_reg( R_EAX, Rm );
nkeynes@359
   540
    load_reg( R_ECX, Rn );
nkeynes@359
   541
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   542
    SETA_t();
nkeynes@359
   543
:}
nkeynes@359
   544
CMP/HS Rm, Rn {: 
nkeynes@359
   545
    load_reg( R_EAX, Rm );
nkeynes@359
   546
    load_reg( R_ECX, Rn );
nkeynes@359
   547
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   548
    SETAE_t();
nkeynes@359
   549
 :}
nkeynes@359
   550
CMP/PL Rn {: 
nkeynes@359
   551
    load_reg( R_EAX, Rn );
nkeynes@359
   552
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   553
    SETG_t();
nkeynes@359
   554
:}
nkeynes@359
   555
CMP/PZ Rn {:  
nkeynes@359
   556
    load_reg( R_EAX, Rn );
nkeynes@359
   557
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   558
    SETGE_t();
nkeynes@359
   559
:}
nkeynes@361
   560
CMP/STR Rm, Rn {:  
nkeynes@368
   561
    load_reg( R_EAX, Rm );
nkeynes@368
   562
    load_reg( R_ECX, Rn );
nkeynes@368
   563
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   564
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   565
    JE_rel8(13, target1);
nkeynes@368
   566
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   567
    JE_rel8(9, target2);
nkeynes@368
   568
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   569
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   570
    JE_rel8(2, target3);
nkeynes@368
   571
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   572
    JMP_TARGET(target1);
nkeynes@380
   573
    JMP_TARGET(target2);
nkeynes@380
   574
    JMP_TARGET(target3);
nkeynes@368
   575
    SETE_t();
nkeynes@361
   576
:}
nkeynes@361
   577
DIV0S Rm, Rn {:
nkeynes@361
   578
    load_reg( R_EAX, Rm );
nkeynes@386
   579
    load_reg( R_ECX, Rn );
nkeynes@361
   580
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   581
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   582
    store_spreg( R_EAX, R_M );
nkeynes@361
   583
    store_spreg( R_ECX, R_Q );
nkeynes@361
   584
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   585
    SETNE_t();
nkeynes@361
   586
:}
nkeynes@361
   587
DIV0U {:  
nkeynes@361
   588
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   589
    store_spreg( R_EAX, R_Q );
nkeynes@361
   590
    store_spreg( R_EAX, R_M );
nkeynes@361
   591
    store_spreg( R_EAX, R_T );
nkeynes@361
   592
:}
nkeynes@386
   593
DIV1 Rm, Rn {:
nkeynes@386
   594
    load_spreg( R_ECX, R_M );
nkeynes@386
   595
    load_reg( R_EAX, Rn );
nkeynes@374
   596
    LDC_t();
nkeynes@386
   597
    RCL1_r32( R_EAX );
nkeynes@386
   598
    SETC_r8( R_DL ); // Q'
nkeynes@386
   599
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   600
    JE_rel8(5, mqequal);
nkeynes@386
   601
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   602
    JMP_rel8(3, end);
nkeynes@380
   603
    JMP_TARGET(mqequal);
nkeynes@386
   604
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   605
    JMP_TARGET(end);
nkeynes@386
   606
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   607
    SETC_r8(R_AL); // tmp1
nkeynes@386
   608
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   609
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   610
    store_spreg( R_ECX, R_Q );
nkeynes@386
   611
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   612
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   613
    store_spreg( R_EAX, R_T );
nkeynes@374
   614
:}
nkeynes@361
   615
DMULS.L Rm, Rn {:  
nkeynes@361
   616
    load_reg( R_EAX, Rm );
nkeynes@361
   617
    load_reg( R_ECX, Rn );
nkeynes@361
   618
    IMUL_r32(R_ECX);
nkeynes@361
   619
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   620
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   621
:}
nkeynes@361
   622
DMULU.L Rm, Rn {:  
nkeynes@361
   623
    load_reg( R_EAX, Rm );
nkeynes@361
   624
    load_reg( R_ECX, Rn );
nkeynes@361
   625
    MUL_r32(R_ECX);
nkeynes@361
   626
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   627
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   628
:}
nkeynes@359
   629
DT Rn {:  
nkeynes@359
   630
    load_reg( R_EAX, Rn );
nkeynes@382
   631
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   632
    store_reg( R_EAX, Rn );
nkeynes@359
   633
    SETE_t();
nkeynes@359
   634
:}
nkeynes@359
   635
EXTS.B Rm, Rn {:  
nkeynes@359
   636
    load_reg( R_EAX, Rm );
nkeynes@359
   637
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   638
    store_reg( R_EAX, Rn );
nkeynes@359
   639
:}
nkeynes@361
   640
EXTS.W Rm, Rn {:  
nkeynes@361
   641
    load_reg( R_EAX, Rm );
nkeynes@361
   642
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   643
    store_reg( R_EAX, Rn );
nkeynes@361
   644
:}
nkeynes@361
   645
EXTU.B Rm, Rn {:  
nkeynes@361
   646
    load_reg( R_EAX, Rm );
nkeynes@361
   647
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   648
    store_reg( R_EAX, Rn );
nkeynes@361
   649
:}
nkeynes@361
   650
EXTU.W Rm, Rn {:  
nkeynes@361
   651
    load_reg( R_EAX, Rm );
nkeynes@361
   652
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   653
    store_reg( R_EAX, Rn );
nkeynes@361
   654
:}
nkeynes@386
   655
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   656
    load_reg( R_ECX, Rm );
nkeynes@386
   657
    check_ralign32( R_ECX );
nkeynes@386
   658
    load_reg( R_ECX, Rn );
nkeynes@386
   659
    check_ralign32( R_ECX );
nkeynes@386
   660
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   661
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   662
    PUSH_r32( R_EAX );
nkeynes@386
   663
    load_reg( R_ECX, Rm );
nkeynes@386
   664
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   665
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   666
    POP_r32( R_ECX );
nkeynes@386
   667
    IMUL_r32( R_ECX );
nkeynes@386
   668
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   669
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   670
nkeynes@386
   671
    load_spreg( R_ECX, R_S );
nkeynes@386
   672
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   673
    JE_rel8( 7, nosat );
nkeynes@386
   674
    call_func0( signsat48 );
nkeynes@386
   675
    JMP_TARGET( nosat );
nkeynes@386
   676
:}
nkeynes@386
   677
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   678
    load_reg( R_ECX, Rm );
nkeynes@386
   679
    check_ralign16( R_ECX );
nkeynes@386
   680
    load_reg( R_ECX, Rn );
nkeynes@386
   681
    check_ralign16( R_ECX );
nkeynes@386
   682
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   683
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   684
    PUSH_r32( R_EAX );
nkeynes@386
   685
    load_reg( R_ECX, Rm );
nkeynes@386
   686
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   687
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   688
    POP_r32( R_ECX );
nkeynes@386
   689
    IMUL_r32( R_ECX );
nkeynes@386
   690
nkeynes@386
   691
    load_spreg( R_ECX, R_S );
nkeynes@386
   692
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   693
    JE_rel8( 47, nosat );
nkeynes@386
   694
nkeynes@386
   695
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   696
    JNO_rel8( 51, end );            // 2
nkeynes@386
   697
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   698
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   699
    JS_rel8( 13, positive );        // 2
nkeynes@386
   700
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   701
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   702
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   703
nkeynes@386
   704
    JMP_TARGET(positive);
nkeynes@386
   705
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   706
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   707
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   708
nkeynes@386
   709
    JMP_TARGET(nosat);
nkeynes@386
   710
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   711
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   712
    JMP_TARGET(end);
nkeynes@386
   713
    JMP_TARGET(end2);
nkeynes@386
   714
    JMP_TARGET(end3);
nkeynes@386
   715
:}
nkeynes@359
   716
MOVT Rn {:  
nkeynes@359
   717
    load_spreg( R_EAX, R_T );
nkeynes@359
   718
    store_reg( R_EAX, Rn );
nkeynes@359
   719
:}
nkeynes@361
   720
MUL.L Rm, Rn {:  
nkeynes@361
   721
    load_reg( R_EAX, Rm );
nkeynes@361
   722
    load_reg( R_ECX, Rn );
nkeynes@361
   723
    MUL_r32( R_ECX );
nkeynes@361
   724
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   725
:}
nkeynes@374
   726
MULS.W Rm, Rn {:
nkeynes@374
   727
    load_reg16s( R_EAX, Rm );
nkeynes@374
   728
    load_reg16s( R_ECX, Rn );
nkeynes@374
   729
    MUL_r32( R_ECX );
nkeynes@374
   730
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   731
:}
nkeynes@374
   732
MULU.W Rm, Rn {:  
nkeynes@374
   733
    load_reg16u( R_EAX, Rm );
nkeynes@374
   734
    load_reg16u( R_ECX, Rn );
nkeynes@374
   735
    MUL_r32( R_ECX );
nkeynes@374
   736
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   737
:}
nkeynes@359
   738
NEG Rm, Rn {:
nkeynes@359
   739
    load_reg( R_EAX, Rm );
nkeynes@359
   740
    NEG_r32( R_EAX );
nkeynes@359
   741
    store_reg( R_EAX, Rn );
nkeynes@359
   742
:}
nkeynes@359
   743
NEGC Rm, Rn {:  
nkeynes@359
   744
    load_reg( R_EAX, Rm );
nkeynes@359
   745
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   746
    LDC_t();
nkeynes@359
   747
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   748
    store_reg( R_ECX, Rn );
nkeynes@359
   749
    SETC_t();
nkeynes@359
   750
:}
nkeynes@359
   751
NOT Rm, Rn {:  
nkeynes@359
   752
    load_reg( R_EAX, Rm );
nkeynes@359
   753
    NOT_r32( R_EAX );
nkeynes@359
   754
    store_reg( R_EAX, Rn );
nkeynes@359
   755
:}
nkeynes@359
   756
OR Rm, Rn {:  
nkeynes@359
   757
    load_reg( R_EAX, Rm );
nkeynes@359
   758
    load_reg( R_ECX, Rn );
nkeynes@359
   759
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   760
    store_reg( R_ECX, Rn );
nkeynes@359
   761
:}
nkeynes@359
   762
OR #imm, R0 {:
nkeynes@359
   763
    load_reg( R_EAX, 0 );
nkeynes@359
   764
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   765
    store_reg( R_EAX, 0 );
nkeynes@359
   766
:}
nkeynes@374
   767
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   768
    load_reg( R_EAX, 0 );
nkeynes@374
   769
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   770
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   771
    PUSH_r32(R_ECX);
nkeynes@386
   772
    call_func0(sh4_read_byte);
nkeynes@386
   773
    POP_r32(R_ECX);
nkeynes@386
   774
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   775
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   776
:}
nkeynes@359
   777
ROTCL Rn {:
nkeynes@359
   778
    load_reg( R_EAX, Rn );
nkeynes@359
   779
    LDC_t();
nkeynes@359
   780
    RCL1_r32( R_EAX );
nkeynes@359
   781
    store_reg( R_EAX, Rn );
nkeynes@359
   782
    SETC_t();
nkeynes@359
   783
:}
nkeynes@359
   784
ROTCR Rn {:  
nkeynes@359
   785
    load_reg( R_EAX, Rn );
nkeynes@359
   786
    LDC_t();
nkeynes@359
   787
    RCR1_r32( R_EAX );
nkeynes@359
   788
    store_reg( R_EAX, Rn );
nkeynes@359
   789
    SETC_t();
nkeynes@359
   790
:}
nkeynes@359
   791
ROTL Rn {:  
nkeynes@359
   792
    load_reg( R_EAX, Rn );
nkeynes@359
   793
    ROL1_r32( R_EAX );
nkeynes@359
   794
    store_reg( R_EAX, Rn );
nkeynes@359
   795
    SETC_t();
nkeynes@359
   796
:}
nkeynes@359
   797
ROTR Rn {:  
nkeynes@359
   798
    load_reg( R_EAX, Rn );
nkeynes@359
   799
    ROR1_r32( R_EAX );
nkeynes@359
   800
    store_reg( R_EAX, Rn );
nkeynes@359
   801
    SETC_t();
nkeynes@359
   802
:}
nkeynes@359
   803
SHAD Rm, Rn {:
nkeynes@359
   804
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   805
    load_reg( R_EAX, Rn );
nkeynes@361
   806
    load_reg( R_ECX, Rm );
nkeynes@361
   807
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   808
    JGE_rel8(16, doshl);
nkeynes@361
   809
                    
nkeynes@361
   810
    NEG_r32( R_ECX );      // 2
nkeynes@361
   811
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   812
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   813
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   814
    JMP_rel8(10, end);          // 2
nkeynes@386
   815
nkeynes@386
   816
    JMP_TARGET(emptysar);
nkeynes@386
   817
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   818
    JMP_rel8(5, end2);
nkeynes@382
   819
nkeynes@380
   820
    JMP_TARGET(doshl);
nkeynes@361
   821
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   822
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   823
    JMP_TARGET(end);
nkeynes@386
   824
    JMP_TARGET(end2);
nkeynes@361
   825
    store_reg( R_EAX, Rn );
nkeynes@359
   826
:}
nkeynes@359
   827
SHLD Rm, Rn {:  
nkeynes@368
   828
    load_reg( R_EAX, Rn );
nkeynes@368
   829
    load_reg( R_ECX, Rm );
nkeynes@382
   830
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   831
    JGE_rel8(15, doshl);
nkeynes@368
   832
nkeynes@382
   833
    NEG_r32( R_ECX );      // 2
nkeynes@382
   834
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   835
    JE_rel8( 4, emptyshr );
nkeynes@382
   836
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   837
    JMP_rel8(9, end);          // 2
nkeynes@386
   838
nkeynes@386
   839
    JMP_TARGET(emptyshr);
nkeynes@386
   840
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   841
    JMP_rel8(5, end2);
nkeynes@382
   842
nkeynes@382
   843
    JMP_TARGET(doshl);
nkeynes@382
   844
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   845
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   846
    JMP_TARGET(end);
nkeynes@386
   847
    JMP_TARGET(end2);
nkeynes@368
   848
    store_reg( R_EAX, Rn );
nkeynes@359
   849
:}
nkeynes@359
   850
SHAL Rn {: 
nkeynes@359
   851
    load_reg( R_EAX, Rn );
nkeynes@359
   852
    SHL1_r32( R_EAX );
nkeynes@359
   853
    store_reg( R_EAX, Rn );
nkeynes@359
   854
:}
nkeynes@359
   855
SHAR Rn {:  
nkeynes@359
   856
    load_reg( R_EAX, Rn );
nkeynes@359
   857
    SAR1_r32( R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, Rn );
nkeynes@359
   859
:}
nkeynes@359
   860
SHLL Rn {:  
nkeynes@359
   861
    load_reg( R_EAX, Rn );
nkeynes@359
   862
    SHL1_r32( R_EAX );
nkeynes@359
   863
    store_reg( R_EAX, Rn );
nkeynes@359
   864
:}
nkeynes@359
   865
SHLL2 Rn {:
nkeynes@359
   866
    load_reg( R_EAX, Rn );
nkeynes@359
   867
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   868
    store_reg( R_EAX, Rn );
nkeynes@359
   869
:}
nkeynes@359
   870
SHLL8 Rn {:  
nkeynes@359
   871
    load_reg( R_EAX, Rn );
nkeynes@359
   872
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   873
    store_reg( R_EAX, Rn );
nkeynes@359
   874
:}
nkeynes@359
   875
SHLL16 Rn {:  
nkeynes@359
   876
    load_reg( R_EAX, Rn );
nkeynes@359
   877
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   878
    store_reg( R_EAX, Rn );
nkeynes@359
   879
:}
nkeynes@359
   880
SHLR Rn {:  
nkeynes@359
   881
    load_reg( R_EAX, Rn );
nkeynes@359
   882
    SHR1_r32( R_EAX );
nkeynes@359
   883
    store_reg( R_EAX, Rn );
nkeynes@359
   884
:}
nkeynes@359
   885
SHLR2 Rn {:  
nkeynes@359
   886
    load_reg( R_EAX, Rn );
nkeynes@359
   887
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   888
    store_reg( R_EAX, Rn );
nkeynes@359
   889
:}
nkeynes@359
   890
SHLR8 Rn {:  
nkeynes@359
   891
    load_reg( R_EAX, Rn );
nkeynes@359
   892
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   893
    store_reg( R_EAX, Rn );
nkeynes@359
   894
:}
nkeynes@359
   895
SHLR16 Rn {:  
nkeynes@359
   896
    load_reg( R_EAX, Rn );
nkeynes@359
   897
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   898
    store_reg( R_EAX, Rn );
nkeynes@359
   899
:}
nkeynes@359
   900
SUB Rm, Rn {:  
nkeynes@359
   901
    load_reg( R_EAX, Rm );
nkeynes@359
   902
    load_reg( R_ECX, Rn );
nkeynes@359
   903
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   904
    store_reg( R_ECX, Rn );
nkeynes@359
   905
:}
nkeynes@359
   906
SUBC Rm, Rn {:  
nkeynes@359
   907
    load_reg( R_EAX, Rm );
nkeynes@359
   908
    load_reg( R_ECX, Rn );
nkeynes@359
   909
    LDC_t();
nkeynes@359
   910
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   911
    store_reg( R_ECX, Rn );
nkeynes@359
   912
:}
nkeynes@359
   913
SUBV Rm, Rn {:  
nkeynes@359
   914
    load_reg( R_EAX, Rm );
nkeynes@359
   915
    load_reg( R_ECX, Rn );
nkeynes@359
   916
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   917
    store_reg( R_ECX, Rn );
nkeynes@359
   918
    SETO_t();
nkeynes@359
   919
:}
nkeynes@359
   920
SWAP.B Rm, Rn {:  
nkeynes@359
   921
    load_reg( R_EAX, Rm );
nkeynes@359
   922
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   923
    store_reg( R_EAX, Rn );
nkeynes@359
   924
:}
nkeynes@359
   925
SWAP.W Rm, Rn {:  
nkeynes@359
   926
    load_reg( R_EAX, Rm );
nkeynes@359
   927
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   928
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   929
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   930
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   931
    store_reg( R_ECX, Rn );
nkeynes@359
   932
:}
nkeynes@361
   933
TAS.B @Rn {:  
nkeynes@361
   934
    load_reg( R_ECX, Rn );
nkeynes@361
   935
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   936
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   937
    SETE_t();
nkeynes@361
   938
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   939
    load_reg( R_ECX, Rn );
nkeynes@361
   940
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   941
:}
nkeynes@361
   942
TST Rm, Rn {:  
nkeynes@361
   943
    load_reg( R_EAX, Rm );
nkeynes@361
   944
    load_reg( R_ECX, Rn );
nkeynes@361
   945
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   946
    SETE_t();
nkeynes@361
   947
:}
nkeynes@368
   948
TST #imm, R0 {:  
nkeynes@368
   949
    load_reg( R_EAX, 0 );
nkeynes@368
   950
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   951
    SETE_t();
nkeynes@368
   952
:}
nkeynes@368
   953
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   954
    load_reg( R_EAX, 0);
nkeynes@368
   955
    load_reg( R_ECX, R_GBR);
nkeynes@368
   956
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   957
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
   958
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
   959
    SETE_t();
nkeynes@368
   960
:}
nkeynes@359
   961
XOR Rm, Rn {:  
nkeynes@359
   962
    load_reg( R_EAX, Rm );
nkeynes@359
   963
    load_reg( R_ECX, Rn );
nkeynes@359
   964
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   965
    store_reg( R_ECX, Rn );
nkeynes@359
   966
:}
nkeynes@359
   967
XOR #imm, R0 {:  
nkeynes@359
   968
    load_reg( R_EAX, 0 );
nkeynes@359
   969
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   970
    store_reg( R_EAX, 0 );
nkeynes@359
   971
:}
nkeynes@359
   972
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   973
    load_reg( R_EAX, 0 );
nkeynes@359
   974
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   975
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   976
    PUSH_r32(R_ECX);
nkeynes@386
   977
    call_func0(sh4_read_byte);
nkeynes@386
   978
    POP_r32(R_ECX);
nkeynes@359
   979
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   980
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   981
:}
nkeynes@361
   982
XTRCT Rm, Rn {:
nkeynes@361
   983
    load_reg( R_EAX, Rm );
nkeynes@361
   984
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   985
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   986
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   987
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   988
    store_reg( R_ECX, Rn );
nkeynes@359
   989
:}
nkeynes@359
   990
nkeynes@359
   991
/* Data move instructions */
nkeynes@359
   992
MOV Rm, Rn {:  
nkeynes@359
   993
    load_reg( R_EAX, Rm );
nkeynes@359
   994
    store_reg( R_EAX, Rn );
nkeynes@359
   995
:}
nkeynes@359
   996
MOV #imm, Rn {:  
nkeynes@359
   997
    load_imm32( R_EAX, imm );
nkeynes@359
   998
    store_reg( R_EAX, Rn );
nkeynes@359
   999
:}
nkeynes@359
  1000
MOV.B Rm, @Rn {:  
nkeynes@359
  1001
    load_reg( R_EAX, Rm );
nkeynes@359
  1002
    load_reg( R_ECX, Rn );
nkeynes@359
  1003
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1004
:}
nkeynes@359
  1005
MOV.B Rm, @-Rn {:  
nkeynes@359
  1006
    load_reg( R_EAX, Rm );
nkeynes@359
  1007
    load_reg( R_ECX, Rn );
nkeynes@382
  1008
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1009
    store_reg( R_ECX, Rn );
nkeynes@359
  1010
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1011
:}
nkeynes@359
  1012
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1013
    load_reg( R_EAX, 0 );
nkeynes@359
  1014
    load_reg( R_ECX, Rn );
nkeynes@359
  1015
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1016
    load_reg( R_EAX, Rm );
nkeynes@359
  1017
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1018
:}
nkeynes@359
  1019
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1020
    load_reg( R_EAX, 0 );
nkeynes@359
  1021
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1022
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1023
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1024
:}
nkeynes@359
  1025
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1026
    load_reg( R_EAX, 0 );
nkeynes@359
  1027
    load_reg( R_ECX, Rn );
nkeynes@359
  1028
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1029
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1030
:}
nkeynes@359
  1031
MOV.B @Rm, Rn {:  
nkeynes@359
  1032
    load_reg( R_ECX, Rm );
nkeynes@359
  1033
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1034
    store_reg( R_EAX, Rn );
nkeynes@359
  1035
:}
nkeynes@359
  1036
MOV.B @Rm+, Rn {:  
nkeynes@359
  1037
    load_reg( R_ECX, Rm );
nkeynes@359
  1038
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1039
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1040
    store_reg( R_EAX, Rm );
nkeynes@359
  1041
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1042
    store_reg( R_EAX, Rn );
nkeynes@359
  1043
:}
nkeynes@359
  1044
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1045
    load_reg( R_EAX, 0 );
nkeynes@359
  1046
    load_reg( R_ECX, Rm );
nkeynes@359
  1047
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1048
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1049
    store_reg( R_EAX, Rn );
nkeynes@359
  1050
:}
nkeynes@359
  1051
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1052
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1053
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1054
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1055
    store_reg( R_EAX, 0 );
nkeynes@359
  1056
:}
nkeynes@359
  1057
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1058
    load_reg( R_ECX, Rm );
nkeynes@359
  1059
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1060
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1061
    store_reg( R_EAX, 0 );
nkeynes@359
  1062
:}
nkeynes@374
  1063
MOV.L Rm, @Rn {:
nkeynes@361
  1064
    load_reg( R_EAX, Rm );
nkeynes@361
  1065
    load_reg( R_ECX, Rn );
nkeynes@374
  1066
    check_walign32(R_ECX);
nkeynes@361
  1067
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1068
:}
nkeynes@361
  1069
MOV.L Rm, @-Rn {:  
nkeynes@361
  1070
    load_reg( R_EAX, Rm );
nkeynes@361
  1071
    load_reg( R_ECX, Rn );
nkeynes@374
  1072
    check_walign32( R_ECX );
nkeynes@361
  1073
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1074
    store_reg( R_ECX, Rn );
nkeynes@361
  1075
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1076
:}
nkeynes@361
  1077
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1078
    load_reg( R_EAX, 0 );
nkeynes@361
  1079
    load_reg( R_ECX, Rn );
nkeynes@361
  1080
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1081
    check_walign32( R_ECX );
nkeynes@361
  1082
    load_reg( R_EAX, Rm );
nkeynes@361
  1083
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1084
:}
nkeynes@361
  1085
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1086
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1087
    load_reg( R_EAX, 0 );
nkeynes@361
  1088
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1089
    check_walign32( R_ECX );
nkeynes@361
  1090
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1091
:}
nkeynes@361
  1092
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1093
    load_reg( R_ECX, Rn );
nkeynes@361
  1094
    load_reg( R_EAX, Rm );
nkeynes@361
  1095
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1096
    check_walign32( R_ECX );
nkeynes@361
  1097
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1098
:}
nkeynes@361
  1099
MOV.L @Rm, Rn {:  
nkeynes@361
  1100
    load_reg( R_ECX, Rm );
nkeynes@374
  1101
    check_ralign32( R_ECX );
nkeynes@361
  1102
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1103
    store_reg( R_EAX, Rn );
nkeynes@361
  1104
:}
nkeynes@361
  1105
MOV.L @Rm+, Rn {:  
nkeynes@361
  1106
    load_reg( R_EAX, Rm );
nkeynes@382
  1107
    check_ralign32( R_EAX );
nkeynes@361
  1108
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1109
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1110
    store_reg( R_EAX, Rm );
nkeynes@361
  1111
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1112
    store_reg( R_EAX, Rn );
nkeynes@361
  1113
:}
nkeynes@361
  1114
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1115
    load_reg( R_EAX, 0 );
nkeynes@361
  1116
    load_reg( R_ECX, Rm );
nkeynes@361
  1117
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1118
    check_ralign32( R_ECX );
nkeynes@361
  1119
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1120
    store_reg( R_EAX, Rn );
nkeynes@361
  1121
:}
nkeynes@361
  1122
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1123
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1124
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1125
    check_ralign32( R_ECX );
nkeynes@361
  1126
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1127
    store_reg( R_EAX, 0 );
nkeynes@361
  1128
:}
nkeynes@361
  1129
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1130
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1131
	SLOTILLEGAL();
nkeynes@374
  1132
    } else {
nkeynes@374
  1133
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1134
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@382
  1135
	store_reg( R_EAX, Rn );
nkeynes@374
  1136
    }
nkeynes@361
  1137
:}
nkeynes@361
  1138
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1139
    load_reg( R_ECX, Rm );
nkeynes@361
  1140
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1141
    check_ralign32( R_ECX );
nkeynes@361
  1142
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1143
    store_reg( R_EAX, Rn );
nkeynes@361
  1144
:}
nkeynes@361
  1145
MOV.W Rm, @Rn {:  
nkeynes@361
  1146
    load_reg( R_ECX, Rn );
nkeynes@374
  1147
    check_walign16( R_ECX );
nkeynes@382
  1148
    load_reg( R_EAX, Rm );
nkeynes@382
  1149
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1150
:}
nkeynes@361
  1151
MOV.W Rm, @-Rn {:  
nkeynes@361
  1152
    load_reg( R_ECX, Rn );
nkeynes@374
  1153
    check_walign16( R_ECX );
nkeynes@361
  1154
    load_reg( R_EAX, Rm );
nkeynes@361
  1155
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1156
    store_reg( R_ECX, Rn );
nkeynes@361
  1157
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1158
:}
nkeynes@361
  1159
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1160
    load_reg( R_EAX, 0 );
nkeynes@361
  1161
    load_reg( R_ECX, Rn );
nkeynes@361
  1162
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1163
    check_walign16( R_ECX );
nkeynes@361
  1164
    load_reg( R_EAX, Rm );
nkeynes@361
  1165
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1166
:}
nkeynes@361
  1167
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1168
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1169
    load_reg( R_EAX, 0 );
nkeynes@361
  1170
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1171
    check_walign16( R_ECX );
nkeynes@361
  1172
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1173
:}
nkeynes@361
  1174
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1175
    load_reg( R_ECX, Rn );
nkeynes@361
  1176
    load_reg( R_EAX, 0 );
nkeynes@361
  1177
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1178
    check_walign16( R_ECX );
nkeynes@361
  1179
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1180
:}
nkeynes@361
  1181
MOV.W @Rm, Rn {:  
nkeynes@361
  1182
    load_reg( R_ECX, Rm );
nkeynes@374
  1183
    check_ralign16( R_ECX );
nkeynes@361
  1184
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1185
    store_reg( R_EAX, Rn );
nkeynes@361
  1186
:}
nkeynes@361
  1187
MOV.W @Rm+, Rn {:  
nkeynes@361
  1188
    load_reg( R_EAX, Rm );
nkeynes@374
  1189
    check_ralign16( R_EAX );
nkeynes@361
  1190
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1191
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1192
    store_reg( R_EAX, Rm );
nkeynes@361
  1193
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1194
    store_reg( R_EAX, Rn );
nkeynes@361
  1195
:}
nkeynes@361
  1196
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1197
    load_reg( R_EAX, 0 );
nkeynes@361
  1198
    load_reg( R_ECX, Rm );
nkeynes@361
  1199
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1200
    check_ralign16( R_ECX );
nkeynes@361
  1201
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1202
    store_reg( R_EAX, Rn );
nkeynes@361
  1203
:}
nkeynes@361
  1204
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1205
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1206
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1207
    check_ralign16( R_ECX );
nkeynes@361
  1208
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1209
    store_reg( R_EAX, 0 );
nkeynes@361
  1210
:}
nkeynes@361
  1211
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1212
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1213
	SLOTILLEGAL();
nkeynes@374
  1214
    } else {
nkeynes@374
  1215
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1216
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1217
	store_reg( R_EAX, Rn );
nkeynes@374
  1218
    }
nkeynes@361
  1219
:}
nkeynes@361
  1220
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1221
    load_reg( R_ECX, Rm );
nkeynes@361
  1222
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1223
    check_ralign16( R_ECX );
nkeynes@361
  1224
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1225
    store_reg( R_EAX, 0 );
nkeynes@361
  1226
:}
nkeynes@361
  1227
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1228
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1229
	SLOTILLEGAL();
nkeynes@374
  1230
    } else {
nkeynes@374
  1231
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1232
	store_reg( R_ECX, 0 );
nkeynes@374
  1233
    }
nkeynes@361
  1234
:}
nkeynes@361
  1235
MOVCA.L R0, @Rn {:  
nkeynes@361
  1236
    load_reg( R_EAX, 0 );
nkeynes@361
  1237
    load_reg( R_ECX, Rn );
nkeynes@374
  1238
    check_walign32( R_ECX );
nkeynes@361
  1239
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1240
:}
nkeynes@359
  1241
nkeynes@359
  1242
/* Control transfer instructions */
nkeynes@374
  1243
BF disp {:
nkeynes@374
  1244
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1245
	SLOTILLEGAL();
nkeynes@374
  1246
    } else {
nkeynes@374
  1247
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1248
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1249
	JNE_rel8( 5, nottaken );
nkeynes@374
  1250
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1251
	JMP_TARGET(nottaken);
nkeynes@374
  1252
	INC_r32(R_ESI);
nkeynes@374
  1253
	return 1;
nkeynes@374
  1254
    }
nkeynes@374
  1255
:}
nkeynes@374
  1256
BF/S disp {:
nkeynes@374
  1257
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1258
	SLOTILLEGAL();
nkeynes@374
  1259
    } else {
nkeynes@386
  1260
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1261
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1262
	JNE_rel8( 5, nottaken );
nkeynes@374
  1263
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1264
	JMP_TARGET(nottaken);
nkeynes@374
  1265
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1266
	return 0;
nkeynes@374
  1267
    }
nkeynes@374
  1268
:}
nkeynes@374
  1269
BRA disp {:  
nkeynes@374
  1270
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1271
	SLOTILLEGAL();
nkeynes@374
  1272
    } else {
nkeynes@374
  1273
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1274
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1275
	return 0;
nkeynes@374
  1276
    }
nkeynes@374
  1277
:}
nkeynes@374
  1278
BRAF Rn {:  
nkeynes@374
  1279
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1280
	SLOTILLEGAL();
nkeynes@374
  1281
    } else {
nkeynes@374
  1282
	load_reg( R_EDI, Rn );
nkeynes@382
  1283
	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
  1284
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1285
	return 0;
nkeynes@374
  1286
    }
nkeynes@374
  1287
:}
nkeynes@374
  1288
BSR disp {:  
nkeynes@374
  1289
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1290
	SLOTILLEGAL();
nkeynes@374
  1291
    } else {
nkeynes@374
  1292
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1293
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1294
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1295
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1296
	return 0;
nkeynes@374
  1297
    }
nkeynes@374
  1298
:}
nkeynes@374
  1299
BSRF Rn {:  
nkeynes@374
  1300
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1301
	SLOTILLEGAL();
nkeynes@374
  1302
    } else {
nkeynes@374
  1303
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1304
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1305
	load_reg( R_EDI, Rn );
nkeynes@374
  1306
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1307
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1308
	return 0;
nkeynes@374
  1309
    }
nkeynes@374
  1310
:}
nkeynes@374
  1311
BT disp {:
nkeynes@374
  1312
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1313
	SLOTILLEGAL();
nkeynes@374
  1314
    } else {
nkeynes@374
  1315
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1316
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1317
	JE_rel8( 5, nottaken );
nkeynes@374
  1318
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1319
	JMP_TARGET(nottaken);
nkeynes@374
  1320
	INC_r32(R_ESI);
nkeynes@374
  1321
	return 1;
nkeynes@374
  1322
    }
nkeynes@374
  1323
:}
nkeynes@374
  1324
BT/S disp {:
nkeynes@374
  1325
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1326
	SLOTILLEGAL();
nkeynes@374
  1327
    } else {
nkeynes@386
  1328
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1329
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1330
	JE_rel8( 5, nottaken );
nkeynes@374
  1331
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1332
	JMP_TARGET(nottaken);
nkeynes@374
  1333
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1334
	return 0;
nkeynes@374
  1335
    }
nkeynes@374
  1336
:}
nkeynes@374
  1337
JMP @Rn {:  
nkeynes@374
  1338
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1339
	SLOTILLEGAL();
nkeynes@374
  1340
    } else {
nkeynes@374
  1341
	load_reg( R_EDI, Rn );
nkeynes@374
  1342
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1343
	return 0;
nkeynes@374
  1344
    }
nkeynes@374
  1345
:}
nkeynes@374
  1346
JSR @Rn {:  
nkeynes@374
  1347
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1348
	SLOTILLEGAL();
nkeynes@374
  1349
    } else {
nkeynes@374
  1350
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1351
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1352
	load_reg( R_EDI, Rn );
nkeynes@374
  1353
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1354
	return 0;
nkeynes@374
  1355
    }
nkeynes@374
  1356
:}
nkeynes@374
  1357
RTE {:  
nkeynes@374
  1358
    check_priv();
nkeynes@374
  1359
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1360
	SLOTILLEGAL();
nkeynes@374
  1361
    } else {
nkeynes@386
  1362
	load_spreg( R_EDI, R_SPC );
nkeynes@374
  1363
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1364
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1365
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1366
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1367
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1368
	return 0;
nkeynes@374
  1369
    }
nkeynes@374
  1370
:}
nkeynes@374
  1371
RTS {:  
nkeynes@374
  1372
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1373
	SLOTILLEGAL();
nkeynes@374
  1374
    } else {
nkeynes@374
  1375
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1376
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1377
	return 0;
nkeynes@374
  1378
    }
nkeynes@374
  1379
:}
nkeynes@374
  1380
TRAPA #imm {:  
nkeynes@374
  1381
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1382
	SLOTILLEGAL();
nkeynes@374
  1383
    } else {
nkeynes@374
  1384
	// TODO: Write TRA 
nkeynes@374
  1385
	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  1386
    }
nkeynes@374
  1387
:}
nkeynes@374
  1388
UNDEF {:  
nkeynes@374
  1389
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1390
	SLOTILLEGAL();
nkeynes@374
  1391
    } else {
nkeynes@386
  1392
	JMP_exit(EXIT_ILLEGAL);
nkeynes@382
  1393
	return 1;
nkeynes@374
  1394
    }
nkeynes@368
  1395
:}
nkeynes@374
  1396
nkeynes@374
  1397
CLRMAC {:  
nkeynes@374
  1398
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1399
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1400
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1401
:}
nkeynes@374
  1402
CLRS {:
nkeynes@374
  1403
    CLC();
nkeynes@374
  1404
    SETC_sh4r(R_S);
nkeynes@368
  1405
:}
nkeynes@374
  1406
CLRT {:  
nkeynes@374
  1407
    CLC();
nkeynes@374
  1408
    SETC_t();
nkeynes@359
  1409
:}
nkeynes@374
  1410
SETS {:  
nkeynes@374
  1411
    STC();
nkeynes@374
  1412
    SETC_sh4r(R_S);
nkeynes@359
  1413
:}
nkeynes@374
  1414
SETT {:  
nkeynes@374
  1415
    STC();
nkeynes@374
  1416
    SETC_t();
nkeynes@374
  1417
:}
nkeynes@359
  1418
nkeynes@375
  1419
/* Floating point moves */
nkeynes@375
  1420
FMOV FRm, FRn {:  
nkeynes@375
  1421
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1422
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1423
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1424
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1425
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1426
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1427
     */
nkeynes@377
  1428
    check_fpuen();
nkeynes@375
  1429
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1430
    load_fr_bank( R_EDX );
nkeynes@375
  1431
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1432
    JNE_rel8(8, doublesize);
nkeynes@375
  1433
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1434
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1435
    if( FRm&1 ) {
nkeynes@386
  1436
	JMP_rel8(24, end);
nkeynes@380
  1437
	JMP_TARGET(doublesize);
nkeynes@375
  1438
	load_xf_bank( R_ECX ); 
nkeynes@375
  1439
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1440
	if( FRn&1 ) {
nkeynes@375
  1441
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1442
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1443
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1444
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1445
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  1446
	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  1447
	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  1448
	}
nkeynes@380
  1449
	JMP_TARGET(end);
nkeynes@375
  1450
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1451
	if( FRn&1 ) {
nkeynes@386
  1452
	    JMP_rel8(24, end);
nkeynes@375
  1453
	    load_xf_bank( R_ECX );
nkeynes@375
  1454
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1455
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1456
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1457
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1458
	    JMP_TARGET(end);
nkeynes@375
  1459
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1460
	    JMP_rel8(12, end);
nkeynes@375
  1461
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1462
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1463
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1464
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1465
	    JMP_TARGET(end);
nkeynes@375
  1466
	}
nkeynes@375
  1467
    }
nkeynes@375
  1468
:}
nkeynes@375
  1469
FMOV FRm, @Rn {:  
nkeynes@377
  1470
    check_fpuen();
nkeynes@375
  1471
    load_reg( R_EDX, Rn );
nkeynes@375
  1472
    check_walign32( R_EDX );
nkeynes@375
  1473
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1474
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1475
    JNE_rel8(20, doublesize);
nkeynes@377
  1476
    load_fr_bank( R_ECX );
nkeynes@375
  1477
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1478
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1479
    if( FRm&1 ) {
nkeynes@386
  1480
	JMP_rel8( 48, end );
nkeynes@380
  1481
	JMP_TARGET(doublesize);
nkeynes@375
  1482
	load_xf_bank( R_ECX );
nkeynes@380
  1483
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1484
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1485
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1486
	JMP_TARGET(end);
nkeynes@375
  1487
    } else {
nkeynes@380
  1488
	JMP_rel8( 39, end );
nkeynes@380
  1489
	JMP_TARGET(doublesize);
nkeynes@377
  1490
	load_fr_bank( R_ECX );
nkeynes@380
  1491
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1492
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1493
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1494
	JMP_TARGET(end);
nkeynes@375
  1495
    }
nkeynes@375
  1496
:}
nkeynes@375
  1497
FMOV @Rm, FRn {:  
nkeynes@377
  1498
    check_fpuen();
nkeynes@375
  1499
    load_reg( R_EDX, Rm );
nkeynes@375
  1500
    check_ralign32( R_EDX );
nkeynes@375
  1501
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1502
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1503
    JNE_rel8(19, doublesize);
nkeynes@375
  1504
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1505
    load_fr_bank( R_ECX );
nkeynes@375
  1506
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1507
    if( FRn&1 ) {
nkeynes@386
  1508
	JMP_rel8(48, end);
nkeynes@380
  1509
	JMP_TARGET(doublesize);
nkeynes@375
  1510
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1511
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1512
	load_xf_bank( R_ECX );
nkeynes@380
  1513
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1514
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1515
	JMP_TARGET(end);
nkeynes@375
  1516
    } else {
nkeynes@380
  1517
	JMP_rel8(36, end);
nkeynes@380
  1518
	JMP_TARGET(doublesize);
nkeynes@375
  1519
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1520
	load_fr_bank( R_ECX );
nkeynes@380
  1521
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1522
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1523
	JMP_TARGET(end);
nkeynes@375
  1524
    }
nkeynes@375
  1525
:}
nkeynes@377
  1526
FMOV FRm, @-Rn {:  
nkeynes@377
  1527
    check_fpuen();
nkeynes@377
  1528
    load_reg( R_EDX, Rn );
nkeynes@377
  1529
    check_walign32( R_EDX );
nkeynes@377
  1530
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1531
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@382
  1532
    JNE_rel8(26, doublesize);
nkeynes@377
  1533
    load_fr_bank( R_ECX );
nkeynes@377
  1534
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1535
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1536
    store_reg( R_EDX, Rn );
nkeynes@377
  1537
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1538
    if( FRm&1 ) {
nkeynes@386
  1539
	JMP_rel8( 54, end );
nkeynes@380
  1540
	JMP_TARGET(doublesize);
nkeynes@377
  1541
	load_xf_bank( R_ECX );
nkeynes@380
  1542
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1543
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1544
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1545
	store_reg( R_EDX, Rn );
nkeynes@380
  1546
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1547
	JMP_TARGET(end);
nkeynes@377
  1548
    } else {
nkeynes@382
  1549
	JMP_rel8( 45, end );
nkeynes@380
  1550
	JMP_TARGET(doublesize);
nkeynes@377
  1551
	load_fr_bank( R_ECX );
nkeynes@380
  1552
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1553
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1554
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1555
	store_reg( R_EDX, Rn );
nkeynes@380
  1556
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1557
	JMP_TARGET(end);
nkeynes@377
  1558
    }
nkeynes@377
  1559
:}
nkeynes@377
  1560
FMOV @Rm+, FRn {:  
nkeynes@377
  1561
    check_fpuen();
nkeynes@377
  1562
    load_reg( R_EDX, Rm );
nkeynes@377
  1563
    check_ralign32( R_EDX );
nkeynes@377
  1564
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1565
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1566
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1567
    JNE_rel8(25, doublesize);
nkeynes@377
  1568
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1569
    store_reg( R_EAX, Rm );
nkeynes@377
  1570
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1571
    load_fr_bank( R_ECX );
nkeynes@377
  1572
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1573
    if( FRn&1 ) {
nkeynes@386
  1574
	JMP_rel8(54, end);
nkeynes@380
  1575
	JMP_TARGET(doublesize);
nkeynes@377
  1576
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1577
	store_reg(R_EAX, Rm);
nkeynes@377
  1578
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1579
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1580
	load_xf_bank( R_ECX );
nkeynes@380
  1581
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1582
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1583
	JMP_TARGET(end);
nkeynes@377
  1584
    } else {
nkeynes@380
  1585
	JMP_rel8(42, end);
nkeynes@377
  1586
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1587
	store_reg(R_EAX, Rm);
nkeynes@377
  1588
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1589
	load_fr_bank( R_ECX );
nkeynes@380
  1590
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1591
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1592
	JMP_TARGET(end);
nkeynes@377
  1593
    }
nkeynes@377
  1594
:}
nkeynes@377
  1595
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1596
    check_fpuen();
nkeynes@377
  1597
    load_reg( R_EDX, Rn );
nkeynes@377
  1598
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1599
    check_walign32( R_EDX );
nkeynes@377
  1600
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1601
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1602
    JNE_rel8(20, doublesize);
nkeynes@377
  1603
    load_fr_bank( R_ECX );
nkeynes@377
  1604
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1605
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1606
    if( FRm&1 ) {
nkeynes@386
  1607
	JMP_rel8( 48, end );
nkeynes@380
  1608
	JMP_TARGET(doublesize);
nkeynes@377
  1609
	load_xf_bank( R_ECX );
nkeynes@380
  1610
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1611
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1612
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1613
	JMP_TARGET(end);
nkeynes@377
  1614
    } else {
nkeynes@380
  1615
	JMP_rel8( 39, end );
nkeynes@380
  1616
	JMP_TARGET(doublesize);
nkeynes@377
  1617
	load_fr_bank( R_ECX );
nkeynes@380
  1618
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1619
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1620
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1621
	JMP_TARGET(end);
nkeynes@377
  1622
    }
nkeynes@377
  1623
:}
nkeynes@377
  1624
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1625
    check_fpuen();
nkeynes@377
  1626
    load_reg( R_EDX, Rm );
nkeynes@377
  1627
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1628
    check_ralign32( R_EDX );
nkeynes@377
  1629
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1630
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1631
    JNE_rel8(19, doublesize);
nkeynes@377
  1632
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1633
    load_fr_bank( R_ECX );
nkeynes@377
  1634
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1635
    if( FRn&1 ) {
nkeynes@386
  1636
	JMP_rel8(48, end);
nkeynes@380
  1637
	JMP_TARGET(doublesize);
nkeynes@377
  1638
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1639
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1640
	load_xf_bank( R_ECX );
nkeynes@380
  1641
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1642
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1643
	JMP_TARGET(end);
nkeynes@377
  1644
    } else {
nkeynes@380
  1645
	JMP_rel8(36, end);
nkeynes@380
  1646
	JMP_TARGET(doublesize);
nkeynes@377
  1647
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1648
	load_fr_bank( R_ECX );
nkeynes@380
  1649
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1650
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1651
	JMP_TARGET(end);
nkeynes@377
  1652
    }
nkeynes@377
  1653
:}
nkeynes@377
  1654
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1655
    check_fpuen();
nkeynes@377
  1656
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1657
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1658
    JNE_rel8(8, end);
nkeynes@377
  1659
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1660
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1661
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1662
    JMP_TARGET(end);
nkeynes@377
  1663
:}
nkeynes@377
  1664
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1665
    check_fpuen();
nkeynes@377
  1666
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1667
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1668
    JNE_rel8(11, end);
nkeynes@377
  1669
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1670
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1671
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1672
    JMP_TARGET(end);
nkeynes@377
  1673
:}
nkeynes@377
  1674
nkeynes@377
  1675
FLOAT FPUL, FRn {:  
nkeynes@377
  1676
    check_fpuen();
nkeynes@377
  1677
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1678
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1679
    FILD_sh4r(R_FPUL);
nkeynes@377
  1680
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1681
    JNE_rel8(5, doubleprec);
nkeynes@377
  1682
    pop_fr( R_EDX, FRn );
nkeynes@380
  1683
    JMP_rel8(3, end);
nkeynes@380
  1684
    JMP_TARGET(doubleprec);
nkeynes@377
  1685
    pop_dr( R_EDX, FRn );
nkeynes@380
  1686
    JMP_TARGET(end);
nkeynes@377
  1687
:}
nkeynes@377
  1688
FTRC FRm, FPUL {:  
nkeynes@377
  1689
    check_fpuen();
nkeynes@377
  1690
    // TODO
nkeynes@377
  1691
:}
nkeynes@377
  1692
FLDS FRm, FPUL {:  
nkeynes@377
  1693
    check_fpuen();
nkeynes@377
  1694
    load_fr_bank( R_ECX );
nkeynes@377
  1695
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1696
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1697
:}
nkeynes@377
  1698
FSTS FPUL, FRn {:  
nkeynes@377
  1699
    check_fpuen();
nkeynes@377
  1700
    load_fr_bank( R_ECX );
nkeynes@377
  1701
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1702
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1703
:}
nkeynes@377
  1704
FCNVDS FRm, FPUL {:  
nkeynes@377
  1705
    check_fpuen();
nkeynes@377
  1706
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1707
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1708
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1709
    load_fr_bank( R_ECX );
nkeynes@377
  1710
    push_dr( R_ECX, FRm );
nkeynes@377
  1711
    pop_fpul();
nkeynes@380
  1712
    JMP_TARGET(end);
nkeynes@377
  1713
:}
nkeynes@377
  1714
FCNVSD FPUL, FRn {:  
nkeynes@377
  1715
    check_fpuen();
nkeynes@377
  1716
    check_fpuen();
nkeynes@377
  1717
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1718
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1719
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1720
    load_fr_bank( R_ECX );
nkeynes@377
  1721
    push_fpul();
nkeynes@377
  1722
    pop_dr( R_ECX, FRn );
nkeynes@380
  1723
    JMP_TARGET(end);
nkeynes@377
  1724
:}
nkeynes@375
  1725
nkeynes@359
  1726
/* Floating point instructions */
nkeynes@374
  1727
FABS FRn {:  
nkeynes@377
  1728
    check_fpuen();
nkeynes@374
  1729
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1730
    load_fr_bank( R_EDX );
nkeynes@374
  1731
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1732
    JNE_rel8(10, doubleprec);
nkeynes@374
  1733
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1734
    FABS_st0(); // 2
nkeynes@374
  1735
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1736
    JMP_rel8(8,end); // 2
nkeynes@380
  1737
    JMP_TARGET(doubleprec);
nkeynes@374
  1738
    push_dr(R_EDX, FRn);
nkeynes@374
  1739
    FABS_st0();
nkeynes@374
  1740
    pop_dr(R_EDX, FRn);
nkeynes@380
  1741
    JMP_TARGET(end);
nkeynes@374
  1742
:}
nkeynes@377
  1743
FADD FRm, FRn {:  
nkeynes@377
  1744
    check_fpuen();
nkeynes@375
  1745
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1746
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1747
    load_fr_bank( R_EDX );
nkeynes@380
  1748
    JNE_rel8(13,doubleprec);
nkeynes@377
  1749
    push_fr(R_EDX, FRm);
nkeynes@377
  1750
    push_fr(R_EDX, FRn);
nkeynes@377
  1751
    FADDP_st(1);
nkeynes@377
  1752
    pop_fr(R_EDX, FRn);
nkeynes@380
  1753
    JMP_rel8(11,end);
nkeynes@380
  1754
    JMP_TARGET(doubleprec);
nkeynes@377
  1755
    push_dr(R_EDX, FRm);
nkeynes@377
  1756
    push_dr(R_EDX, FRn);
nkeynes@377
  1757
    FADDP_st(1);
nkeynes@377
  1758
    pop_dr(R_EDX, FRn);
nkeynes@380
  1759
    JMP_TARGET(end);
nkeynes@375
  1760
:}
nkeynes@377
  1761
FDIV FRm, FRn {:  
nkeynes@377
  1762
    check_fpuen();
nkeynes@375
  1763
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1764
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1765
    load_fr_bank( R_EDX );
nkeynes@380
  1766
    JNE_rel8(13, doubleprec);
nkeynes@377
  1767
    push_fr(R_EDX, FRn);
nkeynes@377
  1768
    push_fr(R_EDX, FRm);
nkeynes@377
  1769
    FDIVP_st(1);
nkeynes@377
  1770
    pop_fr(R_EDX, FRn);
nkeynes@380
  1771
    JMP_rel8(11, end);
nkeynes@380
  1772
    JMP_TARGET(doubleprec);
nkeynes@377
  1773
    push_dr(R_EDX, FRn);
nkeynes@377
  1774
    push_dr(R_EDX, FRm);
nkeynes@377
  1775
    FDIVP_st(1);
nkeynes@377
  1776
    pop_dr(R_EDX, FRn);
nkeynes@380
  1777
    JMP_TARGET(end);
nkeynes@375
  1778
:}
nkeynes@375
  1779
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1780
    check_fpuen();
nkeynes@375
  1781
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1782
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1783
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1784
    JNE_rel8(18, doubleprec);
nkeynes@375
  1785
    push_fr( R_EDX, 0 );
nkeynes@375
  1786
    push_fr( R_EDX, FRm );
nkeynes@375
  1787
    FMULP_st(1);
nkeynes@375
  1788
    push_fr( R_EDX, FRn );
nkeynes@375
  1789
    FADDP_st(1);
nkeynes@375
  1790
    pop_fr( R_EDX, FRn );
nkeynes@380
  1791
    JMP_rel8(16, end);
nkeynes@380
  1792
    JMP_TARGET(doubleprec);
nkeynes@375
  1793
    push_dr( R_EDX, 0 );
nkeynes@375
  1794
    push_dr( R_EDX, FRm );
nkeynes@375
  1795
    FMULP_st(1);
nkeynes@375
  1796
    push_dr( R_EDX, FRn );
nkeynes@375
  1797
    FADDP_st(1);
nkeynes@375
  1798
    pop_dr( R_EDX, FRn );
nkeynes@380
  1799
    JMP_TARGET(end);
nkeynes@375
  1800
:}
nkeynes@375
  1801
nkeynes@377
  1802
FMUL FRm, FRn {:  
nkeynes@377
  1803
    check_fpuen();
nkeynes@377
  1804
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1805
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1806
    load_fr_bank( R_EDX );
nkeynes@380
  1807
    JNE_rel8(13, doubleprec);
nkeynes@377
  1808
    push_fr(R_EDX, FRm);
nkeynes@377
  1809
    push_fr(R_EDX, FRn);
nkeynes@377
  1810
    FMULP_st(1);
nkeynes@377
  1811
    pop_fr(R_EDX, FRn);
nkeynes@380
  1812
    JMP_rel8(11, end);
nkeynes@380
  1813
    JMP_TARGET(doubleprec);
nkeynes@377
  1814
    push_dr(R_EDX, FRm);
nkeynes@377
  1815
    push_dr(R_EDX, FRn);
nkeynes@377
  1816
    FMULP_st(1);
nkeynes@377
  1817
    pop_dr(R_EDX, FRn);
nkeynes@380
  1818
    JMP_TARGET(end);
nkeynes@377
  1819
:}
nkeynes@377
  1820
FNEG FRn {:  
nkeynes@377
  1821
    check_fpuen();
nkeynes@377
  1822
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1823
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1824
    load_fr_bank( R_EDX );
nkeynes@380
  1825
    JNE_rel8(10, doubleprec);
nkeynes@377
  1826
    push_fr(R_EDX, FRn);
nkeynes@377
  1827
    FCHS_st0();
nkeynes@377
  1828
    pop_fr(R_EDX, FRn);
nkeynes@380
  1829
    JMP_rel8(8, end);
nkeynes@380
  1830
    JMP_TARGET(doubleprec);
nkeynes@377
  1831
    push_dr(R_EDX, FRn);
nkeynes@377
  1832
    FCHS_st0();
nkeynes@377
  1833
    pop_dr(R_EDX, FRn);
nkeynes@380
  1834
    JMP_TARGET(end);
nkeynes@377
  1835
:}
nkeynes@377
  1836
FSRRA FRn {:  
nkeynes@377
  1837
    check_fpuen();
nkeynes@377
  1838
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1839
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1840
    load_fr_bank( R_EDX );
nkeynes@380
  1841
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1842
    FLD1_st0();
nkeynes@377
  1843
    push_fr(R_EDX, FRn);
nkeynes@377
  1844
    FSQRT_st0();
nkeynes@377
  1845
    FDIVP_st(1);
nkeynes@377
  1846
    pop_fr(R_EDX, FRn);
nkeynes@380
  1847
    JMP_TARGET(end);
nkeynes@377
  1848
:}
nkeynes@377
  1849
FSQRT FRn {:  
nkeynes@377
  1850
    check_fpuen();
nkeynes@377
  1851
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1852
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1853
    load_fr_bank( R_EDX );
nkeynes@380
  1854
    JNE_rel8(10, doubleprec);
nkeynes@377
  1855
    push_fr(R_EDX, FRn);
nkeynes@377
  1856
    FSQRT_st0();
nkeynes@377
  1857
    pop_fr(R_EDX, FRn);
nkeynes@380
  1858
    JMP_rel8(8, end);
nkeynes@380
  1859
    JMP_TARGET(doubleprec);
nkeynes@377
  1860
    push_dr(R_EDX, FRn);
nkeynes@377
  1861
    FSQRT_st0();
nkeynes@377
  1862
    pop_dr(R_EDX, FRn);
nkeynes@380
  1863
    JMP_TARGET(end);
nkeynes@377
  1864
:}
nkeynes@377
  1865
FSUB FRm, FRn {:  
nkeynes@377
  1866
    check_fpuen();
nkeynes@377
  1867
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1868
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1869
    load_fr_bank( R_EDX );
nkeynes@380
  1870
    JNE_rel8(13, doubleprec);
nkeynes@377
  1871
    push_fr(R_EDX, FRn);
nkeynes@377
  1872
    push_fr(R_EDX, FRm);
nkeynes@377
  1873
    FMULP_st(1);
nkeynes@377
  1874
    pop_fr(R_EDX, FRn);
nkeynes@380
  1875
    JMP_rel8(11, end);
nkeynes@380
  1876
    JMP_TARGET(doubleprec);
nkeynes@377
  1877
    push_dr(R_EDX, FRn);
nkeynes@377
  1878
    push_dr(R_EDX, FRm);
nkeynes@377
  1879
    FMULP_st(1);
nkeynes@377
  1880
    pop_dr(R_EDX, FRn);
nkeynes@380
  1881
    JMP_TARGET(end);
nkeynes@377
  1882
:}
nkeynes@377
  1883
nkeynes@377
  1884
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1885
    check_fpuen();
nkeynes@377
  1886
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1887
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1888
    load_fr_bank( R_EDX );
nkeynes@380
  1889
    JNE_rel8(8, doubleprec);
nkeynes@377
  1890
    push_fr(R_EDX, FRm);
nkeynes@377
  1891
    push_fr(R_EDX, FRn);
nkeynes@380
  1892
    JMP_rel8(6, end);
nkeynes@380
  1893
    JMP_TARGET(doubleprec);
nkeynes@377
  1894
    push_dr(R_EDX, FRm);
nkeynes@377
  1895
    push_dr(R_EDX, FRn);
nkeynes@382
  1896
    JMP_TARGET(end);
nkeynes@377
  1897
    FCOMIP_st(1);
nkeynes@377
  1898
    SETE_t();
nkeynes@377
  1899
    FPOP_st();
nkeynes@377
  1900
:}
nkeynes@377
  1901
FCMP/GT FRm, FRn {:  
nkeynes@377
  1902
    check_fpuen();
nkeynes@377
  1903
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1904
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1905
    load_fr_bank( R_EDX );
nkeynes@380
  1906
    JNE_rel8(8, doubleprec);
nkeynes@377
  1907
    push_fr(R_EDX, FRm);
nkeynes@377
  1908
    push_fr(R_EDX, FRn);
nkeynes@380
  1909
    JMP_rel8(6, end);
nkeynes@380
  1910
    JMP_TARGET(doubleprec);
nkeynes@377
  1911
    push_dr(R_EDX, FRm);
nkeynes@377
  1912
    push_dr(R_EDX, FRn);
nkeynes@380
  1913
    JMP_TARGET(end);
nkeynes@377
  1914
    FCOMIP_st(1);
nkeynes@377
  1915
    SETA_t();
nkeynes@377
  1916
    FPOP_st();
nkeynes@377
  1917
:}
nkeynes@377
  1918
nkeynes@377
  1919
FSCA FPUL, FRn {:  
nkeynes@377
  1920
    check_fpuen();
nkeynes@377
  1921
:}
nkeynes@377
  1922
FIPR FVm, FVn {:  
nkeynes@377
  1923
    check_fpuen();
nkeynes@377
  1924
:}
nkeynes@377
  1925
FTRV XMTRX, FVn {:  
nkeynes@377
  1926
    check_fpuen();
nkeynes@377
  1927
:}
nkeynes@377
  1928
nkeynes@377
  1929
FRCHG {:  
nkeynes@377
  1930
    check_fpuen();
nkeynes@377
  1931
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1932
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  1933
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  1934
    update_fr_bank( R_ECX );
nkeynes@377
  1935
:}
nkeynes@377
  1936
FSCHG {:  
nkeynes@377
  1937
    check_fpuen();
nkeynes@377
  1938
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1939
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1940
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1941
:}
nkeynes@359
  1942
nkeynes@359
  1943
/* Processor control instructions */
nkeynes@368
  1944
LDC Rm, SR {:
nkeynes@386
  1945
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1946
	SLOTILLEGAL();
nkeynes@386
  1947
    } else {
nkeynes@386
  1948
	check_priv();
nkeynes@386
  1949
	load_reg( R_EAX, Rm );
nkeynes@386
  1950
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1951
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1952
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  1953
    }
nkeynes@368
  1954
:}
nkeynes@359
  1955
LDC Rm, GBR {: 
nkeynes@359
  1956
    load_reg( R_EAX, Rm );
nkeynes@359
  1957
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1958
:}
nkeynes@359
  1959
LDC Rm, VBR {:  
nkeynes@386
  1960
    check_priv();
nkeynes@359
  1961
    load_reg( R_EAX, Rm );
nkeynes@359
  1962
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1963
:}
nkeynes@359
  1964
LDC Rm, SSR {:  
nkeynes@386
  1965
    check_priv();
nkeynes@359
  1966
    load_reg( R_EAX, Rm );
nkeynes@359
  1967
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1968
:}
nkeynes@359
  1969
LDC Rm, SGR {:  
nkeynes@386
  1970
    check_priv();
nkeynes@359
  1971
    load_reg( R_EAX, Rm );
nkeynes@359
  1972
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1973
:}
nkeynes@359
  1974
LDC Rm, SPC {:  
nkeynes@386
  1975
    check_priv();
nkeynes@359
  1976
    load_reg( R_EAX, Rm );
nkeynes@359
  1977
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1978
:}
nkeynes@359
  1979
LDC Rm, DBR {:  
nkeynes@386
  1980
    check_priv();
nkeynes@359
  1981
    load_reg( R_EAX, Rm );
nkeynes@359
  1982
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1983
:}
nkeynes@374
  1984
LDC Rm, Rn_BANK {:  
nkeynes@386
  1985
    check_priv();
nkeynes@374
  1986
    load_reg( R_EAX, Rm );
nkeynes@374
  1987
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  1988
:}
nkeynes@359
  1989
LDC.L @Rm+, GBR {:  
nkeynes@359
  1990
    load_reg( R_EAX, Rm );
nkeynes@359
  1991
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1992
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1993
    store_reg( R_EAX, Rm );
nkeynes@359
  1994
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1995
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1996
:}
nkeynes@368
  1997
LDC.L @Rm+, SR {:
nkeynes@386
  1998
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1999
	SLOTILLEGAL();
nkeynes@386
  2000
    } else {
nkeynes@386
  2001
	check_priv();
nkeynes@386
  2002
	load_reg( R_EAX, Rm );
nkeynes@386
  2003
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2004
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2005
	store_reg( R_EAX, Rm );
nkeynes@386
  2006
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2007
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2008
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2009
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2010
    }
nkeynes@359
  2011
:}
nkeynes@359
  2012
LDC.L @Rm+, VBR {:  
nkeynes@386
  2013
    check_priv();
nkeynes@359
  2014
    load_reg( R_EAX, Rm );
nkeynes@359
  2015
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2016
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2017
    store_reg( R_EAX, Rm );
nkeynes@359
  2018
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2019
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2020
:}
nkeynes@359
  2021
LDC.L @Rm+, SSR {:
nkeynes@386
  2022
    check_priv();
nkeynes@359
  2023
    load_reg( R_EAX, Rm );
nkeynes@359
  2024
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2025
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2026
    store_reg( R_EAX, Rm );
nkeynes@359
  2027
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2028
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2029
:}
nkeynes@359
  2030
LDC.L @Rm+, SGR {:  
nkeynes@386
  2031
    check_priv();
nkeynes@359
  2032
    load_reg( R_EAX, Rm );
nkeynes@359
  2033
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2034
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2035
    store_reg( R_EAX, Rm );
nkeynes@359
  2036
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2037
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2038
:}
nkeynes@359
  2039
LDC.L @Rm+, SPC {:  
nkeynes@386
  2040
    check_priv();
nkeynes@359
  2041
    load_reg( R_EAX, Rm );
nkeynes@359
  2042
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2043
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2044
    store_reg( R_EAX, Rm );
nkeynes@359
  2045
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2046
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2047
:}
nkeynes@359
  2048
LDC.L @Rm+, DBR {:  
nkeynes@386
  2049
    check_priv();
nkeynes@359
  2050
    load_reg( R_EAX, Rm );
nkeynes@359
  2051
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2052
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2053
    store_reg( R_EAX, Rm );
nkeynes@359
  2054
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2055
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2056
:}
nkeynes@359
  2057
LDC.L @Rm+, Rn_BANK {:  
nkeynes@386
  2058
    check_priv();
nkeynes@374
  2059
    load_reg( R_EAX, Rm );
nkeynes@374
  2060
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2061
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2062
    store_reg( R_EAX, Rm );
nkeynes@374
  2063
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2064
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  2065
:}
nkeynes@359
  2066
LDS Rm, FPSCR {:  
nkeynes@359
  2067
    load_reg( R_EAX, Rm );
nkeynes@359
  2068
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2069
    update_fr_bank( R_EAX );
nkeynes@359
  2070
:}
nkeynes@359
  2071
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2072
    load_reg( R_EAX, Rm );
nkeynes@359
  2073
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2074
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2075
    store_reg( R_EAX, Rm );
nkeynes@359
  2076
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2077
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2078
    update_fr_bank( R_EAX );
nkeynes@359
  2079
:}
nkeynes@359
  2080
LDS Rm, FPUL {:  
nkeynes@359
  2081
    load_reg( R_EAX, Rm );
nkeynes@359
  2082
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2083
:}
nkeynes@359
  2084
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2085
    load_reg( R_EAX, Rm );
nkeynes@359
  2086
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2087
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2088
    store_reg( R_EAX, Rm );
nkeynes@359
  2089
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2090
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2091
:}
nkeynes@359
  2092
LDS Rm, MACH {: 
nkeynes@359
  2093
    load_reg( R_EAX, Rm );
nkeynes@359
  2094
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2095
:}
nkeynes@359
  2096
LDS.L @Rm+, MACH {:  
nkeynes@359
  2097
    load_reg( R_EAX, Rm );
nkeynes@359
  2098
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2099
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2100
    store_reg( R_EAX, Rm );
nkeynes@359
  2101
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2102
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2103
:}
nkeynes@359
  2104
LDS Rm, MACL {:  
nkeynes@359
  2105
    load_reg( R_EAX, Rm );
nkeynes@359
  2106
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2107
:}
nkeynes@359
  2108
LDS.L @Rm+, MACL {:  
nkeynes@359
  2109
    load_reg( R_EAX, Rm );
nkeynes@359
  2110
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2111
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2112
    store_reg( R_EAX, Rm );
nkeynes@359
  2113
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2114
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2115
:}
nkeynes@359
  2116
LDS Rm, PR {:  
nkeynes@359
  2117
    load_reg( R_EAX, Rm );
nkeynes@359
  2118
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2119
:}
nkeynes@359
  2120
LDS.L @Rm+, PR {:  
nkeynes@359
  2121
    load_reg( R_EAX, Rm );
nkeynes@359
  2122
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2123
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2124
    store_reg( R_EAX, Rm );
nkeynes@359
  2125
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2126
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2127
:}
nkeynes@359
  2128
LDTLB {:  :}
nkeynes@359
  2129
OCBI @Rn {:  :}
nkeynes@359
  2130
OCBP @Rn {:  :}
nkeynes@359
  2131
OCBWB @Rn {:  :}
nkeynes@374
  2132
PREF @Rn {:
nkeynes@374
  2133
    load_reg( R_EAX, Rn );
nkeynes@374
  2134
    PUSH_r32( R_EAX );
nkeynes@374
  2135
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2136
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2137
    JNE_rel8(7, end);
nkeynes@374
  2138
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2139
    JMP_TARGET(end);
nkeynes@377
  2140
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2141
:}
nkeynes@386
  2142
SLEEP {: /* TODO */ :}
nkeynes@386
  2143
STC SR, Rn {:
nkeynes@386
  2144
    check_priv();
nkeynes@386
  2145
    call_func0(sh4_read_sr);
nkeynes@386
  2146
    store_reg( R_EAX, Rn );
nkeynes@359
  2147
:}
nkeynes@359
  2148
STC GBR, Rn {:  
nkeynes@359
  2149
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2150
    store_reg( R_EAX, Rn );
nkeynes@359
  2151
:}
nkeynes@359
  2152
STC VBR, Rn {:  
nkeynes@386
  2153
    check_priv();
nkeynes@359
  2154
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2155
    store_reg( R_EAX, Rn );
nkeynes@359
  2156
:}
nkeynes@359
  2157
STC SSR, Rn {:  
nkeynes@386
  2158
    check_priv();
nkeynes@359
  2159
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2160
    store_reg( R_EAX, Rn );
nkeynes@359
  2161
:}
nkeynes@359
  2162
STC SPC, Rn {:  
nkeynes@386
  2163
    check_priv();
nkeynes@359
  2164
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2165
    store_reg( R_EAX, Rn );
nkeynes@359
  2166
:}
nkeynes@359
  2167
STC SGR, Rn {:  
nkeynes@386
  2168
    check_priv();
nkeynes@359
  2169
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2170
    store_reg( R_EAX, Rn );
nkeynes@359
  2171
:}
nkeynes@359
  2172
STC DBR, Rn {:  
nkeynes@386
  2173
    check_priv();
nkeynes@359
  2174
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2175
    store_reg( R_EAX, Rn );
nkeynes@359
  2176
:}
nkeynes@374
  2177
STC Rm_BANK, Rn {:
nkeynes@386
  2178
    check_priv();
nkeynes@374
  2179
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2180
    store_reg( R_EAX, Rn );
nkeynes@359
  2181
:}
nkeynes@374
  2182
STC.L SR, @-Rn {:
nkeynes@386
  2183
    check_priv();
nkeynes@368
  2184
    load_reg( R_ECX, Rn );
nkeynes@382
  2185
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2186
    store_reg( R_ECX, Rn );
nkeynes@374
  2187
    call_func0( sh4_read_sr );
nkeynes@368
  2188
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2189
:}
nkeynes@359
  2190
STC.L VBR, @-Rn {:  
nkeynes@386
  2191
    check_priv();
nkeynes@359
  2192
    load_reg( R_ECX, Rn );
nkeynes@382
  2193
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2194
    store_reg( R_ECX, Rn );
nkeynes@359
  2195
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2196
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2197
:}
nkeynes@359
  2198
STC.L SSR, @-Rn {:  
nkeynes@386
  2199
    check_priv();
nkeynes@359
  2200
    load_reg( R_ECX, Rn );
nkeynes@382
  2201
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2202
    store_reg( R_ECX, Rn );
nkeynes@359
  2203
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2204
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2205
:}
nkeynes@359
  2206
STC.L SPC, @-Rn {:  
nkeynes@386
  2207
    check_priv();
nkeynes@359
  2208
    load_reg( R_ECX, Rn );
nkeynes@382
  2209
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2210
    store_reg( R_ECX, Rn );
nkeynes@359
  2211
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2212
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2213
:}
nkeynes@359
  2214
STC.L SGR, @-Rn {:  
nkeynes@386
  2215
    check_priv();
nkeynes@359
  2216
    load_reg( R_ECX, Rn );
nkeynes@382
  2217
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2218
    store_reg( R_ECX, Rn );
nkeynes@359
  2219
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2220
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2221
:}
nkeynes@359
  2222
STC.L DBR, @-Rn {:  
nkeynes@386
  2223
    check_priv();
nkeynes@359
  2224
    load_reg( R_ECX, Rn );
nkeynes@382
  2225
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2226
    store_reg( R_ECX, Rn );
nkeynes@359
  2227
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2228
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2229
:}
nkeynes@374
  2230
STC.L Rm_BANK, @-Rn {:  
nkeynes@386
  2231
    check_priv();
nkeynes@374
  2232
    load_reg( R_ECX, Rn );
nkeynes@382
  2233
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2234
    store_reg( R_ECX, Rn );
nkeynes@374
  2235
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2236
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2237
:}
nkeynes@359
  2238
STC.L GBR, @-Rn {:  
nkeynes@359
  2239
    load_reg( R_ECX, Rn );
nkeynes@382
  2240
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2241
    store_reg( R_ECX, Rn );
nkeynes@359
  2242
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2243
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2244
:}
nkeynes@359
  2245
STS FPSCR, Rn {:  
nkeynes@359
  2246
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2247
    store_reg( R_EAX, Rn );
nkeynes@359
  2248
:}
nkeynes@359
  2249
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2250
    load_reg( R_ECX, Rn );
nkeynes@382
  2251
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2252
    store_reg( R_ECX, Rn );
nkeynes@359
  2253
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2254
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2255
:}
nkeynes@359
  2256
STS FPUL, Rn {:  
nkeynes@359
  2257
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2258
    store_reg( R_EAX, Rn );
nkeynes@359
  2259
:}
nkeynes@359
  2260
STS.L FPUL, @-Rn {:  
nkeynes@359
  2261
    load_reg( R_ECX, Rn );
nkeynes@382
  2262
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2263
    store_reg( R_ECX, Rn );
nkeynes@359
  2264
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2265
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2266
:}
nkeynes@359
  2267
STS MACH, Rn {:  
nkeynes@359
  2268
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2269
    store_reg( R_EAX, Rn );
nkeynes@359
  2270
:}
nkeynes@359
  2271
STS.L MACH, @-Rn {:  
nkeynes@359
  2272
    load_reg( R_ECX, Rn );
nkeynes@382
  2273
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2274
    store_reg( R_ECX, Rn );
nkeynes@359
  2275
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2276
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2277
:}
nkeynes@359
  2278
STS MACL, Rn {:  
nkeynes@359
  2279
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2280
    store_reg( R_EAX, Rn );
nkeynes@359
  2281
:}
nkeynes@359
  2282
STS.L MACL, @-Rn {:  
nkeynes@359
  2283
    load_reg( R_ECX, Rn );
nkeynes@382
  2284
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2285
    store_reg( R_ECX, Rn );
nkeynes@359
  2286
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2287
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2288
:}
nkeynes@359
  2289
STS PR, Rn {:  
nkeynes@359
  2290
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2291
    store_reg( R_EAX, Rn );
nkeynes@359
  2292
:}
nkeynes@359
  2293
STS.L PR, @-Rn {:  
nkeynes@359
  2294
    load_reg( R_ECX, Rn );
nkeynes@382
  2295
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2296
    store_reg( R_ECX, Rn );
nkeynes@359
  2297
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2298
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2299
:}
nkeynes@359
  2300
nkeynes@359
  2301
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2302
%%
nkeynes@374
  2303
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2304
	ADD_imm8s_r32(2,R_ESI);
nkeynes@374
  2305
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2306
	return 1;
nkeynes@386
  2307
    } else {
nkeynes@386
  2308
	INC_r32(R_ESI);
nkeynes@374
  2309
    }
nkeynes@359
  2310
    return 0;
nkeynes@359
  2311
}
.