nkeynes@378 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@378 | 3 | *
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nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral
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nkeynes@378 | 5 | * modules.
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nkeynes@378 | 6 | *
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nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@378 | 8 | *
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nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@378 | 12 | * (at your option) any later version.
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nkeynes@378 | 13 | *
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nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@378 | 17 | * GNU General Public License for more details.
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nkeynes@378 | 18 | */
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nkeynes@378 | 19 |
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nkeynes@378 | 20 | #define MODULE sh4_module
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nkeynes@378 | 21 | #include <math.h>
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nkeynes@740 | 22 | #include <setjmp.h>
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nkeynes@617 | 23 | #include <assert.h>
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nkeynes@671 | 24 | #include "lxdream.h"
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nkeynes@422 | 25 | #include "dreamcast.h"
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nkeynes@669 | 26 | #include "mem.h"
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nkeynes@669 | 27 | #include "clock.h"
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nkeynes@669 | 28 | #include "eventq.h"
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nkeynes@669 | 29 | #include "syscall.h"
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nkeynes@669 | 30 | #include "sh4/intc.h"
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nkeynes@968 | 31 | #include "sh4/mmu.h"
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nkeynes@378 | 32 | #include "sh4/sh4core.h"
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nkeynes@378 | 33 | #include "sh4/sh4mmio.h"
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nkeynes@422 | 34 | #include "sh4/sh4stat.h"
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nkeynes@617 | 35 | #include "sh4/sh4trans.h"
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nkeynes@669 | 36 | #include "sh4/xltcache.h"
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nkeynes@378 | 37 |
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nkeynes@378 | 38 | void sh4_init( void );
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nkeynes@526 | 39 | void sh4_xlat_init( void );
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nkeynes@953 | 40 | void sh4_poweron_reset( void );
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nkeynes@378 | 41 | void sh4_start( void );
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nkeynes@378 | 42 | void sh4_stop( void );
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nkeynes@378 | 43 | void sh4_save_state( FILE *f );
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nkeynes@378 | 44 | int sh4_load_state( FILE *f );
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nkeynes@378 | 45 |
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nkeynes@378 | 46 | uint32_t sh4_run_slice( uint32_t );
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nkeynes@378 | 47 | uint32_t sh4_xlat_run_slice( uint32_t );
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nkeynes@378 | 48 |
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nkeynes@953 | 49 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_poweron_reset,
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nkeynes@736 | 50 | sh4_start, sh4_run_slice, sh4_stop,
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nkeynes@736 | 51 | sh4_save_state, sh4_load_state };
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nkeynes@378 | 52 |
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nkeynes@903 | 53 | struct sh4_registers sh4r __attribute__((aligned(16)));
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nkeynes@378 | 54 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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nkeynes@378 | 55 | int sh4_breakpoint_count = 0;
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nkeynes@953 | 56 |
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nkeynes@591 | 57 | gboolean sh4_starting = FALSE;
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nkeynes@526 | 58 | static gboolean sh4_use_translator = FALSE;
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nkeynes@740 | 59 | static jmp_buf sh4_exit_jmp_buf;
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nkeynes@740 | 60 | static gboolean sh4_running = FALSE;
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nkeynes@586 | 61 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
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nkeynes@378 | 62 |
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nkeynes@740 | 63 | void sh4_translate_set_enabled( gboolean use )
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nkeynes@378 | 64 | {
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nkeynes@736 | 65 | // No-op if the translator was not built
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nkeynes@526 | 66 | #ifdef SH4_TRANSLATOR
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nkeynes@378 | 67 | if( use ) {
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nkeynes@736 | 68 | sh4_translate_init();
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nkeynes@378 | 69 | }
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nkeynes@526 | 70 | sh4_use_translator = use;
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nkeynes@526 | 71 | #endif
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nkeynes@378 | 72 | }
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nkeynes@378 | 73 |
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nkeynes@740 | 74 | gboolean sh4_translate_is_enabled()
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nkeynes@586 | 75 | {
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nkeynes@586 | 76 | return sh4_use_translator;
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nkeynes@586 | 77 | }
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nkeynes@586 | 78 |
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nkeynes@378 | 79 | void sh4_init(void)
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nkeynes@378 | 80 | {
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nkeynes@378 | 81 | register_io_regions( mmio_list_sh4mmio );
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nkeynes@378 | 82 | MMU_init();
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nkeynes@619 | 83 | TMU_init();
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nkeynes@953 | 84 | xlat_cache_init();
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nkeynes@953 | 85 | sh4_poweron_reset();
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nkeynes@671 | 86 | #ifdef ENABLE_SH4STATS
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nkeynes@671 | 87 | sh4_stats_reset();
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nkeynes@671 | 88 | #endif
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nkeynes@378 | 89 | }
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nkeynes@378 | 90 |
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nkeynes@591 | 91 | void sh4_start(void)
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nkeynes@591 | 92 | {
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nkeynes@591 | 93 | sh4_starting = TRUE;
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nkeynes@591 | 94 | }
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nkeynes@591 | 95 |
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nkeynes@953 | 96 | void sh4_poweron_reset(void)
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nkeynes@378 | 97 | {
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nkeynes@953 | 98 | /* zero everything out, for the sake of having a consistent state. */
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nkeynes@953 | 99 | memset( &sh4r, 0, sizeof(sh4r) );
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nkeynes@526 | 100 | if( sh4_use_translator ) {
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nkeynes@736 | 101 | xlat_flush_cache();
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nkeynes@472 | 102 | }
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nkeynes@472 | 103 |
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nkeynes@378 | 104 | /* Resume running if we were halted */
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nkeynes@378 | 105 | sh4r.sh4_state = SH4_STATE_RUNNING;
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nkeynes@378 | 106 |
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nkeynes@378 | 107 | sh4r.pc = 0xA0000000;
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nkeynes@378 | 108 | sh4r.new_pc= 0xA0000002;
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nkeynes@378 | 109 | sh4r.vbr = 0x00000000;
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nkeynes@378 | 110 | sh4r.fpscr = 0x00040001;
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nkeynes@953 | 111 | sh4_write_sr(0x700000F0);
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nkeynes@378 | 112 |
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nkeynes@378 | 113 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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nkeynes@378 | 114 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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nkeynes@378 | 115 |
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nkeynes@378 | 116 | /* Peripheral modules */
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nkeynes@378 | 117 | CPG_reset();
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nkeynes@378 | 118 | INTC_reset();
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nkeynes@841 | 119 | PMM_reset();
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nkeynes@378 | 120 | TMU_reset();
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nkeynes@378 | 121 | SCIF_reset();
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nkeynes@953 | 122 | MMU_reset();
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nkeynes@378 | 123 | }
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nkeynes@378 | 124 |
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nkeynes@378 | 125 | void sh4_stop(void)
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nkeynes@378 | 126 | {
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nkeynes@526 | 127 | if( sh4_use_translator ) {
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nkeynes@736 | 128 | /* If we were running with the translator, update new_pc and in_delay_slot */
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nkeynes@736 | 129 | sh4r.new_pc = sh4r.pc+2;
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nkeynes@736 | 130 | sh4r.in_delay_slot = FALSE;
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nkeynes@502 | 131 | }
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nkeynes@378 | 132 |
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nkeynes@378 | 133 | }
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nkeynes@378 | 134 |
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nkeynes@740 | 135 | /**
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nkeynes@740 | 136 | * Execute a timeslice using translated code only (ie translate/execute loop)
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nkeynes@740 | 137 | */
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nkeynes@740 | 138 | uint32_t sh4_run_slice( uint32_t nanosecs )
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nkeynes@740 | 139 | {
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nkeynes@740 | 140 | sh4r.slice_cycle = 0;
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nkeynes@740 | 141 |
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nkeynes@740 | 142 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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nkeynes@740 | 143 | sh4_sleep_run_slice(nanosecs);
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nkeynes@740 | 144 | }
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nkeynes@740 | 145 |
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nkeynes@740 | 146 | /* Setup for sudden vm exits */
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nkeynes@740 | 147 | switch( setjmp(sh4_exit_jmp_buf) ) {
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nkeynes@740 | 148 | case CORE_EXIT_BREAKPOINT:
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nkeynes@740 | 149 | sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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nkeynes@740 | 150 | /* fallthrough */
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nkeynes@740 | 151 | case CORE_EXIT_HALT:
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nkeynes@740 | 152 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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nkeynes@740 | 153 | TMU_run_slice( sh4r.slice_cycle );
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nkeynes@740 | 154 | SCIF_run_slice( sh4r.slice_cycle );
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nkeynes@841 | 155 | PMM_run_slice( sh4r.slice_cycle );
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nkeynes@740 | 156 | dreamcast_stop();
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nkeynes@740 | 157 | return sh4r.slice_cycle;
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nkeynes@740 | 158 | }
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nkeynes@740 | 159 | case CORE_EXIT_SYSRESET:
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nkeynes@740 | 160 | dreamcast_reset();
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nkeynes@740 | 161 | break;
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nkeynes@740 | 162 | case CORE_EXIT_SLEEP:
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nkeynes@740 | 163 | sh4_sleep_run_slice(nanosecs);
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nkeynes@740 | 164 | break;
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nkeynes@740 | 165 | case CORE_EXIT_FLUSH_ICACHE:
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nkeynes@740 | 166 | xlat_flush_cache();
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nkeynes@740 | 167 | break;
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nkeynes@740 | 168 | }
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nkeynes@740 | 169 |
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nkeynes@740 | 170 | sh4_running = TRUE;
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nkeynes@740 | 171 |
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nkeynes@740 | 172 | /* Execute the core's real slice */
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nkeynes@740 | 173 | #ifdef SH4_TRANSLATOR
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nkeynes@740 | 174 | if( sh4_use_translator ) {
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nkeynes@740 | 175 | sh4_translate_run_slice(nanosecs);
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nkeynes@740 | 176 | } else {
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nkeynes@740 | 177 | sh4_emulate_run_slice(nanosecs);
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nkeynes@740 | 178 | }
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nkeynes@740 | 179 | #else
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nkeynes@740 | 180 | sh4_emulate_run_slice(nanosecs);
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nkeynes@740 | 181 | #endif
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nkeynes@740 | 182 |
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nkeynes@740 | 183 | /* And finish off the peripherals afterwards */
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nkeynes@740 | 184 |
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nkeynes@740 | 185 | sh4_running = FALSE;
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nkeynes@740 | 186 | sh4_starting = FALSE;
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nkeynes@740 | 187 | sh4r.slice_cycle = nanosecs;
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nkeynes@740 | 188 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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nkeynes@740 | 189 | TMU_run_slice( nanosecs );
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nkeynes@740 | 190 | SCIF_run_slice( nanosecs );
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nkeynes@841 | 191 | PMM_run_slice( sh4r.slice_cycle );
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nkeynes@740 | 192 | }
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nkeynes@740 | 193 | return nanosecs;
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nkeynes@740 | 194 | }
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nkeynes@740 | 195 |
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nkeynes@740 | 196 | void sh4_core_exit( int exit_code )
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nkeynes@740 | 197 | {
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nkeynes@740 | 198 | if( sh4_running ) {
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nkeynes@740 | 199 | #ifdef SH4_TRANSLATOR
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nkeynes@740 | 200 | if( sh4_use_translator ) {
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nkeynes@953 | 201 | if( exit_code == CORE_EXIT_EXCEPTION ) {
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nkeynes@953 | 202 | sh4_translate_exception_exit_recover();
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nkeynes@953 | 203 | } else {
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nkeynes@953 | 204 | sh4_translate_exit_recover();
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nkeynes@953 | 205 | }
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nkeynes@740 | 206 | }
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nkeynes@740 | 207 | #endif
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nkeynes@953 | 208 | if( exit_code != CORE_EXIT_EXCEPTION ) {
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nkeynes@953 | 209 | sh4_finalize_instruction();
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nkeynes@953 | 210 | }
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nkeynes@740 | 211 | // longjmp back into sh4_run_slice
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nkeynes@740 | 212 | sh4_running = FALSE;
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nkeynes@740 | 213 | longjmp(sh4_exit_jmp_buf, exit_code);
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nkeynes@740 | 214 | }
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nkeynes@740 | 215 | }
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nkeynes@740 | 216 |
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nkeynes@378 | 217 | void sh4_save_state( FILE *f )
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nkeynes@378 | 218 | {
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nkeynes@526 | 219 | if( sh4_use_translator ) {
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nkeynes@736 | 220 | /* If we were running with the translator, update new_pc and in_delay_slot */
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nkeynes@736 | 221 | sh4r.new_pc = sh4r.pc+2;
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nkeynes@736 | 222 | sh4r.in_delay_slot = FALSE;
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nkeynes@401 | 223 | }
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nkeynes@401 | 224 |
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nkeynes@953 | 225 | fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
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nkeynes@378 | 226 | MMU_save_state( f );
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nkeynes@953 | 227 | CCN_save_state( f );
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nkeynes@841 | 228 | PMM_save_state( f );
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nkeynes@378 | 229 | INTC_save_state( f );
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nkeynes@378 | 230 | TMU_save_state( f );
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nkeynes@378 | 231 | SCIF_save_state( f );
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nkeynes@378 | 232 | }
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nkeynes@378 | 233 |
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nkeynes@378 | 234 | int sh4_load_state( FILE * f )
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nkeynes@378 | 235 | {
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nkeynes@526 | 236 | if( sh4_use_translator ) {
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nkeynes@736 | 237 | xlat_flush_cache();
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nkeynes@472 | 238 | }
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nkeynes@953 | 239 | fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
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nkeynes@953 | 240 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
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nkeynes@378 | 241 | MMU_load_state( f );
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nkeynes@953 | 242 | CCN_load_state( f );
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nkeynes@841 | 243 | PMM_load_state( f );
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nkeynes@378 | 244 | INTC_load_state( f );
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nkeynes@378 | 245 | TMU_load_state( f );
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nkeynes@378 | 246 | return SCIF_load_state( f );
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nkeynes@378 | 247 | }
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nkeynes@378 | 248 |
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nkeynes@586 | 249 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
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nkeynes@378 | 250 | {
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nkeynes@378 | 251 | sh4_breakpoints[sh4_breakpoint_count].address = pc;
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nkeynes@378 | 252 | sh4_breakpoints[sh4_breakpoint_count].type = type;
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nkeynes@586 | 253 | if( sh4_use_translator ) {
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nkeynes@736 | 254 | xlat_invalidate_word( pc );
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nkeynes@586 | 255 | }
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nkeynes@378 | 256 | sh4_breakpoint_count++;
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nkeynes@378 | 257 | }
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nkeynes@378 | 258 |
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nkeynes@586 | 259 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
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nkeynes@378 | 260 | {
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nkeynes@378 | 261 | int i;
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nkeynes@378 | 262 |
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nkeynes@378 | 263 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@736 | 264 | if( sh4_breakpoints[i].address == pc &&
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nkeynes@736 | 265 | sh4_breakpoints[i].type == type ) {
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nkeynes@736 | 266 | while( ++i < sh4_breakpoint_count ) {
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nkeynes@736 | 267 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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nkeynes@736 | 268 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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nkeynes@736 | 269 | }
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nkeynes@736 | 270 | if( sh4_use_translator ) {
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nkeynes@736 | 271 | xlat_invalidate_word( pc );
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nkeynes@736 | 272 | }
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nkeynes@736 | 273 | sh4_breakpoint_count--;
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nkeynes@736 | 274 | return TRUE;
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nkeynes@736 | 275 | }
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nkeynes@378 | 276 | }
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nkeynes@378 | 277 | return FALSE;
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nkeynes@378 | 278 | }
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nkeynes@378 | 279 |
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nkeynes@378 | 280 | int sh4_get_breakpoint( uint32_t pc )
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nkeynes@378 | 281 | {
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nkeynes@378 | 282 | int i;
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nkeynes@378 | 283 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@736 | 284 | if( sh4_breakpoints[i].address == pc )
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nkeynes@736 | 285 | return sh4_breakpoints[i].type;
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nkeynes@378 | 286 | }
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nkeynes@378 | 287 | return 0;
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nkeynes@378 | 288 | }
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nkeynes@378 | 289 |
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nkeynes@401 | 290 | void sh4_set_pc( int pc )
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nkeynes@401 | 291 | {
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nkeynes@401 | 292 | sh4r.pc = pc;
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nkeynes@401 | 293 | sh4r.new_pc = pc+2;
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nkeynes@401 | 294 | }
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nkeynes@401 | 295 |
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nkeynes@401 | 296 |
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nkeynes@401 | 297 | /******************************* Support methods ***************************/
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nkeynes@401 | 298 |
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nkeynes@401 | 299 | static void sh4_switch_banks( )
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nkeynes@401 | 300 | {
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nkeynes@401 | 301 | uint32_t tmp[8];
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nkeynes@401 | 302 |
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nkeynes@401 | 303 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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nkeynes@401 | 304 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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nkeynes@401 | 305 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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nkeynes@401 | 306 | }
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nkeynes@401 | 307 |
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nkeynes@905 | 308 | void FASTCALL sh4_switch_fr_banks()
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nkeynes@669 | 309 | {
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nkeynes@669 | 310 | int i;
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nkeynes@669 | 311 | for( i=0; i<16; i++ ) {
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nkeynes@736 | 312 | float tmp = sh4r.fr[0][i];
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nkeynes@736 | 313 | sh4r.fr[0][i] = sh4r.fr[1][i];
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nkeynes@736 | 314 | sh4r.fr[1][i] = tmp;
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nkeynes@669 | 315 | }
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nkeynes@669 | 316 | }
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nkeynes@669 | 317 |
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nkeynes@905 | 318 | void FASTCALL sh4_write_sr( uint32_t newval )
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nkeynes@401 | 319 | {
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nkeynes@586 | 320 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
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nkeynes@586 | 321 | int newbank = (newval&SR_MDRB) == SR_MDRB;
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nkeynes@586 | 322 | if( oldbank != newbank )
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nkeynes@401 | 323 | sh4_switch_banks();
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nkeynes@822 | 324 | sh4r.sr = newval & SR_MASK;
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nkeynes@401 | 325 | sh4r.t = (newval&SR_T) ? 1 : 0;
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nkeynes@401 | 326 | sh4r.s = (newval&SR_S) ? 1 : 0;
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nkeynes@401 | 327 | sh4r.m = (newval&SR_M) ? 1 : 0;
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nkeynes@401 | 328 | sh4r.q = (newval&SR_Q) ? 1 : 0;
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nkeynes@953 | 329 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
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nkeynes@401 | 330 | intc_mask_changed();
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nkeynes@401 | 331 | }
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nkeynes@401 | 332 |
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nkeynes@905 | 333 | void FASTCALL sh4_write_fpscr( uint32_t newval )
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nkeynes@669 | 334 | {
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nkeynes@669 | 335 | if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
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nkeynes@736 | 336 | sh4_switch_fr_banks();
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nkeynes@669 | 337 | }
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nkeynes@823 | 338 | sh4r.fpscr = newval & FPSCR_MASK;
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nkeynes@953 | 339 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
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nkeynes@669 | 340 | }
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nkeynes@669 | 341 |
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nkeynes@905 | 342 | uint32_t FASTCALL sh4_read_sr( void )
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nkeynes@401 | 343 | {
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nkeynes@401 | 344 | /* synchronize sh4r.sr with the various bitflags */
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nkeynes@401 | 345 | sh4r.sr &= SR_MQSTMASK;
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nkeynes@401 | 346 | if( sh4r.t ) sh4r.sr |= SR_T;
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nkeynes@401 | 347 | if( sh4r.s ) sh4r.sr |= SR_S;
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nkeynes@401 | 348 | if( sh4r.m ) sh4r.sr |= SR_M;
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nkeynes@401 | 349 | if( sh4r.q ) sh4r.sr |= SR_Q;
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nkeynes@401 | 350 | return sh4r.sr;
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nkeynes@401 | 351 | }
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nkeynes@401 | 352 |
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nkeynes@953 | 353 | /**
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nkeynes@953 | 354 | * Raise a CPU reset exception with the specified exception code.
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nkeynes@953 | 355 | */
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nkeynes@953 | 356 | void FASTCALL sh4_raise_reset( int code )
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nkeynes@953 | 357 | {
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nkeynes@953 | 358 | MMIO_WRITE(MMU,EXPEVT,code);
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nkeynes@953 | 359 | sh4r.vbr = 0x00000000;
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nkeynes@953 | 360 | sh4r.pc = 0xA0000000;
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nkeynes@953 | 361 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@953 | 362 | sh4r.in_delay_slot = 0;
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nkeynes@953 | 363 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)&(~SR_FD) );
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nkeynes@953 | 364 |
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nkeynes@953 | 365 | /* Peripheral manual reset (FIXME: incomplete) */
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nkeynes@953 | 366 | INTC_reset();
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nkeynes@953 | 367 | SCIF_reset();
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nkeynes@953 | 368 | MMU_reset();
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nkeynes@953 | 369 | }
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nkeynes@401 | 370 |
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nkeynes@953 | 371 | void FASTCALL sh4_raise_tlb_multihit( sh4vma_t vpn )
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nkeynes@953 | 372 | {
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nkeynes@953 | 373 | MMIO_WRITE( MMU, TEA, vpn );
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nkeynes@953 | 374 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
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nkeynes@953 | 375 | sh4_raise_reset( EXC_TLB_MULTI_HIT );
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nkeynes@953 | 376 | }
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nkeynes@401 | 377 |
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nkeynes@401 | 378 | /**
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nkeynes@401 | 379 | * Raise a general CPU exception for the specified exception code.
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nkeynes@401 | 380 | * (NOT for TRAPA or TLB exceptions)
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nkeynes@401 | 381 | */
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nkeynes@953 | 382 | void FASTCALL sh4_raise_exception( int code )
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nkeynes@401 | 383 | {
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nkeynes@953 | 384 | if( sh4r.sr & SR_BL ) {
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nkeynes@953 | 385 | sh4_raise_reset( EXC_MANUAL_RESET );
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nkeynes@401 | 386 | } else {
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nkeynes@953 | 387 | sh4r.spc = sh4r.pc;
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nkeynes@953 | 388 | sh4r.ssr = sh4_read_sr();
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nkeynes@953 | 389 | sh4r.sgr = sh4r.r[15];
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nkeynes@953 | 390 | MMIO_WRITE(MMU,EXPEVT, code);
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nkeynes@953 | 391 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
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nkeynes@953 | 392 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@953 | 393 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
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nkeynes@953 | 394 | sh4r.in_delay_slot = 0;
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nkeynes@401 | 395 | }
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nkeynes@401 | 396 | }
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nkeynes@401 | 397 |
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nkeynes@953 | 398 | void FASTCALL sh4_raise_trap( int trap )
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nkeynes@401 | 399 | {
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nkeynes@953 | 400 | MMIO_WRITE( MMU, TRA, trap<<2 );
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nkeynes@953 | 401 | MMIO_WRITE( MMU, EXPEVT, EXC_TRAP );
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nkeynes@953 | 402 | sh4r.spc = sh4r.pc;
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nkeynes@953 | 403 | sh4r.ssr = sh4_read_sr();
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nkeynes@953 | 404 | sh4r.sgr = sh4r.r[15];
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nkeynes@953 | 405 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
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nkeynes@953 | 406 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@953 | 407 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
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nkeynes@953 | 408 | sh4r.in_delay_slot = 0;
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nkeynes@953 | 409 | }
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nkeynes@953 | 410 |
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nkeynes@953 | 411 | void FASTCALL sh4_raise_tlb_exception( int code, sh4vma_t vpn )
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nkeynes@953 | 412 | {
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nkeynes@953 | 413 | MMIO_WRITE( MMU, TEA, vpn );
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nkeynes@953 | 414 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
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nkeynes@953 | 415 | MMIO_WRITE( MMU, EXPEVT, code );
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nkeynes@953 | 416 | sh4r.spc = sh4r.pc;
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nkeynes@953 | 417 | sh4r.ssr = sh4_read_sr();
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nkeynes@953 | 418 | sh4r.sgr = sh4r.r[15];
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nkeynes@953 | 419 | sh4r.pc = sh4r.vbr + EXV_TLBMISS;
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nkeynes@953 | 420 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@953 | 421 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
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nkeynes@953 | 422 | sh4r.in_delay_slot = 0;
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nkeynes@401 | 423 | }
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nkeynes@401 | 424 |
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nkeynes@905 | 425 | void FASTCALL sh4_accept_interrupt( void )
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nkeynes@401 | 426 | {
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nkeynes@401 | 427 | uint32_t code = intc_accept_interrupt();
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nkeynes@953 | 428 | MMIO_WRITE( MMU, INTEVT, code );
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nkeynes@401 | 429 | sh4r.ssr = sh4_read_sr();
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nkeynes@401 | 430 | sh4r.spc = sh4r.pc;
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nkeynes@401 | 431 | sh4r.sgr = sh4r.r[15];
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nkeynes@401 | 432 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
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nkeynes@401 | 433 | sh4r.pc = sh4r.vbr + 0x600;
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nkeynes@401 | 434 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@401 | 435 | }
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nkeynes@401 | 436 |
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nkeynes@905 | 437 | void FASTCALL signsat48( void )
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nkeynes@401 | 438 | {
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nkeynes@401 | 439 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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nkeynes@736 | 440 | sh4r.mac = 0xFFFF800000000000LL;
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nkeynes@401 | 441 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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nkeynes@736 | 442 | sh4r.mac = 0x00007FFFFFFFFFFFLL;
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nkeynes@401 | 443 | }
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nkeynes@401 | 444 |
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nkeynes@905 | 445 | void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
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nkeynes@401 | 446 | {
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nkeynes@401 | 447 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
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nkeynes@401 | 448 | *fr++ = cosf(angle);
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nkeynes@401 | 449 | *fr = sinf(angle);
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nkeynes@401 | 450 | }
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nkeynes@401 | 451 |
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nkeynes@617 | 452 | /**
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nkeynes@617 | 453 | * Enter sleep mode (eg by executing a SLEEP instruction).
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nkeynes@617 | 454 | * Sets sh4_state appropriately and ensures any stopping peripheral modules
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nkeynes@617 | 455 | * are up to date.
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nkeynes@617 | 456 | */
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nkeynes@905 | 457 | void FASTCALL sh4_sleep(void)
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nkeynes@401 | 458 | {
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nkeynes@401 | 459 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
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nkeynes@736 | 460 | sh4r.sh4_state = SH4_STATE_STANDBY;
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nkeynes@736 | 461 | /* Bring all running peripheral modules up to date, and then halt them. */
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nkeynes@736 | 462 | TMU_run_slice( sh4r.slice_cycle );
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nkeynes@736 | 463 | SCIF_run_slice( sh4r.slice_cycle );
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nkeynes@841 | 464 | PMM_run_slice( sh4r.slice_cycle );
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nkeynes@401 | 465 | } else {
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nkeynes@736 | 466 | if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
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nkeynes@736 | 467 | sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
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nkeynes@736 | 468 | /* Halt DMAC but other peripherals still running */
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nkeynes@736 | 469 |
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nkeynes@736 | 470 | } else {
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nkeynes@736 | 471 | sh4r.sh4_state = SH4_STATE_SLEEP;
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nkeynes@736 | 472 | }
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nkeynes@617 | 473 | }
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nkeynes@740 | 474 | sh4_core_exit( CORE_EXIT_SLEEP );
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nkeynes@401 | 475 | }
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nkeynes@401 | 476 |
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nkeynes@401 | 477 | /**
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nkeynes@617 | 478 | * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
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nkeynes@617 | 479 | * and restarts any peripheral devices that were stopped.
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nkeynes@617 | 480 | */
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nkeynes@617 | 481 | void sh4_wakeup(void)
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nkeynes@617 | 482 | {
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nkeynes@617 | 483 | switch( sh4r.sh4_state ) {
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nkeynes@617 | 484 | case SH4_STATE_STANDBY:
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nkeynes@736 | 485 | break;
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nkeynes@617 | 486 | case SH4_STATE_DEEP_SLEEP:
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nkeynes@736 | 487 | break;
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nkeynes@617 | 488 | case SH4_STATE_SLEEP:
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nkeynes@736 | 489 | break;
|
nkeynes@617 | 490 | }
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nkeynes@617 | 491 | sh4r.sh4_state = SH4_STATE_RUNNING;
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nkeynes@617 | 492 | }
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nkeynes@617 | 493 |
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nkeynes@617 | 494 | /**
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nkeynes@617 | 495 | * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
|
nkeynes@617 | 496 | * Returns when either the SH4 wakes up (interrupt received) or the end of
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nkeynes@617 | 497 | * the slice is reached. Updates sh4.slice_cycle with the exit time and
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nkeynes@617 | 498 | * returns the same value.
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nkeynes@617 | 499 | */
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nkeynes@617 | 500 | uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
|
nkeynes@617 | 501 | {
|
nkeynes@617 | 502 | int sleep_state = sh4r.sh4_state;
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nkeynes@617 | 503 | assert( sleep_state != SH4_STATE_RUNNING );
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nkeynes@736 | 504 |
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nkeynes@617 | 505 | while( sh4r.event_pending < nanosecs ) {
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nkeynes@736 | 506 | sh4r.slice_cycle = sh4r.event_pending;
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nkeynes@736 | 507 | if( sh4r.event_types & PENDING_EVENT ) {
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nkeynes@736 | 508 | event_execute();
|
nkeynes@736 | 509 | }
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nkeynes@736 | 510 | if( sh4r.event_types & PENDING_IRQ ) {
|
nkeynes@736 | 511 | sh4_wakeup();
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nkeynes@736 | 512 | return sh4r.slice_cycle;
|
nkeynes@736 | 513 | }
|
nkeynes@617 | 514 | }
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nkeynes@617 | 515 | sh4r.slice_cycle = nanosecs;
|
nkeynes@617 | 516 | return sh4r.slice_cycle;
|
nkeynes@617 | 517 | }
|
nkeynes@617 | 518 |
|
nkeynes@617 | 519 |
|
nkeynes@617 | 520 | /**
|
nkeynes@401 | 521 | * Compute the matrix tranform of fv given the matrix xf.
|
nkeynes@401 | 522 | * Both fv and xf are word-swapped as per the sh4r.fr banks
|
nkeynes@401 | 523 | */
|
nkeynes@905 | 524 | void FASTCALL sh4_ftrv( float *target )
|
nkeynes@401 | 525 | {
|
nkeynes@401 | 526 | float fv[4] = { target[1], target[0], target[3], target[2] };
|
nkeynes@669 | 527 | target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
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nkeynes@736 | 528 | sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
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nkeynes@669 | 529 | target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
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nkeynes@736 | 530 | sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
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nkeynes@669 | 531 | target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
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nkeynes@736 | 532 | sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
|
nkeynes@669 | 533 | target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
|
nkeynes@736 | 534 | sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
|
nkeynes@401 | 535 | }
|
nkeynes@401 | 536 |
|
nkeynes@597 | 537 | gboolean sh4_has_page( sh4vma_t vma )
|
nkeynes@597 | 538 | {
|
nkeynes@597 | 539 | sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
|
nkeynes@597 | 540 | return addr != MMU_VMA_ERROR && mem_has_page(addr);
|
nkeynes@597 | 541 | }
|