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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 416:714df603c869
prev409:549e00835448
next417:bd927df302a9
author nkeynes
date Wed Oct 03 12:19:03 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Remove INC %esi (and esi in general), replace with load immediates (faster)
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.18 2007-10-03 12:19:03 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	precheck();\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exit( EXIT_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exit( EXIT_ILLEGAL );\
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	}\
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    }\
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static void check_priv_no_precheck()
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	precheck();\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exit(EXIT_FPU_DISABLED);\
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	}\
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    }
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static void check_fpuen_no_precheck()
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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   355
{
nkeynes@368
   356
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   357
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   358
}
nkeynes@368
   359
nkeynes@368
   360
static void check_walign16( int x86reg )
nkeynes@368
   361
{
nkeynes@368
   362
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   363
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   364
}
nkeynes@368
   365
nkeynes@368
   366
static void check_ralign32( int x86reg )
nkeynes@368
   367
{
nkeynes@368
   368
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   369
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   370
}
nkeynes@368
   371
static void check_walign32( int x86reg )
nkeynes@368
   372
{
nkeynes@368
   373
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   374
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   375
}
nkeynes@368
   376
nkeynes@361
   377
#define UNDEF()
nkeynes@361
   378
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   379
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   380
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   381
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   382
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   383
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   384
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   385
nkeynes@416
   386
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   387
nkeynes@368
   388
nkeynes@359
   389
nkeynes@359
   390
/**
nkeynes@359
   391
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   392
 * SI/DI as required
nkeynes@359
   393
 */
nkeynes@408
   394
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   395
{
nkeynes@368
   396
    PUSH_r32(R_EBP);
nkeynes@359
   397
    /* mov &sh4r, ebp */
nkeynes@359
   398
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@368
   399
    
nkeynes@368
   400
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   401
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   402
    sh4_x86.fpuen_checked = FALSE;
nkeynes@409
   403
    sh4_x86.branch_taken = FALSE;
nkeynes@368
   404
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   405
    sh4_x86.block_start_pc = pc;
nkeynes@368
   406
}
nkeynes@359
   407
nkeynes@368
   408
/**
nkeynes@408
   409
 * Exit the block to an absolute PC
nkeynes@416
   410
 * Bytes: 29
nkeynes@368
   411
 */
nkeynes@408
   412
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@368
   413
{
nkeynes@408
   414
    load_imm32( R_ECX, pc );                            // 5
nkeynes@408
   415
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@408
   416
    MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
nkeynes@408
   417
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@408
   418
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   419
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@374
   420
    POP_r32(R_EBP);
nkeynes@368
   421
    RET();
nkeynes@359
   422
}
nkeynes@359
   423
nkeynes@359
   424
/**
nkeynes@408
   425
 * Exit the block with sh4r.pc already written
nkeynes@416
   426
 * Bytes: 15
nkeynes@408
   427
 */
nkeynes@408
   428
void exit_block_pcset( pc )
nkeynes@408
   429
{
nkeynes@408
   430
    XOR_r32_r32( R_EAX, R_EAX );                       // 2
nkeynes@408
   431
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   432
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@408
   433
    POP_r32(R_EBP);
nkeynes@408
   434
    RET();
nkeynes@408
   435
}
nkeynes@408
   436
nkeynes@408
   437
/**
nkeynes@408
   438
 * Write the block trailer (exception handling block)
nkeynes@359
   439
 */
nkeynes@359
   440
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@409
   441
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@409
   442
	// Didn't exit unconditionally already, so write the termination here
nkeynes@409
   443
	exit_block( pc, pc );
nkeynes@409
   444
    }
nkeynes@388
   445
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   446
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   447
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   448
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   449
	JMP_rel8( 33, target1 );
nkeynes@388
   450
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   451
	JMP_rel8( 26, target2 );
nkeynes@388
   452
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   453
	JMP_rel8( 19, target3 );
nkeynes@388
   454
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   455
	JMP_rel8( 12, target4 );
nkeynes@388
   456
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   457
	JMP_rel8( 5, target5 );
nkeynes@388
   458
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   459
	// target
nkeynes@388
   460
	JMP_TARGET(target1);
nkeynes@388
   461
	JMP_TARGET(target2);
nkeynes@388
   462
	JMP_TARGET(target3);
nkeynes@388
   463
	JMP_TARGET(target4);
nkeynes@388
   464
	JMP_TARGET(target5);
nkeynes@388
   465
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@416
   466
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@416
   467
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@388
   468
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   469
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388
   470
	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@416
   471
	MUL_r32( R_EDX );
nkeynes@388
   472
	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388
   473
	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   474
	
nkeynes@388
   475
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   476
	CALL_r32( R_EAX ); // 2
nkeynes@388
   477
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@408
   478
	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@388
   479
	POP_r32(R_EBP);
nkeynes@388
   480
	RET();
nkeynes@368
   481
nkeynes@388
   482
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   483
    }
nkeynes@368
   484
nkeynes@359
   485
}
nkeynes@359
   486
nkeynes@388
   487
nkeynes@388
   488
extern uint16_t *sh4_icache;
nkeynes@388
   489
extern uint32_t sh4_icache_addr;
nkeynes@388
   490
nkeynes@359
   491
/**
nkeynes@359
   492
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   493
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   494
 * 
nkeynes@359
   495
 *
nkeynes@359
   496
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   497
 * (eg a branch or 
nkeynes@359
   498
 */
nkeynes@408
   499
uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
nkeynes@359
   500
{
nkeynes@388
   501
    uint32_t ir;
nkeynes@388
   502
    /* Read instruction */
nkeynes@388
   503
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   504
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   505
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   506
    } else {
nkeynes@388
   507
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   508
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   509
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   510
	     * region, fallback on the full-blown memory read
nkeynes@388
   511
	     */
nkeynes@388
   512
	    sh4_icache = NULL;
nkeynes@388
   513
	    ir = sh4_read_word(pc);
nkeynes@388
   514
	} else {
nkeynes@388
   515
	    sh4_icache_addr = pageaddr;
nkeynes@388
   516
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   517
	}
nkeynes@388
   518
    }
nkeynes@388
   519
nkeynes@359
   520
%%
nkeynes@359
   521
/* ALU operations */
nkeynes@359
   522
ADD Rm, Rn {:
nkeynes@359
   523
    load_reg( R_EAX, Rm );
nkeynes@359
   524
    load_reg( R_ECX, Rn );
nkeynes@359
   525
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   526
    store_reg( R_ECX, Rn );
nkeynes@359
   527
:}
nkeynes@359
   528
ADD #imm, Rn {:  
nkeynes@359
   529
    load_reg( R_EAX, Rn );
nkeynes@359
   530
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   531
    store_reg( R_EAX, Rn );
nkeynes@359
   532
:}
nkeynes@359
   533
ADDC Rm, Rn {:
nkeynes@359
   534
    load_reg( R_EAX, Rm );
nkeynes@359
   535
    load_reg( R_ECX, Rn );
nkeynes@359
   536
    LDC_t();
nkeynes@359
   537
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   538
    store_reg( R_ECX, Rn );
nkeynes@359
   539
    SETC_t();
nkeynes@359
   540
:}
nkeynes@359
   541
ADDV Rm, Rn {:
nkeynes@359
   542
    load_reg( R_EAX, Rm );
nkeynes@359
   543
    load_reg( R_ECX, Rn );
nkeynes@359
   544
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   545
    store_reg( R_ECX, Rn );
nkeynes@359
   546
    SETO_t();
nkeynes@359
   547
:}
nkeynes@359
   548
AND Rm, Rn {:
nkeynes@359
   549
    load_reg( R_EAX, Rm );
nkeynes@359
   550
    load_reg( R_ECX, Rn );
nkeynes@359
   551
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   552
    store_reg( R_ECX, Rn );
nkeynes@359
   553
:}
nkeynes@359
   554
AND #imm, R0 {:  
nkeynes@359
   555
    load_reg( R_EAX, 0 );
nkeynes@359
   556
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   557
    store_reg( R_EAX, 0 );
nkeynes@359
   558
:}
nkeynes@359
   559
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   560
    load_reg( R_EAX, 0 );
nkeynes@359
   561
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   562
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   563
    PUSH_r32(R_ECX);
nkeynes@386
   564
    call_func0(sh4_read_byte);
nkeynes@386
   565
    POP_r32(R_ECX);
nkeynes@386
   566
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   567
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   568
:}
nkeynes@359
   569
CMP/EQ Rm, Rn {:  
nkeynes@359
   570
    load_reg( R_EAX, Rm );
nkeynes@359
   571
    load_reg( R_ECX, Rn );
nkeynes@359
   572
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   573
    SETE_t();
nkeynes@359
   574
:}
nkeynes@359
   575
CMP/EQ #imm, R0 {:  
nkeynes@359
   576
    load_reg( R_EAX, 0 );
nkeynes@359
   577
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   578
    SETE_t();
nkeynes@359
   579
:}
nkeynes@359
   580
CMP/GE Rm, Rn {:  
nkeynes@359
   581
    load_reg( R_EAX, Rm );
nkeynes@359
   582
    load_reg( R_ECX, Rn );
nkeynes@359
   583
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   584
    SETGE_t();
nkeynes@359
   585
:}
nkeynes@359
   586
CMP/GT Rm, Rn {: 
nkeynes@359
   587
    load_reg( R_EAX, Rm );
nkeynes@359
   588
    load_reg( R_ECX, Rn );
nkeynes@359
   589
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   590
    SETG_t();
nkeynes@359
   591
:}
nkeynes@359
   592
CMP/HI Rm, Rn {:  
nkeynes@359
   593
    load_reg( R_EAX, Rm );
nkeynes@359
   594
    load_reg( R_ECX, Rn );
nkeynes@359
   595
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   596
    SETA_t();
nkeynes@359
   597
:}
nkeynes@359
   598
CMP/HS Rm, Rn {: 
nkeynes@359
   599
    load_reg( R_EAX, Rm );
nkeynes@359
   600
    load_reg( R_ECX, Rn );
nkeynes@359
   601
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   602
    SETAE_t();
nkeynes@359
   603
 :}
nkeynes@359
   604
CMP/PL Rn {: 
nkeynes@359
   605
    load_reg( R_EAX, Rn );
nkeynes@359
   606
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   607
    SETG_t();
nkeynes@359
   608
:}
nkeynes@359
   609
CMP/PZ Rn {:  
nkeynes@359
   610
    load_reg( R_EAX, Rn );
nkeynes@359
   611
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   612
    SETGE_t();
nkeynes@359
   613
:}
nkeynes@361
   614
CMP/STR Rm, Rn {:  
nkeynes@368
   615
    load_reg( R_EAX, Rm );
nkeynes@368
   616
    load_reg( R_ECX, Rn );
nkeynes@368
   617
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   618
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   619
    JE_rel8(13, target1);
nkeynes@368
   620
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   621
    JE_rel8(9, target2);
nkeynes@368
   622
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   623
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   624
    JE_rel8(2, target3);
nkeynes@368
   625
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   626
    JMP_TARGET(target1);
nkeynes@380
   627
    JMP_TARGET(target2);
nkeynes@380
   628
    JMP_TARGET(target3);
nkeynes@368
   629
    SETE_t();
nkeynes@361
   630
:}
nkeynes@361
   631
DIV0S Rm, Rn {:
nkeynes@361
   632
    load_reg( R_EAX, Rm );
nkeynes@386
   633
    load_reg( R_ECX, Rn );
nkeynes@361
   634
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   635
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   636
    store_spreg( R_EAX, R_M );
nkeynes@361
   637
    store_spreg( R_ECX, R_Q );
nkeynes@361
   638
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   639
    SETNE_t();
nkeynes@361
   640
:}
nkeynes@361
   641
DIV0U {:  
nkeynes@361
   642
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   643
    store_spreg( R_EAX, R_Q );
nkeynes@361
   644
    store_spreg( R_EAX, R_M );
nkeynes@361
   645
    store_spreg( R_EAX, R_T );
nkeynes@361
   646
:}
nkeynes@386
   647
DIV1 Rm, Rn {:
nkeynes@386
   648
    load_spreg( R_ECX, R_M );
nkeynes@386
   649
    load_reg( R_EAX, Rn );
nkeynes@374
   650
    LDC_t();
nkeynes@386
   651
    RCL1_r32( R_EAX );
nkeynes@386
   652
    SETC_r8( R_DL ); // Q'
nkeynes@386
   653
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   654
    JE_rel8(5, mqequal);
nkeynes@386
   655
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   656
    JMP_rel8(3, end);
nkeynes@380
   657
    JMP_TARGET(mqequal);
nkeynes@386
   658
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   659
    JMP_TARGET(end);
nkeynes@386
   660
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   661
    SETC_r8(R_AL); // tmp1
nkeynes@386
   662
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   663
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   664
    store_spreg( R_ECX, R_Q );
nkeynes@386
   665
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   666
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   667
    store_spreg( R_EAX, R_T );
nkeynes@374
   668
:}
nkeynes@361
   669
DMULS.L Rm, Rn {:  
nkeynes@361
   670
    load_reg( R_EAX, Rm );
nkeynes@361
   671
    load_reg( R_ECX, Rn );
nkeynes@361
   672
    IMUL_r32(R_ECX);
nkeynes@361
   673
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   674
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   675
:}
nkeynes@361
   676
DMULU.L Rm, Rn {:  
nkeynes@361
   677
    load_reg( R_EAX, Rm );
nkeynes@361
   678
    load_reg( R_ECX, Rn );
nkeynes@361
   679
    MUL_r32(R_ECX);
nkeynes@361
   680
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   681
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   682
:}
nkeynes@359
   683
DT Rn {:  
nkeynes@359
   684
    load_reg( R_EAX, Rn );
nkeynes@382
   685
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   686
    store_reg( R_EAX, Rn );
nkeynes@359
   687
    SETE_t();
nkeynes@359
   688
:}
nkeynes@359
   689
EXTS.B Rm, Rn {:  
nkeynes@359
   690
    load_reg( R_EAX, Rm );
nkeynes@359
   691
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   692
    store_reg( R_EAX, Rn );
nkeynes@359
   693
:}
nkeynes@361
   694
EXTS.W Rm, Rn {:  
nkeynes@361
   695
    load_reg( R_EAX, Rm );
nkeynes@361
   696
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   697
    store_reg( R_EAX, Rn );
nkeynes@361
   698
:}
nkeynes@361
   699
EXTU.B Rm, Rn {:  
nkeynes@361
   700
    load_reg( R_EAX, Rm );
nkeynes@361
   701
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   702
    store_reg( R_EAX, Rn );
nkeynes@361
   703
:}
nkeynes@361
   704
EXTU.W Rm, Rn {:  
nkeynes@361
   705
    load_reg( R_EAX, Rm );
nkeynes@361
   706
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   707
    store_reg( R_EAX, Rn );
nkeynes@361
   708
:}
nkeynes@386
   709
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   710
    load_reg( R_ECX, Rm );
nkeynes@416
   711
    precheck();
nkeynes@386
   712
    check_ralign32( R_ECX );
nkeynes@386
   713
    load_reg( R_ECX, Rn );
nkeynes@386
   714
    check_ralign32( R_ECX );
nkeynes@386
   715
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   716
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   717
    PUSH_r32( R_EAX );
nkeynes@386
   718
    load_reg( R_ECX, Rm );
nkeynes@386
   719
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   720
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   721
    POP_r32( R_ECX );
nkeynes@386
   722
    IMUL_r32( R_ECX );
nkeynes@386
   723
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   724
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   725
nkeynes@386
   726
    load_spreg( R_ECX, R_S );
nkeynes@386
   727
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   728
    JE_rel8( 7, nosat );
nkeynes@386
   729
    call_func0( signsat48 );
nkeynes@386
   730
    JMP_TARGET( nosat );
nkeynes@386
   731
:}
nkeynes@386
   732
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   733
    load_reg( R_ECX, Rm );
nkeynes@416
   734
    precheck();
nkeynes@386
   735
    check_ralign16( R_ECX );
nkeynes@386
   736
    load_reg( R_ECX, Rn );
nkeynes@386
   737
    check_ralign16( R_ECX );
nkeynes@386
   738
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   739
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   740
    PUSH_r32( R_EAX );
nkeynes@386
   741
    load_reg( R_ECX, Rm );
nkeynes@386
   742
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   743
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   744
    POP_r32( R_ECX );
nkeynes@386
   745
    IMUL_r32( R_ECX );
nkeynes@386
   746
nkeynes@386
   747
    load_spreg( R_ECX, R_S );
nkeynes@386
   748
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   749
    JE_rel8( 47, nosat );
nkeynes@386
   750
nkeynes@386
   751
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   752
    JNO_rel8( 51, end );            // 2
nkeynes@386
   753
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   754
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   755
    JS_rel8( 13, positive );        // 2
nkeynes@386
   756
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   757
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   758
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   759
nkeynes@386
   760
    JMP_TARGET(positive);
nkeynes@386
   761
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   762
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   763
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   764
nkeynes@386
   765
    JMP_TARGET(nosat);
nkeynes@386
   766
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   767
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   768
    JMP_TARGET(end);
nkeynes@386
   769
    JMP_TARGET(end2);
nkeynes@386
   770
    JMP_TARGET(end3);
nkeynes@386
   771
:}
nkeynes@359
   772
MOVT Rn {:  
nkeynes@359
   773
    load_spreg( R_EAX, R_T );
nkeynes@359
   774
    store_reg( R_EAX, Rn );
nkeynes@359
   775
:}
nkeynes@361
   776
MUL.L Rm, Rn {:  
nkeynes@361
   777
    load_reg( R_EAX, Rm );
nkeynes@361
   778
    load_reg( R_ECX, Rn );
nkeynes@361
   779
    MUL_r32( R_ECX );
nkeynes@361
   780
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   781
:}
nkeynes@374
   782
MULS.W Rm, Rn {:
nkeynes@374
   783
    load_reg16s( R_EAX, Rm );
nkeynes@374
   784
    load_reg16s( R_ECX, Rn );
nkeynes@374
   785
    MUL_r32( R_ECX );
nkeynes@374
   786
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   787
:}
nkeynes@374
   788
MULU.W Rm, Rn {:  
nkeynes@374
   789
    load_reg16u( R_EAX, Rm );
nkeynes@374
   790
    load_reg16u( R_ECX, Rn );
nkeynes@374
   791
    MUL_r32( R_ECX );
nkeynes@374
   792
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   793
:}
nkeynes@359
   794
NEG Rm, Rn {:
nkeynes@359
   795
    load_reg( R_EAX, Rm );
nkeynes@359
   796
    NEG_r32( R_EAX );
nkeynes@359
   797
    store_reg( R_EAX, Rn );
nkeynes@359
   798
:}
nkeynes@359
   799
NEGC Rm, Rn {:  
nkeynes@359
   800
    load_reg( R_EAX, Rm );
nkeynes@359
   801
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   802
    LDC_t();
nkeynes@359
   803
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   804
    store_reg( R_ECX, Rn );
nkeynes@359
   805
    SETC_t();
nkeynes@359
   806
:}
nkeynes@359
   807
NOT Rm, Rn {:  
nkeynes@359
   808
    load_reg( R_EAX, Rm );
nkeynes@359
   809
    NOT_r32( R_EAX );
nkeynes@359
   810
    store_reg( R_EAX, Rn );
nkeynes@359
   811
:}
nkeynes@359
   812
OR Rm, Rn {:  
nkeynes@359
   813
    load_reg( R_EAX, Rm );
nkeynes@359
   814
    load_reg( R_ECX, Rn );
nkeynes@359
   815
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   816
    store_reg( R_ECX, Rn );
nkeynes@359
   817
:}
nkeynes@359
   818
OR #imm, R0 {:
nkeynes@359
   819
    load_reg( R_EAX, 0 );
nkeynes@359
   820
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   821
    store_reg( R_EAX, 0 );
nkeynes@359
   822
:}
nkeynes@374
   823
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   824
    load_reg( R_EAX, 0 );
nkeynes@374
   825
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   826
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   827
    PUSH_r32(R_ECX);
nkeynes@386
   828
    call_func0(sh4_read_byte);
nkeynes@386
   829
    POP_r32(R_ECX);
nkeynes@386
   830
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   831
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   832
:}
nkeynes@359
   833
ROTCL Rn {:
nkeynes@359
   834
    load_reg( R_EAX, Rn );
nkeynes@359
   835
    LDC_t();
nkeynes@359
   836
    RCL1_r32( R_EAX );
nkeynes@359
   837
    store_reg( R_EAX, Rn );
nkeynes@359
   838
    SETC_t();
nkeynes@359
   839
:}
nkeynes@359
   840
ROTCR Rn {:  
nkeynes@359
   841
    load_reg( R_EAX, Rn );
nkeynes@359
   842
    LDC_t();
nkeynes@359
   843
    RCR1_r32( R_EAX );
nkeynes@359
   844
    store_reg( R_EAX, Rn );
nkeynes@359
   845
    SETC_t();
nkeynes@359
   846
:}
nkeynes@359
   847
ROTL Rn {:  
nkeynes@359
   848
    load_reg( R_EAX, Rn );
nkeynes@359
   849
    ROL1_r32( R_EAX );
nkeynes@359
   850
    store_reg( R_EAX, Rn );
nkeynes@359
   851
    SETC_t();
nkeynes@359
   852
:}
nkeynes@359
   853
ROTR Rn {:  
nkeynes@359
   854
    load_reg( R_EAX, Rn );
nkeynes@359
   855
    ROR1_r32( R_EAX );
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@359
   857
    SETC_t();
nkeynes@359
   858
:}
nkeynes@359
   859
SHAD Rm, Rn {:
nkeynes@359
   860
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   861
    load_reg( R_EAX, Rn );
nkeynes@361
   862
    load_reg( R_ECX, Rm );
nkeynes@361
   863
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   864
    JGE_rel8(16, doshl);
nkeynes@361
   865
                    
nkeynes@361
   866
    NEG_r32( R_ECX );      // 2
nkeynes@361
   867
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   868
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   869
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   870
    JMP_rel8(10, end);          // 2
nkeynes@386
   871
nkeynes@386
   872
    JMP_TARGET(emptysar);
nkeynes@386
   873
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   874
    JMP_rel8(5, end2);
nkeynes@382
   875
nkeynes@380
   876
    JMP_TARGET(doshl);
nkeynes@361
   877
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   878
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   879
    JMP_TARGET(end);
nkeynes@386
   880
    JMP_TARGET(end2);
nkeynes@361
   881
    store_reg( R_EAX, Rn );
nkeynes@359
   882
:}
nkeynes@359
   883
SHLD Rm, Rn {:  
nkeynes@368
   884
    load_reg( R_EAX, Rn );
nkeynes@368
   885
    load_reg( R_ECX, Rm );
nkeynes@382
   886
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   887
    JGE_rel8(15, doshl);
nkeynes@368
   888
nkeynes@382
   889
    NEG_r32( R_ECX );      // 2
nkeynes@382
   890
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   891
    JE_rel8( 4, emptyshr );
nkeynes@382
   892
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   893
    JMP_rel8(9, end);          // 2
nkeynes@386
   894
nkeynes@386
   895
    JMP_TARGET(emptyshr);
nkeynes@386
   896
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   897
    JMP_rel8(5, end2);
nkeynes@382
   898
nkeynes@382
   899
    JMP_TARGET(doshl);
nkeynes@382
   900
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   901
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   902
    JMP_TARGET(end);
nkeynes@386
   903
    JMP_TARGET(end2);
nkeynes@368
   904
    store_reg( R_EAX, Rn );
nkeynes@359
   905
:}
nkeynes@359
   906
SHAL Rn {: 
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@359
   908
    SHL1_r32( R_EAX );
nkeynes@397
   909
    SETC_t();
nkeynes@359
   910
    store_reg( R_EAX, Rn );
nkeynes@359
   911
:}
nkeynes@359
   912
SHAR Rn {:  
nkeynes@359
   913
    load_reg( R_EAX, Rn );
nkeynes@359
   914
    SAR1_r32( R_EAX );
nkeynes@397
   915
    SETC_t();
nkeynes@359
   916
    store_reg( R_EAX, Rn );
nkeynes@359
   917
:}
nkeynes@359
   918
SHLL Rn {:  
nkeynes@359
   919
    load_reg( R_EAX, Rn );
nkeynes@359
   920
    SHL1_r32( R_EAX );
nkeynes@397
   921
    SETC_t();
nkeynes@359
   922
    store_reg( R_EAX, Rn );
nkeynes@359
   923
:}
nkeynes@359
   924
SHLL2 Rn {:
nkeynes@359
   925
    load_reg( R_EAX, Rn );
nkeynes@359
   926
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   927
    store_reg( R_EAX, Rn );
nkeynes@359
   928
:}
nkeynes@359
   929
SHLL8 Rn {:  
nkeynes@359
   930
    load_reg( R_EAX, Rn );
nkeynes@359
   931
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   932
    store_reg( R_EAX, Rn );
nkeynes@359
   933
:}
nkeynes@359
   934
SHLL16 Rn {:  
nkeynes@359
   935
    load_reg( R_EAX, Rn );
nkeynes@359
   936
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   937
    store_reg( R_EAX, Rn );
nkeynes@359
   938
:}
nkeynes@359
   939
SHLR Rn {:  
nkeynes@359
   940
    load_reg( R_EAX, Rn );
nkeynes@359
   941
    SHR1_r32( R_EAX );
nkeynes@397
   942
    SETC_t();
nkeynes@359
   943
    store_reg( R_EAX, Rn );
nkeynes@359
   944
:}
nkeynes@359
   945
SHLR2 Rn {:  
nkeynes@359
   946
    load_reg( R_EAX, Rn );
nkeynes@359
   947
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@359
   949
:}
nkeynes@359
   950
SHLR8 Rn {:  
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@359
   952
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   953
    store_reg( R_EAX, Rn );
nkeynes@359
   954
:}
nkeynes@359
   955
SHLR16 Rn {:  
nkeynes@359
   956
    load_reg( R_EAX, Rn );
nkeynes@359
   957
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   958
    store_reg( R_EAX, Rn );
nkeynes@359
   959
:}
nkeynes@359
   960
SUB Rm, Rn {:  
nkeynes@359
   961
    load_reg( R_EAX, Rm );
nkeynes@359
   962
    load_reg( R_ECX, Rn );
nkeynes@359
   963
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   964
    store_reg( R_ECX, Rn );
nkeynes@359
   965
:}
nkeynes@359
   966
SUBC Rm, Rn {:  
nkeynes@359
   967
    load_reg( R_EAX, Rm );
nkeynes@359
   968
    load_reg( R_ECX, Rn );
nkeynes@359
   969
    LDC_t();
nkeynes@359
   970
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   971
    store_reg( R_ECX, Rn );
nkeynes@394
   972
    SETC_t();
nkeynes@359
   973
:}
nkeynes@359
   974
SUBV Rm, Rn {:  
nkeynes@359
   975
    load_reg( R_EAX, Rm );
nkeynes@359
   976
    load_reg( R_ECX, Rn );
nkeynes@359
   977
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   978
    store_reg( R_ECX, Rn );
nkeynes@359
   979
    SETO_t();
nkeynes@359
   980
:}
nkeynes@359
   981
SWAP.B Rm, Rn {:  
nkeynes@359
   982
    load_reg( R_EAX, Rm );
nkeynes@359
   983
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   984
    store_reg( R_EAX, Rn );
nkeynes@359
   985
:}
nkeynes@359
   986
SWAP.W Rm, Rn {:  
nkeynes@359
   987
    load_reg( R_EAX, Rm );
nkeynes@359
   988
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   989
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   990
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   991
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   992
    store_reg( R_ECX, Rn );
nkeynes@359
   993
:}
nkeynes@361
   994
TAS.B @Rn {:  
nkeynes@361
   995
    load_reg( R_ECX, Rn );
nkeynes@361
   996
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   997
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   998
    SETE_t();
nkeynes@361
   999
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1000
    load_reg( R_ECX, Rn );
nkeynes@361
  1001
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
  1002
:}
nkeynes@361
  1003
TST Rm, Rn {:  
nkeynes@361
  1004
    load_reg( R_EAX, Rm );
nkeynes@361
  1005
    load_reg( R_ECX, Rn );
nkeynes@361
  1006
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1007
    SETE_t();
nkeynes@361
  1008
:}
nkeynes@368
  1009
TST #imm, R0 {:  
nkeynes@368
  1010
    load_reg( R_EAX, 0 );
nkeynes@368
  1011
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1012
    SETE_t();
nkeynes@368
  1013
:}
nkeynes@368
  1014
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1015
    load_reg( R_EAX, 0);
nkeynes@368
  1016
    load_reg( R_ECX, R_GBR);
nkeynes@368
  1017
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1018
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  1019
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1020
    SETE_t();
nkeynes@368
  1021
:}
nkeynes@359
  1022
XOR Rm, Rn {:  
nkeynes@359
  1023
    load_reg( R_EAX, Rm );
nkeynes@359
  1024
    load_reg( R_ECX, Rn );
nkeynes@359
  1025
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1026
    store_reg( R_ECX, Rn );
nkeynes@359
  1027
:}
nkeynes@359
  1028
XOR #imm, R0 {:  
nkeynes@359
  1029
    load_reg( R_EAX, 0 );
nkeynes@359
  1030
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1031
    store_reg( R_EAX, 0 );
nkeynes@359
  1032
:}
nkeynes@359
  1033
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1034
    load_reg( R_EAX, 0 );
nkeynes@359
  1035
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1036
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1037
    PUSH_r32(R_ECX);
nkeynes@386
  1038
    call_func0(sh4_read_byte);
nkeynes@386
  1039
    POP_r32(R_ECX);
nkeynes@359
  1040
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1041
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1042
:}
nkeynes@361
  1043
XTRCT Rm, Rn {:
nkeynes@361
  1044
    load_reg( R_EAX, Rm );
nkeynes@394
  1045
    load_reg( R_ECX, Rn );
nkeynes@394
  1046
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1047
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1048
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1049
    store_reg( R_ECX, Rn );
nkeynes@359
  1050
:}
nkeynes@359
  1051
nkeynes@359
  1052
/* Data move instructions */
nkeynes@359
  1053
MOV Rm, Rn {:  
nkeynes@359
  1054
    load_reg( R_EAX, Rm );
nkeynes@359
  1055
    store_reg( R_EAX, Rn );
nkeynes@359
  1056
:}
nkeynes@359
  1057
MOV #imm, Rn {:  
nkeynes@359
  1058
    load_imm32( R_EAX, imm );
nkeynes@359
  1059
    store_reg( R_EAX, Rn );
nkeynes@359
  1060
:}
nkeynes@359
  1061
MOV.B Rm, @Rn {:  
nkeynes@359
  1062
    load_reg( R_EAX, Rm );
nkeynes@359
  1063
    load_reg( R_ECX, Rn );
nkeynes@359
  1064
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1065
:}
nkeynes@359
  1066
MOV.B Rm, @-Rn {:  
nkeynes@359
  1067
    load_reg( R_EAX, Rm );
nkeynes@359
  1068
    load_reg( R_ECX, Rn );
nkeynes@382
  1069
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1070
    store_reg( R_ECX, Rn );
nkeynes@359
  1071
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1072
:}
nkeynes@359
  1073
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1074
    load_reg( R_EAX, 0 );
nkeynes@359
  1075
    load_reg( R_ECX, Rn );
nkeynes@359
  1076
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1077
    load_reg( R_EAX, Rm );
nkeynes@359
  1078
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1079
:}
nkeynes@359
  1080
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1081
    load_reg( R_EAX, 0 );
nkeynes@359
  1082
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1083
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1084
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1085
:}
nkeynes@359
  1086
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1087
    load_reg( R_EAX, 0 );
nkeynes@359
  1088
    load_reg( R_ECX, Rn );
nkeynes@359
  1089
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1090
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1091
:}
nkeynes@359
  1092
MOV.B @Rm, Rn {:  
nkeynes@359
  1093
    load_reg( R_ECX, Rm );
nkeynes@359
  1094
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1095
    store_reg( R_EAX, Rn );
nkeynes@359
  1096
:}
nkeynes@359
  1097
MOV.B @Rm+, Rn {:  
nkeynes@359
  1098
    load_reg( R_ECX, Rm );
nkeynes@359
  1099
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1100
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1101
    store_reg( R_EAX, Rm );
nkeynes@359
  1102
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1103
    store_reg( R_EAX, Rn );
nkeynes@359
  1104
:}
nkeynes@359
  1105
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1106
    load_reg( R_EAX, 0 );
nkeynes@359
  1107
    load_reg( R_ECX, Rm );
nkeynes@359
  1108
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1109
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1110
    store_reg( R_EAX, Rn );
nkeynes@359
  1111
:}
nkeynes@359
  1112
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1113
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1114
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1115
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1116
    store_reg( R_EAX, 0 );
nkeynes@359
  1117
:}
nkeynes@359
  1118
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1119
    load_reg( R_ECX, Rm );
nkeynes@359
  1120
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1121
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1122
    store_reg( R_EAX, 0 );
nkeynes@359
  1123
:}
nkeynes@374
  1124
MOV.L Rm, @Rn {:
nkeynes@361
  1125
    load_reg( R_EAX, Rm );
nkeynes@361
  1126
    load_reg( R_ECX, Rn );
nkeynes@416
  1127
    precheck();
nkeynes@374
  1128
    check_walign32(R_ECX);
nkeynes@361
  1129
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1130
:}
nkeynes@361
  1131
MOV.L Rm, @-Rn {:  
nkeynes@361
  1132
    load_reg( R_EAX, Rm );
nkeynes@361
  1133
    load_reg( R_ECX, Rn );
nkeynes@416
  1134
    precheck();
nkeynes@374
  1135
    check_walign32( R_ECX );
nkeynes@361
  1136
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1137
    store_reg( R_ECX, Rn );
nkeynes@361
  1138
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1139
:}
nkeynes@361
  1140
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1141
    load_reg( R_EAX, 0 );
nkeynes@361
  1142
    load_reg( R_ECX, Rn );
nkeynes@361
  1143
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1144
    precheck();
nkeynes@374
  1145
    check_walign32( R_ECX );
nkeynes@361
  1146
    load_reg( R_EAX, Rm );
nkeynes@361
  1147
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1148
:}
nkeynes@361
  1149
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1150
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1151
    load_reg( R_EAX, 0 );
nkeynes@361
  1152
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1153
    precheck();
nkeynes@374
  1154
    check_walign32( R_ECX );
nkeynes@361
  1155
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1156
:}
nkeynes@361
  1157
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1158
    load_reg( R_ECX, Rn );
nkeynes@361
  1159
    load_reg( R_EAX, Rm );
nkeynes@361
  1160
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1161
    precheck();
nkeynes@374
  1162
    check_walign32( R_ECX );
nkeynes@361
  1163
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1164
:}
nkeynes@361
  1165
MOV.L @Rm, Rn {:  
nkeynes@361
  1166
    load_reg( R_ECX, Rm );
nkeynes@416
  1167
    precheck();
nkeynes@374
  1168
    check_ralign32( R_ECX );
nkeynes@361
  1169
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1170
    store_reg( R_EAX, Rn );
nkeynes@361
  1171
:}
nkeynes@361
  1172
MOV.L @Rm+, Rn {:  
nkeynes@361
  1173
    load_reg( R_EAX, Rm );
nkeynes@416
  1174
    precheck();
nkeynes@382
  1175
    check_ralign32( R_EAX );
nkeynes@361
  1176
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1177
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1178
    store_reg( R_EAX, Rm );
nkeynes@361
  1179
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1180
    store_reg( R_EAX, Rn );
nkeynes@361
  1181
:}
nkeynes@361
  1182
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1183
    load_reg( R_EAX, 0 );
nkeynes@361
  1184
    load_reg( R_ECX, Rm );
nkeynes@361
  1185
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1186
    precheck();
nkeynes@374
  1187
    check_ralign32( R_ECX );
nkeynes@361
  1188
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1189
    store_reg( R_EAX, Rn );
nkeynes@361
  1190
:}
nkeynes@361
  1191
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1192
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1193
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1194
    precheck();
nkeynes@374
  1195
    check_ralign32( R_ECX );
nkeynes@361
  1196
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1197
    store_reg( R_EAX, 0 );
nkeynes@361
  1198
:}
nkeynes@361
  1199
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1200
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1201
	SLOTILLEGAL();
nkeynes@374
  1202
    } else {
nkeynes@388
  1203
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  1204
	char *ptr = mem_get_region(target);
nkeynes@388
  1205
	if( ptr != NULL ) {
nkeynes@388
  1206
	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  1207
	} else {
nkeynes@388
  1208
	    load_imm32( R_ECX, target );
nkeynes@388
  1209
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1210
	}
nkeynes@382
  1211
	store_reg( R_EAX, Rn );
nkeynes@374
  1212
    }
nkeynes@361
  1213
:}
nkeynes@361
  1214
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1215
    load_reg( R_ECX, Rm );
nkeynes@361
  1216
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  1217
    precheck();
nkeynes@374
  1218
    check_ralign32( R_ECX );
nkeynes@361
  1219
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1220
    store_reg( R_EAX, Rn );
nkeynes@361
  1221
:}
nkeynes@361
  1222
MOV.W Rm, @Rn {:  
nkeynes@361
  1223
    load_reg( R_ECX, Rn );
nkeynes@416
  1224
    precheck();
nkeynes@374
  1225
    check_walign16( R_ECX );
nkeynes@382
  1226
    load_reg( R_EAX, Rm );
nkeynes@382
  1227
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1228
:}
nkeynes@361
  1229
MOV.W Rm, @-Rn {:  
nkeynes@361
  1230
    load_reg( R_ECX, Rn );
nkeynes@416
  1231
    precheck();
nkeynes@374
  1232
    check_walign16( R_ECX );
nkeynes@361
  1233
    load_reg( R_EAX, Rm );
nkeynes@361
  1234
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1235
    store_reg( R_ECX, Rn );
nkeynes@361
  1236
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1237
:}
nkeynes@361
  1238
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1239
    load_reg( R_EAX, 0 );
nkeynes@361
  1240
    load_reg( R_ECX, Rn );
nkeynes@361
  1241
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1242
    precheck();
nkeynes@374
  1243
    check_walign16( R_ECX );
nkeynes@361
  1244
    load_reg( R_EAX, Rm );
nkeynes@361
  1245
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1246
:}
nkeynes@361
  1247
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1248
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1249
    load_reg( R_EAX, 0 );
nkeynes@361
  1250
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1251
    precheck();
nkeynes@374
  1252
    check_walign16( R_ECX );
nkeynes@361
  1253
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1256
    load_reg( R_ECX, Rn );
nkeynes@361
  1257
    load_reg( R_EAX, 0 );
nkeynes@361
  1258
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1259
    precheck();
nkeynes@374
  1260
    check_walign16( R_ECX );
nkeynes@361
  1261
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1262
:}
nkeynes@361
  1263
MOV.W @Rm, Rn {:  
nkeynes@361
  1264
    load_reg( R_ECX, Rm );
nkeynes@416
  1265
    precheck();
nkeynes@374
  1266
    check_ralign16( R_ECX );
nkeynes@361
  1267
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1268
    store_reg( R_EAX, Rn );
nkeynes@361
  1269
:}
nkeynes@361
  1270
MOV.W @Rm+, Rn {:  
nkeynes@361
  1271
    load_reg( R_EAX, Rm );
nkeynes@416
  1272
    precheck();
nkeynes@374
  1273
    check_ralign16( R_EAX );
nkeynes@361
  1274
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1275
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1276
    store_reg( R_EAX, Rm );
nkeynes@361
  1277
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1278
    store_reg( R_EAX, Rn );
nkeynes@361
  1279
:}
nkeynes@361
  1280
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1281
    load_reg( R_EAX, 0 );
nkeynes@361
  1282
    load_reg( R_ECX, Rm );
nkeynes@361
  1283
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1284
    precheck();
nkeynes@374
  1285
    check_ralign16( R_ECX );
nkeynes@361
  1286
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1287
    store_reg( R_EAX, Rn );
nkeynes@361
  1288
:}
nkeynes@361
  1289
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1290
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1291
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1292
    precheck();
nkeynes@374
  1293
    check_ralign16( R_ECX );
nkeynes@361
  1294
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1295
    store_reg( R_EAX, 0 );
nkeynes@361
  1296
:}
nkeynes@361
  1297
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1298
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1299
	SLOTILLEGAL();
nkeynes@374
  1300
    } else {
nkeynes@374
  1301
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1302
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1303
	store_reg( R_EAX, Rn );
nkeynes@374
  1304
    }
nkeynes@361
  1305
:}
nkeynes@361
  1306
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1307
    load_reg( R_ECX, Rm );
nkeynes@361
  1308
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1309
    precheck();
nkeynes@374
  1310
    check_ralign16( R_ECX );
nkeynes@361
  1311
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1312
    store_reg( R_EAX, 0 );
nkeynes@361
  1313
:}
nkeynes@361
  1314
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1315
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1316
	SLOTILLEGAL();
nkeynes@374
  1317
    } else {
nkeynes@374
  1318
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1319
	store_reg( R_ECX, 0 );
nkeynes@374
  1320
    }
nkeynes@361
  1321
:}
nkeynes@361
  1322
MOVCA.L R0, @Rn {:  
nkeynes@361
  1323
    load_reg( R_EAX, 0 );
nkeynes@361
  1324
    load_reg( R_ECX, Rn );
nkeynes@416
  1325
    precheck();
nkeynes@374
  1326
    check_walign32( R_ECX );
nkeynes@361
  1327
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1328
:}
nkeynes@359
  1329
nkeynes@359
  1330
/* Control transfer instructions */
nkeynes@374
  1331
BF disp {:
nkeynes@374
  1332
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1333
	SLOTILLEGAL();
nkeynes@374
  1334
    } else {
nkeynes@374
  1335
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@416
  1336
	JNE_rel8( 29, nottaken );
nkeynes@408
  1337
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1338
	JMP_TARGET(nottaken);
nkeynes@408
  1339
	return 2;
nkeynes@374
  1340
    }
nkeynes@374
  1341
:}
nkeynes@374
  1342
BF/S disp {:
nkeynes@374
  1343
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1344
	SLOTILLEGAL();
nkeynes@374
  1345
    } else {
nkeynes@408
  1346
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1347
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1348
	OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@408
  1349
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1350
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1351
	// not taken
nkeynes@408
  1352
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1353
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1354
	return 4;
nkeynes@374
  1355
    }
nkeynes@374
  1356
:}
nkeynes@374
  1357
BRA disp {:  
nkeynes@374
  1358
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1359
	SLOTILLEGAL();
nkeynes@374
  1360
    } else {
nkeynes@374
  1361
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1362
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1363
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1364
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1365
	return 4;
nkeynes@374
  1366
    }
nkeynes@374
  1367
:}
nkeynes@374
  1368
BRAF Rn {:  
nkeynes@374
  1369
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1370
	SLOTILLEGAL();
nkeynes@374
  1371
    } else {
nkeynes@408
  1372
	load_reg( R_EAX, Rn );
nkeynes@408
  1373
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1374
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1375
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1376
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1377
	exit_block_pcset(pc+2);
nkeynes@409
  1378
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1379
	return 4;
nkeynes@374
  1380
    }
nkeynes@374
  1381
:}
nkeynes@374
  1382
BSR disp {:  
nkeynes@374
  1383
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1384
	SLOTILLEGAL();
nkeynes@374
  1385
    } else {
nkeynes@374
  1386
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1387
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1388
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1389
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1390
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1391
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1392
	return 4;
nkeynes@374
  1393
    }
nkeynes@374
  1394
:}
nkeynes@374
  1395
BSRF Rn {:  
nkeynes@374
  1396
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1397
	SLOTILLEGAL();
nkeynes@374
  1398
    } else {
nkeynes@408
  1399
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1400
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1401
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1402
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1403
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1404
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1405
	exit_block_pcset(pc+2);
nkeynes@409
  1406
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1407
	return 4;
nkeynes@374
  1408
    }
nkeynes@374
  1409
:}
nkeynes@374
  1410
BT disp {:
nkeynes@374
  1411
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1412
	SLOTILLEGAL();
nkeynes@374
  1413
    } else {
nkeynes@374
  1414
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@416
  1415
	JE_rel8( 29, nottaken );
nkeynes@408
  1416
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1417
	JMP_TARGET(nottaken);
nkeynes@408
  1418
	return 2;
nkeynes@374
  1419
    }
nkeynes@374
  1420
:}
nkeynes@374
  1421
BT/S disp {:
nkeynes@374
  1422
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1423
	SLOTILLEGAL();
nkeynes@374
  1424
    } else {
nkeynes@408
  1425
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1426
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1427
	OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@408
  1428
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1429
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1430
	// not taken
nkeynes@408
  1431
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1432
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1433
	return 4;
nkeynes@374
  1434
    }
nkeynes@374
  1435
:}
nkeynes@374
  1436
JMP @Rn {:  
nkeynes@374
  1437
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1438
	SLOTILLEGAL();
nkeynes@374
  1439
    } else {
nkeynes@408
  1440
	load_reg( R_ECX, Rn );
nkeynes@408
  1441
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1442
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1443
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1444
	exit_block_pcset(pc+2);
nkeynes@409
  1445
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1446
	return 4;
nkeynes@374
  1447
    }
nkeynes@374
  1448
:}
nkeynes@374
  1449
JSR @Rn {:  
nkeynes@374
  1450
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1451
	SLOTILLEGAL();
nkeynes@374
  1452
    } else {
nkeynes@374
  1453
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1454
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1455
	load_reg( R_ECX, Rn );
nkeynes@408
  1456
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1457
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1458
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1459
	exit_block_pcset(pc+2);
nkeynes@409
  1460
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1461
	return 4;
nkeynes@374
  1462
    }
nkeynes@374
  1463
:}
nkeynes@374
  1464
RTE {:  
nkeynes@374
  1465
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1466
	SLOTILLEGAL();
nkeynes@374
  1467
    } else {
nkeynes@408
  1468
	check_priv();
nkeynes@408
  1469
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1470
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1471
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1472
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1473
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1474
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1475
	sh4_x86.fpuen_checked = FALSE;
nkeynes@408
  1476
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1477
	exit_block_pcset(pc+2);
nkeynes@409
  1478
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1479
	return 4;
nkeynes@374
  1480
    }
nkeynes@374
  1481
:}
nkeynes@374
  1482
RTS {:  
nkeynes@374
  1483
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1484
	SLOTILLEGAL();
nkeynes@374
  1485
    } else {
nkeynes@408
  1486
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1487
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1488
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1489
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1490
	exit_block_pcset(pc+2);
nkeynes@409
  1491
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1492
	return 4;
nkeynes@374
  1493
    }
nkeynes@374
  1494
:}
nkeynes@374
  1495
TRAPA #imm {:  
nkeynes@374
  1496
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1497
	SLOTILLEGAL();
nkeynes@374
  1498
    } else {
nkeynes@388
  1499
	PUSH_imm32( imm );
nkeynes@388
  1500
	call_func0( sh4_raise_trap );
nkeynes@388
  1501
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@408
  1502
	exit_block_pcset(pc);
nkeynes@409
  1503
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1504
	return 2;
nkeynes@374
  1505
    }
nkeynes@374
  1506
:}
nkeynes@374
  1507
UNDEF {:  
nkeynes@374
  1508
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1509
	SLOTILLEGAL();
nkeynes@374
  1510
    } else {
nkeynes@416
  1511
	precheck();
nkeynes@386
  1512
	JMP_exit(EXIT_ILLEGAL);
nkeynes@408
  1513
	return 2;
nkeynes@374
  1514
    }
nkeynes@368
  1515
:}
nkeynes@374
  1516
nkeynes@374
  1517
CLRMAC {:  
nkeynes@374
  1518
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1519
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1520
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1521
:}
nkeynes@374
  1522
CLRS {:
nkeynes@374
  1523
    CLC();
nkeynes@374
  1524
    SETC_sh4r(R_S);
nkeynes@368
  1525
:}
nkeynes@374
  1526
CLRT {:  
nkeynes@374
  1527
    CLC();
nkeynes@374
  1528
    SETC_t();
nkeynes@359
  1529
:}
nkeynes@374
  1530
SETS {:  
nkeynes@374
  1531
    STC();
nkeynes@374
  1532
    SETC_sh4r(R_S);
nkeynes@359
  1533
:}
nkeynes@374
  1534
SETT {:  
nkeynes@374
  1535
    STC();
nkeynes@374
  1536
    SETC_t();
nkeynes@374
  1537
:}
nkeynes@359
  1538
nkeynes@375
  1539
/* Floating point moves */
nkeynes@375
  1540
FMOV FRm, FRn {:  
nkeynes@375
  1541
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1542
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1543
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1544
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1545
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1546
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1547
     */
nkeynes@377
  1548
    check_fpuen();
nkeynes@375
  1549
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1550
    load_fr_bank( R_EDX );
nkeynes@375
  1551
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1552
    JNE_rel8(8, doublesize);
nkeynes@375
  1553
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1554
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1555
    if( FRm&1 ) {
nkeynes@386
  1556
	JMP_rel8(24, end);
nkeynes@380
  1557
	JMP_TARGET(doublesize);
nkeynes@375
  1558
	load_xf_bank( R_ECX ); 
nkeynes@375
  1559
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1560
	if( FRn&1 ) {
nkeynes@375
  1561
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1562
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1563
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1564
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1565
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1566
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1567
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1568
	}
nkeynes@380
  1569
	JMP_TARGET(end);
nkeynes@375
  1570
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1571
	if( FRn&1 ) {
nkeynes@386
  1572
	    JMP_rel8(24, end);
nkeynes@375
  1573
	    load_xf_bank( R_ECX );
nkeynes@375
  1574
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1575
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1576
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1577
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1578
	    JMP_TARGET(end);
nkeynes@375
  1579
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1580
	    JMP_rel8(12, end);
nkeynes@375
  1581
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1582
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1583
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1584
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1585
	    JMP_TARGET(end);
nkeynes@375
  1586
	}
nkeynes@375
  1587
    }
nkeynes@375
  1588
:}
nkeynes@416
  1589
FMOV FRm, @Rn {: 
nkeynes@416
  1590
    precheck();
nkeynes@416
  1591
    check_fpuen_no_precheck();
nkeynes@416
  1592
    load_reg( R_ECX, Rn );
nkeynes@416
  1593
    check_walign32( R_ECX );
nkeynes@416
  1594
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1595
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1596
    JNE_rel8(20, doublesize);
nkeynes@416
  1597
    load_fr_bank( R_EDX );
nkeynes@416
  1598
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1599
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1600
    if( FRm&1 ) {
nkeynes@386
  1601
	JMP_rel8( 48, end );
nkeynes@380
  1602
	JMP_TARGET(doublesize);
nkeynes@416
  1603
	load_xf_bank( R_EDX );
nkeynes@416
  1604
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1605
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1606
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1607
	JMP_TARGET(end);
nkeynes@375
  1608
    } else {
nkeynes@380
  1609
	JMP_rel8( 39, end );
nkeynes@380
  1610
	JMP_TARGET(doublesize);
nkeynes@416
  1611
	load_fr_bank( R_EDX );
nkeynes@416
  1612
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1613
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1614
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1615
	JMP_TARGET(end);
nkeynes@375
  1616
    }
nkeynes@375
  1617
:}
nkeynes@375
  1618
FMOV @Rm, FRn {:  
nkeynes@416
  1619
    precheck();
nkeynes@416
  1620
    check_fpuen_no_precheck();
nkeynes@416
  1621
    load_reg( R_ECX, Rm );
nkeynes@416
  1622
    check_ralign32( R_ECX );
nkeynes@416
  1623
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1624
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1625
    JNE_rel8(19, doublesize);
nkeynes@416
  1626
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1627
    load_fr_bank( R_EDX );
nkeynes@416
  1628
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1629
    if( FRn&1 ) {
nkeynes@386
  1630
	JMP_rel8(48, end);
nkeynes@380
  1631
	JMP_TARGET(doublesize);
nkeynes@416
  1632
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1633
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1634
	load_xf_bank( R_EDX );
nkeynes@416
  1635
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1636
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1637
	JMP_TARGET(end);
nkeynes@375
  1638
    } else {
nkeynes@380
  1639
	JMP_rel8(36, end);
nkeynes@380
  1640
	JMP_TARGET(doublesize);
nkeynes@416
  1641
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1642
	load_fr_bank( R_EDX );
nkeynes@416
  1643
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1644
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1645
	JMP_TARGET(end);
nkeynes@375
  1646
    }
nkeynes@375
  1647
:}
nkeynes@377
  1648
FMOV FRm, @-Rn {:  
nkeynes@416
  1649
    precheck();
nkeynes@416
  1650
    check_fpuen_no_precheck();
nkeynes@416
  1651
    load_reg( R_ECX, Rn );
nkeynes@416
  1652
    check_walign32( R_ECX );
nkeynes@416
  1653
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1654
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@382
  1655
    JNE_rel8(26, doublesize);
nkeynes@416
  1656
    load_fr_bank( R_EDX );
nkeynes@416
  1657
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1658
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1659
    store_reg( R_ECX, Rn );
nkeynes@416
  1660
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1661
    if( FRm&1 ) {
nkeynes@386
  1662
	JMP_rel8( 54, end );
nkeynes@380
  1663
	JMP_TARGET(doublesize);
nkeynes@416
  1664
	load_xf_bank( R_EDX );
nkeynes@416
  1665
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1666
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1667
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1668
	store_reg( R_ECX, Rn );
nkeynes@416
  1669
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1670
	JMP_TARGET(end);
nkeynes@377
  1671
    } else {
nkeynes@382
  1672
	JMP_rel8( 45, end );
nkeynes@380
  1673
	JMP_TARGET(doublesize);
nkeynes@416
  1674
	load_fr_bank( R_EDX );
nkeynes@416
  1675
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1676
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1677
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1678
	store_reg( R_ECX, Rn );
nkeynes@416
  1679
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1680
	JMP_TARGET(end);
nkeynes@377
  1681
    }
nkeynes@377
  1682
:}
nkeynes@416
  1683
FMOV @Rm+, FRn {:
nkeynes@416
  1684
    precheck();
nkeynes@416
  1685
    check_fpuen_no_precheck();
nkeynes@416
  1686
    load_reg( R_ECX, Rm );
nkeynes@416
  1687
    check_ralign32( R_ECX );
nkeynes@416
  1688
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1689
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1690
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1691
    JNE_rel8(25, doublesize);
nkeynes@377
  1692
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1693
    store_reg( R_EAX, Rm );
nkeynes@416
  1694
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1695
    load_fr_bank( R_EDX );
nkeynes@416
  1696
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1697
    if( FRn&1 ) {
nkeynes@386
  1698
	JMP_rel8(54, end);
nkeynes@380
  1699
	JMP_TARGET(doublesize);
nkeynes@377
  1700
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1701
	store_reg(R_EAX, Rm);
nkeynes@416
  1702
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1703
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1704
	load_xf_bank( R_EDX );
nkeynes@416
  1705
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1706
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1707
	JMP_TARGET(end);
nkeynes@377
  1708
    } else {
nkeynes@380
  1709
	JMP_rel8(42, end);
nkeynes@377
  1710
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1711
	store_reg(R_EAX, Rm);
nkeynes@416
  1712
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1713
	load_fr_bank( R_EDX );
nkeynes@416
  1714
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1715
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1716
	JMP_TARGET(end);
nkeynes@377
  1717
    }
nkeynes@377
  1718
:}
nkeynes@377
  1719
FMOV FRm, @(R0, Rn) {:  
nkeynes@416
  1720
    precheck();
nkeynes@416
  1721
    check_fpuen_no_precheck();
nkeynes@416
  1722
    load_reg( R_ECX, Rn );
nkeynes@416
  1723
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1724
    check_walign32( R_ECX );
nkeynes@416
  1725
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1726
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1727
    JNE_rel8(20, doublesize);
nkeynes@416
  1728
    load_fr_bank( R_EDX );
nkeynes@416
  1729
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1730
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1731
    if( FRm&1 ) {
nkeynes@386
  1732
	JMP_rel8( 48, end );
nkeynes@380
  1733
	JMP_TARGET(doublesize);
nkeynes@416
  1734
	load_xf_bank( R_EDX );
nkeynes@416
  1735
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1736
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1737
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1738
	JMP_TARGET(end);
nkeynes@377
  1739
    } else {
nkeynes@380
  1740
	JMP_rel8( 39, end );
nkeynes@380
  1741
	JMP_TARGET(doublesize);
nkeynes@416
  1742
	load_fr_bank( R_EDX );
nkeynes@416
  1743
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1744
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1745
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1746
	JMP_TARGET(end);
nkeynes@377
  1747
    }
nkeynes@377
  1748
:}
nkeynes@377
  1749
FMOV @(R0, Rm), FRn {:  
nkeynes@416
  1750
    precheck();
nkeynes@416
  1751
    check_fpuen_no_precheck();
nkeynes@416
  1752
    load_reg( R_ECX, Rm );
nkeynes@416
  1753
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1754
    check_ralign32( R_ECX );
nkeynes@416
  1755
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1756
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1757
    JNE_rel8(19, doublesize);
nkeynes@416
  1758
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1759
    load_fr_bank( R_EDX );
nkeynes@416
  1760
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1761
    if( FRn&1 ) {
nkeynes@386
  1762
	JMP_rel8(48, end);
nkeynes@380
  1763
	JMP_TARGET(doublesize);
nkeynes@416
  1764
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1765
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1766
	load_xf_bank( R_EDX );
nkeynes@416
  1767
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1768
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1769
	JMP_TARGET(end);
nkeynes@377
  1770
    } else {
nkeynes@380
  1771
	JMP_rel8(36, end);
nkeynes@380
  1772
	JMP_TARGET(doublesize);
nkeynes@416
  1773
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1774
	load_fr_bank( R_EDX );
nkeynes@416
  1775
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1776
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1777
	JMP_TARGET(end);
nkeynes@377
  1778
    }
nkeynes@377
  1779
:}
nkeynes@377
  1780
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1781
    check_fpuen();
nkeynes@377
  1782
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1783
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1784
    JNE_rel8(8, end);
nkeynes@377
  1785
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1786
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1787
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1788
    JMP_TARGET(end);
nkeynes@377
  1789
:}
nkeynes@377
  1790
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1791
    check_fpuen();
nkeynes@377
  1792
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1793
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1794
    JNE_rel8(11, end);
nkeynes@377
  1795
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1796
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1797
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1798
    JMP_TARGET(end);
nkeynes@377
  1799
:}
nkeynes@377
  1800
nkeynes@377
  1801
FLOAT FPUL, FRn {:  
nkeynes@377
  1802
    check_fpuen();
nkeynes@377
  1803
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1804
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1805
    FILD_sh4r(R_FPUL);
nkeynes@377
  1806
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1807
    JNE_rel8(5, doubleprec);
nkeynes@377
  1808
    pop_fr( R_EDX, FRn );
nkeynes@380
  1809
    JMP_rel8(3, end);
nkeynes@380
  1810
    JMP_TARGET(doubleprec);
nkeynes@377
  1811
    pop_dr( R_EDX, FRn );
nkeynes@380
  1812
    JMP_TARGET(end);
nkeynes@377
  1813
:}
nkeynes@377
  1814
FTRC FRm, FPUL {:  
nkeynes@377
  1815
    check_fpuen();
nkeynes@388
  1816
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1817
    load_fr_bank( R_EDX );
nkeynes@388
  1818
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1819
    JNE_rel8(5, doubleprec);
nkeynes@388
  1820
    push_fr( R_EDX, FRm );
nkeynes@388
  1821
    JMP_rel8(3, doop);
nkeynes@388
  1822
    JMP_TARGET(doubleprec);
nkeynes@388
  1823
    push_dr( R_EDX, FRm );
nkeynes@388
  1824
    JMP_TARGET( doop );
nkeynes@388
  1825
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1826
    FILD_r32ind( R_ECX );
nkeynes@388
  1827
    FCOMIP_st(1);
nkeynes@394
  1828
    JNA_rel8( 32, sat );
nkeynes@388
  1829
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1830
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1831
    FCOMIP_st(1);                   // 2
nkeynes@394
  1832
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1833
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1834
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1835
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1836
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1837
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1838
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1839
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1840
nkeynes@388
  1841
    JMP_TARGET(sat);
nkeynes@388
  1842
    JMP_TARGET(sat2);
nkeynes@388
  1843
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1844
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1845
    FPOP_st();
nkeynes@388
  1846
    JMP_TARGET(end);
nkeynes@377
  1847
:}
nkeynes@377
  1848
FLDS FRm, FPUL {:  
nkeynes@377
  1849
    check_fpuen();
nkeynes@377
  1850
    load_fr_bank( R_ECX );
nkeynes@377
  1851
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1852
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1853
:}
nkeynes@377
  1854
FSTS FPUL, FRn {:  
nkeynes@377
  1855
    check_fpuen();
nkeynes@377
  1856
    load_fr_bank( R_ECX );
nkeynes@377
  1857
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1858
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1859
:}
nkeynes@377
  1860
FCNVDS FRm, FPUL {:  
nkeynes@377
  1861
    check_fpuen();
nkeynes@377
  1862
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1863
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1864
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1865
    load_fr_bank( R_ECX );
nkeynes@377
  1866
    push_dr( R_ECX, FRm );
nkeynes@377
  1867
    pop_fpul();
nkeynes@380
  1868
    JMP_TARGET(end);
nkeynes@377
  1869
:}
nkeynes@377
  1870
FCNVSD FPUL, FRn {:  
nkeynes@377
  1871
    check_fpuen();
nkeynes@377
  1872
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1873
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1874
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1875
    load_fr_bank( R_ECX );
nkeynes@377
  1876
    push_fpul();
nkeynes@377
  1877
    pop_dr( R_ECX, FRn );
nkeynes@380
  1878
    JMP_TARGET(end);
nkeynes@377
  1879
:}
nkeynes@375
  1880
nkeynes@359
  1881
/* Floating point instructions */
nkeynes@374
  1882
FABS FRn {:  
nkeynes@377
  1883
    check_fpuen();
nkeynes@374
  1884
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1885
    load_fr_bank( R_EDX );
nkeynes@374
  1886
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1887
    JNE_rel8(10, doubleprec);
nkeynes@374
  1888
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1889
    FABS_st0(); // 2
nkeynes@374
  1890
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1891
    JMP_rel8(8,end); // 2
nkeynes@380
  1892
    JMP_TARGET(doubleprec);
nkeynes@374
  1893
    push_dr(R_EDX, FRn);
nkeynes@374
  1894
    FABS_st0();
nkeynes@374
  1895
    pop_dr(R_EDX, FRn);
nkeynes@380
  1896
    JMP_TARGET(end);
nkeynes@374
  1897
:}
nkeynes@377
  1898
FADD FRm, FRn {:  
nkeynes@377
  1899
    check_fpuen();
nkeynes@375
  1900
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1901
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1902
    load_fr_bank( R_EDX );
nkeynes@380
  1903
    JNE_rel8(13,doubleprec);
nkeynes@377
  1904
    push_fr(R_EDX, FRm);
nkeynes@377
  1905
    push_fr(R_EDX, FRn);
nkeynes@377
  1906
    FADDP_st(1);
nkeynes@377
  1907
    pop_fr(R_EDX, FRn);
nkeynes@380
  1908
    JMP_rel8(11,end);
nkeynes@380
  1909
    JMP_TARGET(doubleprec);
nkeynes@377
  1910
    push_dr(R_EDX, FRm);
nkeynes@377
  1911
    push_dr(R_EDX, FRn);
nkeynes@377
  1912
    FADDP_st(1);
nkeynes@377
  1913
    pop_dr(R_EDX, FRn);
nkeynes@380
  1914
    JMP_TARGET(end);
nkeynes@375
  1915
:}
nkeynes@377
  1916
FDIV FRm, FRn {:  
nkeynes@377
  1917
    check_fpuen();
nkeynes@375
  1918
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1919
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1920
    load_fr_bank( R_EDX );
nkeynes@380
  1921
    JNE_rel8(13, doubleprec);
nkeynes@377
  1922
    push_fr(R_EDX, FRn);
nkeynes@377
  1923
    push_fr(R_EDX, FRm);
nkeynes@377
  1924
    FDIVP_st(1);
nkeynes@377
  1925
    pop_fr(R_EDX, FRn);
nkeynes@380
  1926
    JMP_rel8(11, end);
nkeynes@380
  1927
    JMP_TARGET(doubleprec);
nkeynes@377
  1928
    push_dr(R_EDX, FRn);
nkeynes@377
  1929
    push_dr(R_EDX, FRm);
nkeynes@377
  1930
    FDIVP_st(1);
nkeynes@377
  1931
    pop_dr(R_EDX, FRn);
nkeynes@380
  1932
    JMP_TARGET(end);
nkeynes@375
  1933
:}
nkeynes@375
  1934
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1935
    check_fpuen();
nkeynes@375
  1936
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1937
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1938
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1939
    JNE_rel8(18, doubleprec);
nkeynes@375
  1940
    push_fr( R_EDX, 0 );
nkeynes@375
  1941
    push_fr( R_EDX, FRm );
nkeynes@375
  1942
    FMULP_st(1);
nkeynes@375
  1943
    push_fr( R_EDX, FRn );
nkeynes@375
  1944
    FADDP_st(1);
nkeynes@375
  1945
    pop_fr( R_EDX, FRn );
nkeynes@380
  1946
    JMP_rel8(16, end);
nkeynes@380
  1947
    JMP_TARGET(doubleprec);
nkeynes@375
  1948
    push_dr( R_EDX, 0 );
nkeynes@375
  1949
    push_dr( R_EDX, FRm );
nkeynes@375
  1950
    FMULP_st(1);
nkeynes@375
  1951
    push_dr( R_EDX, FRn );
nkeynes@375
  1952
    FADDP_st(1);
nkeynes@375
  1953
    pop_dr( R_EDX, FRn );
nkeynes@380
  1954
    JMP_TARGET(end);
nkeynes@375
  1955
:}
nkeynes@375
  1956
nkeynes@377
  1957
FMUL FRm, FRn {:  
nkeynes@377
  1958
    check_fpuen();
nkeynes@377
  1959
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1960
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1961
    load_fr_bank( R_EDX );
nkeynes@380
  1962
    JNE_rel8(13, doubleprec);
nkeynes@377
  1963
    push_fr(R_EDX, FRm);
nkeynes@377
  1964
    push_fr(R_EDX, FRn);
nkeynes@377
  1965
    FMULP_st(1);
nkeynes@377
  1966
    pop_fr(R_EDX, FRn);
nkeynes@380
  1967
    JMP_rel8(11, end);
nkeynes@380
  1968
    JMP_TARGET(doubleprec);
nkeynes@377
  1969
    push_dr(R_EDX, FRm);
nkeynes@377
  1970
    push_dr(R_EDX, FRn);
nkeynes@377
  1971
    FMULP_st(1);
nkeynes@377
  1972
    pop_dr(R_EDX, FRn);
nkeynes@380
  1973
    JMP_TARGET(end);
nkeynes@377
  1974
:}
nkeynes@377
  1975
FNEG FRn {:  
nkeynes@377
  1976
    check_fpuen();
nkeynes@377
  1977
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1978
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1979
    load_fr_bank( R_EDX );
nkeynes@380
  1980
    JNE_rel8(10, doubleprec);
nkeynes@377
  1981
    push_fr(R_EDX, FRn);
nkeynes@377
  1982
    FCHS_st0();
nkeynes@377
  1983
    pop_fr(R_EDX, FRn);
nkeynes@380
  1984
    JMP_rel8(8, end);
nkeynes@380
  1985
    JMP_TARGET(doubleprec);
nkeynes@377
  1986
    push_dr(R_EDX, FRn);
nkeynes@377
  1987
    FCHS_st0();
nkeynes@377
  1988
    pop_dr(R_EDX, FRn);
nkeynes@380
  1989
    JMP_TARGET(end);
nkeynes@377
  1990
:}
nkeynes@377
  1991
FSRRA FRn {:  
nkeynes@377
  1992
    check_fpuen();
nkeynes@377
  1993
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1994
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1995
    load_fr_bank( R_EDX );
nkeynes@380
  1996
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1997
    FLD1_st0();
nkeynes@377
  1998
    push_fr(R_EDX, FRn);
nkeynes@377
  1999
    FSQRT_st0();
nkeynes@377
  2000
    FDIVP_st(1);
nkeynes@377
  2001
    pop_fr(R_EDX, FRn);
nkeynes@380
  2002
    JMP_TARGET(end);
nkeynes@377
  2003
:}
nkeynes@377
  2004
FSQRT FRn {:  
nkeynes@377
  2005
    check_fpuen();
nkeynes@377
  2006
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2007
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2008
    load_fr_bank( R_EDX );
nkeynes@380
  2009
    JNE_rel8(10, doubleprec);
nkeynes@377
  2010
    push_fr(R_EDX, FRn);
nkeynes@377
  2011
    FSQRT_st0();
nkeynes@377
  2012
    pop_fr(R_EDX, FRn);
nkeynes@380
  2013
    JMP_rel8(8, end);
nkeynes@380
  2014
    JMP_TARGET(doubleprec);
nkeynes@377
  2015
    push_dr(R_EDX, FRn);
nkeynes@377
  2016
    FSQRT_st0();
nkeynes@377
  2017
    pop_dr(R_EDX, FRn);
nkeynes@380
  2018
    JMP_TARGET(end);
nkeynes@377
  2019
:}
nkeynes@377
  2020
FSUB FRm, FRn {:  
nkeynes@377
  2021
    check_fpuen();
nkeynes@377
  2022
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2023
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2024
    load_fr_bank( R_EDX );
nkeynes@380
  2025
    JNE_rel8(13, doubleprec);
nkeynes@377
  2026
    push_fr(R_EDX, FRn);
nkeynes@377
  2027
    push_fr(R_EDX, FRm);
nkeynes@388
  2028
    FSUBP_st(1);
nkeynes@377
  2029
    pop_fr(R_EDX, FRn);
nkeynes@380
  2030
    JMP_rel8(11, end);
nkeynes@380
  2031
    JMP_TARGET(doubleprec);
nkeynes@377
  2032
    push_dr(R_EDX, FRn);
nkeynes@377
  2033
    push_dr(R_EDX, FRm);
nkeynes@388
  2034
    FSUBP_st(1);
nkeynes@377
  2035
    pop_dr(R_EDX, FRn);
nkeynes@380
  2036
    JMP_TARGET(end);
nkeynes@377
  2037
:}
nkeynes@377
  2038
nkeynes@377
  2039
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2040
    check_fpuen();
nkeynes@377
  2041
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2042
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2043
    load_fr_bank( R_EDX );
nkeynes@380
  2044
    JNE_rel8(8, doubleprec);
nkeynes@377
  2045
    push_fr(R_EDX, FRm);
nkeynes@377
  2046
    push_fr(R_EDX, FRn);
nkeynes@380
  2047
    JMP_rel8(6, end);
nkeynes@380
  2048
    JMP_TARGET(doubleprec);
nkeynes@377
  2049
    push_dr(R_EDX, FRm);
nkeynes@377
  2050
    push_dr(R_EDX, FRn);
nkeynes@382
  2051
    JMP_TARGET(end);
nkeynes@377
  2052
    FCOMIP_st(1);
nkeynes@377
  2053
    SETE_t();
nkeynes@377
  2054
    FPOP_st();
nkeynes@377
  2055
:}
nkeynes@377
  2056
FCMP/GT FRm, FRn {:  
nkeynes@377
  2057
    check_fpuen();
nkeynes@377
  2058
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2059
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2060
    load_fr_bank( R_EDX );
nkeynes@380
  2061
    JNE_rel8(8, doubleprec);
nkeynes@377
  2062
    push_fr(R_EDX, FRm);
nkeynes@377
  2063
    push_fr(R_EDX, FRn);
nkeynes@380
  2064
    JMP_rel8(6, end);
nkeynes@380
  2065
    JMP_TARGET(doubleprec);
nkeynes@377
  2066
    push_dr(R_EDX, FRm);
nkeynes@377
  2067
    push_dr(R_EDX, FRn);
nkeynes@380
  2068
    JMP_TARGET(end);
nkeynes@377
  2069
    FCOMIP_st(1);
nkeynes@377
  2070
    SETA_t();
nkeynes@377
  2071
    FPOP_st();
nkeynes@377
  2072
:}
nkeynes@377
  2073
nkeynes@377
  2074
FSCA FPUL, FRn {:  
nkeynes@377
  2075
    check_fpuen();
nkeynes@388
  2076
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2077
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2078
    JNE_rel8( 21, doubleprec );
nkeynes@388
  2079
    load_fr_bank( R_ECX );
nkeynes@388
  2080
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2081
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2082
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2083
    JMP_TARGET(doubleprec);
nkeynes@377
  2084
:}
nkeynes@377
  2085
FIPR FVm, FVn {:  
nkeynes@377
  2086
    check_fpuen();
nkeynes@388
  2087
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2088
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2089
    JNE_rel8(44, doubleprec);
nkeynes@388
  2090
    
nkeynes@388
  2091
    load_fr_bank( R_ECX );
nkeynes@388
  2092
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2093
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2094
    FMULP_st(1);
nkeynes@388
  2095
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2096
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2097
    FMULP_st(1);
nkeynes@388
  2098
    FADDP_st(1);
nkeynes@388
  2099
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2100
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2101
    FMULP_st(1);
nkeynes@388
  2102
    FADDP_st(1);
nkeynes@388
  2103
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2104
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2105
    FMULP_st(1);
nkeynes@388
  2106
    FADDP_st(1);
nkeynes@388
  2107
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2108
    JMP_TARGET(doubleprec);
nkeynes@377
  2109
:}
nkeynes@377
  2110
FTRV XMTRX, FVn {:  
nkeynes@377
  2111
    check_fpuen();
nkeynes@388
  2112
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2113
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2114
    JNE_rel8( 30, doubleprec );
nkeynes@388
  2115
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2116
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2117
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2118
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2119
    JMP_TARGET(doubleprec);
nkeynes@377
  2120
:}
nkeynes@377
  2121
nkeynes@377
  2122
FRCHG {:  
nkeynes@377
  2123
    check_fpuen();
nkeynes@377
  2124
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2125
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2126
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2127
    update_fr_bank( R_ECX );
nkeynes@377
  2128
:}
nkeynes@377
  2129
FSCHG {:  
nkeynes@377
  2130
    check_fpuen();
nkeynes@377
  2131
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2132
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2133
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2134
:}
nkeynes@359
  2135
nkeynes@359
  2136
/* Processor control instructions */
nkeynes@368
  2137
LDC Rm, SR {:
nkeynes@386
  2138
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2139
	SLOTILLEGAL();
nkeynes@386
  2140
    } else {
nkeynes@386
  2141
	check_priv();
nkeynes@386
  2142
	load_reg( R_EAX, Rm );
nkeynes@386
  2143
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2144
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2145
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2146
    }
nkeynes@368
  2147
:}
nkeynes@359
  2148
LDC Rm, GBR {: 
nkeynes@359
  2149
    load_reg( R_EAX, Rm );
nkeynes@359
  2150
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2151
:}
nkeynes@359
  2152
LDC Rm, VBR {:  
nkeynes@386
  2153
    check_priv();
nkeynes@359
  2154
    load_reg( R_EAX, Rm );
nkeynes@359
  2155
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2156
:}
nkeynes@359
  2157
LDC Rm, SSR {:  
nkeynes@386
  2158
    check_priv();
nkeynes@359
  2159
    load_reg( R_EAX, Rm );
nkeynes@359
  2160
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2161
:}
nkeynes@359
  2162
LDC Rm, SGR {:  
nkeynes@386
  2163
    check_priv();
nkeynes@359
  2164
    load_reg( R_EAX, Rm );
nkeynes@359
  2165
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2166
:}
nkeynes@359
  2167
LDC Rm, SPC {:  
nkeynes@386
  2168
    check_priv();
nkeynes@359
  2169
    load_reg( R_EAX, Rm );
nkeynes@359
  2170
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2171
:}
nkeynes@359
  2172
LDC Rm, DBR {:  
nkeynes@386
  2173
    check_priv();
nkeynes@359
  2174
    load_reg( R_EAX, Rm );
nkeynes@359
  2175
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2176
:}
nkeynes@374
  2177
LDC Rm, Rn_BANK {:  
nkeynes@386
  2178
    check_priv();
nkeynes@374
  2179
    load_reg( R_EAX, Rm );
nkeynes@374
  2180
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  2181
:}
nkeynes@359
  2182
LDC.L @Rm+, GBR {:  
nkeynes@359
  2183
    load_reg( R_EAX, Rm );
nkeynes@416
  2184
    precheck();
nkeynes@395
  2185
    check_ralign32( R_EAX );
nkeynes@359
  2186
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2187
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2188
    store_reg( R_EAX, Rm );
nkeynes@359
  2189
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2190
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2191
:}
nkeynes@368
  2192
LDC.L @Rm+, SR {:
nkeynes@386
  2193
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2194
	SLOTILLEGAL();
nkeynes@386
  2195
    } else {
nkeynes@416
  2196
	precheck();
nkeynes@416
  2197
	check_priv_no_precheck();
nkeynes@386
  2198
	load_reg( R_EAX, Rm );
nkeynes@395
  2199
	check_ralign32( R_EAX );
nkeynes@386
  2200
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2201
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2202
	store_reg( R_EAX, Rm );
nkeynes@386
  2203
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2204
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2205
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2206
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2207
    }
nkeynes@359
  2208
:}
nkeynes@359
  2209
LDC.L @Rm+, VBR {:  
nkeynes@416
  2210
    precheck();
nkeynes@416
  2211
    check_priv_no_precheck();
nkeynes@359
  2212
    load_reg( R_EAX, Rm );
nkeynes@395
  2213
    check_ralign32( R_EAX );
nkeynes@359
  2214
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2215
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2216
    store_reg( R_EAX, Rm );
nkeynes@359
  2217
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2218
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2219
:}
nkeynes@359
  2220
LDC.L @Rm+, SSR {:
nkeynes@416
  2221
    precheck();
nkeynes@416
  2222
    check_priv_no_precheck();
nkeynes@359
  2223
    load_reg( R_EAX, Rm );
nkeynes@416
  2224
    check_ralign32( R_EAX );
nkeynes@359
  2225
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2226
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2227
    store_reg( R_EAX, Rm );
nkeynes@359
  2228
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2229
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2230
:}
nkeynes@359
  2231
LDC.L @Rm+, SGR {:  
nkeynes@416
  2232
    precheck();
nkeynes@416
  2233
    check_priv_no_precheck();
nkeynes@359
  2234
    load_reg( R_EAX, Rm );
nkeynes@395
  2235
    check_ralign32( R_EAX );
nkeynes@359
  2236
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2237
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2238
    store_reg( R_EAX, Rm );
nkeynes@359
  2239
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2240
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2241
:}
nkeynes@359
  2242
LDC.L @Rm+, SPC {:  
nkeynes@416
  2243
    precheck();
nkeynes@416
  2244
    check_priv_no_precheck();
nkeynes@359
  2245
    load_reg( R_EAX, Rm );
nkeynes@395
  2246
    check_ralign32( R_EAX );
nkeynes@359
  2247
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2248
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2249
    store_reg( R_EAX, Rm );
nkeynes@359
  2250
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2251
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2252
:}
nkeynes@359
  2253
LDC.L @Rm+, DBR {:  
nkeynes@416
  2254
    precheck();
nkeynes@416
  2255
    check_priv_no_precheck();
nkeynes@359
  2256
    load_reg( R_EAX, Rm );
nkeynes@395
  2257
    check_ralign32( R_EAX );
nkeynes@359
  2258
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2259
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2260
    store_reg( R_EAX, Rm );
nkeynes@359
  2261
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2262
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2263
:}
nkeynes@359
  2264
LDC.L @Rm+, Rn_BANK {:  
nkeynes@416
  2265
    precheck();
nkeynes@416
  2266
    check_priv_no_precheck();
nkeynes@374
  2267
    load_reg( R_EAX, Rm );
nkeynes@395
  2268
    check_ralign32( R_EAX );
nkeynes@374
  2269
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2270
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2271
    store_reg( R_EAX, Rm );
nkeynes@374
  2272
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2273
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  2274
:}
nkeynes@359
  2275
LDS Rm, FPSCR {:  
nkeynes@359
  2276
    load_reg( R_EAX, Rm );
nkeynes@359
  2277
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2278
    update_fr_bank( R_EAX );
nkeynes@359
  2279
:}
nkeynes@359
  2280
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2281
    load_reg( R_EAX, Rm );
nkeynes@416
  2282
    precheck();
nkeynes@395
  2283
    check_ralign32( R_EAX );
nkeynes@359
  2284
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2285
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2286
    store_reg( R_EAX, Rm );
nkeynes@359
  2287
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2288
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2289
    update_fr_bank( R_EAX );
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDS Rm, FPUL {:  
nkeynes@359
  2292
    load_reg( R_EAX, Rm );
nkeynes@359
  2293
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2294
:}
nkeynes@359
  2295
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2296
    load_reg( R_EAX, Rm );
nkeynes@416
  2297
    precheck();
nkeynes@395
  2298
    check_ralign32( R_EAX );
nkeynes@359
  2299
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2300
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2301
    store_reg( R_EAX, Rm );
nkeynes@359
  2302
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2303
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2304
:}
nkeynes@359
  2305
LDS Rm, MACH {: 
nkeynes@359
  2306
    load_reg( R_EAX, Rm );
nkeynes@359
  2307
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2308
:}
nkeynes@359
  2309
LDS.L @Rm+, MACH {:  
nkeynes@359
  2310
    load_reg( R_EAX, Rm );
nkeynes@416
  2311
    precheck();
nkeynes@395
  2312
    check_ralign32( R_EAX );
nkeynes@359
  2313
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2314
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2315
    store_reg( R_EAX, Rm );
nkeynes@359
  2316
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2317
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2318
:}
nkeynes@359
  2319
LDS Rm, MACL {:  
nkeynes@359
  2320
    load_reg( R_EAX, Rm );
nkeynes@359
  2321
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2322
:}
nkeynes@359
  2323
LDS.L @Rm+, MACL {:  
nkeynes@359
  2324
    load_reg( R_EAX, Rm );
nkeynes@416
  2325
    precheck();
nkeynes@395
  2326
    check_ralign32( R_EAX );
nkeynes@359
  2327
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2328
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2329
    store_reg( R_EAX, Rm );
nkeynes@359
  2330
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2331
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2332
:}
nkeynes@359
  2333
LDS Rm, PR {:  
nkeynes@359
  2334
    load_reg( R_EAX, Rm );
nkeynes@359
  2335
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2336
:}
nkeynes@359
  2337
LDS.L @Rm+, PR {:  
nkeynes@359
  2338
    load_reg( R_EAX, Rm );
nkeynes@416
  2339
    precheck();
nkeynes@395
  2340
    check_ralign32( R_EAX );
nkeynes@359
  2341
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2342
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2343
    store_reg( R_EAX, Rm );
nkeynes@359
  2344
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2345
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2346
:}
nkeynes@359
  2347
LDTLB {:  :}
nkeynes@359
  2348
OCBI @Rn {:  :}
nkeynes@359
  2349
OCBP @Rn {:  :}
nkeynes@359
  2350
OCBWB @Rn {:  :}
nkeynes@374
  2351
PREF @Rn {:
nkeynes@374
  2352
    load_reg( R_EAX, Rn );
nkeynes@374
  2353
    PUSH_r32( R_EAX );
nkeynes@374
  2354
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2355
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2356
    JNE_rel8(7, end);
nkeynes@374
  2357
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2358
    JMP_TARGET(end);
nkeynes@377
  2359
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2360
:}
nkeynes@388
  2361
SLEEP {: 
nkeynes@388
  2362
    check_priv();
nkeynes@388
  2363
    call_func0( sh4_sleep );
nkeynes@388
  2364
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2365
    return 2;
nkeynes@388
  2366
:}
nkeynes@386
  2367
STC SR, Rn {:
nkeynes@386
  2368
    check_priv();
nkeynes@386
  2369
    call_func0(sh4_read_sr);
nkeynes@386
  2370
    store_reg( R_EAX, Rn );
nkeynes@359
  2371
:}
nkeynes@359
  2372
STC GBR, Rn {:  
nkeynes@359
  2373
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2374
    store_reg( R_EAX, Rn );
nkeynes@359
  2375
:}
nkeynes@359
  2376
STC VBR, Rn {:  
nkeynes@386
  2377
    check_priv();
nkeynes@359
  2378
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2379
    store_reg( R_EAX, Rn );
nkeynes@359
  2380
:}
nkeynes@359
  2381
STC SSR, Rn {:  
nkeynes@386
  2382
    check_priv();
nkeynes@359
  2383
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2384
    store_reg( R_EAX, Rn );
nkeynes@359
  2385
:}
nkeynes@359
  2386
STC SPC, Rn {:  
nkeynes@386
  2387
    check_priv();
nkeynes@359
  2388
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2389
    store_reg( R_EAX, Rn );
nkeynes@359
  2390
:}
nkeynes@359
  2391
STC SGR, Rn {:  
nkeynes@386
  2392
    check_priv();
nkeynes@359
  2393
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2394
    store_reg( R_EAX, Rn );
nkeynes@359
  2395
:}
nkeynes@359
  2396
STC DBR, Rn {:  
nkeynes@386
  2397
    check_priv();
nkeynes@359
  2398
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2399
    store_reg( R_EAX, Rn );
nkeynes@359
  2400
:}
nkeynes@374
  2401
STC Rm_BANK, Rn {:
nkeynes@386
  2402
    check_priv();
nkeynes@374
  2403
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2404
    store_reg( R_EAX, Rn );
nkeynes@359
  2405
:}
nkeynes@374
  2406
STC.L SR, @-Rn {:
nkeynes@416
  2407
    precheck();
nkeynes@416
  2408
    check_priv_no_precheck();
nkeynes@395
  2409
    call_func0( sh4_read_sr );
nkeynes@368
  2410
    load_reg( R_ECX, Rn );
nkeynes@395
  2411
    check_walign32( R_ECX );
nkeynes@382
  2412
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2413
    store_reg( R_ECX, Rn );
nkeynes@368
  2414
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2415
:}
nkeynes@359
  2416
STC.L VBR, @-Rn {:  
nkeynes@416
  2417
    precheck();
nkeynes@416
  2418
    check_priv_no_precheck();
nkeynes@359
  2419
    load_reg( R_ECX, Rn );
nkeynes@395
  2420
    check_walign32( R_ECX );
nkeynes@382
  2421
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2422
    store_reg( R_ECX, Rn );
nkeynes@359
  2423
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2424
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2425
:}
nkeynes@359
  2426
STC.L SSR, @-Rn {:  
nkeynes@416
  2427
    precheck();
nkeynes@416
  2428
    check_priv_no_precheck();
nkeynes@359
  2429
    load_reg( R_ECX, Rn );
nkeynes@395
  2430
    check_walign32( R_ECX );
nkeynes@382
  2431
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2432
    store_reg( R_ECX, Rn );
nkeynes@359
  2433
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2434
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2435
:}
nkeynes@416
  2436
STC.L SPC, @-Rn {:
nkeynes@416
  2437
    precheck();
nkeynes@416
  2438
    check_priv_no_precheck();
nkeynes@359
  2439
    load_reg( R_ECX, Rn );
nkeynes@395
  2440
    check_walign32( R_ECX );
nkeynes@382
  2441
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2442
    store_reg( R_ECX, Rn );
nkeynes@359
  2443
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2444
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2445
:}
nkeynes@359
  2446
STC.L SGR, @-Rn {:  
nkeynes@416
  2447
    precheck();
nkeynes@416
  2448
    check_priv_no_precheck();
nkeynes@359
  2449
    load_reg( R_ECX, Rn );
nkeynes@395
  2450
    check_walign32( R_ECX );
nkeynes@382
  2451
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2452
    store_reg( R_ECX, Rn );
nkeynes@359
  2453
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2454
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2455
:}
nkeynes@359
  2456
STC.L DBR, @-Rn {:  
nkeynes@416
  2457
    precheck();
nkeynes@416
  2458
    check_priv_no_precheck();
nkeynes@359
  2459
    load_reg( R_ECX, Rn );
nkeynes@395
  2460
    check_walign32( R_ECX );
nkeynes@382
  2461
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2462
    store_reg( R_ECX, Rn );
nkeynes@359
  2463
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2464
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2465
:}
nkeynes@374
  2466
STC.L Rm_BANK, @-Rn {:  
nkeynes@416
  2467
    precheck();
nkeynes@416
  2468
    check_priv_no_precheck();
nkeynes@374
  2469
    load_reg( R_ECX, Rn );
nkeynes@395
  2470
    check_walign32( R_ECX );
nkeynes@382
  2471
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2472
    store_reg( R_ECX, Rn );
nkeynes@374
  2473
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2474
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2475
:}
nkeynes@359
  2476
STC.L GBR, @-Rn {:  
nkeynes@359
  2477
    load_reg( R_ECX, Rn );
nkeynes@416
  2478
    precheck();
nkeynes@395
  2479
    check_walign32( R_ECX );
nkeynes@382
  2480
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2481
    store_reg( R_ECX, Rn );
nkeynes@359
  2482
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2483
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2484
:}
nkeynes@359
  2485
STS FPSCR, Rn {:  
nkeynes@359
  2486
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2487
    store_reg( R_EAX, Rn );
nkeynes@359
  2488
:}
nkeynes@359
  2489
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2490
    load_reg( R_ECX, Rn );
nkeynes@416
  2491
    precheck();
nkeynes@395
  2492
    check_walign32( R_ECX );
nkeynes@382
  2493
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2494
    store_reg( R_ECX, Rn );
nkeynes@359
  2495
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2496
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2497
:}
nkeynes@359
  2498
STS FPUL, Rn {:  
nkeynes@359
  2499
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2500
    store_reg( R_EAX, Rn );
nkeynes@359
  2501
:}
nkeynes@359
  2502
STS.L FPUL, @-Rn {:  
nkeynes@359
  2503
    load_reg( R_ECX, Rn );
nkeynes@416
  2504
    precheck();
nkeynes@395
  2505
    check_walign32( R_ECX );
nkeynes@382
  2506
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2507
    store_reg( R_ECX, Rn );
nkeynes@359
  2508
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2509
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2510
:}
nkeynes@359
  2511
STS MACH, Rn {:  
nkeynes@359
  2512
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2513
    store_reg( R_EAX, Rn );
nkeynes@359
  2514
:}
nkeynes@359
  2515
STS.L MACH, @-Rn {:  
nkeynes@359
  2516
    load_reg( R_ECX, Rn );
nkeynes@416
  2517
    precheck();
nkeynes@395
  2518
    check_walign32( R_ECX );
nkeynes@382
  2519
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2520
    store_reg( R_ECX, Rn );
nkeynes@359
  2521
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2522
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2523
:}
nkeynes@359
  2524
STS MACL, Rn {:  
nkeynes@359
  2525
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2526
    store_reg( R_EAX, Rn );
nkeynes@359
  2527
:}
nkeynes@359
  2528
STS.L MACL, @-Rn {:  
nkeynes@359
  2529
    load_reg( R_ECX, Rn );
nkeynes@416
  2530
    precheck();
nkeynes@395
  2531
    check_walign32( R_ECX );
nkeynes@382
  2532
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2533
    store_reg( R_ECX, Rn );
nkeynes@359
  2534
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2535
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2536
:}
nkeynes@359
  2537
STS PR, Rn {:  
nkeynes@359
  2538
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2539
    store_reg( R_EAX, Rn );
nkeynes@359
  2540
:}
nkeynes@359
  2541
STS.L PR, @-Rn {:  
nkeynes@359
  2542
    load_reg( R_ECX, Rn );
nkeynes@416
  2543
    precheck();
nkeynes@395
  2544
    check_walign32( R_ECX );
nkeynes@382
  2545
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2546
    store_reg( R_ECX, Rn );
nkeynes@359
  2547
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2548
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2549
:}
nkeynes@359
  2550
nkeynes@359
  2551
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2552
%%
nkeynes@416
  2553
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2554
    return 0;
nkeynes@359
  2555
}
.