nkeynes@31 | 1 | /**
|
nkeynes@561 | 2 | * $Id$
|
nkeynes@31 | 3 | *
|
nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
|
nkeynes@31 | 5 | * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
|
nkeynes@31 | 6 | * although some functions (maple, ide) are implemented elsewhere.
|
nkeynes@31 | 7 | *
|
nkeynes@31 | 8 | * Copyright (c) 2005 Nathan Keynes.
|
nkeynes@31 | 9 | *
|
nkeynes@31 | 10 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@31 | 11 | * it under the terms of the GNU General Public License as published by
|
nkeynes@31 | 12 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@31 | 13 | * (at your option) any later version.
|
nkeynes@31 | 14 | *
|
nkeynes@31 | 15 | * This program is distributed in the hope that it will be useful,
|
nkeynes@31 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@31 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@31 | 18 | * GNU General Public License for more details.
|
nkeynes@31 | 19 | */
|
nkeynes@31 | 20 |
|
nkeynes@1 | 21 | #include "mmio.h"
|
nkeynes@1 | 22 |
|
nkeynes@1 | 23 | /**
|
nkeynes@1 | 24 | * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines.
|
nkeynes@1 | 25 | * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9.
|
nkeynes@1 | 26 | */
|
nkeynes@1 | 27 |
|
nkeynes@1 | 28 | MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" )
|
nkeynes@56 | 29 | LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
|
nkeynes@56 | 30 | LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
|
nkeynes@56 | 31 | LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
|
nkeynes@728 | 32 | LONG_PORT( 0x810, SORTDMATBL, PORT_MRW, 0, "Sort DMA Table address" )
|
nkeynes@728 | 33 | LONG_PORT( 0x814, SORTDMADATA, PORT_MRW, 0, "Sort DMA Data base address" )
|
nkeynes@728 | 34 | LONG_PORT( 0x818, SORTDMATSIZ, PORT_MRW, 0, "Sort DMA Table entry size" )
|
nkeynes@753 | 35 | LONG_PORT( 0x81C, SORTDMAASIZ, PORT_MRW, 0, "Sort DMA Table address size" )
|
nkeynes@728 | 36 | LONG_PORT( 0x820, SORTDMACTL, PORT_MRW, 0, "Sort DMA Control" )
|
nkeynes@147 | 37 | LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
|
nkeynes@147 | 38 | LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
|
nkeynes@147 | 39 | LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )
|
nkeynes@147 | 40 | LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
|
nkeynes@753 | 41 | LONG_PORT( 0x860, SORTDMACNT, PORT_MR, 0, "Sort DMA Transfer count" )
|
nkeynes@325 | 42 | LONG_PORT( 0x884, PVRDMARGN1, PORT_MRW, 0, "PVR DMA Dest region 1" )
|
nkeynes@325 | 43 | LONG_PORT( 0x888, PVRDMARGN2, PORT_MRW, 0, "PVR DMA Dest region 2" )
|
nkeynes@302 | 44 | LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0x0E, "G2 Fifo status" )
|
nkeynes@244 | 45 | LONG_PORT( 0x890, SYSRESET, PORT_W, 0, "System reset port" )
|
nkeynes@147 | 46 | LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )
|
nkeynes@147 | 47 | LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC <unknownC>" )
|
nkeynes@147 | 48 | LONG_PORT( 0x8A4, ASICUNKD, PORT_MRW, 0, "ASIC <unknownD>" )
|
nkeynes@147 | 49 | LONG_PORT( 0x8AC, ASICUNKE, PORT_MRW, 0, "ASIC <unknownE>" )
|
nkeynes@172 | 50 | LONG_PORT( 0x900, PIRQ0, PORT_MRW|PORT_NOTRACE, 0, "Pending interrupts 0" )
|
nkeynes@1 | 51 | LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
|
nkeynes@1 | 52 | LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
|
nkeynes@1 | 53 | LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" )
|
nkeynes@1 | 54 | LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" )
|
nkeynes@1 | 55 | LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" )
|
nkeynes@1 | 56 | LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" )
|
nkeynes@1 | 57 | LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" )
|
nkeynes@1 | 58 | LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" )
|
nkeynes@1 | 59 | LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" )
|
nkeynes@1 | 60 | LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" )
|
nkeynes@1 | 61 | LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" )
|
nkeynes@2 | 62 | LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" )
|
nkeynes@2 | 63 | LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" )
|
nkeynes@2 | 64 | LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" )
|
nkeynes@2 | 65 | LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" )
|
nkeynes@2 | 66 | /* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff
|
nkeynes@2 | 67 | * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff.
|
nkeynes@2 | 68 | * The whole region 800..8ff is long-readable, but since I so far have no idea
|
nkeynes@2 | 69 | * what any of it means (nor have I seen any of it accessed), they're not
|
nkeynes@2 | 70 | * listed above.
|
nkeynes@2 | 71 | */
|
nkeynes@56 | 72 |
|
nkeynes@1 | 73 |
|
nkeynes@1 | 74 | LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" )
|
nkeynes@1 | 75 | LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" )
|
nkeynes@1 | 76 | LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" )
|
nkeynes@1 | 77 | LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" )
|
nkeynes@2 | 78 | LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" )
|
nkeynes@2 | 79 | LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" )
|
nkeynes@2 | 80 | LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" )
|
nkeynes@2 | 81 | LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" )
|
nkeynes@1 | 82 | LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" )
|
nkeynes@2 | 83 | LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" )
|
nkeynes@1 | 84 | LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" )
|
nkeynes@2 | 85 | LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" )
|
nkeynes@2 | 86 | LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" )
|
nkeynes@2 | 87 | LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" )
|
nkeynes@2 | 88 | LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" )
|
nkeynes@2 | 89 | /* Note: Maple registers repeat at 0xD00..0xDFF,
|
nkeynes@2 | 90 | * 0xE00..0xEFF and 0xF00..0xFFF */
|
nkeynes@1 | 91 | MMIO_REGION_END
|
nkeynes@1 | 92 |
|
nkeynes@1 | 93 | MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" )
|
nkeynes@2 | 94 | BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */
|
nkeynes@2 | 95 | BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" )
|
nkeynes@2 | 96 | WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" )
|
nkeynes@2 | 97 | BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" )
|
nkeynes@2 | 98 | BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" )
|
nkeynes@2 | 99 | BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */
|
nkeynes@2 | 100 | BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */
|
nkeynes@2 | 101 | BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */
|
nkeynes@2 | 102 | BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" )
|
nkeynes@2 | 103 | BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" )
|
nkeynes@125 | 104 | LONG_PORT( 0x404, IDEDMASH4, PORT_MRW, 0, "IDE DMA SH4 address" )
|
nkeynes@125 | 105 | LONG_PORT( 0x408, IDEDMASIZ, PORT_MRW, 0, "IDE DMA Size" )
|
nkeynes@125 | 106 | LONG_PORT( 0x40C, IDEDMADIR, PORT_MRW, 0, "IDE DMA Direction" )
|
nkeynes@125 | 107 | LONG_PORT( 0x414, IDEDMACTL1, PORT_MRW, 0, "IDE DMA Control 1" )
|
nkeynes@125 | 108 | LONG_PORT( 0x418, IDEDMACTL2, PORT_MRW, 0, "IDE DMA Control 2" )
|
nkeynes@1 | 109 | WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" )
|
nkeynes@1 | 110 | LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" )
|
nkeynes@1 | 111 | LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" )
|
nkeynes@1 | 112 | LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA <unknown3>" )
|
nkeynes@1 | 113 | LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA <unknown4>" )
|
nkeynes@1 | 114 | LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA <unknown5>" )
|
nkeynes@1 | 115 | LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" )
|
nkeynes@1 | 116 | LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" )
|
nkeynes@1 | 117 | LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" )
|
nkeynes@172 | 118 | LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" ) /* 88437F00 */
|
nkeynes@2 | 119 | LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )
|
nkeynes@158 | 120 | LONG_PORT( 0x4F8, IDEDMATXSIZ, PORT_MRW, 0, "IDE DMA transfered size" )
|
nkeynes@302 | 121 | LONG_PORT( 0x800, G2DMA0EXT, PORT_MRW, 0, "G2 DMA0 External address" )
|
nkeynes@302 | 122 | LONG_PORT( 0x804, G2DMA0SH4, PORT_MRW, 0, "G2 DMA0 SH4-based address" )
|
nkeynes@302 | 123 | LONG_PORT( 0x808, G2DMA0SIZ, PORT_MRW, 0, "G2 DMA0 Size" )
|
nkeynes@302 | 124 | LONG_PORT( 0x80C, G2DMA0DIR, PORT_MRW, 0, "G2 DMA0 Direction" )
|
nkeynes@302 | 125 | LONG_PORT( 0x810, G2DMA0MOD, PORT_MRW, 0, "G2 DMA0 Mode" )
|
nkeynes@302 | 126 | LONG_PORT( 0x814, G2DMA0CTL1, PORT_MRW, 0, "G2 DMA0 Control 1" )
|
nkeynes@302 | 127 | LONG_PORT( 0x818, G2DMA0CTL2, PORT_MRW, 0, "G2 DMA0 Control 2" )
|
nkeynes@302 | 128 | LONG_PORT( 0x81C, G2DMA0STOP, PORT_MRW, 0x20, "G2 DMA0 Stop" )
|
nkeynes@302 | 129 | LONG_PORT( 0x820, G2DMA1EXT, PORT_MRW, 0, "G2 DMA1 External address" )
|
nkeynes@302 | 130 | LONG_PORT( 0x824, G2DMA1SH4, PORT_MRW, 0, "G2 DMA1 SH4-based address" )
|
nkeynes@302 | 131 | LONG_PORT( 0x828, G2DMA1SIZ, PORT_MRW, 0, "G2 DMA1 Size" )
|
nkeynes@302 | 132 | LONG_PORT( 0x82C, G2DMA1DIR, PORT_MRW, 0, "G2 DMA1 Direction" )
|
nkeynes@302 | 133 | LONG_PORT( 0x830, G2DMA1MOD, PORT_MRW, 0, "G2 DMA1 Mode" )
|
nkeynes@302 | 134 | LONG_PORT( 0x834, G2DMA1CTL1, PORT_MRW, 0, "G2 DMA1 Control 1" )
|
nkeynes@302 | 135 | LONG_PORT( 0x838, G2DMA1CTL2, PORT_MRW, 0, "G2 DMA1 Control 2" )
|
nkeynes@302 | 136 | LONG_PORT( 0x83C, G2DMA1STOP, PORT_MRW, 0, "G2 DMA1 Stop" )
|
nkeynes@302 | 137 | LONG_PORT( 0x840, G2DMA2EXT, PORT_MRW, 0, "G2 DMA2 External address" )
|
nkeynes@302 | 138 | LONG_PORT( 0x844, G2DMA2SH4, PORT_MRW, 0, "G2 DMA2 SH4-based address" )
|
nkeynes@302 | 139 | LONG_PORT( 0x848, G2DMA2SIZ, PORT_MRW, 0, "G2 DMA2 Size" )
|
nkeynes@302 | 140 | LONG_PORT( 0x84C, G2DMA2DIR, PORT_MRW, 0, "G2 DMA2 Direction" )
|
nkeynes@302 | 141 | LONG_PORT( 0x850, G2DMA2MOD, PORT_MRW, 0, "G2 DMA2 Mode" )
|
nkeynes@302 | 142 | LONG_PORT( 0x854, G2DMA2CTL1, PORT_MRW, 0, "G2 DMA2 Control 1" )
|
nkeynes@302 | 143 | LONG_PORT( 0x858, G2DMA2CTL2, PORT_MRW, 0, "G2 DMA2 Control 2" )
|
nkeynes@302 | 144 | LONG_PORT( 0x85C, G2DMA2STOP, PORT_MRW, 0, "G2 DMA2 Stop" )
|
nkeynes@302 | 145 | LONG_PORT( 0x860, G2DMA3EXT, PORT_MRW, 0, "G2 DMA3 External address" )
|
nkeynes@302 | 146 | LONG_PORT( 0x864, G2DMA3SH4, PORT_MRW, 0, "G2 DMA3 SH4-based address" )
|
nkeynes@302 | 147 | LONG_PORT( 0x868, G2DMA3SIZ, PORT_MRW, 0, "G2 DMA3 Size" )
|
nkeynes@302 | 148 | LONG_PORT( 0x86C, G2DMA3DIR, PORT_MRW, 0, "G2 DMA3 Direction" )
|
nkeynes@302 | 149 | LONG_PORT( 0x870, G2DMA3MOD, PORT_MRW, 0, "G2 DMA3 Mode" )
|
nkeynes@302 | 150 | LONG_PORT( 0x874, G2DMA3CTL1, PORT_MRW, 0, "G2 DMA3 Control 1" )
|
nkeynes@302 | 151 | LONG_PORT( 0x878, G2DMA3CTL2, PORT_MRW, 0, "G2 DMA3 Control 2" )
|
nkeynes@302 | 152 | LONG_PORT( 0x87C, G2DMA3STOP, PORT_MRW, 0, "G2 DMA3 Stop" )
|
nkeynes@302 | 153 | LONG_PORT( 0x890, G2DMAWAIT, PORT_MRW, 0, "G2 DMA wait states (?)" )
|
nkeynes@302 | 154 | LONG_PORT( 0x894, G2DMAUN1, PORT_MRW, 0, "G2 DMA <unknown1>" )
|
nkeynes@302 | 155 | LONG_PORT( 0x898, G2DMAUN2, PORT_MRW, 0, "G2 DMA <unknown2>" )
|
nkeynes@302 | 156 | LONG_PORT( 0x89C, G2DMAUN3, PORT_MRW, 0, "G2 DMA <unknown3>" )
|
nkeynes@302 | 157 | LONG_PORT( 0x8A0, G2DMAUN4, PORT_MRW, 0, "G2 DMA <unknown4>" )
|
nkeynes@302 | 158 | LONG_PORT( 0x8A4, G2DMAUN5, PORT_MRW, 0, "G2 DMA <unknown5>" )
|
nkeynes@302 | 159 | LONG_PORT( 0x8A8, G2DMAUN6, PORT_MRW, 0, "G2 DMA <unknown6>" )
|
nkeynes@302 | 160 | LONG_PORT( 0x8AC, G2DMAUN7, PORT_MRW, 0, "G2 DMA <unknown7>" )
|
nkeynes@302 | 161 | LONG_PORT( 0x8B0, G2DMAUN8, PORT_MRW, 0, "G2 DMA <unknown8>" )
|
nkeynes@302 | 162 | LONG_PORT( 0x8B4, G2DMAUN9, PORT_MRW, 0, "G2 DMA <unknown9>" )
|
nkeynes@302 | 163 | LONG_PORT( 0x8B8, G2DMAUN10, PORT_MRW, 0, "G2 DMA <unknown10>" )
|
nkeynes@302 | 164 | LONG_PORT( 0x8BC, G2DMACFG, PORT_MRW, 0, "G2 DMA Config" ) /* 46597F00 */
|
nkeynes@56 | 165 | LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
|
nkeynes@56 | 166 | LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
|
nkeynes@56 | 167 | LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
|
nkeynes@56 | 168 | LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" )
|
nkeynes@56 | 169 | LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
|
nkeynes@56 | 170 | LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
|
nkeynes@56 | 171 | LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
|
nkeynes@172 | 172 | LONG_PORT( 0xC80, PVRDMA2CFG, PORT_MRW, 0, "PVR DMA Config" ) /* 67027F00 */
|
nkeynes@1 | 173 |
|
nkeynes@1 | 174 | MMIO_REGION_END
|
nkeynes@1 | 175 |
|
nkeynes@56 | 176 | #define EVENT_PVR_RENDER_DONE 2
|
nkeynes@265 | 177 | #define EVENT_SCANLINE2 3
|
nkeynes@265 | 178 | #define EVENT_SCANLINE1 4
|
nkeynes@305 | 179 | #define EVENT_HPOS 5
|
nkeynes@282 | 180 | #define EVENT_PVR_YUV_DONE 6
|
nkeynes@56 | 181 | #define EVENT_PVR_OPAQUE_DONE 7
|
nkeynes@56 | 182 | #define EVENT_PVR_OPAQUEMOD_DONE 8
|
nkeynes@56 | 183 | #define EVENT_PVR_TRANS_DONE 9
|
nkeynes@65 | 184 | #define EVENT_PVR_TRANSMOD_DONE 10
|
nkeynes@1 | 185 | #define EVENT_MAPLE_DMA 12
|
nkeynes@1 | 186 | #define EVENT_MAPLE_ERR 13 /* ??? */
|
nkeynes@125 | 187 | #define EVENT_IDE_DMA 14
|
nkeynes@302 | 188 | #define EVENT_G2_DMA0 15
|
nkeynes@302 | 189 | #define EVENT_G2_DMA1 16
|
nkeynes@302 | 190 | #define EVENT_G2_DMA2 17
|
nkeynes@302 | 191 | #define EVENT_G2_DMA3 18
|
nkeynes@56 | 192 | #define EVENT_PVR_DMA 19
|
nkeynes@753 | 193 | #define EVENT_SORT_DMA 20
|
nkeynes@56 | 194 | #define EVENT_PVR_PUNCHOUT_DONE 21
|
nkeynes@305 | 195 | #define EVENT_CASCADE1 30 /* Set if something in the second word is active */
|
nkeynes@305 | 196 | #define EVENT_CASCADE2 31 /* Set if something in the third word is active */
|
nkeynes@56 | 197 |
|
nkeynes@125 | 198 | #define EVENT_IDE 32
|
nkeynes@1 | 199 | #define EVENT_AICA 33
|
nkeynes@1 | 200 |
|
nkeynes@184 | 201 | #define EVENT_PVR_PRIM_ALLOC_FAIL 66
|
nkeynes@184 | 202 | #define EVENT_PVR_MATRIX_ALLOC_FAIL 67
|
nkeynes@189 | 203 | #define EVENT_PVR_BAD_INPUT 68
|
nkeynes@753 | 204 | #define EVENT_SORT_DMA_ERR 92
|
nkeynes@184 | 205 |
|
nkeynes@244 | 206 | #define IS_IDE_REGISTER(x) ( (x) <= IDEDMACTL2 )
|
nkeynes@244 | 207 |
|
nkeynes@125 | 208 | /**
|
nkeynes@125 | 209 | * Raise an ASIC event
|
nkeynes@125 | 210 | */
|
nkeynes@1 | 211 | void asic_event( int event );
|
nkeynes@125 | 212 |
|
nkeynes@125 | 213 | /**
|
nkeynes@125 | 214 | * Clear an ASIC event. Currently only the IDE controller is known to use
|
nkeynes@125 | 215 | * this functionality.
|
nkeynes@125 | 216 | */
|
nkeynes@125 | 217 | void asic_clear_event( int event );
|
nkeynes@125 | 218 |
|
nkeynes@137 | 219 | void asic_g2_write_word( );
|