nkeynes@359 | 1 | /**
|
nkeynes@526 | 2 | * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
|
nkeynes@359 | 3 | *
|
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
|
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
|
nkeynes@359 | 6 | * to test the optimizing versions against.
|
nkeynes@359 | 7 | *
|
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
|
nkeynes@359 | 9 | *
|
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
|
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@359 | 13 | * (at your option) any later version.
|
nkeynes@359 | 14 | *
|
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
|
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@359 | 18 | * GNU General Public License for more details.
|
nkeynes@359 | 19 | */
|
nkeynes@359 | 20 |
|
nkeynes@368 | 21 | #include <assert.h>
|
nkeynes@388 | 22 | #include <math.h>
|
nkeynes@368 | 23 |
|
nkeynes@380 | 24 | #ifndef NDEBUG
|
nkeynes@380 | 25 | #define DEBUG_JUMPS 1
|
nkeynes@380 | 26 | #endif
|
nkeynes@380 | 27 |
|
nkeynes@417 | 28 | #include "sh4/xltcache.h"
|
nkeynes@368 | 29 | #include "sh4/sh4core.h"
|
nkeynes@368 | 30 | #include "sh4/sh4trans.h"
|
nkeynes@388 | 31 | #include "sh4/sh4mmio.h"
|
nkeynes@368 | 32 | #include "sh4/x86op.h"
|
nkeynes@368 | 33 | #include "clock.h"
|
nkeynes@368 | 34 |
|
nkeynes@368 | 35 | #define DEFAULT_BACKPATCH_SIZE 4096
|
nkeynes@368 | 36 |
|
nkeynes@368 | 37 | /**
|
nkeynes@368 | 38 | * Struct to manage internal translation state. This state is not saved -
|
nkeynes@368 | 39 | * it is only valid between calls to sh4_translate_begin_block() and
|
nkeynes@368 | 40 | * sh4_translate_end_block()
|
nkeynes@368 | 41 | */
|
nkeynes@368 | 42 | struct sh4_x86_state {
|
nkeynes@368 | 43 | gboolean in_delay_slot;
|
nkeynes@368 | 44 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
|
nkeynes@368 | 45 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
|
nkeynes@409 | 46 | gboolean branch_taken; /* true if we branched unconditionally */
|
nkeynes@408 | 47 | uint32_t block_start_pc;
|
nkeynes@539 | 48 | uint32_t stack_posn; /* Trace stack height for alignment purposes */
|
nkeynes@417 | 49 | int tstate;
|
nkeynes@368 | 50 |
|
nkeynes@368 | 51 | /* Allocated memory for the (block-wide) back-patch list */
|
nkeynes@368 | 52 | uint32_t **backpatch_list;
|
nkeynes@368 | 53 | uint32_t backpatch_posn;
|
nkeynes@368 | 54 | uint32_t backpatch_size;
|
nkeynes@368 | 55 | };
|
nkeynes@368 | 56 |
|
nkeynes@417 | 57 | #define TSTATE_NONE -1
|
nkeynes@417 | 58 | #define TSTATE_O 0
|
nkeynes@417 | 59 | #define TSTATE_C 2
|
nkeynes@417 | 60 | #define TSTATE_E 4
|
nkeynes@417 | 61 | #define TSTATE_NE 5
|
nkeynes@417 | 62 | #define TSTATE_G 0xF
|
nkeynes@417 | 63 | #define TSTATE_GE 0xD
|
nkeynes@417 | 64 | #define TSTATE_A 7
|
nkeynes@417 | 65 | #define TSTATE_AE 3
|
nkeynes@417 | 66 |
|
nkeynes@417 | 67 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
|
nkeynes@417 | 68 | #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
|
nkeynes@417 | 69 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
|
nkeynes@417 | 70 | OP(0x70+sh4_x86.tstate); OP(rel8); \
|
nkeynes@417 | 71 | MARK_JMP(rel8,label)
|
nkeynes@417 | 72 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
|
nkeynes@417 | 73 | #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
|
nkeynes@417 | 74 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
|
nkeynes@417 | 75 | OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
|
nkeynes@417 | 76 | MARK_JMP(rel8, label)
|
nkeynes@417 | 77 |
|
nkeynes@417 | 78 |
|
nkeynes@368 | 79 | #define EXIT_DATA_ADDR_READ 0
|
nkeynes@368 | 80 | #define EXIT_DATA_ADDR_WRITE 7
|
nkeynes@368 | 81 | #define EXIT_ILLEGAL 14
|
nkeynes@368 | 82 | #define EXIT_SLOT_ILLEGAL 21
|
nkeynes@368 | 83 | #define EXIT_FPU_DISABLED 28
|
nkeynes@368 | 84 | #define EXIT_SLOT_FPU_DISABLED 35
|
nkeynes@368 | 85 |
|
nkeynes@368 | 86 | static struct sh4_x86_state sh4_x86;
|
nkeynes@368 | 87 |
|
nkeynes@388 | 88 | static uint32_t max_int = 0x7FFFFFFF;
|
nkeynes@388 | 89 | static uint32_t min_int = 0x80000000;
|
nkeynes@394 | 90 | static uint32_t save_fcw; /* save value for fpu control word */
|
nkeynes@394 | 91 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
|
nkeynes@386 | 92 |
|
nkeynes@368 | 93 | void sh4_x86_init()
|
nkeynes@368 | 94 | {
|
nkeynes@368 | 95 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
|
nkeynes@368 | 96 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
|
nkeynes@368 | 97 | }
|
nkeynes@368 | 98 |
|
nkeynes@368 | 99 |
|
nkeynes@368 | 100 | static void sh4_x86_add_backpatch( uint8_t *ptr )
|
nkeynes@368 | 101 | {
|
nkeynes@368 | 102 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
|
nkeynes@368 | 103 | sh4_x86.backpatch_size <<= 1;
|
nkeynes@368 | 104 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
|
nkeynes@368 | 105 | assert( sh4_x86.backpatch_list != NULL );
|
nkeynes@368 | 106 | }
|
nkeynes@368 | 107 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
|
nkeynes@368 | 108 | }
|
nkeynes@368 | 109 |
|
nkeynes@368 | 110 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
|
nkeynes@368 | 111 | {
|
nkeynes@368 | 112 | unsigned int i;
|
nkeynes@368 | 113 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
|
nkeynes@374 | 114 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
|
nkeynes@368 | 115 | }
|
nkeynes@368 | 116 | }
|
nkeynes@368 | 117 |
|
nkeynes@359 | 118 | /**
|
nkeynes@359 | 119 | * Emit an instruction to load an SH4 reg into a real register
|
nkeynes@359 | 120 | */
|
nkeynes@359 | 121 | static inline void load_reg( int x86reg, int sh4reg )
|
nkeynes@359 | 122 | {
|
nkeynes@359 | 123 | /* mov [bp+n], reg */
|
nkeynes@361 | 124 | OP(0x8B);
|
nkeynes@361 | 125 | OP(0x45 + (x86reg<<3));
|
nkeynes@359 | 126 | OP(REG_OFFSET(r[sh4reg]));
|
nkeynes@359 | 127 | }
|
nkeynes@359 | 128 |
|
nkeynes@374 | 129 | static inline void load_reg16s( int x86reg, int sh4reg )
|
nkeynes@368 | 130 | {
|
nkeynes@374 | 131 | OP(0x0F);
|
nkeynes@374 | 132 | OP(0xBF);
|
nkeynes@374 | 133 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
|
nkeynes@368 | 134 | }
|
nkeynes@368 | 135 |
|
nkeynes@374 | 136 | static inline void load_reg16u( int x86reg, int sh4reg )
|
nkeynes@368 | 137 | {
|
nkeynes@374 | 138 | OP(0x0F);
|
nkeynes@374 | 139 | OP(0xB7);
|
nkeynes@374 | 140 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
|
nkeynes@374 | 141 |
|
nkeynes@368 | 142 | }
|
nkeynes@368 | 143 |
|
nkeynes@380 | 144 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
|
nkeynes@380 | 145 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
|
nkeynes@359 | 146 | /**
|
nkeynes@359 | 147 | * Emit an instruction to load an immediate value into a register
|
nkeynes@359 | 148 | */
|
nkeynes@359 | 149 | static inline void load_imm32( int x86reg, uint32_t value ) {
|
nkeynes@359 | 150 | /* mov #value, reg */
|
nkeynes@359 | 151 | OP(0xB8 + x86reg);
|
nkeynes@359 | 152 | OP32(value);
|
nkeynes@359 | 153 | }
|
nkeynes@359 | 154 |
|
nkeynes@359 | 155 | /**
|
nkeynes@527 | 156 | * Load an immediate 64-bit quantity (note: x86-64 only)
|
nkeynes@527 | 157 | */
|
nkeynes@527 | 158 | static inline void load_imm64( int x86reg, uint32_t value ) {
|
nkeynes@527 | 159 | /* mov #value, reg */
|
nkeynes@527 | 160 | REXW();
|
nkeynes@527 | 161 | OP(0xB8 + x86reg);
|
nkeynes@527 | 162 | OP64(value);
|
nkeynes@527 | 163 | }
|
nkeynes@527 | 164 |
|
nkeynes@527 | 165 |
|
nkeynes@527 | 166 | /**
|
nkeynes@359 | 167 | * Emit an instruction to store an SH4 reg (RN)
|
nkeynes@359 | 168 | */
|
nkeynes@359 | 169 | void static inline store_reg( int x86reg, int sh4reg ) {
|
nkeynes@359 | 170 | /* mov reg, [bp+n] */
|
nkeynes@361 | 171 | OP(0x89);
|
nkeynes@361 | 172 | OP(0x45 + (x86reg<<3));
|
nkeynes@359 | 173 | OP(REG_OFFSET(r[sh4reg]));
|
nkeynes@359 | 174 | }
|
nkeynes@374 | 175 |
|
nkeynes@374 | 176 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
|
nkeynes@374 | 177 |
|
nkeynes@375 | 178 | /**
|
nkeynes@375 | 179 | * Load an FR register (single-precision floating point) into an integer x86
|
nkeynes@375 | 180 | * register (eg for register-to-register moves)
|
nkeynes@375 | 181 | */
|
nkeynes@375 | 182 | void static inline load_fr( int bankreg, int x86reg, int frm )
|
nkeynes@375 | 183 | {
|
nkeynes@375 | 184 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
|
nkeynes@375 | 185 | }
|
nkeynes@375 | 186 |
|
nkeynes@375 | 187 | /**
|
nkeynes@375 | 188 | * Store an FR register (single-precision floating point) into an integer x86
|
nkeynes@375 | 189 | * register (eg for register-to-register moves)
|
nkeynes@375 | 190 | */
|
nkeynes@375 | 191 | void static inline store_fr( int bankreg, int x86reg, int frn )
|
nkeynes@375 | 192 | {
|
nkeynes@375 | 193 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
|
nkeynes@375 | 194 | }
|
nkeynes@375 | 195 |
|
nkeynes@375 | 196 |
|
nkeynes@375 | 197 | /**
|
nkeynes@375 | 198 | * Load a pointer to the back fp back into the specified x86 register. The
|
nkeynes@375 | 199 | * bankreg must have been previously loaded with FPSCR.
|
nkeynes@388 | 200 | * NB: 12 bytes
|
nkeynes@375 | 201 | */
|
nkeynes@374 | 202 | static inline void load_xf_bank( int bankreg )
|
nkeynes@374 | 203 | {
|
nkeynes@386 | 204 | NOT_r32( bankreg );
|
nkeynes@374 | 205 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
|
nkeynes@374 | 206 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
|
nkeynes@374 | 207 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
|
nkeynes@374 | 208 | }
|
nkeynes@374 | 209 |
|
nkeynes@375 | 210 | /**
|
nkeynes@386 | 211 | * Update the fr_bank pointer based on the current fpscr value.
|
nkeynes@386 | 212 | */
|
nkeynes@386 | 213 | static inline void update_fr_bank( int fpscrreg )
|
nkeynes@386 | 214 | {
|
nkeynes@386 | 215 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
|
nkeynes@386 | 216 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
|
nkeynes@386 | 217 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
|
nkeynes@386 | 218 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
|
nkeynes@386 | 219 | }
|
nkeynes@386 | 220 | /**
|
nkeynes@377 | 221 | * Push FPUL (as a 32-bit float) onto the FPU stack
|
nkeynes@377 | 222 | */
|
nkeynes@377 | 223 | static inline void push_fpul( )
|
nkeynes@377 | 224 | {
|
nkeynes@377 | 225 | OP(0xD9); OP(0x45); OP(R_FPUL);
|
nkeynes@377 | 226 | }
|
nkeynes@377 | 227 |
|
nkeynes@377 | 228 | /**
|
nkeynes@377 | 229 | * Pop FPUL (as a 32-bit float) from the FPU stack
|
nkeynes@377 | 230 | */
|
nkeynes@377 | 231 | static inline void pop_fpul( )
|
nkeynes@377 | 232 | {
|
nkeynes@377 | 233 | OP(0xD9); OP(0x5D); OP(R_FPUL);
|
nkeynes@377 | 234 | }
|
nkeynes@377 | 235 |
|
nkeynes@377 | 236 | /**
|
nkeynes@375 | 237 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
|
nkeynes@375 | 238 | * with the location of the current fp bank.
|
nkeynes@375 | 239 | */
|
nkeynes@374 | 240 | static inline void push_fr( int bankreg, int frm )
|
nkeynes@374 | 241 | {
|
nkeynes@374 | 242 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
|
nkeynes@374 | 243 | }
|
nkeynes@374 | 244 |
|
nkeynes@375 | 245 | /**
|
nkeynes@375 | 246 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
|
nkeynes@375 | 247 | * with bankreg previously loaded with the location of the current fp bank.
|
nkeynes@375 | 248 | */
|
nkeynes@374 | 249 | static inline void pop_fr( int bankreg, int frm )
|
nkeynes@374 | 250 | {
|
nkeynes@374 | 251 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
|
nkeynes@374 | 252 | }
|
nkeynes@374 | 253 |
|
nkeynes@375 | 254 | /**
|
nkeynes@375 | 255 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
|
nkeynes@375 | 256 | * with the location of the current fp bank.
|
nkeynes@375 | 257 | */
|
nkeynes@374 | 258 | static inline void push_dr( int bankreg, int frm )
|
nkeynes@374 | 259 | {
|
nkeynes@377 | 260 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
|
nkeynes@374 | 261 | }
|
nkeynes@374 | 262 |
|
nkeynes@374 | 263 | static inline void pop_dr( int bankreg, int frm )
|
nkeynes@374 | 264 | {
|
nkeynes@377 | 265 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
|
nkeynes@374 | 266 | }
|
nkeynes@374 | 267 |
|
nkeynes@368 | 268 | /* Exception checks - Note that all exception checks will clobber EAX */
|
nkeynes@416 | 269 | #define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
|
nkeynes@416 | 270 |
|
nkeynes@416 | 271 | #define check_priv( ) \
|
nkeynes@416 | 272 | if( !sh4_x86.priv_checked ) { \
|
nkeynes@416 | 273 | sh4_x86.priv_checked = TRUE;\
|
nkeynes@416 | 274 | precheck();\
|
nkeynes@416 | 275 | load_spreg( R_EAX, R_SR );\
|
nkeynes@416 | 276 | AND_imm32_r32( SR_MD, R_EAX );\
|
nkeynes@416 | 277 | if( sh4_x86.in_delay_slot ) {\
|
nkeynes@416 | 278 | JE_exit( EXIT_SLOT_ILLEGAL );\
|
nkeynes@416 | 279 | } else {\
|
nkeynes@416 | 280 | JE_exit( EXIT_ILLEGAL );\
|
nkeynes@416 | 281 | }\
|
nkeynes@416 | 282 | }\
|
nkeynes@416 | 283 |
|
nkeynes@416 | 284 |
|
nkeynes@416 | 285 | static void check_priv_no_precheck()
|
nkeynes@368 | 286 | {
|
nkeynes@368 | 287 | if( !sh4_x86.priv_checked ) {
|
nkeynes@368 | 288 | sh4_x86.priv_checked = TRUE;
|
nkeynes@368 | 289 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 290 | AND_imm32_r32( SR_MD, R_EAX );
|
nkeynes@368 | 291 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 292 | JE_exit( EXIT_SLOT_ILLEGAL );
|
nkeynes@368 | 293 | } else {
|
nkeynes@368 | 294 | JE_exit( EXIT_ILLEGAL );
|
nkeynes@368 | 295 | }
|
nkeynes@368 | 296 | }
|
nkeynes@368 | 297 | }
|
nkeynes@368 | 298 |
|
nkeynes@416 | 299 | #define check_fpuen( ) \
|
nkeynes@416 | 300 | if( !sh4_x86.fpuen_checked ) {\
|
nkeynes@416 | 301 | sh4_x86.fpuen_checked = TRUE;\
|
nkeynes@416 | 302 | precheck();\
|
nkeynes@416 | 303 | load_spreg( R_EAX, R_SR );\
|
nkeynes@416 | 304 | AND_imm32_r32( SR_FD, R_EAX );\
|
nkeynes@416 | 305 | if( sh4_x86.in_delay_slot ) {\
|
nkeynes@416 | 306 | JNE_exit(EXIT_SLOT_FPU_DISABLED);\
|
nkeynes@416 | 307 | } else {\
|
nkeynes@416 | 308 | JNE_exit(EXIT_FPU_DISABLED);\
|
nkeynes@416 | 309 | }\
|
nkeynes@416 | 310 | }
|
nkeynes@416 | 311 |
|
nkeynes@416 | 312 | static void check_fpuen_no_precheck()
|
nkeynes@368 | 313 | {
|
nkeynes@368 | 314 | if( !sh4_x86.fpuen_checked ) {
|
nkeynes@368 | 315 | sh4_x86.fpuen_checked = TRUE;
|
nkeynes@368 | 316 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 317 | AND_imm32_r32( SR_FD, R_EAX );
|
nkeynes@368 | 318 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 319 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
|
nkeynes@368 | 320 | } else {
|
nkeynes@368 | 321 | JNE_exit(EXIT_FPU_DISABLED);
|
nkeynes@368 | 322 | }
|
nkeynes@368 | 323 | }
|
nkeynes@416 | 324 |
|
nkeynes@368 | 325 | }
|
nkeynes@368 | 326 |
|
nkeynes@368 | 327 | static void check_ralign16( int x86reg )
|
nkeynes@368 | 328 | {
|
nkeynes@368 | 329 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 330 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 331 | }
|
nkeynes@368 | 332 |
|
nkeynes@368 | 333 | static void check_walign16( int x86reg )
|
nkeynes@368 | 334 | {
|
nkeynes@368 | 335 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 336 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 337 | }
|
nkeynes@368 | 338 |
|
nkeynes@368 | 339 | static void check_ralign32( int x86reg )
|
nkeynes@368 | 340 | {
|
nkeynes@368 | 341 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 342 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 343 | }
|
nkeynes@368 | 344 | static void check_walign32( int x86reg )
|
nkeynes@368 | 345 | {
|
nkeynes@368 | 346 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 347 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 348 | }
|
nkeynes@368 | 349 |
|
nkeynes@361 | 350 | #define UNDEF()
|
nkeynes@361 | 351 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
|
nkeynes@361 | 352 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 353 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 354 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 355 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
|
nkeynes@361 | 356 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
|
nkeynes@361 | 357 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
|
nkeynes@361 | 358 |
|
nkeynes@416 | 359 | #define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
|
nkeynes@368 | 360 |
|
nkeynes@388 | 361 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 362 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 363 |
|
nkeynes@539 | 364 | /****** Import appropriate calling conventions ******/
|
nkeynes@539 | 365 | #if SH4_TRANSLATOR == TARGET_X86_64
|
nkeynes@539 | 366 | #include "sh4/ia64abi.h"
|
nkeynes@539 | 367 | #else /* SH4_TRANSLATOR == TARGET_X86 */
|
nkeynes@539 | 368 | #ifdef APPLE_BUILD
|
nkeynes@539 | 369 | #include "sh4/ia32mac.h"
|
nkeynes@539 | 370 | #else
|
nkeynes@539 | 371 | #include "sh4/ia32abi.h"
|
nkeynes@539 | 372 | #endif
|
nkeynes@539 | 373 | #endif
|
nkeynes@539 | 374 |
|
nkeynes@539 | 375 |
|
nkeynes@359 | 376 | /**
|
nkeynes@359 | 377 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 378 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 379 | *
|
nkeynes@359 | 380 | *
|
nkeynes@359 | 381 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 382 | * (eg a branch or
|
nkeynes@359 | 383 | */
|
nkeynes@526 | 384 | uint32_t sh4_translate_instruction( sh4addr_t pc )
|
nkeynes@359 | 385 | {
|
nkeynes@388 | 386 | uint32_t ir;
|
nkeynes@388 | 387 | /* Read instruction */
|
nkeynes@388 | 388 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 389 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 390 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 391 | } else {
|
nkeynes@388 | 392 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@527 | 393 | if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 394 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 395 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 396 | */
|
nkeynes@388 | 397 | sh4_icache = NULL;
|
nkeynes@388 | 398 | ir = sh4_read_word(pc);
|
nkeynes@388 | 399 | } else {
|
nkeynes@388 | 400 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 401 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 402 | }
|
nkeynes@388 | 403 | }
|
nkeynes@388 | 404 |
|
nkeynes@359 | 405 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 406 | case 0x0:
|
nkeynes@359 | 407 | switch( ir&0xF ) {
|
nkeynes@359 | 408 | case 0x2:
|
nkeynes@359 | 409 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 410 | case 0x0:
|
nkeynes@359 | 411 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 412 | case 0x0:
|
nkeynes@359 | 413 | { /* STC SR, Rn */
|
nkeynes@359 | 414 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 415 | check_priv();
|
nkeynes@374 | 416 | call_func0(sh4_read_sr);
|
nkeynes@368 | 417 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 418 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 419 | }
|
nkeynes@359 | 420 | break;
|
nkeynes@359 | 421 | case 0x1:
|
nkeynes@359 | 422 | { /* STC GBR, Rn */
|
nkeynes@359 | 423 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 424 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 425 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 426 | }
|
nkeynes@359 | 427 | break;
|
nkeynes@359 | 428 | case 0x2:
|
nkeynes@359 | 429 | { /* STC VBR, Rn */
|
nkeynes@359 | 430 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 431 | check_priv();
|
nkeynes@359 | 432 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 433 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 434 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 435 | }
|
nkeynes@359 | 436 | break;
|
nkeynes@359 | 437 | case 0x3:
|
nkeynes@359 | 438 | { /* STC SSR, Rn */
|
nkeynes@359 | 439 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 440 | check_priv();
|
nkeynes@359 | 441 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 442 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 443 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 444 | }
|
nkeynes@359 | 445 | break;
|
nkeynes@359 | 446 | case 0x4:
|
nkeynes@359 | 447 | { /* STC SPC, Rn */
|
nkeynes@359 | 448 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 449 | check_priv();
|
nkeynes@359 | 450 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 451 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 452 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 453 | }
|
nkeynes@359 | 454 | break;
|
nkeynes@359 | 455 | default:
|
nkeynes@359 | 456 | UNDEF();
|
nkeynes@359 | 457 | break;
|
nkeynes@359 | 458 | }
|
nkeynes@359 | 459 | break;
|
nkeynes@359 | 460 | case 0x1:
|
nkeynes@359 | 461 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 462 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 463 | check_priv();
|
nkeynes@374 | 464 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 465 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 466 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 467 | }
|
nkeynes@359 | 468 | break;
|
nkeynes@359 | 469 | }
|
nkeynes@359 | 470 | break;
|
nkeynes@359 | 471 | case 0x3:
|
nkeynes@359 | 472 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 473 | case 0x0:
|
nkeynes@359 | 474 | { /* BSRF Rn */
|
nkeynes@359 | 475 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 476 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 477 | SLOTILLEGAL();
|
nkeynes@374 | 478 | } else {
|
nkeynes@408 | 479 | load_imm32( R_ECX, pc + 4 );
|
nkeynes@408 | 480 | store_spreg( R_ECX, R_PR );
|
nkeynes@408 | 481 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
|
nkeynes@408 | 482 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 483 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 484 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 485 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 486 | exit_block_pcset(pc+2);
|
nkeynes@409 | 487 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 488 | return 4;
|
nkeynes@374 | 489 | }
|
nkeynes@359 | 490 | }
|
nkeynes@359 | 491 | break;
|
nkeynes@359 | 492 | case 0x2:
|
nkeynes@359 | 493 | { /* BRAF Rn */
|
nkeynes@359 | 494 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 495 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 496 | SLOTILLEGAL();
|
nkeynes@374 | 497 | } else {
|
nkeynes@408 | 498 | load_reg( R_EAX, Rn );
|
nkeynes@408 | 499 | ADD_imm32_r32( pc + 4, R_EAX );
|
nkeynes@408 | 500 | store_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@374 | 501 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 502 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 503 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 504 | exit_block_pcset(pc+2);
|
nkeynes@409 | 505 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 506 | return 4;
|
nkeynes@374 | 507 | }
|
nkeynes@359 | 508 | }
|
nkeynes@359 | 509 | break;
|
nkeynes@359 | 510 | case 0x8:
|
nkeynes@359 | 511 | { /* PREF @Rn */
|
nkeynes@359 | 512 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 513 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 514 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 515 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 516 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@532 | 517 | JNE_rel8(CALL_FUNC1_SIZE, end);
|
nkeynes@532 | 518 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@380 | 519 | JMP_TARGET(end);
|
nkeynes@417 | 520 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 521 | }
|
nkeynes@359 | 522 | break;
|
nkeynes@359 | 523 | case 0x9:
|
nkeynes@359 | 524 | { /* OCBI @Rn */
|
nkeynes@359 | 525 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 526 | }
|
nkeynes@359 | 527 | break;
|
nkeynes@359 | 528 | case 0xA:
|
nkeynes@359 | 529 | { /* OCBP @Rn */
|
nkeynes@359 | 530 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 531 | }
|
nkeynes@359 | 532 | break;
|
nkeynes@359 | 533 | case 0xB:
|
nkeynes@359 | 534 | { /* OCBWB @Rn */
|
nkeynes@359 | 535 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 536 | }
|
nkeynes@359 | 537 | break;
|
nkeynes@359 | 538 | case 0xC:
|
nkeynes@359 | 539 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 540 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 541 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 542 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 543 | precheck();
|
nkeynes@374 | 544 | check_walign32( R_ECX );
|
nkeynes@361 | 545 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 546 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 547 | }
|
nkeynes@359 | 548 | break;
|
nkeynes@359 | 549 | default:
|
nkeynes@359 | 550 | UNDEF();
|
nkeynes@359 | 551 | break;
|
nkeynes@359 | 552 | }
|
nkeynes@359 | 553 | break;
|
nkeynes@359 | 554 | case 0x4:
|
nkeynes@359 | 555 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 556 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 557 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 558 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 559 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 560 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 561 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 562 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 563 | }
|
nkeynes@359 | 564 | break;
|
nkeynes@359 | 565 | case 0x5:
|
nkeynes@359 | 566 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 567 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 568 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 569 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 570 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 571 | precheck();
|
nkeynes@374 | 572 | check_walign16( R_ECX );
|
nkeynes@361 | 573 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 574 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 575 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 576 | }
|
nkeynes@359 | 577 | break;
|
nkeynes@359 | 578 | case 0x6:
|
nkeynes@359 | 579 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 580 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 581 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 582 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 583 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 584 | precheck();
|
nkeynes@374 | 585 | check_walign32( R_ECX );
|
nkeynes@361 | 586 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 587 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 588 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 589 | }
|
nkeynes@359 | 590 | break;
|
nkeynes@359 | 591 | case 0x7:
|
nkeynes@359 | 592 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 593 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 594 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 595 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 596 | MUL_r32( R_ECX );
|
nkeynes@361 | 597 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 598 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 599 | }
|
nkeynes@359 | 600 | break;
|
nkeynes@359 | 601 | case 0x8:
|
nkeynes@359 | 602 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 603 | case 0x0:
|
nkeynes@359 | 604 | { /* CLRT */
|
nkeynes@374 | 605 | CLC();
|
nkeynes@374 | 606 | SETC_t();
|
nkeynes@417 | 607 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 608 | }
|
nkeynes@359 | 609 | break;
|
nkeynes@359 | 610 | case 0x1:
|
nkeynes@359 | 611 | { /* SETT */
|
nkeynes@374 | 612 | STC();
|
nkeynes@374 | 613 | SETC_t();
|
nkeynes@417 | 614 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 615 | }
|
nkeynes@359 | 616 | break;
|
nkeynes@359 | 617 | case 0x2:
|
nkeynes@359 | 618 | { /* CLRMAC */
|
nkeynes@374 | 619 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 620 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 621 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 622 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 623 | }
|
nkeynes@359 | 624 | break;
|
nkeynes@359 | 625 | case 0x3:
|
nkeynes@359 | 626 | { /* LDTLB */
|
nkeynes@359 | 627 | }
|
nkeynes@359 | 628 | break;
|
nkeynes@359 | 629 | case 0x4:
|
nkeynes@359 | 630 | { /* CLRS */
|
nkeynes@374 | 631 | CLC();
|
nkeynes@374 | 632 | SETC_sh4r(R_S);
|
nkeynes@417 | 633 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 634 | }
|
nkeynes@359 | 635 | break;
|
nkeynes@359 | 636 | case 0x5:
|
nkeynes@359 | 637 | { /* SETS */
|
nkeynes@374 | 638 | STC();
|
nkeynes@374 | 639 | SETC_sh4r(R_S);
|
nkeynes@417 | 640 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 641 | }
|
nkeynes@359 | 642 | break;
|
nkeynes@359 | 643 | default:
|
nkeynes@359 | 644 | UNDEF();
|
nkeynes@359 | 645 | break;
|
nkeynes@359 | 646 | }
|
nkeynes@359 | 647 | break;
|
nkeynes@359 | 648 | case 0x9:
|
nkeynes@359 | 649 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 650 | case 0x0:
|
nkeynes@359 | 651 | { /* NOP */
|
nkeynes@359 | 652 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 653 | }
|
nkeynes@359 | 654 | break;
|
nkeynes@359 | 655 | case 0x1:
|
nkeynes@359 | 656 | { /* DIV0U */
|
nkeynes@361 | 657 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 658 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 659 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 660 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 661 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@359 | 662 | }
|
nkeynes@359 | 663 | break;
|
nkeynes@359 | 664 | case 0x2:
|
nkeynes@359 | 665 | { /* MOVT Rn */
|
nkeynes@359 | 666 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 667 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 668 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 669 | }
|
nkeynes@359 | 670 | break;
|
nkeynes@359 | 671 | default:
|
nkeynes@359 | 672 | UNDEF();
|
nkeynes@359 | 673 | break;
|
nkeynes@359 | 674 | }
|
nkeynes@359 | 675 | break;
|
nkeynes@359 | 676 | case 0xA:
|
nkeynes@359 | 677 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 678 | case 0x0:
|
nkeynes@359 | 679 | { /* STS MACH, Rn */
|
nkeynes@359 | 680 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 681 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 682 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 683 | }
|
nkeynes@359 | 684 | break;
|
nkeynes@359 | 685 | case 0x1:
|
nkeynes@359 | 686 | { /* STS MACL, Rn */
|
nkeynes@359 | 687 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 688 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 689 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 690 | }
|
nkeynes@359 | 691 | break;
|
nkeynes@359 | 692 | case 0x2:
|
nkeynes@359 | 693 | { /* STS PR, Rn */
|
nkeynes@359 | 694 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 695 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 696 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 697 | }
|
nkeynes@359 | 698 | break;
|
nkeynes@359 | 699 | case 0x3:
|
nkeynes@359 | 700 | { /* STC SGR, Rn */
|
nkeynes@359 | 701 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 702 | check_priv();
|
nkeynes@359 | 703 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 704 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 705 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 706 | }
|
nkeynes@359 | 707 | break;
|
nkeynes@359 | 708 | case 0x5:
|
nkeynes@359 | 709 | { /* STS FPUL, Rn */
|
nkeynes@359 | 710 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 711 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 712 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 713 | }
|
nkeynes@359 | 714 | break;
|
nkeynes@359 | 715 | case 0x6:
|
nkeynes@359 | 716 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 717 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 718 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 719 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 720 | }
|
nkeynes@359 | 721 | break;
|
nkeynes@359 | 722 | case 0xF:
|
nkeynes@359 | 723 | { /* STC DBR, Rn */
|
nkeynes@359 | 724 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 725 | check_priv();
|
nkeynes@359 | 726 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 727 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 728 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 729 | }
|
nkeynes@359 | 730 | break;
|
nkeynes@359 | 731 | default:
|
nkeynes@359 | 732 | UNDEF();
|
nkeynes@359 | 733 | break;
|
nkeynes@359 | 734 | }
|
nkeynes@359 | 735 | break;
|
nkeynes@359 | 736 | case 0xB:
|
nkeynes@359 | 737 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 738 | case 0x0:
|
nkeynes@359 | 739 | { /* RTS */
|
nkeynes@374 | 740 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 741 | SLOTILLEGAL();
|
nkeynes@374 | 742 | } else {
|
nkeynes@408 | 743 | load_spreg( R_ECX, R_PR );
|
nkeynes@408 | 744 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 745 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 746 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 747 | exit_block_pcset(pc+2);
|
nkeynes@409 | 748 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 749 | return 4;
|
nkeynes@374 | 750 | }
|
nkeynes@359 | 751 | }
|
nkeynes@359 | 752 | break;
|
nkeynes@359 | 753 | case 0x1:
|
nkeynes@359 | 754 | { /* SLEEP */
|
nkeynes@388 | 755 | check_priv();
|
nkeynes@388 | 756 | call_func0( sh4_sleep );
|
nkeynes@417 | 757 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 758 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@408 | 759 | return 2;
|
nkeynes@359 | 760 | }
|
nkeynes@359 | 761 | break;
|
nkeynes@359 | 762 | case 0x2:
|
nkeynes@359 | 763 | { /* RTE */
|
nkeynes@374 | 764 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 765 | SLOTILLEGAL();
|
nkeynes@374 | 766 | } else {
|
nkeynes@408 | 767 | check_priv();
|
nkeynes@408 | 768 | load_spreg( R_ECX, R_SPC );
|
nkeynes@408 | 769 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 770 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 771 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 772 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 773 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 774 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 775 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 776 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 777 | exit_block_pcset(pc+2);
|
nkeynes@409 | 778 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 779 | return 4;
|
nkeynes@374 | 780 | }
|
nkeynes@359 | 781 | }
|
nkeynes@359 | 782 | break;
|
nkeynes@359 | 783 | default:
|
nkeynes@359 | 784 | UNDEF();
|
nkeynes@359 | 785 | break;
|
nkeynes@359 | 786 | }
|
nkeynes@359 | 787 | break;
|
nkeynes@359 | 788 | case 0xC:
|
nkeynes@359 | 789 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 790 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 791 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 792 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 793 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 794 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 795 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 796 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 797 | }
|
nkeynes@359 | 798 | break;
|
nkeynes@359 | 799 | case 0xD:
|
nkeynes@359 | 800 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 801 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 802 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 803 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 804 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 805 | precheck();
|
nkeynes@374 | 806 | check_ralign16( R_ECX );
|
nkeynes@361 | 807 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 808 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 809 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 810 | }
|
nkeynes@359 | 811 | break;
|
nkeynes@359 | 812 | case 0xE:
|
nkeynes@359 | 813 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 814 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 815 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 816 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 817 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 818 | precheck();
|
nkeynes@374 | 819 | check_ralign32( R_ECX );
|
nkeynes@361 | 820 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 821 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 822 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 823 | }
|
nkeynes@359 | 824 | break;
|
nkeynes@359 | 825 | case 0xF:
|
nkeynes@359 | 826 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 827 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 828 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 829 | precheck();
|
nkeynes@386 | 830 | check_ralign32( R_ECX );
|
nkeynes@386 | 831 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 832 | check_ralign32( R_ECX );
|
nkeynes@386 | 833 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 834 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 835 | PUSH_r32( R_EAX );
|
nkeynes@386 | 836 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 837 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 838 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 839 | POP_r32( R_ECX );
|
nkeynes@386 | 840 | IMUL_r32( R_ECX );
|
nkeynes@386 | 841 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 842 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 843 |
|
nkeynes@386 | 844 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 845 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@527 | 846 | JE_rel8( CALL_FUNC0_SIZE, nosat );
|
nkeynes@386 | 847 | call_func0( signsat48 );
|
nkeynes@386 | 848 | JMP_TARGET( nosat );
|
nkeynes@417 | 849 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 850 | }
|
nkeynes@359 | 851 | break;
|
nkeynes@359 | 852 | default:
|
nkeynes@359 | 853 | UNDEF();
|
nkeynes@359 | 854 | break;
|
nkeynes@359 | 855 | }
|
nkeynes@359 | 856 | break;
|
nkeynes@359 | 857 | case 0x1:
|
nkeynes@359 | 858 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 859 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 860 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 861 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 862 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 863 | precheck();
|
nkeynes@374 | 864 | check_walign32( R_ECX );
|
nkeynes@361 | 865 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 866 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 867 | }
|
nkeynes@359 | 868 | break;
|
nkeynes@359 | 869 | case 0x2:
|
nkeynes@359 | 870 | switch( ir&0xF ) {
|
nkeynes@359 | 871 | case 0x0:
|
nkeynes@359 | 872 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 873 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 874 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 875 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 876 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 877 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 878 | }
|
nkeynes@359 | 879 | break;
|
nkeynes@359 | 880 | case 0x1:
|
nkeynes@359 | 881 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 882 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 883 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 884 | precheck();
|
nkeynes@374 | 885 | check_walign16( R_ECX );
|
nkeynes@386 | 886 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 887 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 888 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 889 | }
|
nkeynes@359 | 890 | break;
|
nkeynes@359 | 891 | case 0x2:
|
nkeynes@359 | 892 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 893 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 894 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 895 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 896 | precheck();
|
nkeynes@374 | 897 | check_walign32(R_ECX);
|
nkeynes@361 | 898 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 899 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 900 | }
|
nkeynes@359 | 901 | break;
|
nkeynes@359 | 902 | case 0x4:
|
nkeynes@359 | 903 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 904 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 905 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 906 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 907 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 908 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 909 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 910 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 911 | }
|
nkeynes@359 | 912 | break;
|
nkeynes@359 | 913 | case 0x5:
|
nkeynes@359 | 914 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 915 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 916 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 917 | precheck();
|
nkeynes@374 | 918 | check_walign16( R_ECX );
|
nkeynes@361 | 919 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 920 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@386 | 921 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 922 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 923 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 924 | }
|
nkeynes@359 | 925 | break;
|
nkeynes@359 | 926 | case 0x6:
|
nkeynes@359 | 927 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 928 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 929 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 930 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 931 | precheck();
|
nkeynes@374 | 932 | check_walign32( R_ECX );
|
nkeynes@361 | 933 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 934 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 935 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 936 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 937 | }
|
nkeynes@359 | 938 | break;
|
nkeynes@359 | 939 | case 0x7:
|
nkeynes@359 | 940 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 941 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 942 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 943 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 944 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 945 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 946 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 947 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 948 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 949 | SETNE_t();
|
nkeynes@417 | 950 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@359 | 951 | }
|
nkeynes@359 | 952 | break;
|
nkeynes@359 | 953 | case 0x8:
|
nkeynes@359 | 954 | { /* TST Rm, Rn */
|
nkeynes@359 | 955 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 956 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 957 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 958 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 959 | SETE_t();
|
nkeynes@417 | 960 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 961 | }
|
nkeynes@359 | 962 | break;
|
nkeynes@359 | 963 | case 0x9:
|
nkeynes@359 | 964 | { /* AND Rm, Rn */
|
nkeynes@359 | 965 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 966 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 967 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 968 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 969 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 970 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 971 | }
|
nkeynes@359 | 972 | break;
|
nkeynes@359 | 973 | case 0xA:
|
nkeynes@359 | 974 | { /* XOR Rm, Rn */
|
nkeynes@359 | 975 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 976 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 977 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 978 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 979 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 980 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 981 | }
|
nkeynes@359 | 982 | break;
|
nkeynes@359 | 983 | case 0xB:
|
nkeynes@359 | 984 | { /* OR Rm, Rn */
|
nkeynes@359 | 985 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 986 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 987 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 988 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 989 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 990 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 991 | }
|
nkeynes@359 | 992 | break;
|
nkeynes@359 | 993 | case 0xC:
|
nkeynes@359 | 994 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 995 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 996 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 997 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 998 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 999 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 1000 | JE_rel8(13, target1);
|
nkeynes@368 | 1001 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1002 | JE_rel8(9, target2);
|
nkeynes@368 | 1003 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 1004 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 1005 | JE_rel8(2, target3);
|
nkeynes@368 | 1006 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1007 | JMP_TARGET(target1);
|
nkeynes@380 | 1008 | JMP_TARGET(target2);
|
nkeynes@380 | 1009 | JMP_TARGET(target3);
|
nkeynes@368 | 1010 | SETE_t();
|
nkeynes@417 | 1011 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1012 | }
|
nkeynes@359 | 1013 | break;
|
nkeynes@359 | 1014 | case 0xD:
|
nkeynes@359 | 1015 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1016 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1017 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1018 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1019 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1020 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1021 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1022 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1023 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1024 | }
|
nkeynes@359 | 1025 | break;
|
nkeynes@359 | 1026 | case 0xE:
|
nkeynes@359 | 1027 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1028 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1029 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1030 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1031 | MUL_r32( R_ECX );
|
nkeynes@374 | 1032 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1033 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1034 | }
|
nkeynes@359 | 1035 | break;
|
nkeynes@359 | 1036 | case 0xF:
|
nkeynes@359 | 1037 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1038 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1039 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1040 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1041 | MUL_r32( R_ECX );
|
nkeynes@374 | 1042 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1043 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1044 | }
|
nkeynes@359 | 1045 | break;
|
nkeynes@359 | 1046 | default:
|
nkeynes@359 | 1047 | UNDEF();
|
nkeynes@359 | 1048 | break;
|
nkeynes@359 | 1049 | }
|
nkeynes@359 | 1050 | break;
|
nkeynes@359 | 1051 | case 0x3:
|
nkeynes@359 | 1052 | switch( ir&0xF ) {
|
nkeynes@359 | 1053 | case 0x0:
|
nkeynes@359 | 1054 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1055 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1056 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1057 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1058 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1059 | SETE_t();
|
nkeynes@417 | 1060 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1061 | }
|
nkeynes@359 | 1062 | break;
|
nkeynes@359 | 1063 | case 0x2:
|
nkeynes@359 | 1064 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1065 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1066 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1067 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1068 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1069 | SETAE_t();
|
nkeynes@417 | 1070 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 1071 | }
|
nkeynes@359 | 1072 | break;
|
nkeynes@359 | 1073 | case 0x3:
|
nkeynes@359 | 1074 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1075 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1076 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1077 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1078 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1079 | SETGE_t();
|
nkeynes@417 | 1080 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1081 | }
|
nkeynes@359 | 1082 | break;
|
nkeynes@359 | 1083 | case 0x4:
|
nkeynes@359 | 1084 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1085 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 1086 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1087 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1088 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1089 | LDC_t();
|
nkeynes@417 | 1090 | }
|
nkeynes@386 | 1091 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1092 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1093 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 1094 | JE_rel8(5, mqequal);
|
nkeynes@386 | 1095 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1096 | JMP_rel8(3, end);
|
nkeynes@380 | 1097 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1098 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1099 | JMP_TARGET(end);
|
nkeynes@386 | 1100 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1101 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1102 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1103 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1104 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1105 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1106 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1107 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 1108 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1109 | }
|
nkeynes@359 | 1110 | break;
|
nkeynes@359 | 1111 | case 0x5:
|
nkeynes@359 | 1112 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1113 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1114 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1115 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1116 | MUL_r32(R_ECX);
|
nkeynes@361 | 1117 | store_spreg( R_EDX, R_MACH );
|
nkeynes@417 | 1118 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1119 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1120 | }
|
nkeynes@359 | 1121 | break;
|
nkeynes@359 | 1122 | case 0x6:
|
nkeynes@359 | 1123 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1124 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1125 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1126 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1127 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1128 | SETA_t();
|
nkeynes@417 | 1129 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 1130 | }
|
nkeynes@359 | 1131 | break;
|
nkeynes@359 | 1132 | case 0x7:
|
nkeynes@359 | 1133 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1134 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1135 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1136 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1137 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1138 | SETG_t();
|
nkeynes@417 | 1139 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1140 | }
|
nkeynes@359 | 1141 | break;
|
nkeynes@359 | 1142 | case 0x8:
|
nkeynes@359 | 1143 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1144 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1145 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1146 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1147 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1148 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1149 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1150 | }
|
nkeynes@359 | 1151 | break;
|
nkeynes@359 | 1152 | case 0xA:
|
nkeynes@359 | 1153 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1154 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1155 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1156 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 1157 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1158 | LDC_t();
|
nkeynes@417 | 1159 | }
|
nkeynes@359 | 1160 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1161 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1162 | SETC_t();
|
nkeynes@417 | 1163 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1164 | }
|
nkeynes@359 | 1165 | break;
|
nkeynes@359 | 1166 | case 0xB:
|
nkeynes@359 | 1167 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1168 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1169 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1170 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1171 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1172 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1173 | SETO_t();
|
nkeynes@417 | 1174 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1175 | }
|
nkeynes@359 | 1176 | break;
|
nkeynes@359 | 1177 | case 0xC:
|
nkeynes@359 | 1178 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1179 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1180 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1181 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1182 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1183 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1184 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1185 | }
|
nkeynes@359 | 1186 | break;
|
nkeynes@359 | 1187 | case 0xD:
|
nkeynes@359 | 1188 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1189 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1190 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1191 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1192 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1193 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1194 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1195 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1196 | }
|
nkeynes@359 | 1197 | break;
|
nkeynes@359 | 1198 | case 0xE:
|
nkeynes@359 | 1199 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1200 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@417 | 1201 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1202 | LDC_t();
|
nkeynes@417 | 1203 | }
|
nkeynes@359 | 1204 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1205 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1206 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1207 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1208 | SETC_t();
|
nkeynes@417 | 1209 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1210 | }
|
nkeynes@359 | 1211 | break;
|
nkeynes@359 | 1212 | case 0xF:
|
nkeynes@359 | 1213 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1214 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1215 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1216 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1217 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1218 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1219 | SETO_t();
|
nkeynes@417 | 1220 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1221 | }
|
nkeynes@359 | 1222 | break;
|
nkeynes@359 | 1223 | default:
|
nkeynes@359 | 1224 | UNDEF();
|
nkeynes@359 | 1225 | break;
|
nkeynes@359 | 1226 | }
|
nkeynes@359 | 1227 | break;
|
nkeynes@359 | 1228 | case 0x4:
|
nkeynes@359 | 1229 | switch( ir&0xF ) {
|
nkeynes@359 | 1230 | case 0x0:
|
nkeynes@359 | 1231 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1232 | case 0x0:
|
nkeynes@359 | 1233 | { /* SHLL Rn */
|
nkeynes@359 | 1234 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1235 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1236 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1237 | SETC_t();
|
nkeynes@359 | 1238 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1239 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1240 | }
|
nkeynes@359 | 1241 | break;
|
nkeynes@359 | 1242 | case 0x1:
|
nkeynes@359 | 1243 | { /* DT Rn */
|
nkeynes@359 | 1244 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1245 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1246 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1247 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1248 | SETE_t();
|
nkeynes@417 | 1249 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1250 | }
|
nkeynes@359 | 1251 | break;
|
nkeynes@359 | 1252 | case 0x2:
|
nkeynes@359 | 1253 | { /* SHAL Rn */
|
nkeynes@359 | 1254 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1255 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1256 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1257 | SETC_t();
|
nkeynes@359 | 1258 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1259 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1260 | }
|
nkeynes@359 | 1261 | break;
|
nkeynes@359 | 1262 | default:
|
nkeynes@359 | 1263 | UNDEF();
|
nkeynes@359 | 1264 | break;
|
nkeynes@359 | 1265 | }
|
nkeynes@359 | 1266 | break;
|
nkeynes@359 | 1267 | case 0x1:
|
nkeynes@359 | 1268 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1269 | case 0x0:
|
nkeynes@359 | 1270 | { /* SHLR Rn */
|
nkeynes@359 | 1271 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1272 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1273 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1274 | SETC_t();
|
nkeynes@359 | 1275 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1276 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1277 | }
|
nkeynes@359 | 1278 | break;
|
nkeynes@359 | 1279 | case 0x1:
|
nkeynes@359 | 1280 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1281 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1282 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1283 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1284 | SETGE_t();
|
nkeynes@417 | 1285 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1286 | }
|
nkeynes@359 | 1287 | break;
|
nkeynes@359 | 1288 | case 0x2:
|
nkeynes@359 | 1289 | { /* SHAR Rn */
|
nkeynes@359 | 1290 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1291 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1292 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1293 | SETC_t();
|
nkeynes@359 | 1294 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1295 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1296 | }
|
nkeynes@359 | 1297 | break;
|
nkeynes@359 | 1298 | default:
|
nkeynes@359 | 1299 | UNDEF();
|
nkeynes@359 | 1300 | break;
|
nkeynes@359 | 1301 | }
|
nkeynes@359 | 1302 | break;
|
nkeynes@359 | 1303 | case 0x2:
|
nkeynes@359 | 1304 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1305 | case 0x0:
|
nkeynes@359 | 1306 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1307 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1308 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1309 | precheck();
|
nkeynes@395 | 1310 | check_walign32( R_ECX );
|
nkeynes@386 | 1311 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1312 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1313 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1314 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1315 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1316 | }
|
nkeynes@359 | 1317 | break;
|
nkeynes@359 | 1318 | case 0x1:
|
nkeynes@359 | 1319 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1320 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1321 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1322 | precheck();
|
nkeynes@395 | 1323 | check_walign32( R_ECX );
|
nkeynes@386 | 1324 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1325 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1326 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1327 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1328 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1329 | }
|
nkeynes@359 | 1330 | break;
|
nkeynes@359 | 1331 | case 0x2:
|
nkeynes@359 | 1332 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1333 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1334 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1335 | precheck();
|
nkeynes@395 | 1336 | check_walign32( R_ECX );
|
nkeynes@386 | 1337 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1338 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1339 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1340 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1341 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1342 | }
|
nkeynes@359 | 1343 | break;
|
nkeynes@359 | 1344 | case 0x3:
|
nkeynes@359 | 1345 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1346 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1347 | precheck();
|
nkeynes@416 | 1348 | check_priv_no_precheck();
|
nkeynes@359 | 1349 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1350 | check_walign32( R_ECX );
|
nkeynes@386 | 1351 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1352 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1353 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1354 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1355 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1356 | }
|
nkeynes@359 | 1357 | break;
|
nkeynes@359 | 1358 | case 0x5:
|
nkeynes@359 | 1359 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1360 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1361 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1362 | precheck();
|
nkeynes@395 | 1363 | check_walign32( R_ECX );
|
nkeynes@386 | 1364 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1365 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1366 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1367 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1368 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1369 | }
|
nkeynes@359 | 1370 | break;
|
nkeynes@359 | 1371 | case 0x6:
|
nkeynes@359 | 1372 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1373 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1374 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1375 | precheck();
|
nkeynes@395 | 1376 | check_walign32( R_ECX );
|
nkeynes@386 | 1377 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1378 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1379 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1380 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1381 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1382 | }
|
nkeynes@359 | 1383 | break;
|
nkeynes@359 | 1384 | case 0xF:
|
nkeynes@359 | 1385 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1386 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1387 | precheck();
|
nkeynes@416 | 1388 | check_priv_no_precheck();
|
nkeynes@359 | 1389 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1390 | check_walign32( R_ECX );
|
nkeynes@386 | 1391 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1392 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1393 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1394 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1395 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1396 | }
|
nkeynes@359 | 1397 | break;
|
nkeynes@359 | 1398 | default:
|
nkeynes@359 | 1399 | UNDEF();
|
nkeynes@359 | 1400 | break;
|
nkeynes@359 | 1401 | }
|
nkeynes@359 | 1402 | break;
|
nkeynes@359 | 1403 | case 0x3:
|
nkeynes@359 | 1404 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1405 | case 0x0:
|
nkeynes@359 | 1406 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1407 | case 0x0:
|
nkeynes@359 | 1408 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1409 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1410 | precheck();
|
nkeynes@416 | 1411 | check_priv_no_precheck();
|
nkeynes@395 | 1412 | call_func0( sh4_read_sr );
|
nkeynes@374 | 1413 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1414 | check_walign32( R_ECX );
|
nkeynes@386 | 1415 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1416 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1417 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1418 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1419 | }
|
nkeynes@359 | 1420 | break;
|
nkeynes@359 | 1421 | case 0x1:
|
nkeynes@359 | 1422 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1423 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1424 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1425 | precheck();
|
nkeynes@395 | 1426 | check_walign32( R_ECX );
|
nkeynes@386 | 1427 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1428 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1429 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1430 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1431 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1432 | }
|
nkeynes@359 | 1433 | break;
|
nkeynes@359 | 1434 | case 0x2:
|
nkeynes@359 | 1435 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1436 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1437 | precheck();
|
nkeynes@416 | 1438 | check_priv_no_precheck();
|
nkeynes@359 | 1439 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1440 | check_walign32( R_ECX );
|
nkeynes@386 | 1441 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1442 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1443 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1444 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1445 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1446 | }
|
nkeynes@359 | 1447 | break;
|
nkeynes@359 | 1448 | case 0x3:
|
nkeynes@359 | 1449 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1450 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1451 | precheck();
|
nkeynes@416 | 1452 | check_priv_no_precheck();
|
nkeynes@359 | 1453 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1454 | check_walign32( R_ECX );
|
nkeynes@386 | 1455 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1456 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1457 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1458 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1459 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1460 | }
|
nkeynes@359 | 1461 | break;
|
nkeynes@359 | 1462 | case 0x4:
|
nkeynes@359 | 1463 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1464 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@416 | 1465 | precheck();
|
nkeynes@416 | 1466 | check_priv_no_precheck();
|
nkeynes@359 | 1467 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1468 | check_walign32( R_ECX );
|
nkeynes@386 | 1469 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1470 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1471 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1472 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1473 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1474 | }
|
nkeynes@359 | 1475 | break;
|
nkeynes@359 | 1476 | default:
|
nkeynes@359 | 1477 | UNDEF();
|
nkeynes@359 | 1478 | break;
|
nkeynes@359 | 1479 | }
|
nkeynes@359 | 1480 | break;
|
nkeynes@359 | 1481 | case 0x1:
|
nkeynes@359 | 1482 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1483 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@416 | 1484 | precheck();
|
nkeynes@416 | 1485 | check_priv_no_precheck();
|
nkeynes@374 | 1486 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1487 | check_walign32( R_ECX );
|
nkeynes@386 | 1488 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1489 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1490 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 1491 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1492 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1493 | }
|
nkeynes@359 | 1494 | break;
|
nkeynes@359 | 1495 | }
|
nkeynes@359 | 1496 | break;
|
nkeynes@359 | 1497 | case 0x4:
|
nkeynes@359 | 1498 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1499 | case 0x0:
|
nkeynes@359 | 1500 | { /* ROTL Rn */
|
nkeynes@359 | 1501 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1502 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1503 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1504 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1505 | SETC_t();
|
nkeynes@417 | 1506 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1507 | }
|
nkeynes@359 | 1508 | break;
|
nkeynes@359 | 1509 | case 0x2:
|
nkeynes@359 | 1510 | { /* ROTCL Rn */
|
nkeynes@359 | 1511 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1512 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1513 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1514 | LDC_t();
|
nkeynes@417 | 1515 | }
|
nkeynes@359 | 1516 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1517 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1518 | SETC_t();
|
nkeynes@417 | 1519 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1520 | }
|
nkeynes@359 | 1521 | break;
|
nkeynes@359 | 1522 | default:
|
nkeynes@359 | 1523 | UNDEF();
|
nkeynes@359 | 1524 | break;
|
nkeynes@359 | 1525 | }
|
nkeynes@359 | 1526 | break;
|
nkeynes@359 | 1527 | case 0x5:
|
nkeynes@359 | 1528 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1529 | case 0x0:
|
nkeynes@359 | 1530 | { /* ROTR Rn */
|
nkeynes@359 | 1531 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1532 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1533 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1534 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1535 | SETC_t();
|
nkeynes@417 | 1536 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1537 | }
|
nkeynes@359 | 1538 | break;
|
nkeynes@359 | 1539 | case 0x1:
|
nkeynes@359 | 1540 | { /* CMP/PL Rn */
|
nkeynes@359 | 1541 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1542 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1543 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1544 | SETG_t();
|
nkeynes@417 | 1545 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1546 | }
|
nkeynes@359 | 1547 | break;
|
nkeynes@359 | 1548 | case 0x2:
|
nkeynes@359 | 1549 | { /* ROTCR Rn */
|
nkeynes@359 | 1550 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1551 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1552 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1553 | LDC_t();
|
nkeynes@417 | 1554 | }
|
nkeynes@359 | 1555 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1556 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1557 | SETC_t();
|
nkeynes@417 | 1558 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1559 | }
|
nkeynes@359 | 1560 | break;
|
nkeynes@359 | 1561 | default:
|
nkeynes@359 | 1562 | UNDEF();
|
nkeynes@359 | 1563 | break;
|
nkeynes@359 | 1564 | }
|
nkeynes@359 | 1565 | break;
|
nkeynes@359 | 1566 | case 0x6:
|
nkeynes@359 | 1567 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1568 | case 0x0:
|
nkeynes@359 | 1569 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1570 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1571 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1572 | precheck();
|
nkeynes@395 | 1573 | check_ralign32( R_EAX );
|
nkeynes@359 | 1574 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1575 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1576 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1577 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1578 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1579 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1580 | }
|
nkeynes@359 | 1581 | break;
|
nkeynes@359 | 1582 | case 0x1:
|
nkeynes@359 | 1583 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1584 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1585 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1586 | precheck();
|
nkeynes@395 | 1587 | check_ralign32( R_EAX );
|
nkeynes@359 | 1588 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1589 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1590 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1591 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1592 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1593 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1594 | }
|
nkeynes@359 | 1595 | break;
|
nkeynes@359 | 1596 | case 0x2:
|
nkeynes@359 | 1597 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1598 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1599 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1600 | precheck();
|
nkeynes@395 | 1601 | check_ralign32( R_EAX );
|
nkeynes@359 | 1602 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1603 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1604 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1605 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1606 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 1607 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1608 | }
|
nkeynes@359 | 1609 | break;
|
nkeynes@359 | 1610 | case 0x3:
|
nkeynes@359 | 1611 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1612 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@416 | 1613 | precheck();
|
nkeynes@416 | 1614 | check_priv_no_precheck();
|
nkeynes@359 | 1615 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1616 | check_ralign32( R_EAX );
|
nkeynes@359 | 1617 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1618 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1619 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1620 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1621 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1622 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1623 | }
|
nkeynes@359 | 1624 | break;
|
nkeynes@359 | 1625 | case 0x5:
|
nkeynes@359 | 1626 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1627 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1628 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1629 | precheck();
|
nkeynes@395 | 1630 | check_ralign32( R_EAX );
|
nkeynes@359 | 1631 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1632 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1633 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1634 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1635 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 1636 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1637 | }
|
nkeynes@359 | 1638 | break;
|
nkeynes@359 | 1639 | case 0x6:
|
nkeynes@359 | 1640 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1641 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1642 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1643 | precheck();
|
nkeynes@395 | 1644 | check_ralign32( R_EAX );
|
nkeynes@359 | 1645 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1646 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1647 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1648 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1649 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1650 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1651 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1652 | }
|
nkeynes@359 | 1653 | break;
|
nkeynes@359 | 1654 | case 0xF:
|
nkeynes@359 | 1655 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1656 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@416 | 1657 | precheck();
|
nkeynes@416 | 1658 | check_priv_no_precheck();
|
nkeynes@359 | 1659 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1660 | check_ralign32( R_EAX );
|
nkeynes@359 | 1661 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1662 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1663 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1664 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1665 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1666 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1667 | }
|
nkeynes@359 | 1668 | break;
|
nkeynes@359 | 1669 | default:
|
nkeynes@359 | 1670 | UNDEF();
|
nkeynes@359 | 1671 | break;
|
nkeynes@359 | 1672 | }
|
nkeynes@359 | 1673 | break;
|
nkeynes@359 | 1674 | case 0x7:
|
nkeynes@359 | 1675 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1676 | case 0x0:
|
nkeynes@359 | 1677 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1678 | case 0x0:
|
nkeynes@359 | 1679 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1680 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1681 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1682 | SLOTILLEGAL();
|
nkeynes@386 | 1683 | } else {
|
nkeynes@416 | 1684 | precheck();
|
nkeynes@416 | 1685 | check_priv_no_precheck();
|
nkeynes@386 | 1686 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1687 | check_ralign32( R_EAX );
|
nkeynes@386 | 1688 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1689 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 1690 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 1691 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 1692 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1693 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1694 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1695 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 1696 | }
|
nkeynes@359 | 1697 | }
|
nkeynes@359 | 1698 | break;
|
nkeynes@359 | 1699 | case 0x1:
|
nkeynes@359 | 1700 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1701 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1702 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1703 | precheck();
|
nkeynes@395 | 1704 | check_ralign32( R_EAX );
|
nkeynes@359 | 1705 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1706 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1707 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1708 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1709 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 1710 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1711 | }
|
nkeynes@359 | 1712 | break;
|
nkeynes@359 | 1713 | case 0x2:
|
nkeynes@359 | 1714 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1715 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@416 | 1716 | precheck();
|
nkeynes@416 | 1717 | check_priv_no_precheck();
|
nkeynes@359 | 1718 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1719 | check_ralign32( R_EAX );
|
nkeynes@359 | 1720 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1721 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1722 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1723 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1724 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 1725 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1726 | }
|
nkeynes@359 | 1727 | break;
|
nkeynes@359 | 1728 | case 0x3:
|
nkeynes@359 | 1729 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1730 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@416 | 1731 | precheck();
|
nkeynes@416 | 1732 | check_priv_no_precheck();
|
nkeynes@359 | 1733 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1734 | check_ralign32( R_EAX );
|
nkeynes@359 | 1735 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1736 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1737 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1738 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1739 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 1740 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1741 | }
|
nkeynes@359 | 1742 | break;
|
nkeynes@359 | 1743 | case 0x4:
|
nkeynes@359 | 1744 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1745 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@416 | 1746 | precheck();
|
nkeynes@416 | 1747 | check_priv_no_precheck();
|
nkeynes@359 | 1748 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1749 | check_ralign32( R_EAX );
|
nkeynes@359 | 1750 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1751 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1752 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1753 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1754 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 1755 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1756 | }
|
nkeynes@359 | 1757 | break;
|
nkeynes@359 | 1758 | default:
|
nkeynes@359 | 1759 | UNDEF();
|
nkeynes@359 | 1760 | break;
|
nkeynes@359 | 1761 | }
|
nkeynes@359 | 1762 | break;
|
nkeynes@359 | 1763 | case 0x1:
|
nkeynes@359 | 1764 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1765 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@416 | 1766 | precheck();
|
nkeynes@416 | 1767 | check_priv_no_precheck();
|
nkeynes@374 | 1768 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1769 | check_ralign32( R_EAX );
|
nkeynes@374 | 1770 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1771 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 1772 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 1773 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1774 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 1775 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1776 | }
|
nkeynes@359 | 1777 | break;
|
nkeynes@359 | 1778 | }
|
nkeynes@359 | 1779 | break;
|
nkeynes@359 | 1780 | case 0x8:
|
nkeynes@359 | 1781 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1782 | case 0x0:
|
nkeynes@359 | 1783 | { /* SHLL2 Rn */
|
nkeynes@359 | 1784 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1785 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1786 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1787 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1788 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1789 | }
|
nkeynes@359 | 1790 | break;
|
nkeynes@359 | 1791 | case 0x1:
|
nkeynes@359 | 1792 | { /* SHLL8 Rn */
|
nkeynes@359 | 1793 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1794 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1795 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1796 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1797 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1798 | }
|
nkeynes@359 | 1799 | break;
|
nkeynes@359 | 1800 | case 0x2:
|
nkeynes@359 | 1801 | { /* SHLL16 Rn */
|
nkeynes@359 | 1802 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1803 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1804 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1805 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1806 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1807 | }
|
nkeynes@359 | 1808 | break;
|
nkeynes@359 | 1809 | default:
|
nkeynes@359 | 1810 | UNDEF();
|
nkeynes@359 | 1811 | break;
|
nkeynes@359 | 1812 | }
|
nkeynes@359 | 1813 | break;
|
nkeynes@359 | 1814 | case 0x9:
|
nkeynes@359 | 1815 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1816 | case 0x0:
|
nkeynes@359 | 1817 | { /* SHLR2 Rn */
|
nkeynes@359 | 1818 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1819 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1820 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1821 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1822 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1823 | }
|
nkeynes@359 | 1824 | break;
|
nkeynes@359 | 1825 | case 0x1:
|
nkeynes@359 | 1826 | { /* SHLR8 Rn */
|
nkeynes@359 | 1827 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1828 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1829 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1830 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1831 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1832 | }
|
nkeynes@359 | 1833 | break;
|
nkeynes@359 | 1834 | case 0x2:
|
nkeynes@359 | 1835 | { /* SHLR16 Rn */
|
nkeynes@359 | 1836 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1837 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1838 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1839 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1840 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1841 | }
|
nkeynes@359 | 1842 | break;
|
nkeynes@359 | 1843 | default:
|
nkeynes@359 | 1844 | UNDEF();
|
nkeynes@359 | 1845 | break;
|
nkeynes@359 | 1846 | }
|
nkeynes@359 | 1847 | break;
|
nkeynes@359 | 1848 | case 0xA:
|
nkeynes@359 | 1849 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1850 | case 0x0:
|
nkeynes@359 | 1851 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1852 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1853 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1854 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1855 | }
|
nkeynes@359 | 1856 | break;
|
nkeynes@359 | 1857 | case 0x1:
|
nkeynes@359 | 1858 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1859 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1860 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1861 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1862 | }
|
nkeynes@359 | 1863 | break;
|
nkeynes@359 | 1864 | case 0x2:
|
nkeynes@359 | 1865 | { /* LDS Rm, PR */
|
nkeynes@359 | 1866 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1867 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1868 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1869 | }
|
nkeynes@359 | 1870 | break;
|
nkeynes@359 | 1871 | case 0x3:
|
nkeynes@359 | 1872 | { /* LDC Rm, SGR */
|
nkeynes@359 | 1873 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1874 | check_priv();
|
nkeynes@359 | 1875 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1876 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1877 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1878 | }
|
nkeynes@359 | 1879 | break;
|
nkeynes@359 | 1880 | case 0x5:
|
nkeynes@359 | 1881 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 1882 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1883 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1884 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1885 | }
|
nkeynes@359 | 1886 | break;
|
nkeynes@359 | 1887 | case 0x6:
|
nkeynes@359 | 1888 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 1889 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1890 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1891 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1892 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1893 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1894 | }
|
nkeynes@359 | 1895 | break;
|
nkeynes@359 | 1896 | case 0xF:
|
nkeynes@359 | 1897 | { /* LDC Rm, DBR */
|
nkeynes@359 | 1898 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1899 | check_priv();
|
nkeynes@359 | 1900 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1901 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1902 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1903 | }
|
nkeynes@359 | 1904 | break;
|
nkeynes@359 | 1905 | default:
|
nkeynes@359 | 1906 | UNDEF();
|
nkeynes@359 | 1907 | break;
|
nkeynes@359 | 1908 | }
|
nkeynes@359 | 1909 | break;
|
nkeynes@359 | 1910 | case 0xB:
|
nkeynes@359 | 1911 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1912 | case 0x0:
|
nkeynes@359 | 1913 | { /* JSR @Rn */
|
nkeynes@359 | 1914 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1915 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1916 | SLOTILLEGAL();
|
nkeynes@374 | 1917 | } else {
|
nkeynes@374 | 1918 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1919 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1920 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1921 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1922 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1923 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1924 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1925 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1926 | return 4;
|
nkeynes@374 | 1927 | }
|
nkeynes@359 | 1928 | }
|
nkeynes@359 | 1929 | break;
|
nkeynes@359 | 1930 | case 0x1:
|
nkeynes@359 | 1931 | { /* TAS.B @Rn */
|
nkeynes@359 | 1932 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 1933 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1934 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 1935 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1936 | SETE_t();
|
nkeynes@361 | 1937 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 1938 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1939 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1940 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1941 | }
|
nkeynes@359 | 1942 | break;
|
nkeynes@359 | 1943 | case 0x2:
|
nkeynes@359 | 1944 | { /* JMP @Rn */
|
nkeynes@359 | 1945 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1946 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1947 | SLOTILLEGAL();
|
nkeynes@374 | 1948 | } else {
|
nkeynes@408 | 1949 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1950 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1951 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1952 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1953 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1954 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1955 | return 4;
|
nkeynes@374 | 1956 | }
|
nkeynes@359 | 1957 | }
|
nkeynes@359 | 1958 | break;
|
nkeynes@359 | 1959 | default:
|
nkeynes@359 | 1960 | UNDEF();
|
nkeynes@359 | 1961 | break;
|
nkeynes@359 | 1962 | }
|
nkeynes@359 | 1963 | break;
|
nkeynes@359 | 1964 | case 0xC:
|
nkeynes@359 | 1965 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 1966 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1967 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1968 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1969 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1970 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1971 | JGE_rel8(16, doshl);
|
nkeynes@361 | 1972 |
|
nkeynes@361 | 1973 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 1974 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1975 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 1976 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1977 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 1978 |
|
nkeynes@386 | 1979 | JMP_TARGET(emptysar);
|
nkeynes@386 | 1980 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 1981 | JMP_rel8(5, end2);
|
nkeynes@386 | 1982 |
|
nkeynes@380 | 1983 | JMP_TARGET(doshl);
|
nkeynes@361 | 1984 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 1985 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 1986 | JMP_TARGET(end);
|
nkeynes@386 | 1987 | JMP_TARGET(end2);
|
nkeynes@361 | 1988 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1989 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1990 | }
|
nkeynes@359 | 1991 | break;
|
nkeynes@359 | 1992 | case 0xD:
|
nkeynes@359 | 1993 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 1994 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1995 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 1996 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 1997 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1998 | JGE_rel8(15, doshl);
|
nkeynes@368 | 1999 |
|
nkeynes@386 | 2000 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 2001 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2002 | JE_rel8( 4, emptyshr );
|
nkeynes@386 | 2003 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2004 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 2005 |
|
nkeynes@386 | 2006 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 2007 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 2008 | JMP_rel8(5, end2);
|
nkeynes@386 | 2009 |
|
nkeynes@386 | 2010 | JMP_TARGET(doshl);
|
nkeynes@386 | 2011 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2012 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2013 | JMP_TARGET(end);
|
nkeynes@386 | 2014 | JMP_TARGET(end2);
|
nkeynes@368 | 2015 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2016 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2017 | }
|
nkeynes@359 | 2018 | break;
|
nkeynes@359 | 2019 | case 0xE:
|
nkeynes@359 | 2020 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 2021 | case 0x0:
|
nkeynes@359 | 2022 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 2023 | case 0x0:
|
nkeynes@359 | 2024 | { /* LDC Rm, SR */
|
nkeynes@359 | 2025 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2026 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2027 | SLOTILLEGAL();
|
nkeynes@386 | 2028 | } else {
|
nkeynes@386 | 2029 | check_priv();
|
nkeynes@386 | 2030 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2031 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2032 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2033 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2034 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2035 | }
|
nkeynes@359 | 2036 | }
|
nkeynes@359 | 2037 | break;
|
nkeynes@359 | 2038 | case 0x1:
|
nkeynes@359 | 2039 | { /* LDC Rm, GBR */
|
nkeynes@359 | 2040 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 2041 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2042 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2043 | }
|
nkeynes@359 | 2044 | break;
|
nkeynes@359 | 2045 | case 0x2:
|
nkeynes@359 | 2046 | { /* LDC Rm, VBR */
|
nkeynes@359 | 2047 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2048 | check_priv();
|
nkeynes@359 | 2049 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2050 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2051 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2052 | }
|
nkeynes@359 | 2053 | break;
|
nkeynes@359 | 2054 | case 0x3:
|
nkeynes@359 | 2055 | { /* LDC Rm, SSR */
|
nkeynes@359 | 2056 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2057 | check_priv();
|
nkeynes@359 | 2058 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2059 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2060 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2061 | }
|
nkeynes@359 | 2062 | break;
|
nkeynes@359 | 2063 | case 0x4:
|
nkeynes@359 | 2064 | { /* LDC Rm, SPC */
|
nkeynes@359 | 2065 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2066 | check_priv();
|
nkeynes@359 | 2067 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2068 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2069 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2070 | }
|
nkeynes@359 | 2071 | break;
|
nkeynes@359 | 2072 | default:
|
nkeynes@359 | 2073 | UNDEF();
|
nkeynes@359 | 2074 | break;
|
nkeynes@359 | 2075 | }
|
nkeynes@359 | 2076 | break;
|
nkeynes@359 | 2077 | case 0x1:
|
nkeynes@359 | 2078 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2079 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 2080 | check_priv();
|
nkeynes@374 | 2081 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2082 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2083 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2084 | }
|
nkeynes@359 | 2085 | break;
|
nkeynes@359 | 2086 | }
|
nkeynes@359 | 2087 | break;
|
nkeynes@359 | 2088 | case 0xF:
|
nkeynes@359 | 2089 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2090 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 2091 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 2092 | precheck();
|
nkeynes@386 | 2093 | check_ralign16( R_ECX );
|
nkeynes@386 | 2094 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 2095 | check_ralign16( R_ECX );
|
nkeynes@386 | 2096 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 2097 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2098 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2099 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2100 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 2101 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2102 | POP_r32( R_ECX );
|
nkeynes@386 | 2103 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2104 |
|
nkeynes@386 | 2105 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2106 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 2107 | JE_rel8( 47, nosat );
|
nkeynes@386 | 2108 |
|
nkeynes@386 | 2109 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2110 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 2111 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2112 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2113 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 2114 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2115 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2116 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 2117 |
|
nkeynes@386 | 2118 | JMP_TARGET(positive);
|
nkeynes@386 | 2119 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2120 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2121 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 2122 |
|
nkeynes@386 | 2123 | JMP_TARGET(nosat);
|
nkeynes@386 | 2124 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2125 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2126 | JMP_TARGET(end);
|
nkeynes@386 | 2127 | JMP_TARGET(end2);
|
nkeynes@386 | 2128 | JMP_TARGET(end3);
|
nkeynes@417 | 2129 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2130 | }
|
nkeynes@359 | 2131 | break;
|
nkeynes@359 | 2132 | }
|
nkeynes@359 | 2133 | break;
|
nkeynes@359 | 2134 | case 0x5:
|
nkeynes@359 | 2135 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2136 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 2137 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2138 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@416 | 2139 | precheck();
|
nkeynes@374 | 2140 | check_ralign32( R_ECX );
|
nkeynes@361 | 2141 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2142 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2143 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2144 | }
|
nkeynes@359 | 2145 | break;
|
nkeynes@359 | 2146 | case 0x6:
|
nkeynes@359 | 2147 | switch( ir&0xF ) {
|
nkeynes@359 | 2148 | case 0x0:
|
nkeynes@359 | 2149 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2150 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2151 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2152 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 2153 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2154 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2155 | }
|
nkeynes@359 | 2156 | break;
|
nkeynes@359 | 2157 | case 0x1:
|
nkeynes@359 | 2158 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2159 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2160 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 2161 | precheck();
|
nkeynes@374 | 2162 | check_ralign16( R_ECX );
|
nkeynes@361 | 2163 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2164 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2165 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2166 | }
|
nkeynes@359 | 2167 | break;
|
nkeynes@359 | 2168 | case 0x2:
|
nkeynes@359 | 2169 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2170 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2171 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 2172 | precheck();
|
nkeynes@374 | 2173 | check_ralign32( R_ECX );
|
nkeynes@361 | 2174 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2175 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2176 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2177 | }
|
nkeynes@359 | 2178 | break;
|
nkeynes@359 | 2179 | case 0x3:
|
nkeynes@359 | 2180 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2181 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2182 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2183 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2184 | }
|
nkeynes@359 | 2185 | break;
|
nkeynes@359 | 2186 | case 0x4:
|
nkeynes@359 | 2187 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2188 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2189 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2190 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 2191 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 2192 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2193 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2194 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2195 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2196 | }
|
nkeynes@359 | 2197 | break;
|
nkeynes@359 | 2198 | case 0x5:
|
nkeynes@359 | 2199 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2200 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2201 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2202 | precheck();
|
nkeynes@374 | 2203 | check_ralign16( R_EAX );
|
nkeynes@361 | 2204 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2205 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 2206 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2207 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2208 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2209 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2210 | }
|
nkeynes@359 | 2211 | break;
|
nkeynes@359 | 2212 | case 0x6:
|
nkeynes@359 | 2213 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2214 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2215 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2216 | precheck();
|
nkeynes@386 | 2217 | check_ralign32( R_EAX );
|
nkeynes@361 | 2218 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2219 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 2220 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2221 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2222 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2223 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2224 | }
|
nkeynes@359 | 2225 | break;
|
nkeynes@359 | 2226 | case 0x7:
|
nkeynes@359 | 2227 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2228 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2229 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2230 | NOT_r32( R_EAX );
|
nkeynes@359 | 2231 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2232 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2233 | }
|
nkeynes@359 | 2234 | break;
|
nkeynes@359 | 2235 | case 0x8:
|
nkeynes@359 | 2236 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2237 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2238 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2239 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 2240 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2241 | }
|
nkeynes@359 | 2242 | break;
|
nkeynes@359 | 2243 | case 0x9:
|
nkeynes@359 | 2244 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2245 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2246 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2247 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2248 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2249 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2250 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2251 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 2252 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2253 | }
|
nkeynes@359 | 2254 | break;
|
nkeynes@359 | 2255 | case 0xA:
|
nkeynes@359 | 2256 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2257 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2258 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2259 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2260 | LDC_t();
|
nkeynes@359 | 2261 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2262 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2263 | SETC_t();
|
nkeynes@417 | 2264 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 2265 | }
|
nkeynes@359 | 2266 | break;
|
nkeynes@359 | 2267 | case 0xB:
|
nkeynes@359 | 2268 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2269 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2270 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2271 | NEG_r32( R_EAX );
|
nkeynes@359 | 2272 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2273 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2274 | }
|
nkeynes@359 | 2275 | break;
|
nkeynes@359 | 2276 | case 0xC:
|
nkeynes@359 | 2277 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2278 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2279 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2280 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2281 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2282 | }
|
nkeynes@359 | 2283 | break;
|
nkeynes@359 | 2284 | case 0xD:
|
nkeynes@359 | 2285 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2286 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2287 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2288 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2289 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2290 | }
|
nkeynes@359 | 2291 | break;
|
nkeynes@359 | 2292 | case 0xE:
|
nkeynes@359 | 2293 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2294 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2295 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2296 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2297 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2298 | }
|
nkeynes@359 | 2299 | break;
|
nkeynes@359 | 2300 | case 0xF:
|
nkeynes@359 | 2301 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2302 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2303 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2304 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2305 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2306 | }
|
nkeynes@359 | 2307 | break;
|
nkeynes@359 | 2308 | }
|
nkeynes@359 | 2309 | break;
|
nkeynes@359 | 2310 | case 0x7:
|
nkeynes@359 | 2311 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2312 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2313 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2314 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2315 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2316 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2317 | }
|
nkeynes@359 | 2318 | break;
|
nkeynes@359 | 2319 | case 0x8:
|
nkeynes@359 | 2320 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2321 | case 0x0:
|
nkeynes@359 | 2322 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2323 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2324 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2325 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 2326 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2327 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2328 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2329 | }
|
nkeynes@359 | 2330 | break;
|
nkeynes@359 | 2331 | case 0x1:
|
nkeynes@359 | 2332 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2333 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2334 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 2335 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2336 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2337 | precheck();
|
nkeynes@374 | 2338 | check_walign16( R_ECX );
|
nkeynes@361 | 2339 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 2340 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2341 | }
|
nkeynes@359 | 2342 | break;
|
nkeynes@359 | 2343 | case 0x4:
|
nkeynes@359 | 2344 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2345 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2346 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2347 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2348 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2349 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2350 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2351 | }
|
nkeynes@359 | 2352 | break;
|
nkeynes@359 | 2353 | case 0x5:
|
nkeynes@359 | 2354 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2355 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2356 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2357 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2358 | precheck();
|
nkeynes@374 | 2359 | check_ralign16( R_ECX );
|
nkeynes@361 | 2360 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2361 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2362 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2363 | }
|
nkeynes@359 | 2364 | break;
|
nkeynes@359 | 2365 | case 0x8:
|
nkeynes@359 | 2366 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2367 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2368 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2369 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2370 | SETE_t();
|
nkeynes@417 | 2371 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2372 | }
|
nkeynes@359 | 2373 | break;
|
nkeynes@359 | 2374 | case 0x9:
|
nkeynes@359 | 2375 | { /* BT disp */
|
nkeynes@359 | 2376 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2377 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2378 | SLOTILLEGAL();
|
nkeynes@374 | 2379 | } else {
|
nkeynes@527 | 2380 | JF_rel8( EXIT_BLOCK_SIZE, nottaken );
|
nkeynes@408 | 2381 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 2382 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2383 | return 2;
|
nkeynes@374 | 2384 | }
|
nkeynes@359 | 2385 | }
|
nkeynes@359 | 2386 | break;
|
nkeynes@359 | 2387 | case 0xB:
|
nkeynes@359 | 2388 | { /* BF disp */
|
nkeynes@359 | 2389 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2390 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2391 | SLOTILLEGAL();
|
nkeynes@374 | 2392 | } else {
|
nkeynes@527 | 2393 | JT_rel8( EXIT_BLOCK_SIZE, nottaken );
|
nkeynes@408 | 2394 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 2395 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2396 | return 2;
|
nkeynes@374 | 2397 | }
|
nkeynes@359 | 2398 | }
|
nkeynes@359 | 2399 | break;
|
nkeynes@359 | 2400 | case 0xD:
|
nkeynes@359 | 2401 | { /* BT/S disp */
|
nkeynes@359 | 2402 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2403 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2404 | SLOTILLEGAL();
|
nkeynes@374 | 2405 | } else {
|
nkeynes@408 | 2406 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 2407 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2408 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2409 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2410 | }
|
nkeynes@417 | 2411 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@526 | 2412 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2413 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2414 | // not taken
|
nkeynes@408 | 2415 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2416 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2417 | return 4;
|
nkeynes@374 | 2418 | }
|
nkeynes@359 | 2419 | }
|
nkeynes@359 | 2420 | break;
|
nkeynes@359 | 2421 | case 0xF:
|
nkeynes@359 | 2422 | { /* BF/S disp */
|
nkeynes@359 | 2423 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2424 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2425 | SLOTILLEGAL();
|
nkeynes@374 | 2426 | } else {
|
nkeynes@408 | 2427 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 2428 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2429 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2430 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2431 | }
|
nkeynes@417 | 2432 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@526 | 2433 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2434 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2435 | // not taken
|
nkeynes@408 | 2436 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2437 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2438 | return 4;
|
nkeynes@374 | 2439 | }
|
nkeynes@359 | 2440 | }
|
nkeynes@359 | 2441 | break;
|
nkeynes@359 | 2442 | default:
|
nkeynes@359 | 2443 | UNDEF();
|
nkeynes@359 | 2444 | break;
|
nkeynes@359 | 2445 | }
|
nkeynes@359 | 2446 | break;
|
nkeynes@359 | 2447 | case 0x9:
|
nkeynes@359 | 2448 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2449 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@374 | 2450 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2451 | SLOTILLEGAL();
|
nkeynes@374 | 2452 | } else {
|
nkeynes@374 | 2453 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 2454 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 2455 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2456 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2457 | }
|
nkeynes@359 | 2458 | }
|
nkeynes@359 | 2459 | break;
|
nkeynes@359 | 2460 | case 0xA:
|
nkeynes@359 | 2461 | { /* BRA disp */
|
nkeynes@359 | 2462 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2463 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2464 | SLOTILLEGAL();
|
nkeynes@374 | 2465 | } else {
|
nkeynes@374 | 2466 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 2467 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 2468 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2469 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2470 | return 4;
|
nkeynes@374 | 2471 | }
|
nkeynes@359 | 2472 | }
|
nkeynes@359 | 2473 | break;
|
nkeynes@359 | 2474 | case 0xB:
|
nkeynes@359 | 2475 | { /* BSR disp */
|
nkeynes@359 | 2476 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2477 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2478 | SLOTILLEGAL();
|
nkeynes@374 | 2479 | } else {
|
nkeynes@374 | 2480 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 2481 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 2482 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 2483 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 2484 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2485 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2486 | return 4;
|
nkeynes@374 | 2487 | }
|
nkeynes@359 | 2488 | }
|
nkeynes@359 | 2489 | break;
|
nkeynes@359 | 2490 | case 0xC:
|
nkeynes@359 | 2491 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2492 | case 0x0:
|
nkeynes@359 | 2493 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2494 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2495 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2496 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2497 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2498 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2499 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2500 | }
|
nkeynes@359 | 2501 | break;
|
nkeynes@359 | 2502 | case 0x1:
|
nkeynes@359 | 2503 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2504 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2505 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2506 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2507 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2508 | precheck();
|
nkeynes@374 | 2509 | check_walign16( R_ECX );
|
nkeynes@361 | 2510 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 2511 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2512 | }
|
nkeynes@359 | 2513 | break;
|
nkeynes@359 | 2514 | case 0x2:
|
nkeynes@359 | 2515 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2516 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2517 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2518 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2519 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2520 | precheck();
|
nkeynes@374 | 2521 | check_walign32( R_ECX );
|
nkeynes@361 | 2522 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 2523 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2524 | }
|
nkeynes@359 | 2525 | break;
|
nkeynes@359 | 2526 | case 0x3:
|
nkeynes@359 | 2527 | { /* TRAPA #imm */
|
nkeynes@359 | 2528 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2529 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2530 | SLOTILLEGAL();
|
nkeynes@374 | 2531 | } else {
|
nkeynes@533 | 2532 | load_imm32( R_ECX, pc+2 );
|
nkeynes@533 | 2533 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 2534 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 2535 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@417 | 2536 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 2537 | exit_block_pcset(pc);
|
nkeynes@409 | 2538 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2539 | return 2;
|
nkeynes@374 | 2540 | }
|
nkeynes@359 | 2541 | }
|
nkeynes@359 | 2542 | break;
|
nkeynes@359 | 2543 | case 0x4:
|
nkeynes@359 | 2544 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2545 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2546 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2547 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2548 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2549 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2550 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2551 | }
|
nkeynes@359 | 2552 | break;
|
nkeynes@359 | 2553 | case 0x5:
|
nkeynes@359 | 2554 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2555 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2556 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2557 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2558 | precheck();
|
nkeynes@374 | 2559 | check_ralign16( R_ECX );
|
nkeynes@361 | 2560 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2561 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2562 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2563 | }
|
nkeynes@359 | 2564 | break;
|
nkeynes@359 | 2565 | case 0x6:
|
nkeynes@359 | 2566 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2567 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2568 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2569 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 2570 | precheck();
|
nkeynes@374 | 2571 | check_ralign32( R_ECX );
|
nkeynes@361 | 2572 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2573 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2574 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2575 | }
|
nkeynes@359 | 2576 | break;
|
nkeynes@359 | 2577 | case 0x7:
|
nkeynes@359 | 2578 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2579 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2580 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2581 | SLOTILLEGAL();
|
nkeynes@374 | 2582 | } else {
|
nkeynes@374 | 2583 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 2584 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 2585 | }
|
nkeynes@359 | 2586 | }
|
nkeynes@359 | 2587 | break;
|
nkeynes@359 | 2588 | case 0x8:
|
nkeynes@359 | 2589 | { /* TST #imm, R0 */
|
nkeynes@359 | 2590 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2591 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2592 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2593 | SETE_t();
|
nkeynes@417 | 2594 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2595 | }
|
nkeynes@359 | 2596 | break;
|
nkeynes@359 | 2597 | case 0x9:
|
nkeynes@359 | 2598 | { /* AND #imm, R0 */
|
nkeynes@359 | 2599 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2600 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2601 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2602 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2603 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2604 | }
|
nkeynes@359 | 2605 | break;
|
nkeynes@359 | 2606 | case 0xA:
|
nkeynes@359 | 2607 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2608 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2609 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2610 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2611 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2612 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2613 | }
|
nkeynes@359 | 2614 | break;
|
nkeynes@359 | 2615 | case 0xB:
|
nkeynes@359 | 2616 | { /* OR #imm, R0 */
|
nkeynes@359 | 2617 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2618 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2619 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2620 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2621 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2622 | }
|
nkeynes@359 | 2623 | break;
|
nkeynes@359 | 2624 | case 0xC:
|
nkeynes@359 | 2625 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2626 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2627 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2628 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 2629 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 2630 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 2631 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2632 | SETE_t();
|
nkeynes@417 | 2633 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2634 | }
|
nkeynes@359 | 2635 | break;
|
nkeynes@359 | 2636 | case 0xD:
|
nkeynes@359 | 2637 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2638 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2639 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2640 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2641 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2642 | PUSH_r32(R_ECX);
|
nkeynes@527 | 2643 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 2644 | POP_r32(R_ECX);
|
nkeynes@386 | 2645 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2646 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2647 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2648 | }
|
nkeynes@359 | 2649 | break;
|
nkeynes@359 | 2650 | case 0xE:
|
nkeynes@359 | 2651 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2652 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2653 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2654 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2655 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2656 | PUSH_r32(R_ECX);
|
nkeynes@527 | 2657 | MEM_READ_BYTE(R_ECX, R_EAX);
|
nkeynes@386 | 2658 | POP_r32(R_ECX);
|
nkeynes@359 | 2659 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2660 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2661 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2662 | }
|
nkeynes@359 | 2663 | break;
|
nkeynes@359 | 2664 | case 0xF:
|
nkeynes@359 | 2665 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2666 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2667 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2668 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2669 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2670 | PUSH_r32(R_ECX);
|
nkeynes@527 | 2671 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 2672 | POP_r32(R_ECX);
|
nkeynes@386 | 2673 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2674 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2675 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2676 | }
|
nkeynes@359 | 2677 | break;
|
nkeynes@359 | 2678 | }
|
nkeynes@359 | 2679 | break;
|
nkeynes@359 | 2680 | case 0xD:
|
nkeynes@359 | 2681 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2682 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2683 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2684 | SLOTILLEGAL();
|
nkeynes@374 | 2685 | } else {
|
nkeynes@388 | 2686 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@502 | 2687 | sh4ptr_t ptr = mem_get_region(target);
|
nkeynes@388 | 2688 | if( ptr != NULL ) {
|
nkeynes@527 | 2689 | MOV_moff32_EAX( ptr );
|
nkeynes@388 | 2690 | } else {
|
nkeynes@388 | 2691 | load_imm32( R_ECX, target );
|
nkeynes@388 | 2692 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 2693 | }
|
nkeynes@386 | 2694 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2695 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2696 | }
|
nkeynes@359 | 2697 | }
|
nkeynes@359 | 2698 | break;
|
nkeynes@359 | 2699 | case 0xE:
|
nkeynes@359 | 2700 | { /* MOV #imm, Rn */
|
nkeynes@359 | 2701 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2702 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 2703 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2704 | }
|
nkeynes@359 | 2705 | break;
|
nkeynes@359 | 2706 | case 0xF:
|
nkeynes@359 | 2707 | switch( ir&0xF ) {
|
nkeynes@359 | 2708 | case 0x0:
|
nkeynes@359 | 2709 | { /* FADD FRm, FRn */
|
nkeynes@359 | 2710 | |