Search
lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.in
changeset 539:75f3e594d4a7
prev533:9764673fd4a5
next547:d6e00ffc4adc
author nkeynes
date Wed Nov 21 11:40:15 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add support for the darwin ABI
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@502
     2
 * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359
    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359
    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@368
    21
#include <assert.h>
nkeynes@388
    22
#include <math.h>
nkeynes@368
    23
nkeynes@380
    24
#ifndef NDEBUG
nkeynes@380
    25
#define DEBUG_JUMPS 1
nkeynes@380
    26
#endif
nkeynes@380
    27
nkeynes@417
    28
#include "sh4/xltcache.h"
nkeynes@368
    29
#include "sh4/sh4core.h"
nkeynes@368
    30
#include "sh4/sh4trans.h"
nkeynes@388
    31
#include "sh4/sh4mmio.h"
nkeynes@368
    32
#include "sh4/x86op.h"
nkeynes@368
    33
#include "clock.h"
nkeynes@368
    34
nkeynes@368
    35
#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368
    36
nkeynes@368
    37
/** 
nkeynes@368
    38
 * Struct to manage internal translation state. This state is not saved -
nkeynes@368
    39
 * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368
    40
 * sh4_translate_end_block()
nkeynes@368
    41
 */
nkeynes@368
    42
struct sh4_x86_state {
nkeynes@368
    43
    gboolean in_delay_slot;
nkeynes@368
    44
    gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368
    45
    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409
    46
    gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@408
    47
    uint32_t block_start_pc;
nkeynes@539
    48
	uint32_t stack_posn;   /* Trace stack height for alignment purposes */
nkeynes@417
    49
    int tstate;
nkeynes@368
    50
nkeynes@368
    51
    /* Allocated memory for the (block-wide) back-patch list */
nkeynes@368
    52
    uint32_t **backpatch_list;
nkeynes@368
    53
    uint32_t backpatch_posn;
nkeynes@368
    54
    uint32_t backpatch_size;
nkeynes@368
    55
};
nkeynes@368
    56
nkeynes@417
    57
#define TSTATE_NONE -1
nkeynes@417
    58
#define TSTATE_O    0
nkeynes@417
    59
#define TSTATE_C    2
nkeynes@417
    60
#define TSTATE_E    4
nkeynes@417
    61
#define TSTATE_NE   5
nkeynes@417
    62
#define TSTATE_G    0xF
nkeynes@417
    63
#define TSTATE_GE   0xD
nkeynes@417
    64
#define TSTATE_A    7
nkeynes@417
    65
#define TSTATE_AE   3
nkeynes@417
    66
nkeynes@417
    67
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@417
    68
#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    69
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    70
    OP(0x70+sh4_x86.tstate); OP(rel8); \
nkeynes@417
    71
    MARK_JMP(rel8,label)
nkeynes@417
    72
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@417
    73
#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    74
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    75
    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
nkeynes@417
    76
    MARK_JMP(rel8, label)
nkeynes@417
    77
nkeynes@417
    78
nkeynes@368
    79
#define EXIT_DATA_ADDR_READ 0
nkeynes@368
    80
#define EXIT_DATA_ADDR_WRITE 7
nkeynes@368
    81
#define EXIT_ILLEGAL 14
nkeynes@368
    82
#define EXIT_SLOT_ILLEGAL 21
nkeynes@368
    83
#define EXIT_FPU_DISABLED 28
nkeynes@368
    84
#define EXIT_SLOT_FPU_DISABLED 35
nkeynes@368
    85
nkeynes@368
    86
static struct sh4_x86_state sh4_x86;
nkeynes@368
    87
nkeynes@388
    88
static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388
    89
static uint32_t min_int = 0x80000000;
nkeynes@394
    90
static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394
    91
static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386
    92
nkeynes@368
    93
void sh4_x86_init()
nkeynes@368
    94
{
nkeynes@368
    95
    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@368
    96
    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
nkeynes@368
    97
}
nkeynes@368
    98
nkeynes@368
    99
nkeynes@368
   100
static void sh4_x86_add_backpatch( uint8_t *ptr )
nkeynes@368
   101
{
nkeynes@368
   102
    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368
   103
	sh4_x86.backpatch_size <<= 1;
nkeynes@368
   104
	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
nkeynes@368
   105
	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368
   106
    }
nkeynes@368
   107
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
nkeynes@368
   108
}
nkeynes@368
   109
nkeynes@368
   110
static void sh4_x86_do_backpatch( uint8_t *reloc_base )
nkeynes@368
   111
{
nkeynes@368
   112
    unsigned int i;
nkeynes@368
   113
    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
nkeynes@374
   114
	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
nkeynes@368
   115
    }
nkeynes@368
   116
}
nkeynes@368
   117
nkeynes@359
   118
/**
nkeynes@359
   119
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
   120
 */
nkeynes@359
   121
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
   122
{
nkeynes@359
   123
    /* mov [bp+n], reg */
nkeynes@361
   124
    OP(0x8B);
nkeynes@361
   125
    OP(0x45 + (x86reg<<3));
nkeynes@359
   126
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   127
}
nkeynes@359
   128
nkeynes@374
   129
static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368
   130
{
nkeynes@374
   131
    OP(0x0F);
nkeynes@374
   132
    OP(0xBF);
nkeynes@374
   133
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368
   134
}
nkeynes@368
   135
nkeynes@374
   136
static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368
   137
{
nkeynes@374
   138
    OP(0x0F);
nkeynes@374
   139
    OP(0xB7);
nkeynes@374
   140
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374
   141
nkeynes@368
   142
}
nkeynes@368
   143
nkeynes@380
   144
#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380
   145
#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359
   146
/**
nkeynes@359
   147
 * Emit an instruction to load an immediate value into a register
nkeynes@359
   148
 */
nkeynes@359
   149
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
   150
    /* mov #value, reg */
nkeynes@359
   151
    OP(0xB8 + x86reg);
nkeynes@359
   152
    OP32(value);
nkeynes@359
   153
}
nkeynes@359
   154
nkeynes@359
   155
/**
nkeynes@527
   156
 * Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527
   157
 */
nkeynes@527
   158
static inline void load_imm64( int x86reg, uint32_t value ) {
nkeynes@527
   159
    /* mov #value, reg */
nkeynes@527
   160
    REXW();
nkeynes@527
   161
    OP(0xB8 + x86reg);
nkeynes@527
   162
    OP64(value);
nkeynes@527
   163
}
nkeynes@527
   164
nkeynes@527
   165
nkeynes@527
   166
/**
nkeynes@359
   167
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
   168
 */
nkeynes@359
   169
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
   170
    /* mov reg, [bp+n] */
nkeynes@361
   171
    OP(0x89);
nkeynes@361
   172
    OP(0x45 + (x86reg<<3));
nkeynes@359
   173
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   174
}
nkeynes@374
   175
nkeynes@374
   176
#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374
   177
nkeynes@375
   178
/**
nkeynes@375
   179
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   180
 * register (eg for register-to-register moves)
nkeynes@375
   181
 */
nkeynes@375
   182
void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375
   183
{
nkeynes@375
   184
    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375
   185
}
nkeynes@375
   186
nkeynes@375
   187
/**
nkeynes@375
   188
 * Store an FR register (single-precision floating point) into an integer x86
nkeynes@375
   189
 * register (eg for register-to-register moves)
nkeynes@375
   190
 */
nkeynes@375
   191
void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375
   192
{
nkeynes@375
   193
    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375
   194
}
nkeynes@375
   195
nkeynes@375
   196
nkeynes@375
   197
/**
nkeynes@375
   198
 * Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375
   199
 * bankreg must have been previously loaded with FPSCR.
nkeynes@388
   200
 * NB: 12 bytes
nkeynes@375
   201
 */
nkeynes@374
   202
static inline void load_xf_bank( int bankreg )
nkeynes@374
   203
{
nkeynes@386
   204
    NOT_r32( bankreg );
nkeynes@374
   205
    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374
   206
    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
nkeynes@374
   207
    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374
   208
}
nkeynes@374
   209
nkeynes@375
   210
/**
nkeynes@386
   211
 * Update the fr_bank pointer based on the current fpscr value.
nkeynes@386
   212
 */
nkeynes@386
   213
static inline void update_fr_bank( int fpscrreg )
nkeynes@386
   214
{
nkeynes@386
   215
    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386
   216
    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
nkeynes@386
   217
    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386
   218
    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386
   219
}
nkeynes@386
   220
/**
nkeynes@377
   221
 * Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377
   222
 */
nkeynes@377
   223
static inline void push_fpul( )
nkeynes@377
   224
{
nkeynes@377
   225
    OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377
   226
}
nkeynes@377
   227
nkeynes@377
   228
/**
nkeynes@377
   229
 * Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377
   230
 */
nkeynes@377
   231
static inline void pop_fpul( )
nkeynes@377
   232
{
nkeynes@377
   233
    OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377
   234
}
nkeynes@377
   235
nkeynes@377
   236
/**
nkeynes@375
   237
 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375
   238
 * with the location of the current fp bank.
nkeynes@375
   239
 */
nkeynes@374
   240
static inline void push_fr( int bankreg, int frm ) 
nkeynes@374
   241
{
nkeynes@374
   242
    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
nkeynes@374
   243
}
nkeynes@374
   244
nkeynes@375
   245
/**
nkeynes@375
   246
 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
nkeynes@375
   247
 * with bankreg previously loaded with the location of the current fp bank.
nkeynes@375
   248
 */
nkeynes@374
   249
static inline void pop_fr( int bankreg, int frm )
nkeynes@374
   250
{
nkeynes@374
   251
    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374
   252
}
nkeynes@374
   253
nkeynes@375
   254
/**
nkeynes@375
   255
 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375
   256
 * with the location of the current fp bank.
nkeynes@375
   257
 */
nkeynes@374
   258
static inline void push_dr( int bankreg, int frm )
nkeynes@374
   259
{
nkeynes@375
   260
    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374
   261
}
nkeynes@374
   262
nkeynes@374
   263
static inline void pop_dr( int bankreg, int frm )
nkeynes@374
   264
{
nkeynes@375
   265
    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374
   266
}
nkeynes@374
   267
nkeynes@368
   268
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   269
#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
nkeynes@416
   270
nkeynes@416
   271
#define check_priv( ) \
nkeynes@416
   272
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   273
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   274
	precheck();\
nkeynes@416
   275
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   276
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   277
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   278
	    JE_exit( EXIT_SLOT_ILLEGAL );\
nkeynes@416
   279
	} else {\
nkeynes@416
   280
	    JE_exit( EXIT_ILLEGAL );\
nkeynes@416
   281
	}\
nkeynes@416
   282
    }\
nkeynes@416
   283
nkeynes@416
   284
nkeynes@416
   285
static void check_priv_no_precheck()
nkeynes@368
   286
{
nkeynes@368
   287
    if( !sh4_x86.priv_checked ) {
nkeynes@368
   288
	sh4_x86.priv_checked = TRUE;
nkeynes@368
   289
	load_spreg( R_EAX, R_SR );
nkeynes@368
   290
	AND_imm32_r32( SR_MD, R_EAX );
nkeynes@368
   291
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   292
	    JE_exit( EXIT_SLOT_ILLEGAL );
nkeynes@368
   293
	} else {
nkeynes@368
   294
	    JE_exit( EXIT_ILLEGAL );
nkeynes@368
   295
	}
nkeynes@368
   296
    }
nkeynes@368
   297
}
nkeynes@368
   298
nkeynes@416
   299
#define check_fpuen( ) \
nkeynes@416
   300
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   301
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   302
	precheck();\
nkeynes@416
   303
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   304
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   305
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   306
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
nkeynes@416
   307
	} else {\
nkeynes@416
   308
	    JNE_exit(EXIT_FPU_DISABLED);\
nkeynes@416
   309
	}\
nkeynes@416
   310
    }
nkeynes@416
   311
nkeynes@416
   312
static void check_fpuen_no_precheck()
nkeynes@368
   313
{
nkeynes@368
   314
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   315
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   316
	load_spreg( R_EAX, R_SR );
nkeynes@368
   317
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   318
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   319
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   320
	} else {
nkeynes@368
   321
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   322
	}
nkeynes@368
   323
    }
nkeynes@416
   324
nkeynes@368
   325
}
nkeynes@368
   326
nkeynes@368
   327
static void check_ralign16( int x86reg )
nkeynes@368
   328
{
nkeynes@368
   329
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   330
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   331
}
nkeynes@368
   332
nkeynes@368
   333
static void check_walign16( int x86reg )
nkeynes@368
   334
{
nkeynes@368
   335
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   336
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   337
}
nkeynes@368
   338
nkeynes@368
   339
static void check_ralign32( int x86reg )
nkeynes@368
   340
{
nkeynes@368
   341
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   342
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   343
}
nkeynes@368
   344
static void check_walign32( int x86reg )
nkeynes@368
   345
{
nkeynes@368
   346
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   347
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   348
}
nkeynes@368
   349
nkeynes@361
   350
#define UNDEF()
nkeynes@361
   351
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   352
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   353
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   354
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   355
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   356
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   357
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   358
nkeynes@416
   359
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   360
nkeynes@388
   361
extern uint16_t *sh4_icache;
nkeynes@388
   362
extern uint32_t sh4_icache_addr;
nkeynes@388
   363
nkeynes@539
   364
/****** Import appropriate calling conventions ******/
nkeynes@539
   365
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   366
#include "sh4/ia64abi.h"
nkeynes@539
   367
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   368
#ifdef APPLE_BUILD
nkeynes@539
   369
#include "sh4/ia32mac.h"
nkeynes@539
   370
#else
nkeynes@539
   371
#include "sh4/ia32abi.h"
nkeynes@539
   372
#endif
nkeynes@539
   373
#endif
nkeynes@539
   374
nkeynes@539
   375
nkeynes@359
   376
/**
nkeynes@359
   377
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   378
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   379
 * 
nkeynes@359
   380
 *
nkeynes@359
   381
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   382
 * (eg a branch or 
nkeynes@359
   383
 */
nkeynes@526
   384
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   385
{
nkeynes@388
   386
    uint32_t ir;
nkeynes@388
   387
    /* Read instruction */
nkeynes@388
   388
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   389
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   390
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   391
    } else {
nkeynes@388
   392
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@527
   393
	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   394
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   395
	     * region, fallback on the full-blown memory read
nkeynes@388
   396
	     */
nkeynes@388
   397
	    sh4_icache = NULL;
nkeynes@388
   398
	    ir = sh4_read_word(pc);
nkeynes@388
   399
	} else {
nkeynes@388
   400
	    sh4_icache_addr = pageaddr;
nkeynes@388
   401
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   402
	}
nkeynes@388
   403
    }
nkeynes@388
   404
nkeynes@359
   405
%%
nkeynes@359
   406
/* ALU operations */
nkeynes@359
   407
ADD Rm, Rn {:
nkeynes@359
   408
    load_reg( R_EAX, Rm );
nkeynes@359
   409
    load_reg( R_ECX, Rn );
nkeynes@359
   410
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   411
    store_reg( R_ECX, Rn );
nkeynes@417
   412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   413
:}
nkeynes@359
   414
ADD #imm, Rn {:  
nkeynes@359
   415
    load_reg( R_EAX, Rn );
nkeynes@359
   416
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   417
    store_reg( R_EAX, Rn );
nkeynes@417
   418
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   419
:}
nkeynes@359
   420
ADDC Rm, Rn {:
nkeynes@417
   421
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   422
	LDC_t();
nkeynes@417
   423
    }
nkeynes@359
   424
    load_reg( R_EAX, Rm );
nkeynes@359
   425
    load_reg( R_ECX, Rn );
nkeynes@359
   426
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   427
    store_reg( R_ECX, Rn );
nkeynes@359
   428
    SETC_t();
nkeynes@417
   429
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   430
:}
nkeynes@359
   431
ADDV Rm, Rn {:
nkeynes@359
   432
    load_reg( R_EAX, Rm );
nkeynes@359
   433
    load_reg( R_ECX, Rn );
nkeynes@359
   434
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   435
    store_reg( R_ECX, Rn );
nkeynes@359
   436
    SETO_t();
nkeynes@417
   437
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   438
:}
nkeynes@359
   439
AND Rm, Rn {:
nkeynes@359
   440
    load_reg( R_EAX, Rm );
nkeynes@359
   441
    load_reg( R_ECX, Rn );
nkeynes@359
   442
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   443
    store_reg( R_ECX, Rn );
nkeynes@417
   444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   445
:}
nkeynes@359
   446
AND #imm, R0 {:  
nkeynes@359
   447
    load_reg( R_EAX, 0 );
nkeynes@359
   448
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   449
    store_reg( R_EAX, 0 );
nkeynes@417
   450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   451
:}
nkeynes@359
   452
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   453
    load_reg( R_EAX, 0 );
nkeynes@359
   454
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   455
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   456
    PUSH_r32(R_ECX);
nkeynes@527
   457
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
   458
    POP_r32(R_ECX);
nkeynes@386
   459
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   460
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   462
:}
nkeynes@359
   463
CMP/EQ Rm, Rn {:  
nkeynes@359
   464
    load_reg( R_EAX, Rm );
nkeynes@359
   465
    load_reg( R_ECX, Rn );
nkeynes@359
   466
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   467
    SETE_t();
nkeynes@417
   468
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   469
:}
nkeynes@359
   470
CMP/EQ #imm, R0 {:  
nkeynes@359
   471
    load_reg( R_EAX, 0 );
nkeynes@359
   472
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   473
    SETE_t();
nkeynes@417
   474
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   475
:}
nkeynes@359
   476
CMP/GE Rm, Rn {:  
nkeynes@359
   477
    load_reg( R_EAX, Rm );
nkeynes@359
   478
    load_reg( R_ECX, Rn );
nkeynes@359
   479
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   480
    SETGE_t();
nkeynes@417
   481
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   482
:}
nkeynes@359
   483
CMP/GT Rm, Rn {: 
nkeynes@359
   484
    load_reg( R_EAX, Rm );
nkeynes@359
   485
    load_reg( R_ECX, Rn );
nkeynes@359
   486
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   487
    SETG_t();
nkeynes@417
   488
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   489
:}
nkeynes@359
   490
CMP/HI Rm, Rn {:  
nkeynes@359
   491
    load_reg( R_EAX, Rm );
nkeynes@359
   492
    load_reg( R_ECX, Rn );
nkeynes@359
   493
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   494
    SETA_t();
nkeynes@417
   495
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   496
:}
nkeynes@359
   497
CMP/HS Rm, Rn {: 
nkeynes@359
   498
    load_reg( R_EAX, Rm );
nkeynes@359
   499
    load_reg( R_ECX, Rn );
nkeynes@359
   500
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   501
    SETAE_t();
nkeynes@417
   502
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   503
 :}
nkeynes@359
   504
CMP/PL Rn {: 
nkeynes@359
   505
    load_reg( R_EAX, Rn );
nkeynes@359
   506
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   507
    SETG_t();
nkeynes@417
   508
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   509
:}
nkeynes@359
   510
CMP/PZ Rn {:  
nkeynes@359
   511
    load_reg( R_EAX, Rn );
nkeynes@359
   512
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   513
    SETGE_t();
nkeynes@417
   514
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   515
:}
nkeynes@361
   516
CMP/STR Rm, Rn {:  
nkeynes@368
   517
    load_reg( R_EAX, Rm );
nkeynes@368
   518
    load_reg( R_ECX, Rn );
nkeynes@368
   519
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   520
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   521
    JE_rel8(13, target1);
nkeynes@368
   522
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   523
    JE_rel8(9, target2);
nkeynes@368
   524
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   525
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   526
    JE_rel8(2, target3);
nkeynes@368
   527
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   528
    JMP_TARGET(target1);
nkeynes@380
   529
    JMP_TARGET(target2);
nkeynes@380
   530
    JMP_TARGET(target3);
nkeynes@368
   531
    SETE_t();
nkeynes@417
   532
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   533
:}
nkeynes@361
   534
DIV0S Rm, Rn {:
nkeynes@361
   535
    load_reg( R_EAX, Rm );
nkeynes@386
   536
    load_reg( R_ECX, Rn );
nkeynes@361
   537
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   538
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   539
    store_spreg( R_EAX, R_M );
nkeynes@361
   540
    store_spreg( R_ECX, R_Q );
nkeynes@361
   541
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   542
    SETNE_t();
nkeynes@417
   543
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   544
:}
nkeynes@361
   545
DIV0U {:  
nkeynes@361
   546
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   547
    store_spreg( R_EAX, R_Q );
nkeynes@361
   548
    store_spreg( R_EAX, R_M );
nkeynes@361
   549
    store_spreg( R_EAX, R_T );
nkeynes@417
   550
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   551
:}
nkeynes@386
   552
DIV1 Rm, Rn {:
nkeynes@386
   553
    load_spreg( R_ECX, R_M );
nkeynes@386
   554
    load_reg( R_EAX, Rn );
nkeynes@417
   555
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   556
	LDC_t();
nkeynes@417
   557
    }
nkeynes@386
   558
    RCL1_r32( R_EAX );
nkeynes@386
   559
    SETC_r8( R_DL ); // Q'
nkeynes@386
   560
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   561
    JE_rel8(5, mqequal);
nkeynes@386
   562
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   563
    JMP_rel8(3, end);
nkeynes@380
   564
    JMP_TARGET(mqequal);
nkeynes@386
   565
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   566
    JMP_TARGET(end);
nkeynes@386
   567
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   568
    SETC_r8(R_AL); // tmp1
nkeynes@386
   569
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   570
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   571
    store_spreg( R_ECX, R_Q );
nkeynes@386
   572
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   573
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   574
    store_spreg( R_EAX, R_T );
nkeynes@417
   575
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   576
:}
nkeynes@361
   577
DMULS.L Rm, Rn {:  
nkeynes@361
   578
    load_reg( R_EAX, Rm );
nkeynes@361
   579
    load_reg( R_ECX, Rn );
nkeynes@361
   580
    IMUL_r32(R_ECX);
nkeynes@361
   581
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   582
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   583
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   584
:}
nkeynes@361
   585
DMULU.L Rm, Rn {:  
nkeynes@361
   586
    load_reg( R_EAX, Rm );
nkeynes@361
   587
    load_reg( R_ECX, Rn );
nkeynes@361
   588
    MUL_r32(R_ECX);
nkeynes@361
   589
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   590
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   592
:}
nkeynes@359
   593
DT Rn {:  
nkeynes@359
   594
    load_reg( R_EAX, Rn );
nkeynes@382
   595
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   596
    store_reg( R_EAX, Rn );
nkeynes@359
   597
    SETE_t();
nkeynes@417
   598
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   599
:}
nkeynes@359
   600
EXTS.B Rm, Rn {:  
nkeynes@359
   601
    load_reg( R_EAX, Rm );
nkeynes@359
   602
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   603
    store_reg( R_EAX, Rn );
nkeynes@359
   604
:}
nkeynes@361
   605
EXTS.W Rm, Rn {:  
nkeynes@361
   606
    load_reg( R_EAX, Rm );
nkeynes@361
   607
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   608
    store_reg( R_EAX, Rn );
nkeynes@361
   609
:}
nkeynes@361
   610
EXTU.B Rm, Rn {:  
nkeynes@361
   611
    load_reg( R_EAX, Rm );
nkeynes@361
   612
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   613
    store_reg( R_EAX, Rn );
nkeynes@361
   614
:}
nkeynes@361
   615
EXTU.W Rm, Rn {:  
nkeynes@361
   616
    load_reg( R_EAX, Rm );
nkeynes@361
   617
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   618
    store_reg( R_EAX, Rn );
nkeynes@361
   619
:}
nkeynes@386
   620
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   621
    load_reg( R_ECX, Rm );
nkeynes@416
   622
    precheck();
nkeynes@386
   623
    check_ralign32( R_ECX );
nkeynes@386
   624
    load_reg( R_ECX, Rn );
nkeynes@386
   625
    check_ralign32( R_ECX );
nkeynes@386
   626
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   627
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   628
    PUSH_r32( R_EAX );
nkeynes@386
   629
    load_reg( R_ECX, Rm );
nkeynes@386
   630
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   631
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   632
    POP_r32( R_ECX );
nkeynes@386
   633
    IMUL_r32( R_ECX );
nkeynes@386
   634
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   635
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   636
nkeynes@386
   637
    load_spreg( R_ECX, R_S );
nkeynes@386
   638
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   639
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   640
    call_func0( signsat48 );
nkeynes@386
   641
    JMP_TARGET( nosat );
nkeynes@417
   642
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   643
:}
nkeynes@386
   644
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   645
    load_reg( R_ECX, Rm );
nkeynes@416
   646
    precheck();
nkeynes@386
   647
    check_ralign16( R_ECX );
nkeynes@386
   648
    load_reg( R_ECX, Rn );
nkeynes@386
   649
    check_ralign16( R_ECX );
nkeynes@386
   650
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   651
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   652
    PUSH_r32( R_EAX );
nkeynes@386
   653
    load_reg( R_ECX, Rm );
nkeynes@386
   654
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   655
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   656
    POP_r32( R_ECX );
nkeynes@386
   657
    IMUL_r32( R_ECX );
nkeynes@386
   658
nkeynes@386
   659
    load_spreg( R_ECX, R_S );
nkeynes@386
   660
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   661
    JE_rel8( 47, nosat );
nkeynes@386
   662
nkeynes@386
   663
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   664
    JNO_rel8( 51, end );            // 2
nkeynes@386
   665
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   666
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   667
    JS_rel8( 13, positive );        // 2
nkeynes@386
   668
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   669
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   670
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   671
nkeynes@386
   672
    JMP_TARGET(positive);
nkeynes@386
   673
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   674
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   675
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   676
nkeynes@386
   677
    JMP_TARGET(nosat);
nkeynes@386
   678
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   679
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   680
    JMP_TARGET(end);
nkeynes@386
   681
    JMP_TARGET(end2);
nkeynes@386
   682
    JMP_TARGET(end3);
nkeynes@417
   683
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   684
:}
nkeynes@359
   685
MOVT Rn {:  
nkeynes@359
   686
    load_spreg( R_EAX, R_T );
nkeynes@359
   687
    store_reg( R_EAX, Rn );
nkeynes@359
   688
:}
nkeynes@361
   689
MUL.L Rm, Rn {:  
nkeynes@361
   690
    load_reg( R_EAX, Rm );
nkeynes@361
   691
    load_reg( R_ECX, Rn );
nkeynes@361
   692
    MUL_r32( R_ECX );
nkeynes@361
   693
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   695
:}
nkeynes@374
   696
MULS.W Rm, Rn {:
nkeynes@374
   697
    load_reg16s( R_EAX, Rm );
nkeynes@374
   698
    load_reg16s( R_ECX, Rn );
nkeynes@374
   699
    MUL_r32( R_ECX );
nkeynes@374
   700
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   702
:}
nkeynes@374
   703
MULU.W Rm, Rn {:  
nkeynes@374
   704
    load_reg16u( R_EAX, Rm );
nkeynes@374
   705
    load_reg16u( R_ECX, Rn );
nkeynes@374
   706
    MUL_r32( R_ECX );
nkeynes@374
   707
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   708
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   709
:}
nkeynes@359
   710
NEG Rm, Rn {:
nkeynes@359
   711
    load_reg( R_EAX, Rm );
nkeynes@359
   712
    NEG_r32( R_EAX );
nkeynes@359
   713
    store_reg( R_EAX, Rn );
nkeynes@417
   714
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   715
:}
nkeynes@359
   716
NEGC Rm, Rn {:  
nkeynes@359
   717
    load_reg( R_EAX, Rm );
nkeynes@359
   718
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   719
    LDC_t();
nkeynes@359
   720
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   721
    store_reg( R_ECX, Rn );
nkeynes@359
   722
    SETC_t();
nkeynes@417
   723
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   724
:}
nkeynes@359
   725
NOT Rm, Rn {:  
nkeynes@359
   726
    load_reg( R_EAX, Rm );
nkeynes@359
   727
    NOT_r32( R_EAX );
nkeynes@359
   728
    store_reg( R_EAX, Rn );
nkeynes@417
   729
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   730
:}
nkeynes@359
   731
OR Rm, Rn {:  
nkeynes@359
   732
    load_reg( R_EAX, Rm );
nkeynes@359
   733
    load_reg( R_ECX, Rn );
nkeynes@359
   734
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   735
    store_reg( R_ECX, Rn );
nkeynes@417
   736
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   737
:}
nkeynes@359
   738
OR #imm, R0 {:
nkeynes@359
   739
    load_reg( R_EAX, 0 );
nkeynes@359
   740
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   741
    store_reg( R_EAX, 0 );
nkeynes@417
   742
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   743
:}
nkeynes@374
   744
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   745
    load_reg( R_EAX, 0 );
nkeynes@374
   746
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   747
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   748
    PUSH_r32(R_ECX);
nkeynes@527
   749
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
   750
    POP_r32(R_ECX);
nkeynes@386
   751
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   752
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   754
:}
nkeynes@359
   755
ROTCL Rn {:
nkeynes@359
   756
    load_reg( R_EAX, Rn );
nkeynes@417
   757
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   758
	LDC_t();
nkeynes@417
   759
    }
nkeynes@359
   760
    RCL1_r32( R_EAX );
nkeynes@359
   761
    store_reg( R_EAX, Rn );
nkeynes@359
   762
    SETC_t();
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   764
:}
nkeynes@359
   765
ROTCR Rn {:  
nkeynes@359
   766
    load_reg( R_EAX, Rn );
nkeynes@417
   767
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   768
	LDC_t();
nkeynes@417
   769
    }
nkeynes@359
   770
    RCR1_r32( R_EAX );
nkeynes@359
   771
    store_reg( R_EAX, Rn );
nkeynes@359
   772
    SETC_t();
nkeynes@417
   773
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   774
:}
nkeynes@359
   775
ROTL Rn {:  
nkeynes@359
   776
    load_reg( R_EAX, Rn );
nkeynes@359
   777
    ROL1_r32( R_EAX );
nkeynes@359
   778
    store_reg( R_EAX, Rn );
nkeynes@359
   779
    SETC_t();
nkeynes@417
   780
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   781
:}
nkeynes@359
   782
ROTR Rn {:  
nkeynes@359
   783
    load_reg( R_EAX, Rn );
nkeynes@359
   784
    ROR1_r32( R_EAX );
nkeynes@359
   785
    store_reg( R_EAX, Rn );
nkeynes@359
   786
    SETC_t();
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   788
:}
nkeynes@359
   789
SHAD Rm, Rn {:
nkeynes@359
   790
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   791
    load_reg( R_EAX, Rn );
nkeynes@361
   792
    load_reg( R_ECX, Rm );
nkeynes@361
   793
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   794
    JGE_rel8(16, doshl);
nkeynes@361
   795
                    
nkeynes@361
   796
    NEG_r32( R_ECX );      // 2
nkeynes@361
   797
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   798
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   799
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   800
    JMP_rel8(10, end);          // 2
nkeynes@386
   801
nkeynes@386
   802
    JMP_TARGET(emptysar);
nkeynes@386
   803
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   804
    JMP_rel8(5, end2);
nkeynes@382
   805
nkeynes@380
   806
    JMP_TARGET(doshl);
nkeynes@361
   807
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   808
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   809
    JMP_TARGET(end);
nkeynes@386
   810
    JMP_TARGET(end2);
nkeynes@361
   811
    store_reg( R_EAX, Rn );
nkeynes@417
   812
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   813
:}
nkeynes@359
   814
SHLD Rm, Rn {:  
nkeynes@368
   815
    load_reg( R_EAX, Rn );
nkeynes@368
   816
    load_reg( R_ECX, Rm );
nkeynes@382
   817
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   818
    JGE_rel8(15, doshl);
nkeynes@368
   819
nkeynes@382
   820
    NEG_r32( R_ECX );      // 2
nkeynes@382
   821
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   822
    JE_rel8( 4, emptyshr );
nkeynes@382
   823
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   824
    JMP_rel8(9, end);          // 2
nkeynes@386
   825
nkeynes@386
   826
    JMP_TARGET(emptyshr);
nkeynes@386
   827
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   828
    JMP_rel8(5, end2);
nkeynes@382
   829
nkeynes@382
   830
    JMP_TARGET(doshl);
nkeynes@382
   831
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   832
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   833
    JMP_TARGET(end);
nkeynes@386
   834
    JMP_TARGET(end2);
nkeynes@368
   835
    store_reg( R_EAX, Rn );
nkeynes@417
   836
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   837
:}
nkeynes@359
   838
SHAL Rn {: 
nkeynes@359
   839
    load_reg( R_EAX, Rn );
nkeynes@359
   840
    SHL1_r32( R_EAX );
nkeynes@397
   841
    SETC_t();
nkeynes@359
   842
    store_reg( R_EAX, Rn );
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   844
:}
nkeynes@359
   845
SHAR Rn {:  
nkeynes@359
   846
    load_reg( R_EAX, Rn );
nkeynes@359
   847
    SAR1_r32( R_EAX );
nkeynes@397
   848
    SETC_t();
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   851
:}
nkeynes@359
   852
SHLL Rn {:  
nkeynes@359
   853
    load_reg( R_EAX, Rn );
nkeynes@359
   854
    SHL1_r32( R_EAX );
nkeynes@397
   855
    SETC_t();
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   858
:}
nkeynes@359
   859
SHLL2 Rn {:
nkeynes@359
   860
    load_reg( R_EAX, Rn );
nkeynes@359
   861
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   862
    store_reg( R_EAX, Rn );
nkeynes@417
   863
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   864
:}
nkeynes@359
   865
SHLL8 Rn {:  
nkeynes@359
   866
    load_reg( R_EAX, Rn );
nkeynes@359
   867
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   868
    store_reg( R_EAX, Rn );
nkeynes@417
   869
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   870
:}
nkeynes@359
   871
SHLL16 Rn {:  
nkeynes@359
   872
    load_reg( R_EAX, Rn );
nkeynes@359
   873
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   874
    store_reg( R_EAX, Rn );
nkeynes@417
   875
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   876
:}
nkeynes@359
   877
SHLR Rn {:  
nkeynes@359
   878
    load_reg( R_EAX, Rn );
nkeynes@359
   879
    SHR1_r32( R_EAX );
nkeynes@397
   880
    SETC_t();
nkeynes@359
   881
    store_reg( R_EAX, Rn );
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   883
:}
nkeynes@359
   884
SHLR2 Rn {:  
nkeynes@359
   885
    load_reg( R_EAX, Rn );
nkeynes@359
   886
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   887
    store_reg( R_EAX, Rn );
nkeynes@417
   888
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   889
:}
nkeynes@359
   890
SHLR8 Rn {:  
nkeynes@359
   891
    load_reg( R_EAX, Rn );
nkeynes@359
   892
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   893
    store_reg( R_EAX, Rn );
nkeynes@417
   894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   895
:}
nkeynes@359
   896
SHLR16 Rn {:  
nkeynes@359
   897
    load_reg( R_EAX, Rn );
nkeynes@359
   898
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   899
    store_reg( R_EAX, Rn );
nkeynes@417
   900
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   901
:}
nkeynes@359
   902
SUB Rm, Rn {:  
nkeynes@359
   903
    load_reg( R_EAX, Rm );
nkeynes@359
   904
    load_reg( R_ECX, Rn );
nkeynes@359
   905
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   906
    store_reg( R_ECX, Rn );
nkeynes@417
   907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   908
:}
nkeynes@359
   909
SUBC Rm, Rn {:  
nkeynes@359
   910
    load_reg( R_EAX, Rm );
nkeynes@359
   911
    load_reg( R_ECX, Rn );
nkeynes@417
   912
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   913
	LDC_t();
nkeynes@417
   914
    }
nkeynes@359
   915
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   916
    store_reg( R_ECX, Rn );
nkeynes@394
   917
    SETC_t();
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   919
:}
nkeynes@359
   920
SUBV Rm, Rn {:  
nkeynes@359
   921
    load_reg( R_EAX, Rm );
nkeynes@359
   922
    load_reg( R_ECX, Rn );
nkeynes@359
   923
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   924
    store_reg( R_ECX, Rn );
nkeynes@359
   925
    SETO_t();
nkeynes@417
   926
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   927
:}
nkeynes@359
   928
SWAP.B Rm, Rn {:  
nkeynes@359
   929
    load_reg( R_EAX, Rm );
nkeynes@359
   930
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   931
    store_reg( R_EAX, Rn );
nkeynes@359
   932
:}
nkeynes@359
   933
SWAP.W Rm, Rn {:  
nkeynes@359
   934
    load_reg( R_EAX, Rm );
nkeynes@359
   935
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   936
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   937
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   938
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   939
    store_reg( R_ECX, Rn );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
:}
nkeynes@361
   942
TAS.B @Rn {:  
nkeynes@361
   943
    load_reg( R_ECX, Rn );
nkeynes@361
   944
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   945
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   946
    SETE_t();
nkeynes@361
   947
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   948
    load_reg( R_ECX, Rn );
nkeynes@361
   949
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   950
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   951
:}
nkeynes@361
   952
TST Rm, Rn {:  
nkeynes@361
   953
    load_reg( R_EAX, Rm );
nkeynes@361
   954
    load_reg( R_ECX, Rn );
nkeynes@361
   955
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   956
    SETE_t();
nkeynes@417
   957
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   958
:}
nkeynes@368
   959
TST #imm, R0 {:  
nkeynes@368
   960
    load_reg( R_EAX, 0 );
nkeynes@368
   961
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   962
    SETE_t();
nkeynes@417
   963
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   964
:}
nkeynes@368
   965
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   966
    load_reg( R_EAX, 0);
nkeynes@368
   967
    load_reg( R_ECX, R_GBR);
nkeynes@368
   968
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   969
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
   970
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   971
    SETE_t();
nkeynes@417
   972
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   973
:}
nkeynes@359
   974
XOR Rm, Rn {:  
nkeynes@359
   975
    load_reg( R_EAX, Rm );
nkeynes@359
   976
    load_reg( R_ECX, Rn );
nkeynes@359
   977
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   978
    store_reg( R_ECX, Rn );
nkeynes@417
   979
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   980
:}
nkeynes@359
   981
XOR #imm, R0 {:  
nkeynes@359
   982
    load_reg( R_EAX, 0 );
nkeynes@359
   983
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   984
    store_reg( R_EAX, 0 );
nkeynes@417
   985
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   986
:}
nkeynes@359
   987
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   988
    load_reg( R_EAX, 0 );
nkeynes@359
   989
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   990
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   991
    PUSH_r32(R_ECX);
nkeynes@527
   992
    MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@386
   993
    POP_r32(R_ECX);
nkeynes@359
   994
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   995
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   997
:}
nkeynes@361
   998
XTRCT Rm, Rn {:
nkeynes@361
   999
    load_reg( R_EAX, Rm );
nkeynes@394
  1000
    load_reg( R_ECX, Rn );
nkeynes@394
  1001
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1002
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1003
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1004
    store_reg( R_ECX, Rn );
nkeynes@417
  1005
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1006
:}
nkeynes@359
  1007
nkeynes@359
  1008
/* Data move instructions */
nkeynes@359
  1009
MOV Rm, Rn {:  
nkeynes@359
  1010
    load_reg( R_EAX, Rm );
nkeynes@359
  1011
    store_reg( R_EAX, Rn );
nkeynes@359
  1012
:}
nkeynes@359
  1013
MOV #imm, Rn {:  
nkeynes@359
  1014
    load_imm32( R_EAX, imm );
nkeynes@359
  1015
    store_reg( R_EAX, Rn );
nkeynes@359
  1016
:}
nkeynes@359
  1017
MOV.B Rm, @Rn {:  
nkeynes@359
  1018
    load_reg( R_EAX, Rm );
nkeynes@359
  1019
    load_reg( R_ECX, Rn );
nkeynes@359
  1020
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1021
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1022
:}
nkeynes@359
  1023
MOV.B Rm, @-Rn {:  
nkeynes@359
  1024
    load_reg( R_EAX, Rm );
nkeynes@359
  1025
    load_reg( R_ECX, Rn );
nkeynes@382
  1026
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1027
    store_reg( R_ECX, Rn );
nkeynes@359
  1028
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1029
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1030
:}
nkeynes@359
  1031
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1032
    load_reg( R_EAX, 0 );
nkeynes@359
  1033
    load_reg( R_ECX, Rn );
nkeynes@359
  1034
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1035
    load_reg( R_EAX, Rm );
nkeynes@359
  1036
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1037
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1038
:}
nkeynes@359
  1039
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1040
    load_reg( R_EAX, 0 );
nkeynes@359
  1041
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1042
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1043
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1044
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1045
:}
nkeynes@359
  1046
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1047
    load_reg( R_EAX, 0 );
nkeynes@359
  1048
    load_reg( R_ECX, Rn );
nkeynes@359
  1049
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1050
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1052
:}
nkeynes@359
  1053
MOV.B @Rm, Rn {:  
nkeynes@359
  1054
    load_reg( R_ECX, Rm );
nkeynes@359
  1055
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1056
    store_reg( R_EAX, Rn );
nkeynes@417
  1057
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1058
:}
nkeynes@359
  1059
MOV.B @Rm+, Rn {:  
nkeynes@359
  1060
    load_reg( R_ECX, Rm );
nkeynes@359
  1061
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1062
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1063
    store_reg( R_EAX, Rm );
nkeynes@359
  1064
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1065
    store_reg( R_EAX, Rn );
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1067
:}
nkeynes@359
  1068
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1069
    load_reg( R_EAX, 0 );
nkeynes@359
  1070
    load_reg( R_ECX, Rm );
nkeynes@359
  1071
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1072
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1073
    store_reg( R_EAX, Rn );
nkeynes@417
  1074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1075
:}
nkeynes@359
  1076
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1077
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1078
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1079
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1080
    store_reg( R_EAX, 0 );
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1082
:}
nkeynes@359
  1083
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1084
    load_reg( R_ECX, Rm );
nkeynes@359
  1085
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1086
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1087
    store_reg( R_EAX, 0 );
nkeynes@417
  1088
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1089
:}
nkeynes@374
  1090
MOV.L Rm, @Rn {:
nkeynes@361
  1091
    load_reg( R_EAX, Rm );
nkeynes@361
  1092
    load_reg( R_ECX, Rn );
nkeynes@416
  1093
    precheck();
nkeynes@374
  1094
    check_walign32(R_ECX);
nkeynes@361
  1095
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1097
:}
nkeynes@361
  1098
MOV.L Rm, @-Rn {:  
nkeynes@361
  1099
    load_reg( R_EAX, Rm );
nkeynes@361
  1100
    load_reg( R_ECX, Rn );
nkeynes@416
  1101
    precheck();
nkeynes@374
  1102
    check_walign32( R_ECX );
nkeynes@361
  1103
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1104
    store_reg( R_ECX, Rn );
nkeynes@361
  1105
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1107
:}
nkeynes@361
  1108
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1109
    load_reg( R_EAX, 0 );
nkeynes@361
  1110
    load_reg( R_ECX, Rn );
nkeynes@361
  1111
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1112
    precheck();
nkeynes@374
  1113
    check_walign32( R_ECX );
nkeynes@361
  1114
    load_reg( R_EAX, Rm );
nkeynes@361
  1115
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1116
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1117
:}
nkeynes@361
  1118
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1119
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1120
    load_reg( R_EAX, 0 );
nkeynes@361
  1121
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1122
    precheck();
nkeynes@374
  1123
    check_walign32( R_ECX );
nkeynes@361
  1124
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1125
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1126
:}
nkeynes@361
  1127
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1128
    load_reg( R_ECX, Rn );
nkeynes@361
  1129
    load_reg( R_EAX, Rm );
nkeynes@361
  1130
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1131
    precheck();
nkeynes@374
  1132
    check_walign32( R_ECX );
nkeynes@361
  1133
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1134
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1135
:}
nkeynes@361
  1136
MOV.L @Rm, Rn {:  
nkeynes@361
  1137
    load_reg( R_ECX, Rm );
nkeynes@416
  1138
    precheck();
nkeynes@374
  1139
    check_ralign32( R_ECX );
nkeynes@361
  1140
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1141
    store_reg( R_EAX, Rn );
nkeynes@417
  1142
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1143
:}
nkeynes@361
  1144
MOV.L @Rm+, Rn {:  
nkeynes@361
  1145
    load_reg( R_EAX, Rm );
nkeynes@416
  1146
    precheck();
nkeynes@382
  1147
    check_ralign32( R_EAX );
nkeynes@361
  1148
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1149
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1150
    store_reg( R_EAX, Rm );
nkeynes@361
  1151
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1152
    store_reg( R_EAX, Rn );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1154
:}
nkeynes@361
  1155
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1156
    load_reg( R_EAX, 0 );
nkeynes@361
  1157
    load_reg( R_ECX, Rm );
nkeynes@361
  1158
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1159
    precheck();
nkeynes@374
  1160
    check_ralign32( R_ECX );
nkeynes@361
  1161
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1162
    store_reg( R_EAX, Rn );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1164
:}
nkeynes@361
  1165
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1166
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1167
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1168
    precheck();
nkeynes@374
  1169
    check_ralign32( R_ECX );
nkeynes@361
  1170
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1171
    store_reg( R_EAX, 0 );
nkeynes@417
  1172
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1173
:}
nkeynes@361
  1174
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1175
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1176
	SLOTILLEGAL();
nkeynes@374
  1177
    } else {
nkeynes@388
  1178
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@502
  1179
	sh4ptr_t ptr = mem_get_region(target);
nkeynes@388
  1180
	if( ptr != NULL ) {
nkeynes@527
  1181
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1182
	} else {
nkeynes@388
  1183
	    load_imm32( R_ECX, target );
nkeynes@388
  1184
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1185
	}
nkeynes@382
  1186
	store_reg( R_EAX, Rn );
nkeynes@417
  1187
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1188
    }
nkeynes@361
  1189
:}
nkeynes@361
  1190
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1191
    load_reg( R_ECX, Rm );
nkeynes@361
  1192
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  1193
    precheck();
nkeynes@374
  1194
    check_ralign32( R_ECX );
nkeynes@361
  1195
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1196
    store_reg( R_EAX, Rn );
nkeynes@417
  1197
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1198
:}
nkeynes@361
  1199
MOV.W Rm, @Rn {:  
nkeynes@361
  1200
    load_reg( R_ECX, Rn );
nkeynes@416
  1201
    precheck();
nkeynes@374
  1202
    check_walign16( R_ECX );
nkeynes@382
  1203
    load_reg( R_EAX, Rm );
nkeynes@382
  1204
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1205
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1206
:}
nkeynes@361
  1207
MOV.W Rm, @-Rn {:  
nkeynes@361
  1208
    load_reg( R_ECX, Rn );
nkeynes@416
  1209
    precheck();
nkeynes@374
  1210
    check_walign16( R_ECX );
nkeynes@361
  1211
    load_reg( R_EAX, Rm );
nkeynes@361
  1212
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1213
    store_reg( R_ECX, Rn );
nkeynes@361
  1214
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1216
:}
nkeynes@361
  1217
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1218
    load_reg( R_EAX, 0 );
nkeynes@361
  1219
    load_reg( R_ECX, Rn );
nkeynes@361
  1220
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1221
    precheck();
nkeynes@374
  1222
    check_walign16( R_ECX );
nkeynes@361
  1223
    load_reg( R_EAX, Rm );
nkeynes@361
  1224
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1226
:}
nkeynes@361
  1227
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1228
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1229
    load_reg( R_EAX, 0 );
nkeynes@361
  1230
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1231
    precheck();
nkeynes@374
  1232
    check_walign16( R_ECX );
nkeynes@361
  1233
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1235
:}
nkeynes@361
  1236
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1237
    load_reg( R_ECX, Rn );
nkeynes@361
  1238
    load_reg( R_EAX, 0 );
nkeynes@361
  1239
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1240
    precheck();
nkeynes@374
  1241
    check_walign16( R_ECX );
nkeynes@361
  1242
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.W @Rm, Rn {:  
nkeynes@361
  1246
    load_reg( R_ECX, Rm );
nkeynes@416
  1247
    precheck();
nkeynes@374
  1248
    check_ralign16( R_ECX );
nkeynes@361
  1249
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1250
    store_reg( R_EAX, Rn );
nkeynes@417
  1251
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1252
:}
nkeynes@361
  1253
MOV.W @Rm+, Rn {:  
nkeynes@361
  1254
    load_reg( R_EAX, Rm );
nkeynes@416
  1255
    precheck();
nkeynes@374
  1256
    check_ralign16( R_EAX );
nkeynes@361
  1257
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1258
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1259
    store_reg( R_EAX, Rm );
nkeynes@361
  1260
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1261
    store_reg( R_EAX, Rn );
nkeynes@417
  1262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1263
:}
nkeynes@361
  1264
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1265
    load_reg( R_EAX, 0 );
nkeynes@361
  1266
    load_reg( R_ECX, Rm );
nkeynes@361
  1267
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1268
    precheck();
nkeynes@374
  1269
    check_ralign16( R_ECX );
nkeynes@361
  1270
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1271
    store_reg( R_EAX, Rn );
nkeynes@417
  1272
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1273
:}
nkeynes@361
  1274
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1275
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1276
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1277
    precheck();
nkeynes@374
  1278
    check_ralign16( R_ECX );
nkeynes@361
  1279
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1280
    store_reg( R_EAX, 0 );
nkeynes@417
  1281
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1282
:}
nkeynes@361
  1283
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1284
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1285
	SLOTILLEGAL();
nkeynes@374
  1286
    } else {
nkeynes@374
  1287
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1288
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1289
	store_reg( R_EAX, Rn );
nkeynes@417
  1290
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1291
    }
nkeynes@361
  1292
:}
nkeynes@361
  1293
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1294
    load_reg( R_ECX, Rm );
nkeynes@361
  1295
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1296
    precheck();
nkeynes@374
  1297
    check_ralign16( R_ECX );
nkeynes@361
  1298
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1299
    store_reg( R_EAX, 0 );
nkeynes@417
  1300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1301
:}
nkeynes@361
  1302
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1303
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1304
	SLOTILLEGAL();
nkeynes@374
  1305
    } else {
nkeynes@374
  1306
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1307
	store_reg( R_ECX, 0 );
nkeynes@374
  1308
    }
nkeynes@361
  1309
:}
nkeynes@361
  1310
MOVCA.L R0, @Rn {:  
nkeynes@361
  1311
    load_reg( R_EAX, 0 );
nkeynes@361
  1312
    load_reg( R_ECX, Rn );
nkeynes@416
  1313
    precheck();
nkeynes@374
  1314
    check_walign32( R_ECX );
nkeynes@361
  1315
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1316
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1317
:}
nkeynes@359
  1318
nkeynes@359
  1319
/* Control transfer instructions */
nkeynes@374
  1320
BF disp {:
nkeynes@374
  1321
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1322
	SLOTILLEGAL();
nkeynes@374
  1323
    } else {
nkeynes@527
  1324
	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1325
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1326
	JMP_TARGET(nottaken);
nkeynes@408
  1327
	return 2;
nkeynes@374
  1328
    }
nkeynes@374
  1329
:}
nkeynes@374
  1330
BF/S disp {:
nkeynes@374
  1331
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1332
	SLOTILLEGAL();
nkeynes@374
  1333
    } else {
nkeynes@408
  1334
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1335
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1336
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1337
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1338
	}
nkeynes@417
  1339
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1340
	sh4_translate_instruction(pc+2);
nkeynes@408
  1341
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1342
	// not taken
nkeynes@408
  1343
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1344
	sh4_translate_instruction(pc+2);
nkeynes@408
  1345
	return 4;
nkeynes@374
  1346
    }
nkeynes@374
  1347
:}
nkeynes@374
  1348
BRA disp {:  
nkeynes@374
  1349
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1350
	SLOTILLEGAL();
nkeynes@374
  1351
    } else {
nkeynes@374
  1352
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1353
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1354
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1355
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1356
	return 4;
nkeynes@374
  1357
    }
nkeynes@374
  1358
:}
nkeynes@374
  1359
BRAF Rn {:  
nkeynes@374
  1360
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1361
	SLOTILLEGAL();
nkeynes@374
  1362
    } else {
nkeynes@408
  1363
	load_reg( R_EAX, Rn );
nkeynes@408
  1364
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1365
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1366
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1367
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1368
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1369
	exit_block_pcset(pc+2);
nkeynes@409
  1370
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1371
	return 4;
nkeynes@374
  1372
    }
nkeynes@374
  1373
:}
nkeynes@374
  1374
BSR disp {:  
nkeynes@374
  1375
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1376
	SLOTILLEGAL();
nkeynes@374
  1377
    } else {
nkeynes@374
  1378
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1379
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1380
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1381
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1382
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1383
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1384
	return 4;
nkeynes@374
  1385
    }
nkeynes@374
  1386
:}
nkeynes@374
  1387
BSRF Rn {:  
nkeynes@374
  1388
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1389
	SLOTILLEGAL();
nkeynes@374
  1390
    } else {
nkeynes@408
  1391
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1392
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1393
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1394
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1395
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1396
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1397
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1398
	exit_block_pcset(pc+2);
nkeynes@409
  1399
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1400
	return 4;
nkeynes@374
  1401
    }
nkeynes@374
  1402
:}
nkeynes@374
  1403
BT disp {:
nkeynes@374
  1404
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1405
	SLOTILLEGAL();
nkeynes@374
  1406
    } else {
nkeynes@527
  1407
	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1408
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1409
	JMP_TARGET(nottaken);
nkeynes@408
  1410
	return 2;
nkeynes@374
  1411
    }
nkeynes@374
  1412
:}
nkeynes@374
  1413
BT/S disp {:
nkeynes@374
  1414
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1415
	SLOTILLEGAL();
nkeynes@374
  1416
    } else {
nkeynes@408
  1417
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1418
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1419
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1420
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1421
	}
nkeynes@417
  1422
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1423
	sh4_translate_instruction(pc+2);
nkeynes@408
  1424
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1425
	// not taken
nkeynes@408
  1426
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1427
	sh4_translate_instruction(pc+2);
nkeynes@408
  1428
	return 4;
nkeynes@374
  1429
    }
nkeynes@374
  1430
:}
nkeynes@374
  1431
JMP @Rn {:  
nkeynes@374
  1432
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1433
	SLOTILLEGAL();
nkeynes@374
  1434
    } else {
nkeynes@408
  1435
	load_reg( R_ECX, Rn );
nkeynes@408
  1436
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1437
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1438
	sh4_translate_instruction(pc+2);
nkeynes@408
  1439
	exit_block_pcset(pc+2);
nkeynes@409
  1440
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1441
	return 4;
nkeynes@374
  1442
    }
nkeynes@374
  1443
:}
nkeynes@374
  1444
JSR @Rn {:  
nkeynes@374
  1445
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1446
	SLOTILLEGAL();
nkeynes@374
  1447
    } else {
nkeynes@374
  1448
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1449
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1450
	load_reg( R_ECX, Rn );
nkeynes@408
  1451
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1452
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1453
	sh4_translate_instruction(pc+2);
nkeynes@408
  1454
	exit_block_pcset(pc+2);
nkeynes@409
  1455
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1456
	return 4;
nkeynes@374
  1457
    }
nkeynes@374
  1458
:}
nkeynes@374
  1459
RTE {:  
nkeynes@374
  1460
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1461
	SLOTILLEGAL();
nkeynes@374
  1462
    } else {
nkeynes@408
  1463
	check_priv();
nkeynes@408
  1464
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1465
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1466
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1467
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1468
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1469
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1470
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1471
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1472
	sh4_translate_instruction(pc+2);
nkeynes@408
  1473
	exit_block_pcset(pc+2);
nkeynes@409
  1474
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1475
	return 4;
nkeynes@374
  1476
    }
nkeynes@374
  1477
:}
nkeynes@374
  1478
RTS {:  
nkeynes@374
  1479
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1480
	SLOTILLEGAL();
nkeynes@374
  1481
    } else {
nkeynes@408
  1482
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1483
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1484
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1485
	sh4_translate_instruction(pc+2);
nkeynes@408
  1486
	exit_block_pcset(pc+2);
nkeynes@409
  1487
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1488
	return 4;
nkeynes@374
  1489
    }
nkeynes@374
  1490
:}
nkeynes@374
  1491
TRAPA #imm {:  
nkeynes@374
  1492
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1493
	SLOTILLEGAL();
nkeynes@374
  1494
    } else {
nkeynes@533
  1495
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1496
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1497
	load_imm32( R_EAX, imm );
nkeynes@527
  1498
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1499
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1500
	exit_block_pcset(pc);
nkeynes@409
  1501
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1502
	return 2;
nkeynes@374
  1503
    }
nkeynes@374
  1504
:}
nkeynes@374
  1505
UNDEF {:  
nkeynes@374
  1506
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1507
	SLOTILLEGAL();
nkeynes@374
  1508
    } else {
nkeynes@416
  1509
	precheck();
nkeynes@386
  1510
	JMP_exit(EXIT_ILLEGAL);
nkeynes@408
  1511
	return 2;
nkeynes@374
  1512
    }
nkeynes@368
  1513
:}
nkeynes@374
  1514
nkeynes@374
  1515
CLRMAC {:  
nkeynes@374
  1516
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1517
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1518
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1519
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1520
:}
nkeynes@374
  1521
CLRS {:
nkeynes@374
  1522
    CLC();
nkeynes@374
  1523
    SETC_sh4r(R_S);
nkeynes@417
  1524
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1525
:}
nkeynes@374
  1526
CLRT {:  
nkeynes@374
  1527
    CLC();
nkeynes@374
  1528
    SETC_t();
nkeynes@417
  1529
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1530
:}
nkeynes@374
  1531
SETS {:  
nkeynes@374
  1532
    STC();
nkeynes@374
  1533
    SETC_sh4r(R_S);
nkeynes@417
  1534
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1535
:}
nkeynes@374
  1536
SETT {:  
nkeynes@374
  1537
    STC();
nkeynes@374
  1538
    SETC_t();
nkeynes@417
  1539
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1540
:}
nkeynes@359
  1541
nkeynes@375
  1542
/* Floating point moves */
nkeynes@375
  1543
FMOV FRm, FRn {:  
nkeynes@375
  1544
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1545
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1546
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1547
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1548
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1549
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1550
     */
nkeynes@377
  1551
    check_fpuen();
nkeynes@375
  1552
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1553
    load_fr_bank( R_EDX );
nkeynes@375
  1554
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1555
    JNE_rel8(8, doublesize);
nkeynes@375
  1556
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1557
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1558
    if( FRm&1 ) {
nkeynes@386
  1559
	JMP_rel8(24, end);
nkeynes@380
  1560
	JMP_TARGET(doublesize);
nkeynes@375
  1561
	load_xf_bank( R_ECX ); 
nkeynes@375
  1562
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1563
	if( FRn&1 ) {
nkeynes@375
  1564
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1565
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1566
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1567
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1568
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1569
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1570
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1571
	}
nkeynes@380
  1572
	JMP_TARGET(end);
nkeynes@375
  1573
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1574
	if( FRn&1 ) {
nkeynes@386
  1575
	    JMP_rel8(24, end);
nkeynes@375
  1576
	    load_xf_bank( R_ECX );
nkeynes@375
  1577
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1578
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1579
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1580
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1581
	    JMP_TARGET(end);
nkeynes@375
  1582
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1583
	    JMP_rel8(12, end);
nkeynes@375
  1584
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1585
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1586
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1587
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1588
	    JMP_TARGET(end);
nkeynes@375
  1589
	}
nkeynes@375
  1590
    }
nkeynes@417
  1591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1592
:}
nkeynes@416
  1593
FMOV FRm, @Rn {: 
nkeynes@416
  1594
    precheck();
nkeynes@416
  1595
    check_fpuen_no_precheck();
nkeynes@416
  1596
    load_reg( R_ECX, Rn );
nkeynes@416
  1597
    check_walign32( R_ECX );
nkeynes@416
  1598
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1599
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1600
    JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  1601
    load_fr_bank( R_EDX );
nkeynes@416
  1602
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1603
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1604
    if( FRm&1 ) {
nkeynes@527
  1605
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1606
	JMP_TARGET(doublesize);
nkeynes@416
  1607
	load_xf_bank( R_EDX );
nkeynes@416
  1608
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1609
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1610
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1611
	JMP_TARGET(end);
nkeynes@375
  1612
    } else {
nkeynes@527
  1613
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1614
	JMP_TARGET(doublesize);
nkeynes@416
  1615
	load_fr_bank( R_EDX );
nkeynes@416
  1616
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1617
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1618
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1619
	JMP_TARGET(end);
nkeynes@375
  1620
    }
nkeynes@417
  1621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1622
:}
nkeynes@375
  1623
FMOV @Rm, FRn {:  
nkeynes@416
  1624
    precheck();
nkeynes@416
  1625
    check_fpuen_no_precheck();
nkeynes@416
  1626
    load_reg( R_ECX, Rm );
nkeynes@416
  1627
    check_ralign32( R_ECX );
nkeynes@416
  1628
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1629
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1630
    JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
nkeynes@416
  1631
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1632
    load_fr_bank( R_EDX );
nkeynes@416
  1633
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1634
    if( FRn&1 ) {
nkeynes@527
  1635
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1636
	JMP_TARGET(doublesize);
nkeynes@416
  1637
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1638
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1639
	load_xf_bank( R_EDX );
nkeynes@416
  1640
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1641
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1642
	JMP_TARGET(end);
nkeynes@375
  1643
    } else {
nkeynes@527
  1644
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1645
	JMP_TARGET(doublesize);
nkeynes@416
  1646
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1647
	load_fr_bank( R_EDX );
nkeynes@416
  1648
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1649
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1650
	JMP_TARGET(end);
nkeynes@375
  1651
    }
nkeynes@417
  1652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1653
:}
nkeynes@377
  1654
FMOV FRm, @-Rn {:  
nkeynes@416
  1655
    precheck();
nkeynes@416
  1656
    check_fpuen_no_precheck();
nkeynes@416
  1657
    load_reg( R_ECX, Rn );
nkeynes@416
  1658
    check_walign32( R_ECX );
nkeynes@416
  1659
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1660
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1661
    JNE_rel8(14 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  1662
    load_fr_bank( R_EDX );
nkeynes@416
  1663
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1664
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1665
    store_reg( R_ECX, Rn );
nkeynes@416
  1666
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1667
    if( FRm&1 ) {
nkeynes@527
  1668
	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1669
	JMP_TARGET(doublesize);
nkeynes@416
  1670
	load_xf_bank( R_EDX );
nkeynes@416
  1671
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1672
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1673
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1674
	store_reg( R_ECX, Rn );
nkeynes@416
  1675
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1676
	JMP_TARGET(end);
nkeynes@377
  1677
    } else {
nkeynes@527
  1678
	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1679
	JMP_TARGET(doublesize);
nkeynes@416
  1680
	load_fr_bank( R_EDX );
nkeynes@416
  1681
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1682
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1683
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1684
	store_reg( R_ECX, Rn );
nkeynes@416
  1685
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1686
	JMP_TARGET(end);
nkeynes@377
  1687
    }
nkeynes@417
  1688
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1689
:}
nkeynes@416
  1690
FMOV @Rm+, FRn {:
nkeynes@416
  1691
    precheck();
nkeynes@416
  1692
    check_fpuen_no_precheck();
nkeynes@416
  1693
    load_reg( R_ECX, Rm );
nkeynes@416
  1694
    check_ralign32( R_ECX );
nkeynes@416
  1695
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1696
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1697
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1698
    JNE_rel8(14 + CALL_FUNC1_SIZE, doublesize);
nkeynes@377
  1699
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1700
    store_reg( R_EAX, Rm );
nkeynes@416
  1701
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1702
    load_fr_bank( R_EDX );
nkeynes@416
  1703
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1704
    if( FRn&1 ) {
nkeynes@527
  1705
	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1706
	JMP_TARGET(doublesize);
nkeynes@377
  1707
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1708
	store_reg(R_EAX, Rm);
nkeynes@416
  1709
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1710
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1711
	load_xf_bank( R_EDX );
nkeynes@416
  1712
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1713
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1714
	JMP_TARGET(end);
nkeynes@377
  1715
    } else {
nkeynes@527
  1716
	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@377
  1717
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1718
	store_reg(R_EAX, Rm);
nkeynes@416
  1719
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1720
	load_fr_bank( R_EDX );
nkeynes@416
  1721
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1722
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1723
	JMP_TARGET(end);
nkeynes@377
  1724
    }
nkeynes@417
  1725
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1726
:}
nkeynes@377
  1727
FMOV FRm, @(R0, Rn) {:  
nkeynes@416
  1728
    precheck();
nkeynes@416
  1729
    check_fpuen_no_precheck();
nkeynes@416
  1730
    load_reg( R_ECX, Rn );
nkeynes@416
  1731
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1732
    check_walign32( R_ECX );
nkeynes@416
  1733
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1734
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1735
    JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  1736
    load_fr_bank( R_EDX );
nkeynes@416
  1737
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1738
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1739
    if( FRm&1 ) {
nkeynes@527
  1740
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1741
	JMP_TARGET(doublesize);
nkeynes@416
  1742
	load_xf_bank( R_EDX );
nkeynes@416
  1743
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1744
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1745
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1746
	JMP_TARGET(end);
nkeynes@377
  1747
    } else {
nkeynes@527
  1748
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1749
	JMP_TARGET(doublesize);
nkeynes@416
  1750
	load_fr_bank( R_EDX );
nkeynes@416
  1751
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1752
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1753
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1754
	JMP_TARGET(end);
nkeynes@377
  1755
    }
nkeynes@417
  1756
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1757
:}
nkeynes@377
  1758
FMOV @(R0, Rm), FRn {:  
nkeynes@416
  1759
    precheck();
nkeynes@416
  1760
    check_fpuen_no_precheck();
nkeynes@416
  1761
    load_reg( R_ECX, Rm );
nkeynes@416
  1762
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1763
    check_ralign32( R_ECX );
nkeynes@416
  1764
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1765
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1766
    JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
nkeynes@416
  1767
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1768
    load_fr_bank( R_EDX );
nkeynes@416
  1769
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1770
    if( FRn&1 ) {
nkeynes@527
  1771
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1772
	JMP_TARGET(doublesize);
nkeynes@416
  1773
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1774
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1775
	load_xf_bank( R_EDX );
nkeynes@416
  1776
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1777
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1778
	JMP_TARGET(end);
nkeynes@377
  1779
    } else {
nkeynes@527
  1780
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1781
	JMP_TARGET(doublesize);
nkeynes@416
  1782
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1783
	load_fr_bank( R_EDX );
nkeynes@416
  1784
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1785
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1786
	JMP_TARGET(end);
nkeynes@377
  1787
    }
nkeynes@417
  1788
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1789
:}
nkeynes@377
  1790
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1791
    check_fpuen();
nkeynes@377
  1792
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1793
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1794
    JNE_rel8(8, end);
nkeynes@377
  1795
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1796
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1797
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1798
    JMP_TARGET(end);
nkeynes@417
  1799
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1800
:}
nkeynes@377
  1801
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1802
    check_fpuen();
nkeynes@377
  1803
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1804
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1805
    JNE_rel8(11, end);
nkeynes@377
  1806
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1807
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1808
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1809
    JMP_TARGET(end);
nkeynes@417
  1810
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1811
:}
nkeynes@377
  1812
nkeynes@377
  1813
FLOAT FPUL, FRn {:  
nkeynes@377
  1814
    check_fpuen();
nkeynes@377
  1815
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1816
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1817
    FILD_sh4r(R_FPUL);
nkeynes@377
  1818
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1819
    JNE_rel8(5, doubleprec);
nkeynes@377
  1820
    pop_fr( R_EDX, FRn );
nkeynes@380
  1821
    JMP_rel8(3, end);
nkeynes@380
  1822
    JMP_TARGET(doubleprec);
nkeynes@377
  1823
    pop_dr( R_EDX, FRn );
nkeynes@380
  1824
    JMP_TARGET(end);
nkeynes@417
  1825
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1826
:}
nkeynes@377
  1827
FTRC FRm, FPUL {:  
nkeynes@377
  1828
    check_fpuen();
nkeynes@388
  1829
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1830
    load_fr_bank( R_EDX );
nkeynes@388
  1831
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1832
    JNE_rel8(5, doubleprec);
nkeynes@388
  1833
    push_fr( R_EDX, FRm );
nkeynes@388
  1834
    JMP_rel8(3, doop);
nkeynes@388
  1835
    JMP_TARGET(doubleprec);
nkeynes@388
  1836
    push_dr( R_EDX, FRm );
nkeynes@388
  1837
    JMP_TARGET( doop );
nkeynes@388
  1838
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1839
    FILD_r32ind( R_ECX );
nkeynes@388
  1840
    FCOMIP_st(1);
nkeynes@394
  1841
    JNA_rel8( 32, sat );
nkeynes@388
  1842
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1843
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1844
    FCOMIP_st(1);                   // 2
nkeynes@394
  1845
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1846
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1847
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1848
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1849
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1850
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1851
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1852
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1853
nkeynes@388
  1854
    JMP_TARGET(sat);
nkeynes@388
  1855
    JMP_TARGET(sat2);
nkeynes@388
  1856
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1857
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1858
    FPOP_st();
nkeynes@388
  1859
    JMP_TARGET(end);
nkeynes@417
  1860
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1861
:}
nkeynes@377
  1862
FLDS FRm, FPUL {:  
nkeynes@377
  1863
    check_fpuen();
nkeynes@377
  1864
    load_fr_bank( R_ECX );
nkeynes@377
  1865
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1866
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1867
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1868
:}
nkeynes@377
  1869
FSTS FPUL, FRn {:  
nkeynes@377
  1870
    check_fpuen();
nkeynes@377
  1871
    load_fr_bank( R_ECX );
nkeynes@377
  1872
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1873
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1874
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1875
:}
nkeynes@377
  1876
FCNVDS FRm, FPUL {:  
nkeynes@377
  1877
    check_fpuen();
nkeynes@377
  1878
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1879
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1880
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1881
    load_fr_bank( R_ECX );
nkeynes@377
  1882
    push_dr( R_ECX, FRm );
nkeynes@377
  1883
    pop_fpul();
nkeynes@380
  1884
    JMP_TARGET(end);
nkeynes@417
  1885
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1886
:}
nkeynes@377
  1887
FCNVSD FPUL, FRn {:  
nkeynes@377
  1888
    check_fpuen();
nkeynes@377
  1889
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1890
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1891
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1892
    load_fr_bank( R_ECX );
nkeynes@377
  1893
    push_fpul();
nkeynes@377
  1894
    pop_dr( R_ECX, FRn );
nkeynes@380
  1895
    JMP_TARGET(end);
nkeynes@417
  1896
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1897
:}
nkeynes@375
  1898
nkeynes@359
  1899
/* Floating point instructions */
nkeynes@374
  1900
FABS FRn {:  
nkeynes@377
  1901
    check_fpuen();
nkeynes@374
  1902
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1903
    load_fr_bank( R_EDX );
nkeynes@374
  1904
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1905
    JNE_rel8(10, doubleprec);
nkeynes@374
  1906
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1907
    FABS_st0(); // 2
nkeynes@374
  1908
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1909
    JMP_rel8(8,end); // 2
nkeynes@380
  1910
    JMP_TARGET(doubleprec);
nkeynes@374
  1911
    push_dr(R_EDX, FRn);
nkeynes@374
  1912
    FABS_st0();
nkeynes@374
  1913
    pop_dr(R_EDX, FRn);
nkeynes@380
  1914
    JMP_TARGET(end);
nkeynes@417
  1915
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1916
:}
nkeynes@377
  1917
FADD FRm, FRn {:  
nkeynes@377
  1918
    check_fpuen();
nkeynes@375
  1919
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1920
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1921
    load_fr_bank( R_EDX );
nkeynes@380
  1922
    JNE_rel8(13,doubleprec);
nkeynes@377
  1923
    push_fr(R_EDX, FRm);
nkeynes@377
  1924
    push_fr(R_EDX, FRn);
nkeynes@377
  1925
    FADDP_st(1);
nkeynes@377
  1926
    pop_fr(R_EDX, FRn);
nkeynes@380
  1927
    JMP_rel8(11,end);
nkeynes@380
  1928
    JMP_TARGET(doubleprec);
nkeynes@377
  1929
    push_dr(R_EDX, FRm);
nkeynes@377
  1930
    push_dr(R_EDX, FRn);
nkeynes@377
  1931
    FADDP_st(1);
nkeynes@377
  1932
    pop_dr(R_EDX, FRn);
nkeynes@380
  1933
    JMP_TARGET(end);
nkeynes@417
  1934
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1935
:}
nkeynes@377
  1936
FDIV FRm, FRn {:  
nkeynes@377
  1937
    check_fpuen();
nkeynes@375
  1938
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1939
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1940
    load_fr_bank( R_EDX );
nkeynes@380
  1941
    JNE_rel8(13, doubleprec);
nkeynes@377
  1942
    push_fr(R_EDX, FRn);
nkeynes@377
  1943
    push_fr(R_EDX, FRm);
nkeynes@377
  1944
    FDIVP_st(1);
nkeynes@377
  1945
    pop_fr(R_EDX, FRn);
nkeynes@380
  1946
    JMP_rel8(11, end);
nkeynes@380
  1947
    JMP_TARGET(doubleprec);
nkeynes@377
  1948
    push_dr(R_EDX, FRn);
nkeynes@377
  1949
    push_dr(R_EDX, FRm);
nkeynes@377
  1950
    FDIVP_st(1);
nkeynes@377
  1951
    pop_dr(R_EDX, FRn);
nkeynes@380
  1952
    JMP_TARGET(end);
nkeynes@417
  1953
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1954
:}
nkeynes@375
  1955
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1956
    check_fpuen();
nkeynes@375
  1957
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1958
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1959
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1960
    JNE_rel8(18, doubleprec);
nkeynes@375
  1961
    push_fr( R_EDX, 0 );
nkeynes@375
  1962
    push_fr( R_EDX, FRm );
nkeynes@375
  1963
    FMULP_st(1);
nkeynes@375
  1964
    push_fr( R_EDX, FRn );
nkeynes@375
  1965
    FADDP_st(1);
nkeynes@375
  1966
    pop_fr( R_EDX, FRn );
nkeynes@380
  1967
    JMP_rel8(16, end);
nkeynes@380
  1968
    JMP_TARGET(doubleprec);
nkeynes@375
  1969
    push_dr( R_EDX, 0 );
nkeynes@375
  1970
    push_dr( R_EDX, FRm );
nkeynes@375
  1971
    FMULP_st(1);
nkeynes@375
  1972
    push_dr( R_EDX, FRn );
nkeynes@375
  1973
    FADDP_st(1);
nkeynes@375
  1974
    pop_dr( R_EDX, FRn );
nkeynes@380
  1975
    JMP_TARGET(end);
nkeynes@417
  1976
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1977
:}
nkeynes@375
  1978
nkeynes@377
  1979
FMUL FRm, FRn {:  
nkeynes@377
  1980
    check_fpuen();
nkeynes@377
  1981
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1982
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1983
    load_fr_bank( R_EDX );
nkeynes@380
  1984
    JNE_rel8(13, doubleprec);
nkeynes@377
  1985
    push_fr(R_EDX, FRm);
nkeynes@377
  1986
    push_fr(R_EDX, FRn);
nkeynes@377
  1987
    FMULP_st(1);
nkeynes@377
  1988
    pop_fr(R_EDX, FRn);
nkeynes@380
  1989
    JMP_rel8(11, end);
nkeynes@380
  1990
    JMP_TARGET(doubleprec);
nkeynes@377
  1991
    push_dr(R_EDX, FRm);
nkeynes@377
  1992
    push_dr(R_EDX, FRn);
nkeynes@377
  1993
    FMULP_st(1);
nkeynes@377
  1994
    pop_dr(R_EDX, FRn);
nkeynes@380
  1995
    JMP_TARGET(end);
nkeynes@417
  1996
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1997
:}
nkeynes@377
  1998
FNEG FRn {:  
nkeynes@377
  1999
    check_fpuen();
nkeynes@377
  2000
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2001
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2002
    load_fr_bank( R_EDX );
nkeynes@380
  2003
    JNE_rel8(10, doubleprec);
nkeynes@377
  2004
    push_fr(R_EDX, FRn);
nkeynes@377
  2005
    FCHS_st0();
nkeynes@377
  2006
    pop_fr(R_EDX, FRn);
nkeynes@380
  2007
    JMP_rel8(8, end);
nkeynes@380
  2008
    JMP_TARGET(doubleprec);
nkeynes@377
  2009
    push_dr(R_EDX, FRn);
nkeynes@377
  2010
    FCHS_st0();
nkeynes@377
  2011
    pop_dr(R_EDX, FRn);
nkeynes@380
  2012
    JMP_TARGET(end);
nkeynes@417
  2013
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2014
:}
nkeynes@377
  2015
FSRRA FRn {:  
nkeynes@377
  2016
    check_fpuen();
nkeynes@377
  2017
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2018
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2019
    load_fr_bank( R_EDX );
nkeynes@380
  2020
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2021
    FLD1_st0();
nkeynes@377
  2022
    push_fr(R_EDX, FRn);
nkeynes@377
  2023
    FSQRT_st0();
nkeynes@377
  2024
    FDIVP_st(1);
nkeynes@377
  2025
    pop_fr(R_EDX, FRn);
nkeynes@380
  2026
    JMP_TARGET(end);
nkeynes@417
  2027
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2028
:}
nkeynes@377
  2029
FSQRT FRn {:  
nkeynes@377
  2030
    check_fpuen();
nkeynes@377
  2031
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2032
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2033
    load_fr_bank( R_EDX );
nkeynes@380
  2034
    JNE_rel8(10, doubleprec);
nkeynes@377
  2035
    push_fr(R_EDX, FRn);
nkeynes@377
  2036
    FSQRT_st0();
nkeynes@377
  2037
    pop_fr(R_EDX, FRn);
nkeynes@380
  2038
    JMP_rel8(8, end);
nkeynes@380
  2039
    JMP_TARGET(doubleprec);
nkeynes@377
  2040
    push_dr(R_EDX, FRn);
nkeynes@377
  2041
    FSQRT_st0();
nkeynes@377
  2042
    pop_dr(R_EDX, FRn);
nkeynes@380
  2043
    JMP_TARGET(end);
nkeynes@417
  2044
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2045
:}
nkeynes@377
  2046
FSUB FRm, FRn {:  
nkeynes@377
  2047
    check_fpuen();
nkeynes@377
  2048
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2049
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2050
    load_fr_bank( R_EDX );
nkeynes@380
  2051
    JNE_rel8(13, doubleprec);
nkeynes@377
  2052
    push_fr(R_EDX, FRn);
nkeynes@377
  2053
    push_fr(R_EDX, FRm);
nkeynes@388
  2054
    FSUBP_st(1);
nkeynes@377
  2055
    pop_fr(R_EDX, FRn);
nkeynes@380
  2056
    JMP_rel8(11, end);
nkeynes@380
  2057
    JMP_TARGET(doubleprec);
nkeynes@377
  2058
    push_dr(R_EDX, FRn);
nkeynes@377
  2059
    push_dr(R_EDX, FRm);
nkeynes@388
  2060
    FSUBP_st(1);
nkeynes@377
  2061
    pop_dr(R_EDX, FRn);
nkeynes@380
  2062
    JMP_TARGET(end);
nkeynes@417
  2063
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2064
:}
nkeynes@377
  2065
nkeynes@377
  2066
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2067
    check_fpuen();
nkeynes@377
  2068
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2069
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2070
    load_fr_bank( R_EDX );
nkeynes@380
  2071
    JNE_rel8(8, doubleprec);
nkeynes@377
  2072
    push_fr(R_EDX, FRm);
nkeynes@377
  2073
    push_fr(R_EDX, FRn);
nkeynes@380
  2074
    JMP_rel8(6, end);
nkeynes@380
  2075
    JMP_TARGET(doubleprec);
nkeynes@377
  2076
    push_dr(R_EDX, FRm);
nkeynes@377
  2077
    push_dr(R_EDX, FRn);
nkeynes@382
  2078
    JMP_TARGET(end);
nkeynes@377
  2079
    FCOMIP_st(1);
nkeynes@377
  2080
    SETE_t();
nkeynes@377
  2081
    FPOP_st();
nkeynes@417
  2082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2083
:}
nkeynes@377
  2084
FCMP/GT FRm, FRn {:  
nkeynes@377
  2085
    check_fpuen();
nkeynes@377
  2086
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2087
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2088
    load_fr_bank( R_EDX );
nkeynes@380
  2089
    JNE_rel8(8, doubleprec);
nkeynes@377
  2090
    push_fr(R_EDX, FRm);
nkeynes@377
  2091
    push_fr(R_EDX, FRn);
nkeynes@380
  2092
    JMP_rel8(6, end);
nkeynes@380
  2093
    JMP_TARGET(doubleprec);
nkeynes@377
  2094
    push_dr(R_EDX, FRm);
nkeynes@377
  2095
    push_dr(R_EDX, FRn);
nkeynes@380
  2096
    JMP_TARGET(end);
nkeynes@377
  2097
    FCOMIP_st(1);
nkeynes@377
  2098
    SETA_t();
nkeynes@377
  2099
    FPOP_st();
nkeynes@417
  2100
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2101
:}
nkeynes@377
  2102
nkeynes@377
  2103
FSCA FPUL, FRn {:  
nkeynes@377
  2104
    check_fpuen();
nkeynes@388
  2105
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2106
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2107
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2108
    load_fr_bank( R_ECX );
nkeynes@388
  2109
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2110
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2111
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2112
    JMP_TARGET(doubleprec);
nkeynes@417
  2113
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2114
:}
nkeynes@377
  2115
FIPR FVm, FVn {:  
nkeynes@377
  2116
    check_fpuen();
nkeynes@388
  2117
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2118
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2119
    JNE_rel8(44, doubleprec);
nkeynes@388
  2120
    
nkeynes@388
  2121
    load_fr_bank( R_ECX );
nkeynes@388
  2122
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2123
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2124
    FMULP_st(1);
nkeynes@388
  2125
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2126
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2127
    FMULP_st(1);
nkeynes@388
  2128
    FADDP_st(1);
nkeynes@388
  2129
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2130
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2131
    FMULP_st(1);
nkeynes@388
  2132
    FADDP_st(1);
nkeynes@388
  2133
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2134
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2135
    FMULP_st(1);
nkeynes@388
  2136
    FADDP_st(1);
nkeynes@388
  2137
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2138
    JMP_TARGET(doubleprec);
nkeynes@417
  2139
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2140
:}
nkeynes@377
  2141
FTRV XMTRX, FVn {:  
nkeynes@377
  2142
    check_fpuen();
nkeynes@388
  2143
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2144
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2145
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2146
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2147
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2148
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2149
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2150
    JMP_TARGET(doubleprec);
nkeynes@417
  2151
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2152
:}
nkeynes@377
  2153
nkeynes@377
  2154
FRCHG {:  
nkeynes@377
  2155
    check_fpuen();
nkeynes@377
  2156
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2157
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2158
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2159
    update_fr_bank( R_ECX );
nkeynes@417
  2160
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2161
:}
nkeynes@377
  2162
FSCHG {:  
nkeynes@377
  2163
    check_fpuen();
nkeynes@377
  2164
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2165
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2166
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2167
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2168
:}
nkeynes@359
  2169
nkeynes@359
  2170
/* Processor control instructions */
nkeynes@368
  2171
LDC Rm, SR {:
nkeynes@386
  2172
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2173
	SLOTILLEGAL();
nkeynes@386
  2174
    } else {
nkeynes@386
  2175
	check_priv();
nkeynes@386
  2176
	load_reg( R_EAX, Rm );
nkeynes@386
  2177
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2178
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2179
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2180
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2181
    }
nkeynes@368
  2182
:}
nkeynes@359
  2183
LDC Rm, GBR {: 
nkeynes@359
  2184
    load_reg( R_EAX, Rm );
nkeynes@359
  2185
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2186
:}
nkeynes@359
  2187
LDC Rm, VBR {:  
nkeynes@386
  2188
    check_priv();
nkeynes@359
  2189
    load_reg( R_EAX, Rm );
nkeynes@359
  2190
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2192
:}
nkeynes@359
  2193
LDC Rm, SSR {:  
nkeynes@386
  2194
    check_priv();
nkeynes@359
  2195
    load_reg( R_EAX, Rm );
nkeynes@359
  2196
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2197
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2198
:}
nkeynes@359
  2199
LDC Rm, SGR {:  
nkeynes@386
  2200
    check_priv();
nkeynes@359
  2201
    load_reg( R_EAX, Rm );
nkeynes@359
  2202
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2203
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2204
:}
nkeynes@359
  2205
LDC Rm, SPC {:  
nkeynes@386
  2206
    check_priv();
nkeynes@359
  2207
    load_reg( R_EAX, Rm );
nkeynes@359
  2208
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2210
:}
nkeynes@359
  2211
LDC Rm, DBR {:  
nkeynes@386
  2212
    check_priv();
nkeynes@359
  2213
    load_reg( R_EAX, Rm );
nkeynes@359
  2214
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2216
:}
nkeynes@374
  2217
LDC Rm, Rn_BANK {:  
nkeynes@386
  2218
    check_priv();
nkeynes@374
  2219
    load_reg( R_EAX, Rm );
nkeynes@374
  2220
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2221
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2222
:}
nkeynes@359
  2223
LDC.L @Rm+, GBR {:  
nkeynes@359
  2224
    load_reg( R_EAX, Rm );
nkeynes@416
  2225
    precheck();
nkeynes@395
  2226
    check_ralign32( R_EAX );
nkeynes@359
  2227
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2228
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2229
    store_reg( R_EAX, Rm );
nkeynes@359
  2230
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2231
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2233
:}
nkeynes@368
  2234
LDC.L @Rm+, SR {:
nkeynes@386
  2235
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2236
	SLOTILLEGAL();
nkeynes@386
  2237
    } else {
nkeynes@416
  2238
	precheck();
nkeynes@416
  2239
	check_priv_no_precheck();
nkeynes@386
  2240
	load_reg( R_EAX, Rm );
nkeynes@395
  2241
	check_ralign32( R_EAX );
nkeynes@386
  2242
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2243
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2244
	store_reg( R_EAX, Rm );
nkeynes@386
  2245
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2246
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2247
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2248
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2249
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2250
    }
nkeynes@359
  2251
:}
nkeynes@359
  2252
LDC.L @Rm+, VBR {:  
nkeynes@416
  2253
    precheck();
nkeynes@416
  2254
    check_priv_no_precheck();
nkeynes@359
  2255
    load_reg( R_EAX, Rm );
nkeynes@395
  2256
    check_ralign32( R_EAX );
nkeynes@359
  2257
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2258
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2259
    store_reg( R_EAX, Rm );
nkeynes@359
  2260
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2261
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2263
:}
nkeynes@359
  2264
LDC.L @Rm+, SSR {:
nkeynes@416
  2265
    precheck();
nkeynes@416
  2266
    check_priv_no_precheck();
nkeynes@359
  2267
    load_reg( R_EAX, Rm );
nkeynes@416
  2268
    check_ralign32( R_EAX );
nkeynes@359
  2269
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2270
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2271
    store_reg( R_EAX, Rm );
nkeynes@359
  2272
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2273
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2274
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2275
:}
nkeynes@359
  2276
LDC.L @Rm+, SGR {:  
nkeynes@416
  2277
    precheck();
nkeynes@416
  2278
    check_priv_no_precheck();
nkeynes@359
  2279
    load_reg( R_EAX, Rm );
nkeynes@395
  2280
    check_ralign32( R_EAX );
nkeynes@359
  2281
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2282
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2283
    store_reg( R_EAX, Rm );
nkeynes@359
  2284
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2285
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2286
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2287
:}
nkeynes@359
  2288
LDC.L @Rm+, SPC {:  
nkeynes@416
  2289
    precheck();
nkeynes@416
  2290
    check_priv_no_precheck();
nkeynes@359
  2291
    load_reg( R_EAX, Rm );
nkeynes@395
  2292
    check_ralign32( R_EAX );
nkeynes@359
  2293
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2294
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2295
    store_reg( R_EAX, Rm );
nkeynes@359
  2296
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2297
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2298
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2299
:}
nkeynes@359
  2300
LDC.L @Rm+, DBR {:  
nkeynes@416
  2301
    precheck();
nkeynes@416
  2302
    check_priv_no_precheck();
nkeynes@359
  2303
    load_reg( R_EAX, Rm );
nkeynes@395
  2304
    check_ralign32( R_EAX );
nkeynes@359
  2305
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2306
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2307
    store_reg( R_EAX, Rm );
nkeynes@359
  2308
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2309
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2311
:}
nkeynes@359
  2312
LDC.L @Rm+, Rn_BANK {:  
nkeynes@416
  2313
    precheck();
nkeynes@416
  2314
    check_priv_no_precheck();
nkeynes@374
  2315
    load_reg( R_EAX, Rm );
nkeynes@395
  2316
    check_ralign32( R_EAX );
nkeynes@374
  2317
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2318
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2319
    store_reg( R_EAX, Rm );
nkeynes@374
  2320
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2321
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2323
:}
nkeynes@359
  2324
LDS Rm, FPSCR {:  
nkeynes@359
  2325
    load_reg( R_EAX, Rm );
nkeynes@359
  2326
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2327
    update_fr_bank( R_EAX );
nkeynes@417
  2328
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2329
:}
nkeynes@359
  2330
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2331
    load_reg( R_EAX, Rm );
nkeynes@416
  2332
    precheck();
nkeynes@395
  2333
    check_ralign32( R_EAX );
nkeynes@359
  2334
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2335
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2336
    store_reg( R_EAX, Rm );
nkeynes@359
  2337
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2338
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2339
    update_fr_bank( R_EAX );
nkeynes@417
  2340
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2341
:}
nkeynes@359
  2342
LDS Rm, FPUL {:  
nkeynes@359
  2343
    load_reg( R_EAX, Rm );
nkeynes@359
  2344
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2345
:}
nkeynes@359
  2346
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2347
    load_reg( R_EAX, Rm );
nkeynes@416
  2348
    precheck();
nkeynes@395
  2349
    check_ralign32( R_EAX );
nkeynes@359
  2350
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2351
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2352
    store_reg( R_EAX, Rm );
nkeynes@359
  2353
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2354
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2356
:}
nkeynes@359
  2357
LDS Rm, MACH {: 
nkeynes@359
  2358
    load_reg( R_EAX, Rm );
nkeynes@359
  2359
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2360
:}
nkeynes@359
  2361
LDS.L @Rm+, MACH {:  
nkeynes@359
  2362
    load_reg( R_EAX, Rm );
nkeynes@416
  2363
    precheck();
nkeynes@395
  2364
    check_ralign32( R_EAX );
nkeynes@359
  2365
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2366
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2367
    store_reg( R_EAX, Rm );
nkeynes@359
  2368
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2369
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2370
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2371
:}
nkeynes@359
  2372
LDS Rm, MACL {:  
nkeynes@359
  2373
    load_reg( R_EAX, Rm );
nkeynes@359
  2374
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2375
:}
nkeynes@359
  2376
LDS.L @Rm+, MACL {:  
nkeynes@359
  2377
    load_reg( R_EAX, Rm );
nkeynes@416
  2378
    precheck();
nkeynes@395
  2379
    check_ralign32( R_EAX );
nkeynes@359
  2380
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2381
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2382
    store_reg( R_EAX, Rm );
nkeynes@359
  2383
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2384
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2385
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2386
:}
nkeynes@359
  2387
LDS Rm, PR {:  
nkeynes@359
  2388
    load_reg( R_EAX, Rm );
nkeynes@359
  2389
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2390
:}
nkeynes@359
  2391
LDS.L @Rm+, PR {:  
nkeynes@359
  2392
    load_reg( R_EAX, Rm );
nkeynes@416
  2393
    precheck();
nkeynes@395
  2394
    check_ralign32( R_EAX );
nkeynes@359
  2395
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2396
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2397
    store_reg( R_EAX, Rm );
nkeynes@359
  2398
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2399
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2400
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2401
:}
nkeynes@359
  2402
LDTLB {:  :}
nkeynes@359
  2403
OCBI @Rn {:  :}
nkeynes@359
  2404
OCBP @Rn {:  :}
nkeynes@359
  2405
OCBWB @Rn {:  :}
nkeynes@374
  2406
PREF @Rn {:
nkeynes@374
  2407
    load_reg( R_EAX, Rn );
nkeynes@532
  2408
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2409
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2410
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
  2411
    JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
  2412
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
  2413
    JMP_TARGET(end);
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2415
:}
nkeynes@388
  2416
SLEEP {: 
nkeynes@388
  2417
    check_priv();
nkeynes@388
  2418
    call_func0( sh4_sleep );
nkeynes@417
  2419
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2420
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2421
    return 2;
nkeynes@388
  2422
:}
nkeynes@386
  2423
STC SR, Rn {:
nkeynes@386
  2424
    check_priv();
nkeynes@386
  2425
    call_func0(sh4_read_sr);
nkeynes@386
  2426
    store_reg( R_EAX, Rn );
nkeynes@417
  2427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2428
:}
nkeynes@359
  2429
STC GBR, Rn {:  
nkeynes@359
  2430
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2431
    store_reg( R_EAX, Rn );
nkeynes@359
  2432
:}
nkeynes@359
  2433
STC VBR, Rn {:  
nkeynes@386
  2434
    check_priv();
nkeynes@359
  2435
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2436
    store_reg( R_EAX, Rn );
nkeynes@417
  2437
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2438
:}
nkeynes@359
  2439
STC SSR, Rn {:  
nkeynes@386
  2440
    check_priv();
nkeynes@359
  2441
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2442
    store_reg( R_EAX, Rn );
nkeynes@417
  2443
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2444
:}
nkeynes@359
  2445
STC SPC, Rn {:  
nkeynes@386
  2446
    check_priv();
nkeynes@359
  2447
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2448
    store_reg( R_EAX, Rn );
nkeynes@417
  2449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2450
:}
nkeynes@359
  2451
STC SGR, Rn {:  
nkeynes@386
  2452
    check_priv();
nkeynes@359
  2453
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2454
    store_reg( R_EAX, Rn );
nkeynes@417
  2455
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2456
:}
nkeynes@359
  2457
STC DBR, Rn {:  
nkeynes@386
  2458
    check_priv();
nkeynes@359
  2459
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2460
    store_reg( R_EAX, Rn );
nkeynes@417
  2461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2462
:}
nkeynes@374
  2463
STC Rm_BANK, Rn {:
nkeynes@386
  2464
    check_priv();
nkeynes@374
  2465
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2466
    store_reg( R_EAX, Rn );
nkeynes@417
  2467
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2468
:}
nkeynes@374
  2469
STC.L SR, @-Rn {:
nkeynes@416
  2470
    precheck();
nkeynes@416
  2471
    check_priv_no_precheck();
nkeynes@395
  2472
    call_func0( sh4_read_sr );
nkeynes@368
  2473
    load_reg( R_ECX, Rn );
nkeynes@395
  2474
    check_walign32( R_ECX );
nkeynes@382
  2475
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2476
    store_reg( R_ECX, Rn );
nkeynes@368
  2477
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2479
:}
nkeynes@359
  2480
STC.L VBR, @-Rn {:  
nkeynes@416
  2481
    precheck();
nkeynes@416
  2482
    check_priv_no_precheck();
nkeynes@359
  2483
    load_reg( R_ECX, Rn );
nkeynes@395
  2484
    check_walign32( R_ECX );
nkeynes@382
  2485
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2486
    store_reg( R_ECX, Rn );
nkeynes@359
  2487
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2488
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2489
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2490
:}
nkeynes@359
  2491
STC.L SSR, @-Rn {:  
nkeynes@416
  2492
    precheck();
nkeynes@416
  2493
    check_priv_no_precheck();
nkeynes@359
  2494
    load_reg( R_ECX, Rn );
nkeynes@395
  2495
    check_walign32( R_ECX );
nkeynes@382
  2496
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2497
    store_reg( R_ECX, Rn );
nkeynes@359
  2498
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2499
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2500
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2501
:}
nkeynes@416
  2502
STC.L SPC, @-Rn {:
nkeynes@416
  2503
    precheck();
nkeynes@416
  2504
    check_priv_no_precheck();
nkeynes@359
  2505
    load_reg( R_ECX, Rn );
nkeynes@395
  2506
    check_walign32( R_ECX );
nkeynes@382
  2507
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2508
    store_reg( R_ECX, Rn );
nkeynes@359
  2509
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2510
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2511
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2512
:}
nkeynes@359
  2513
STC.L SGR, @-Rn {:  
nkeynes@416
  2514
    precheck();
nkeynes@416
  2515
    check_priv_no_precheck();
nkeynes@359
  2516
    load_reg( R_ECX, Rn );
nkeynes@395
  2517
    check_walign32( R_ECX );
nkeynes@382
  2518
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2519
    store_reg( R_ECX, Rn );
nkeynes@359
  2520
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2521
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2522
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2523
:}
nkeynes@359
  2524
STC.L DBR, @-Rn {:  
nkeynes@416
  2525
    precheck();
nkeynes@416
  2526
    check_priv_no_precheck();
nkeynes@359
  2527
    load_reg( R_ECX, Rn );
nkeynes@395
  2528
    check_walign32( R_ECX );
nkeynes@382
  2529
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2530
    store_reg( R_ECX, Rn );
nkeynes@359
  2531
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2532
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2533
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2534
:}
nkeynes@374
  2535
STC.L Rm_BANK, @-Rn {:  
nkeynes@416
  2536
    precheck();
nkeynes@416
  2537
    check_priv_no_precheck();
nkeynes@374
  2538
    load_reg( R_ECX, Rn );
nkeynes@395
  2539
    check_walign32( R_ECX );
nkeynes@382
  2540
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2541
    store_reg( R_ECX, Rn );
nkeynes@374
  2542
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2543
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2544
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2545
:}
nkeynes@359
  2546
STC.L GBR, @-Rn {:  
nkeynes@359
  2547
    load_reg( R_ECX, Rn );
nkeynes@416
  2548
    precheck();
nkeynes@395
  2549
    check_walign32( R_ECX );
nkeynes@382
  2550
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2551
    store_reg( R_ECX, Rn );
nkeynes@359
  2552
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2553
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2554
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2555
:}
nkeynes@359
  2556
STS FPSCR, Rn {:  
nkeynes@359
  2557
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2558
    store_reg( R_EAX, Rn );
nkeynes@359
  2559
:}
nkeynes@359
  2560
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2561
    load_reg( R_ECX, Rn );
nkeynes@416
  2562
    precheck();
nkeynes@395
  2563
    check_walign32( R_ECX );
nkeynes@382
  2564
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2565
    store_reg( R_ECX, Rn );
nkeynes@359
  2566
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2567
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2568
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2569
:}
nkeynes@359
  2570
STS FPUL, Rn {:  
nkeynes@359
  2571
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2572
    store_reg( R_EAX, Rn );
nkeynes@359
  2573
:}
nkeynes@359
  2574
STS.L FPUL, @-Rn {:  
nkeynes@359
  2575
    load_reg( R_ECX, Rn );
nkeynes@416
  2576
    precheck();
nkeynes@395
  2577
    check_walign32( R_ECX );
nkeynes@382
  2578
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2579
    store_reg( R_ECX, Rn );
nkeynes@359
  2580
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2581
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2582
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2583
:}
nkeynes@359
  2584
STS MACH, Rn {:  
nkeynes@359
  2585
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2586
    store_reg( R_EAX, Rn );
nkeynes@359
  2587
:}
nkeynes@359
  2588
STS.L MACH, @-Rn {:  
nkeynes@359
  2589
    load_reg( R_ECX, Rn );
nkeynes@416
  2590
    precheck();
nkeynes@395
  2591
    check_walign32( R_ECX );
nkeynes@382
  2592
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2593
    store_reg( R_ECX, Rn );
nkeynes@359
  2594
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2595
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2597
:}
nkeynes@359
  2598
STS MACL, Rn {:  
nkeynes@359
  2599
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2600
    store_reg( R_EAX, Rn );
nkeynes@359
  2601
:}
nkeynes@359
  2602
STS.L MACL, @-Rn {:  
nkeynes@359
  2603
    load_reg( R_ECX, Rn );
nkeynes@416
  2604
    precheck();
nkeynes@395
  2605
    check_walign32( R_ECX );
nkeynes@382
  2606
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2607
    store_reg( R_ECX, Rn );
nkeynes@359
  2608
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2609
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2610
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2611
:}
nkeynes@359
  2612
STS PR, Rn {:  
nkeynes@359
  2613
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2614
    store_reg( R_EAX, Rn );
nkeynes@359
  2615
:}
nkeynes@359
  2616
STS.L PR, @-Rn {:  
nkeynes@359
  2617
    load_reg( R_ECX, Rn );
nkeynes@416
  2618
    precheck();
nkeynes@395
  2619
    check_walign32( R_ECX );
nkeynes@382
  2620
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2621
    store_reg( R_ECX, Rn );
nkeynes@359
  2622
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2623
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2624
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2625
:}
nkeynes@359
  2626
nkeynes@359
  2627
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2628
%%
nkeynes@416
  2629
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2630
    return 0;
nkeynes@359
  2631
}
.