filename | src/sh4/sh4core.h |
changeset | 591:7b9612fd2395 |
prev | 589:045ba6eb6df1 |
next | 597:87cbdf62aa35 |
author | nkeynes |
date | Thu Jan 17 10:11:37 2008 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Add flag to skip breakpoints when it's the very first instruction of a run (ie, so executing dreamcast_run() when the current pc is a breakpoint doesn't just return immediately) |
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nkeynes@10 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@10 | 3 | * |
nkeynes@54 | 4 | * This file defines the internal functions exported/used by the SH4 core, |
nkeynes@54 | 5 | * except for disassembly functions defined in sh4dasm.h |
nkeynes@10 | 6 | * |
nkeynes@10 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@10 | 8 | * |
nkeynes@10 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@10 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@10 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@10 | 12 | * (at your option) any later version. |
nkeynes@10 | 13 | * |
nkeynes@10 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@10 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@10 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@10 | 17 | * GNU General Public License for more details. |
nkeynes@1 | 18 | */ |
nkeynes@30 | 19 | |
nkeynes@1 | 20 | #ifndef sh4core_H |
nkeynes@1 | 21 | #define sh4core_H 1 |
nkeynes@1 | 22 | |
nkeynes@27 | 23 | #include <glib/gtypes.h> |
nkeynes@1 | 24 | #include <stdint.h> |
nkeynes@23 | 25 | #include <stdio.h> |
nkeynes@378 | 26 | #include "mem.h" |
nkeynes@586 | 27 | #include "sh4/sh4.h" |
nkeynes@1 | 28 | |
nkeynes@1 | 29 | #ifdef __cplusplus |
nkeynes@1 | 30 | extern "C" { |
nkeynes@1 | 31 | #endif |
nkeynes@1 | 32 | |
nkeynes@586 | 33 | /* Breakpoint data structure */ |
nkeynes@586 | 34 | extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@586 | 35 | extern int sh4_breakpoint_count; |
nkeynes@586 | 36 | extern sh4ptr_t sh4_main_ram; |
nkeynes@591 | 37 | extern gboolean sh4_starting; |
nkeynes@27 | 38 | |
nkeynes@27 | 39 | /** |
nkeynes@586 | 40 | * Cached direct pointer to the current instruction page. If AT is on, this |
nkeynes@586 | 41 | * is derived from the ITLB, otherwise this will be the entire memory region. |
nkeynes@586 | 42 | * This is actually a fairly useful optimization, as we can make a lot of |
nkeynes@586 | 43 | * assumptions about the "current page" that we can't make in general for |
nkeynes@586 | 44 | * arbitrary virtual addresses. |
nkeynes@27 | 45 | */ |
nkeynes@586 | 46 | struct sh4_icache_struct { |
nkeynes@586 | 47 | sh4ptr_t page; // Page pointer (NULL if no page) |
nkeynes@586 | 48 | sh4vma_t page_vma; // virtual address of the page. |
nkeynes@586 | 49 | sh4addr_t page_ppa; // physical address of the page |
nkeynes@586 | 50 | uint32_t mask; // page mask |
nkeynes@586 | 51 | }; |
nkeynes@586 | 52 | extern struct sh4_icache_struct sh4_icache; |
nkeynes@586 | 53 | |
nkeynes@27 | 54 | /** |
nkeynes@586 | 55 | * Test if a given address is contained in the current icache entry |
nkeynes@27 | 56 | */ |
nkeynes@586 | 57 | #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask)) |
nkeynes@27 | 58 | /** |
nkeynes@586 | 59 | * Return a pointer for the given vma, under the assumption that it is |
nkeynes@586 | 60 | * actually contained in the current icache entry. |
nkeynes@27 | 61 | */ |
nkeynes@586 | 62 | #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma)) |
nkeynes@27 | 63 | /** |
nkeynes@586 | 64 | * Return the physical (external) address for the given vma, assuming that it is |
nkeynes@586 | 65 | * actually contained in the current icache entry. |
nkeynes@27 | 66 | */ |
nkeynes@586 | 67 | #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma)) |
nkeynes@27 | 68 | |
nkeynes@589 | 69 | /** |
nkeynes@589 | 70 | * Return the virtual (vma) address for the first address past the end of the |
nkeynes@589 | 71 | * cache entry. Assumes that there is in fact a current icache entry. |
nkeynes@589 | 72 | */ |
nkeynes@589 | 73 | #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1) |
nkeynes@589 | 74 | |
nkeynes@586 | 75 | /* SH4 module functions */ |
nkeynes@1 | 76 | void sh4_init( void ); |
nkeynes@1 | 77 | void sh4_reset( void ); |
nkeynes@1 | 78 | void sh4_run( void ); |
nkeynes@1 | 79 | void sh4_stop( void ); |
nkeynes@586 | 80 | |
nkeynes@586 | 81 | /* SH4 peripheral module functions */ |
nkeynes@586 | 82 | void CPG_reset( void ); |
nkeynes@586 | 83 | void DMAC_reset( void ); |
nkeynes@586 | 84 | void DMAC_run_slice( uint32_t ); |
nkeynes@586 | 85 | void DMAC_save_state( FILE * ); |
nkeynes@586 | 86 | int DMAC_load_state( FILE * ); |
nkeynes@586 | 87 | void INTC_reset( void ); |
nkeynes@586 | 88 | void INTC_save_state( FILE *f ); |
nkeynes@586 | 89 | int INTC_load_state( FILE *f ); |
nkeynes@586 | 90 | void MMU_init( void ); |
nkeynes@586 | 91 | void MMU_reset( void ); |
nkeynes@586 | 92 | void MMU_save_state( FILE *f ); |
nkeynes@586 | 93 | int MMU_load_state( FILE *f ); |
nkeynes@586 | 94 | void MMU_ldtlb(); |
nkeynes@586 | 95 | void SCIF_reset( void ); |
nkeynes@586 | 96 | void SCIF_run_slice( uint32_t ); |
nkeynes@586 | 97 | void SCIF_save_state( FILE *f ); |
nkeynes@586 | 98 | int SCIF_load_state( FILE *f ); |
nkeynes@586 | 99 | void SCIF_update_line_speed(void); |
nkeynes@586 | 100 | void TMU_reset( void ); |
nkeynes@586 | 101 | void TMU_run_slice( uint32_t ); |
nkeynes@586 | 102 | void TMU_save_state( FILE * ); |
nkeynes@586 | 103 | int TMU_load_state( FILE * ); |
nkeynes@586 | 104 | void TMU_update_clocks( void ); |
nkeynes@586 | 105 | |
nkeynes@586 | 106 | /* SH4 instruction support methods */ |
nkeynes@401 | 107 | void sh4_sleep( void ); |
nkeynes@401 | 108 | void sh4_fsca( uint32_t angle, float *fr ); |
nkeynes@401 | 109 | void sh4_ftrv( float *fv, float *xmtrx ); |
nkeynes@586 | 110 | uint32_t sh4_read_sr(void); |
nkeynes@586 | 111 | void sh4_write_sr(uint32_t val); |
nkeynes@401 | 112 | void signsat48(void); |
nkeynes@378 | 113 | |
nkeynes@586 | 114 | /* SH4 Memory */ |
nkeynes@586 | 115 | #define MMU_VMA_ERROR 0x8000000 |
nkeynes@586 | 116 | /** |
nkeynes@586 | 117 | * Update the sh4_icache structure to contain the specified vma. If the vma |
nkeynes@586 | 118 | * cannot be resolved, an MMU exception is raised and the function returns |
nkeynes@586 | 119 | * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly. |
nkeynes@586 | 120 | * Note: If the vma resolves to a non-memory area, sh4_icache will be |
nkeynes@586 | 121 | * invalidated, but the function will still return TRUE. |
nkeynes@586 | 122 | * @return FALSE if an MMU exception was raised, otherwise TRUE. |
nkeynes@586 | 123 | */ |
nkeynes@586 | 124 | gboolean mmu_update_icache( sh4vma_t addr ); |
nkeynes@23 | 125 | |
nkeynes@586 | 126 | /** |
nkeynes@586 | 127 | * Resolve a virtual address through the TLB for a read operation, returning |
nkeynes@586 | 128 | * the resultant P4 or external address. If the resolution fails, the |
nkeynes@586 | 129 | * appropriate MMU exception is raised and the value MMU_VMA_ERROR is returned. |
nkeynes@586 | 130 | * @return An external address (0x00000000-0x1FFFFFFF), a P4 address |
nkeynes@586 | 131 | * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR. |
nkeynes@586 | 132 | */ |
nkeynes@586 | 133 | sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr ); |
nkeynes@586 | 134 | sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr ); |
nkeynes@1 | 135 | |
nkeynes@527 | 136 | int64_t sh4_read_quad( sh4addr_t addr ); |
nkeynes@527 | 137 | int32_t sh4_read_long( sh4addr_t addr ); |
nkeynes@527 | 138 | int32_t sh4_read_word( sh4addr_t addr ); |
nkeynes@527 | 139 | int32_t sh4_read_byte( sh4addr_t addr ); |
nkeynes@527 | 140 | void sh4_write_quad( sh4addr_t addr, uint64_t val ); |
nkeynes@527 | 141 | void sh4_write_long( sh4addr_t addr, uint32_t val ); |
nkeynes@527 | 142 | void sh4_write_word( sh4addr_t addr, uint32_t val ); |
nkeynes@527 | 143 | void sh4_write_byte( sh4addr_t addr, uint32_t val ); |
nkeynes@527 | 144 | int32_t sh4_read_phys_word( sh4addr_t addr ); |
nkeynes@586 | 145 | gboolean sh4_flush_store_queue( sh4addr_t addr ); |
nkeynes@10 | 146 | |
nkeynes@586 | 147 | /* SH4 Exceptions */ |
nkeynes@586 | 148 | #define EXC_POWER_RESET 0x000 /* reset vector */ |
nkeynes@586 | 149 | #define EXC_MANUAL_RESET 0x020 /* reset vector */ |
nkeynes@586 | 150 | #define EXC_TLB_MISS_READ 0x040 /* TLB vector */ |
nkeynes@586 | 151 | #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */ |
nkeynes@586 | 152 | #define EXC_INIT_PAGE_WRITE 0x080 |
nkeynes@586 | 153 | #define EXC_TLB_PROT_READ 0x0A0 |
nkeynes@586 | 154 | #define EXC_TLB_PROT_WRITE 0x0C0 |
nkeynes@586 | 155 | #define EXC_DATA_ADDR_READ 0x0E0 |
nkeynes@586 | 156 | #define EXC_DATA_ADDR_WRITE 0x100 |
nkeynes@586 | 157 | #define EXC_TLB_MULTI_HIT 0x140 |
nkeynes@586 | 158 | #define EXC_SLOT_ILLEGAL 0x1A0 |
nkeynes@586 | 159 | #define EXC_ILLEGAL 0x180 |
nkeynes@586 | 160 | #define EXC_TRAP 0x160 |
nkeynes@586 | 161 | #define EXC_FPU_DISABLED 0x800 |
nkeynes@586 | 162 | #define EXC_SLOT_FPU_DISABLED 0x820 |
nkeynes@374 | 163 | |
nkeynes@586 | 164 | #define EXV_EXCEPTION 0x100 /* General exception vector */ |
nkeynes@586 | 165 | #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */ |
nkeynes@586 | 166 | #define EXV_INTERRUPT 0x600 /* External interrupt vector */ |
nkeynes@586 | 167 | |
nkeynes@586 | 168 | gboolean sh4_raise_exception( int ); |
nkeynes@586 | 169 | gboolean sh4_raise_reset( int ); |
nkeynes@586 | 170 | gboolean sh4_raise_trap( int ); |
nkeynes@586 | 171 | gboolean sh4_raise_slot_exception( int, int ); |
nkeynes@586 | 172 | gboolean sh4_raise_tlb_exception( int ); |
nkeynes@586 | 173 | void sh4_accept_interrupt( void ); |
nkeynes@1 | 174 | |
nkeynes@1 | 175 | #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28) |
nkeynes@1 | 176 | #define SIGNEXT8(n) ((int32_t)((int8_t)(n))) |
nkeynes@1 | 177 | #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20) |
nkeynes@1 | 178 | #define SIGNEXT16(n) ((int32_t)((int16_t)(n))) |
nkeynes@1 | 179 | #define SIGNEXT32(n) ((int64_t)((int32_t)(n))) |
nkeynes@1 | 180 | #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16) |
nkeynes@586 | 181 | #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n)))) |
nkeynes@1 | 182 | |
nkeynes@1 | 183 | /* Status Register (SR) bits */ |
nkeynes@1 | 184 | #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ |
nkeynes@1 | 185 | #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */ |
nkeynes@1 | 186 | #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */ |
nkeynes@1 | 187 | #define SR_FD 0x00008000 /* FPU disable */ |
nkeynes@1 | 188 | #define SR_M 0x00000200 |
nkeynes@1 | 189 | #define SR_Q 0x00000100 |
nkeynes@1 | 190 | #define SR_IMASK 0x000000F0 /* Interrupt mask level */ |
nkeynes@1 | 191 | #define SR_S 0x00000002 /* Saturation operation for MAC instructions */ |
nkeynes@1 | 192 | #define SR_T 0x00000001 /* True/false or carry/borrow */ |
nkeynes@1 | 193 | #define SR_MASK 0x700083F3 |
nkeynes@1 | 194 | #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */ |
nkeynes@586 | 195 | #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */ |
nkeynes@1 | 196 | |
nkeynes@1 | 197 | #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD) |
nkeynes@1 | 198 | #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4) |
nkeynes@265 | 199 | #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot) |
nkeynes@1 | 200 | |
nkeynes@1 | 201 | #define FPSCR_FR 0x00200000 /* FPU register bank */ |
nkeynes@1 | 202 | #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */ |
nkeynes@1 | 203 | #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */ |
nkeynes@1 | 204 | #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */ |
nkeynes@1 | 205 | #define FPSCR_CAUSE 0x0003F000 |
nkeynes@1 | 206 | #define FPSCR_ENABLE 0x00000F80 |
nkeynes@1 | 207 | #define FPSCR_FLAG 0x0000007C |
nkeynes@1 | 208 | #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */ |
nkeynes@1 | 209 | |
nkeynes@1 | 210 | #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR) |
nkeynes@1 | 211 | #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ) |
nkeynes@1 | 212 | #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0) |
nkeynes@1 | 213 | |
nkeynes@374 | 214 | #define FR(x) sh4r.fr_bank[(x)^1] |
nkeynes@374 | 215 | #define DRF(x) ((double *)sh4r.fr_bank)[x] |
nkeynes@84 | 216 | #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1] |
nkeynes@95 | 217 | #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x] |
nkeynes@95 | 218 | #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x] |
nkeynes@359 | 219 | #define DR(x) DRb((x>>1), (x&1)) |
nkeynes@359 | 220 | #define FPULf *((float *)&sh4r.fpul) |
nkeynes@359 | 221 | #define FPULi (sh4r.fpul) |
nkeynes@359 | 222 | |
nkeynes@2 | 223 | #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val; |
nkeynes@1 | 224 | |
nkeynes@1 | 225 | #ifdef __cplusplus |
nkeynes@1 | 226 | } |
nkeynes@1 | 227 | #endif |
nkeynes@1 | 228 | #endif |
nkeynes@359 | 229 |
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