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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 279:7bb759c23271
prev255:ade289880b8d
next302:96b5cc24309c
author nkeynes
date Sun Jan 14 02:54:40 2007 +0000 (15 years ago)
permissions -rw-r--r--
last change Initial SPU dma implementation
file annotate diff log raw
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/**
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 * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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    47
static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
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					NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 8
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#define G2_BIT4_TICKS 16
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#define G2_BIT0_ON_TICKS 24
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#define G2_BIT0_OFF_TICKS 24
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struct asic_g2_state {
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    unsigned int last_update_time;
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    unsigned int bit5_off_timer;
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    unsigned int bit4_on_timer;
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    unsigned int bit4_off_timer;
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    unsigned int bit0_on_timer;
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    unsigned int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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	return 1;
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    else
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	return 0;
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}
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/* FIXME: Handle rollover */
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void asic_g2_write_word()
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{
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    g2_state.last_update_time = sh4r.icount;
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    g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
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    if( g2_state.bit4_off_timer < sh4r.icount )
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	g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
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    g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
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    if( g2_state.bit0_off_timer < sh4r.icount ) {
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	g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
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	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_read_status()
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{
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    if( sh4r.icount < g2_state.last_update_time ) {
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	/* Rollover */
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	if( g2_state.last_update_time < g2_state.bit5_off_timer )
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	    g2_state.bit5_off_timer = 0;
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	if( g2_state.last_update_time < g2_state.bit4_off_timer )
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	    g2_state.bit4_off_timer = 0;
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	if( g2_state.last_update_time < g2_state.bit4_on_timer )
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	    g2_state.bit4_on_timer = 0;
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	if( g2_state.last_update_time < g2_state.bit0_off_timer )
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	    g2_state.bit0_off_timer = 0;
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	if( g2_state.last_update_time < g2_state.bit0_on_timer )
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	    g2_state.bit0_on_timer = 0;
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    }
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( g2_state.bit5_off_timer <= sh4r.icount )
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	val = val & (~0x20);
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    if( g2_state.bit4_off_timer <= sh4r.icount ||
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	(sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
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	val = val & (~0x10);
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    else if( g2_state.bit4_on_timer <= sh4r.icount )
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	val = val | 0x10;
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    if( g2_state.bit0_off_timer <= sh4r.icount )
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	val = val & (~0x01);
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    else if( g2_state.bit0_on_timer <= sh4r.icount )
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	val = val | 0x01;
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    return val | 0x0E;
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}   
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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{
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    uint32_t offset = channel << 5;
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    if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {
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	if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {
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	    uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );
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	    uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );
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	    uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;
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	    uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );
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	    uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );
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	    char buf[length];
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	    if( dir == 0 ) { /* SH4 to device */
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		mem_copy_from_sh4( buf, sh4addr, length );
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		mem_copy_to_sh4( extaddr, buf, length );
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	    } else { /* Device to SH4 */
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		mem_copy_from_sh4( buf, extaddr, length );
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		mem_copy_to_sh4( sh4addr, buf, length );
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	    }
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	    MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
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	    asic_event( EVENT_SPU_DMA0 + channel );
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	} else {
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	    MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
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	}
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    }
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}
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void asic_ide_dma_transfer( )
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{	
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    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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   218
	    
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	    uint32_t xfer = ide_read_data_dma( addr, length );
nkeynes@158
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	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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	} else { /* 0 */
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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	}
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    }
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   226
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}
nkeynes@155
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nkeynes@155
   229
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void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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{
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   232
    switch( reg ) {
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   233
    case PIRQ1:
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   234
	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
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	/* fallthrough */
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   236
    case PIRQ0:
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   237
    case PIRQ2:
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	/* Clear any interrupts */
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   239
	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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   240
	asic_check_cleared_events();
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	break;
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   242
    case SYSRESET:
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   243
	if( val == 0x7611 ) {
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   244
	    dreamcast_reset();
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   245
	    sh4r.new_pc = sh4r.pc;
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   246
	} else {
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   247
	    WARN( "Unknown value %08X written to SYSRESET port", val );
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   248
	}
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   249
	break;
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   250
    case MAPLE_STATE:
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   251
	MMIO_WRITE( ASIC, reg, val );
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   252
	if( val & 1 ) {
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   253
	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@56
   254
	    maple_handle_buffer( maple_addr );
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   255
	    MMIO_WRITE( ASIC, reg, 0 );
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   256
	}
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   257
	break;
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   258
    case PVRDMACTL: /* Initiate PVR DMA transfer */
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   259
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   260
	if( val & 1 ) {
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   261
	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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   262
	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@56
   263
	    char *data = alloca( count );
nkeynes@56
   264
	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@56
   265
	    if( rcount != count )
nkeynes@56
   266
		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@100
   267
	    mem_copy_to_sh4( dest_addr, data, rcount );
nkeynes@56
   268
	    asic_event( EVENT_PVR_DMA );
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   269
	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@186
   270
	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@56
   271
	}
nkeynes@56
   272
	break;
nkeynes@158
   273
    case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
nkeynes@158
   274
	MMIO_WRITE( ASIC, reg, val );
nkeynes@158
   275
	break;
nkeynes@56
   276
    default:
nkeynes@56
   277
	MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   278
    }
nkeynes@1
   279
}
nkeynes@1
   280
nkeynes@1
   281
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   282
{
nkeynes@1
   283
    int32_t val;
nkeynes@1
   284
    switch( reg ) {
nkeynes@2
   285
        /*
nkeynes@2
   286
        case 0x89C:
nkeynes@2
   287
            sh4_stop();
nkeynes@2
   288
            return 0x000000B;
nkeynes@2
   289
        */     
nkeynes@94
   290
    case PIRQ0:
nkeynes@94
   291
    case PIRQ1:
nkeynes@94
   292
    case PIRQ2:
nkeynes@94
   293
    case IRQA0:
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   294
    case IRQA1:
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   295
    case IRQA2:
nkeynes@94
   296
    case IRQB0:
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   297
    case IRQB1:
nkeynes@94
   298
    case IRQB2:
nkeynes@94
   299
    case IRQC0:
nkeynes@94
   300
    case IRQC1:
nkeynes@94
   301
    case IRQC2:
nkeynes@158
   302
    case MAPLE_STATE:
nkeynes@94
   303
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   304
	return val;            
nkeynes@94
   305
    case G2STATUS:
nkeynes@137
   306
	return g2_read_status();
nkeynes@94
   307
    default:
nkeynes@94
   308
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   309
	return val;
nkeynes@1
   310
    }
nkeynes@94
   311
    
nkeynes@1
   312
}
nkeynes@1
   313
nkeynes@1
   314
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   315
{
nkeynes@244
   316
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   317
	return; /* disabled */
nkeynes@244
   318
    }
nkeynes@244
   319
nkeynes@2
   320
    switch( reg ) {
nkeynes@125
   321
    case IDEALTSTATUS: /* Device control */
nkeynes@125
   322
	ide_write_control( val );
nkeynes@125
   323
	break;
nkeynes@125
   324
    case IDEDATA:
nkeynes@125
   325
	ide_write_data_pio( val );
nkeynes@125
   326
	break;
nkeynes@125
   327
    case IDEFEAT:
nkeynes@125
   328
	if( ide_can_write_regs() )
nkeynes@125
   329
	    idereg.feature = (uint8_t)val;
nkeynes@125
   330
	break;
nkeynes@125
   331
    case IDECOUNT:
nkeynes@125
   332
	if( ide_can_write_regs() )
nkeynes@125
   333
	    idereg.count = (uint8_t)val;
nkeynes@125
   334
	break;
nkeynes@125
   335
    case IDELBA0:
nkeynes@125
   336
	if( ide_can_write_regs() )
nkeynes@125
   337
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   338
	break;
nkeynes@125
   339
    case IDELBA1:
nkeynes@125
   340
	if( ide_can_write_regs() )
nkeynes@125
   341
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   342
	break;
nkeynes@125
   343
    case IDELBA2:
nkeynes@125
   344
	if( ide_can_write_regs() )
nkeynes@125
   345
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   346
	break;
nkeynes@125
   347
    case IDEDEV:
nkeynes@125
   348
	if( ide_can_write_regs() )
nkeynes@125
   349
	    idereg.device = (uint8_t)val;
nkeynes@125
   350
	break;
nkeynes@125
   351
    case IDECMD:
nkeynes@240
   352
	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@125
   353
	    ide_write_command( (uint8_t)val );
nkeynes@125
   354
	}
nkeynes@125
   355
	break;
nkeynes@125
   356
    case IDEDMACTL1:
nkeynes@125
   357
    case IDEDMACTL2:
nkeynes@125
   358
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@155
   359
	asic_ide_dma_transfer( );
nkeynes@125
   360
	break;
nkeynes@244
   361
    case IDEACTIVATE:
nkeynes@244
   362
	if( val == 0x001FFFFF ) {
nkeynes@244
   363
	    idereg.interface_enabled = TRUE;
nkeynes@244
   364
	    /* Conventional wisdom says that this is necessary but not
nkeynes@244
   365
	     * sufficient to enable the IDE interface.
nkeynes@244
   366
	     */
nkeynes@244
   367
	} else if( val == 0x000042FE ) {
nkeynes@244
   368
	    idereg.interface_enabled = FALSE;
nkeynes@244
   369
	}
nkeynes@279
   370
	break;
nkeynes@279
   371
    case SPUDMA0CTL1:
nkeynes@279
   372
    case SPUDMA0CTL2:
nkeynes@279
   373
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   374
	g2_dma_transfer( 0 );
nkeynes@279
   375
	break;
nkeynes@279
   376
    case SPUDMA0UN1:
nkeynes@279
   377
	break;
nkeynes@279
   378
    case SPUDMA1CTL1:
nkeynes@279
   379
    case SPUDMA1CTL2:
nkeynes@279
   380
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   381
	g2_dma_transfer( 1 );
nkeynes@279
   382
	break;
nkeynes@279
   383
nkeynes@279
   384
    case SPUDMA1UN1:
nkeynes@279
   385
	break;
nkeynes@279
   386
    case SPUDMA2CTL1:
nkeynes@279
   387
    case SPUDMA2CTL2:
nkeynes@279
   388
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   389
	g2_dma_transfer( 2 );
nkeynes@279
   390
	break;
nkeynes@279
   391
    case SPUDMA2UN1:
nkeynes@279
   392
	break;
nkeynes@279
   393
    case SPUDMA3CTL1:
nkeynes@279
   394
    case SPUDMA3CTL2:
nkeynes@279
   395
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   396
	g2_dma_transfer( 3 );
nkeynes@279
   397
	break;
nkeynes@279
   398
    case SPUDMA3UN1:
nkeynes@279
   399
	break;
nkeynes@279
   400
    case PVRDMA2CTL1:
nkeynes@279
   401
    case PVRDMA2CTL2:
nkeynes@279
   402
	if( val != 0 ) {
nkeynes@279
   403
	    ERROR( "Write to unimplemented DMA control register %08X", reg );
nkeynes@279
   404
	    //dreamcast_stop();
nkeynes@279
   405
	    //sh4_stop();
nkeynes@279
   406
	}
nkeynes@279
   407
	break;
nkeynes@125
   408
    default:
nkeynes@2
   409
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   410
    }
nkeynes@1
   411
}
nkeynes@1
   412
nkeynes@1
   413
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   414
{
nkeynes@56
   415
    uint32_t val;
nkeynes@244
   416
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   417
	return 0xFFFFFFFF; /* disabled */
nkeynes@244
   418
    }
nkeynes@244
   419
nkeynes@1
   420
    switch( reg ) {
nkeynes@158
   421
    case IDEALTSTATUS: 
nkeynes@158
   422
	val = idereg.status;
nkeynes@158
   423
	return val;
nkeynes@158
   424
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   425
    case IDEFEAT: return idereg.error;
nkeynes@158
   426
    case IDECOUNT:return idereg.count;
nkeynes@158
   427
    case IDELBA0: return idereg.disc;
nkeynes@158
   428
    case IDELBA1: return idereg.lba1;
nkeynes@158
   429
    case IDELBA2: return idereg.lba2;
nkeynes@158
   430
    case IDEDEV: return idereg.device;
nkeynes@158
   431
    case IDECMD:
nkeynes@158
   432
	val = ide_read_status();
nkeynes@158
   433
	return val;
nkeynes@158
   434
    default:
nkeynes@158
   435
	val = MMIO_READ( EXTDMA, reg );
nkeynes@158
   436
	return val;
nkeynes@1
   437
    }
nkeynes@1
   438
}
nkeynes@1
   439
.