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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1092:7c4ffe27e7b5
prev1091:186558374345
next1112:4cac5e474d4c
author nkeynes
date Sun Dec 20 21:01:03 2009 +1000 (11 years ago)
permissions -rw-r--r--
last change Fix 64-bit x86 disassembly
Add crash-report hook to SIGILL and SIGBUS
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4dasm.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "x86dasm/x86dasm.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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static struct x86_symbol x86_symbol_table[] = {
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    { "sh4r+128", ((char *)&sh4r)+128 },
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    { "sh4_cpu_period", &sh4_cpu_period },
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    { "sh4_address_space", NULL },
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    { "sh4_user_address_space", NULL },
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    { "sh4_write_fpscr", sh4_write_fpscr },
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    { "sh4_write_sr", sh4_write_sr },
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    { "sh4_read_sr", sh4_read_sr },
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    { "sh4_sleep", sh4_sleep },
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    { "sh4_fsca", sh4_fsca },
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    { "sh4_ftrv", sh4_ftrv },
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    { "sh4_switch_fr_banks", sh4_switch_fr_banks },
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    { "sh4_execute_instruction", sh4_execute_instruction },
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    { "signsat48", signsat48 },
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    { "xlat_get_code_by_vma", xlat_get_code_by_vma },
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    { "xlat_get_code", xlat_get_code }
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};
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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    x86_symbol_table[2].ptr = sh4_address_space;
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    x86_symbol_table[3].ptr = sh4_user_address_space;    
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    x86_disasm_init();
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    x86_set_symtab( x86_symbol_table, sizeof(x86_symbol_table)/sizeof(struct x86_symbol) );
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}
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/**
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 * Disassemble the given translated code block, and it's source SH4 code block
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 * side-by-side. The current native pc will be marked if non-null.
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 */
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void sh4_translate_disasm_block( FILE *out, void *code, sh4addr_t source_start, void *native_pc )
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{
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    char buf[256];
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    char op[256];
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    uintptr_t target_start = (uintptr_t)code, target_pc;
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    uintptr_t target_end = target_start + xlat_get_code_size(code);
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    uint32_t source_pc = source_start;
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    uint32_t source_end = source_pc;
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    xlat_recovery_record_t source_recov_table = XLAT_RECOVERY_TABLE(code);
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    xlat_recovery_record_t source_recov_end = source_recov_table + XLAT_BLOCK_FOR_CODE(code)->recover_table_size - 1;
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    for( target_pc = target_start; target_pc < target_end;  ) {
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        uintptr_t pc2 = x86_disasm_instruction( target_pc, buf, sizeof(buf), op );
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#if SIZEOF_VOID_P == 8
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        fprintf( out, "%c%016lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#else
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        fprintf( out, "%c%08x: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#endif        
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        if( source_recov_table < source_recov_end && 
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            target_pc >= (target_start + source_recov_table->xlat_offset) ) {
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            source_recov_table++;
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            if( source_end < (source_start + (source_recov_table->sh4_icount)*2) )
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                source_end = source_start + (source_recov_table->sh4_icount)*2;
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        }
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        if( source_pc < source_end ) {
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            uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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            fprintf( out, " %08X: %s  %s\n", source_pc, op, buf );
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            source_pc = source_pc2;
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        } else {
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            fprintf( out, "\n" );
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        }
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        target_pc = pc2;
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    }
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    while( source_pc < source_end ) {
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        uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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        fprintf( out, "%*c %08X: %s  %s\n", 72,' ', source_pc, op, buf );
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        source_pc = source_pc2;
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    }
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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   293
#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375
   294
nkeynes@991
   295
#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
nkeynes@991
   296
#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@375
   297
nkeynes@374
   298
nkeynes@991
   299
#define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991
   300
#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991
   301
#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   302
#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   303
#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   304
#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   305
#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   306
#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   307
#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991
   308
#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377
   309
nkeynes@991
   310
#ifdef ENABLE_SH4STATS
nkeynes@995
   311
#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991
   312
#else
nkeynes@991
   313
#define COUNT_INST(id)
nkeynes@991
   314
#endif
nkeynes@377
   315
nkeynes@374
   316
nkeynes@368
   317
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   318
nkeynes@416
   319
#define check_priv( ) \
nkeynes@937
   320
    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
nkeynes@937
   321
        if( sh4_x86.in_delay_slot ) { \
nkeynes@956
   322
            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
nkeynes@937
   323
        } else { \
nkeynes@956
   324
            exit_block_exc(EXC_ILLEGAL, pc); \
nkeynes@937
   325
        } \
nkeynes@956
   326
        sh4_x86.branch_taken = TRUE; \
nkeynes@937
   327
        sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@937
   328
        return 2; \
nkeynes@937
   329
    }
nkeynes@416
   330
nkeynes@416
   331
#define check_fpuen( ) \
nkeynes@416
   332
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   333
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995
   334
	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991
   335
	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416
   336
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   337
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   338
	} else {\
nkeynes@586
   339
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   340
	}\
nkeynes@875
   341
	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416
   342
    }
nkeynes@416
   343
nkeynes@586
   344
#define check_ralign16( x86reg ) \
nkeynes@991
   345
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   346
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   347
nkeynes@586
   348
#define check_walign16( x86reg ) \
nkeynes@991
   349
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   350
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   351
nkeynes@586
   352
#define check_ralign32( x86reg ) \
nkeynes@991
   353
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   354
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   355
nkeynes@586
   356
#define check_walign32( x86reg ) \
nkeynes@991
   357
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   358
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   359
nkeynes@732
   360
#define check_ralign64( x86reg ) \
nkeynes@991
   361
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   362
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732
   363
nkeynes@732
   364
#define check_walign64( x86reg ) \
nkeynes@991
   365
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   366
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732
   367
nkeynes@1004
   368
#define address_space() ((sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space)
nkeynes@1004
   369
nkeynes@824
   370
#define UNDEF(ir)
nkeynes@939
   371
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@939
   372
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@586
   373
 */
nkeynes@941
   374
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   375
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   376
{
nkeynes@1004
   377
    decode_address(address_space(), addr_reg);
nkeynes@995
   378
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   379
        CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   380
    } else {
nkeynes@995
   381
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   382
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   383
        }
nkeynes@995
   384
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   385
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   386
        CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   387
    }
nkeynes@995
   388
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   389
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   390
    }
nkeynes@995
   391
}
nkeynes@995
   392
nkeynes@995
   393
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   394
{
nkeynes@1004
   395
    decode_address(address_space(), addr_reg);
nkeynes@995
   396
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   397
        CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   398
    } else {
nkeynes@995
   399
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   400
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   401
	}        
nkeynes@995
   402
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   403
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   404
        }
nkeynes@995
   405
#if MAX_REG_ARG > 2        
nkeynes@995
   406
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   407
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   408
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   409
#else
nkeynes@995
   410
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   411
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   412
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   413
#endif
nkeynes@995
   414
    }
nkeynes@995
   415
}
nkeynes@995
   416
#else
nkeynes@995
   417
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   418
{
nkeynes@1004
   419
    decode_address(address_space(), addr_reg);
nkeynes@995
   420
    CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   421
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   422
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   423
    }
nkeynes@995
   424
}     
nkeynes@995
   425
nkeynes@996
   426
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   427
{
nkeynes@1004
   428
    decode_address(address_space(), addr_reg);
nkeynes@995
   429
    CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   430
}
nkeynes@941
   431
#endif
nkeynes@939
   432
                
nkeynes@995
   433
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   434
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   435
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   436
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   437
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   438
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   439
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   440
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   441
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@368
   442
nkeynes@956
   443
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@539
   444
nkeynes@901
   445
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   446
{
nkeynes@927
   447
    enter_block();
nkeynes@1004
   448
    MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
nkeynes@901
   449
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   450
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   451
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   452
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   453
    sh4_x86.block_start_pc = pc;
nkeynes@939
   454
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   455
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   456
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   457
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   458
}
nkeynes@901
   459
nkeynes@901
   460
nkeynes@593
   461
uint32_t sh4_translate_end_block_size()
nkeynes@593
   462
{
nkeynes@596
   463
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1008
   464
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*24);
nkeynes@596
   465
    } else {
nkeynes@1008
   466
        return EPILOGUE_SIZE + 72 + (sh4_x86.backpatch_posn-3)*27;
nkeynes@596
   467
    }
nkeynes@593
   468
}
nkeynes@593
   469
nkeynes@593
   470
nkeynes@590
   471
/**
nkeynes@590
   472
 * Embed a breakpoint into the generated code
nkeynes@590
   473
 */
nkeynes@586
   474
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   475
{
nkeynes@995
   476
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   477
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   479
}
nkeynes@590
   480
nkeynes@601
   481
nkeynes@601
   482
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   483
nkeynes@590
   484
/**
nkeynes@995
   485
 * Exit the block with sh4r.pc already written
nkeynes@995
   486
 */
nkeynes@995
   487
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   488
{
nkeynes@995
   489
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   490
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   491
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   492
    if( sh4_x86.tlb_on ) {
nkeynes@995
   493
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   494
    } else {
nkeynes@995
   495
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   496
    }
nkeynes@995
   497
    exit_block();
nkeynes@995
   498
}
nkeynes@995
   499
nkeynes@995
   500
/**
nkeynes@995
   501
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   502
 */
nkeynes@995
   503
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   504
{
nkeynes@995
   505
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   506
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   507
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   508
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@995
   509
    if( sh4_x86.tlb_on ) {
nkeynes@995
   510
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   511
    } else {
nkeynes@995
   512
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   513
    }
nkeynes@995
   514
    exit_block();
nkeynes@995
   515
}
nkeynes@995
   516
nkeynes@995
   517
nkeynes@995
   518
/**
nkeynes@995
   519
 * Exit the block to an absolute PC
nkeynes@995
   520
 */
nkeynes@995
   521
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   522
{
nkeynes@995
   523
    MOVL_imm32_r32( pc, REG_ECX );
nkeynes@995
   524
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   525
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   526
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   527
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   528
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   529
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   530
    } else {
nkeynes@995
   531
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   532
    }
nkeynes@995
   533
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   534
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   535
    exit_block();
nkeynes@995
   536
}
nkeynes@995
   537
nkeynes@995
   538
/**
nkeynes@995
   539
 * Exit the block to a relative PC
nkeynes@995
   540
 */
nkeynes@995
   541
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   542
{
nkeynes@995
   543
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   544
    ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@995
   545
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   546
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   547
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   548
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   549
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   550
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   551
    } else {
nkeynes@995
   552
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   553
    }
nkeynes@995
   554
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   555
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   556
    exit_block();
nkeynes@995
   557
}
nkeynes@995
   558
nkeynes@995
   559
/**
nkeynes@995
   560
 * Exit unconditionally with a general exception
nkeynes@995
   561
 */
nkeynes@995
   562
void exit_block_exc( int code, sh4addr_t pc )
nkeynes@995
   563
{
nkeynes@995
   564
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   565
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   566
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   567
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   568
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   569
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   570
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   571
    if( sh4_x86.tlb_on ) {
nkeynes@995
   572
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   573
    } else {
nkeynes@995
   574
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   575
    }
nkeynes@995
   576
nkeynes@995
   577
    exit_block();
nkeynes@995
   578
}    
nkeynes@995
   579
nkeynes@995
   580
/**
nkeynes@590
   581
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   582
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   583
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   584
 *
nkeynes@601
   585
 * Performs:
nkeynes@601
   586
 *   Set PC = endpc
nkeynes@601
   587
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   588
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   589
 *   Call sh4_execute_instruction
nkeynes@601
   590
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   591
 */
nkeynes@601
   592
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   593
{
nkeynes@995
   594
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   595
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   596
    
nkeynes@995
   597
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   598
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   599
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   600
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   601
nkeynes@995
   602
    CALL_ptr( sh4_execute_instruction );    
nkeynes@995
   603
    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@590
   604
    if( sh4_x86.tlb_on ) {
nkeynes@995
   605
	CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX);
nkeynes@590
   606
    } else {
nkeynes@995
   607
	CALL1_ptr_r32(xlat_get_code,REG_EAX);
nkeynes@590
   608
    }
nkeynes@926
   609
    exit_block();
nkeynes@590
   610
} 
nkeynes@539
   611
nkeynes@359
   612
/**
nkeynes@995
   613
 * Write the block trailer (exception handling block)
nkeynes@995
   614
 */
nkeynes@995
   615
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   616
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   617
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   618
        exit_block_rel( pc, pc );
nkeynes@995
   619
    }
nkeynes@995
   620
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   621
        unsigned int i;
nkeynes@995
   622
        // Exception raised - cleanup and exit
nkeynes@995
   623
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   624
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   625
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   626
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   627
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@995
   628
        MULL_r32( REG_EDX );
nkeynes@995
   629
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   630
        MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   631
        if( sh4_x86.tlb_on ) {
nkeynes@995
   632
            CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@995
   633
        } else {
nkeynes@995
   634
            CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@995
   635
        }
nkeynes@995
   636
        exit_block();
nkeynes@995
   637
nkeynes@995
   638
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   639
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   640
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   641
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   642
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   643
                } else {
nkeynes@995
   644
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   645
                }
nkeynes@995
   646
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   647
                int rel = end_ptr - xlat_output;
nkeynes@995
   648
                JMP_prerel(rel);
nkeynes@995
   649
            } else {
nkeynes@995
   650
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   651
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   652
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   653
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   654
                int rel = end_ptr - xlat_output;
nkeynes@995
   655
                JMP_prerel(rel);
nkeynes@995
   656
            }
nkeynes@995
   657
        }
nkeynes@995
   658
    }
nkeynes@995
   659
}
nkeynes@539
   660
nkeynes@359
   661
/**
nkeynes@359
   662
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   663
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   664
 * 
nkeynes@586
   665
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   666
 *
nkeynes@359
   667
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   668
 * (eg a branch or 
nkeynes@359
   669
 */
nkeynes@590
   670
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   671
{
nkeynes@388
   672
    uint32_t ir;
nkeynes@586
   673
    /* Read instruction from icache */
nkeynes@586
   674
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   675
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   676
    
nkeynes@586
   677
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   678
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   679
    }
nkeynes@1003
   680
    
nkeynes@1003
   681
    /* check for breakpoints at this pc */
nkeynes@1003
   682
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   683
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   684
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   685
            break;
nkeynes@1003
   686
        }
nkeynes@571
   687
    }
nkeynes@359
   688
%%
nkeynes@359
   689
/* ALU operations */
nkeynes@359
   690
ADD Rm, Rn {:
nkeynes@671
   691
    COUNT_INST(I_ADD);
nkeynes@991
   692
    load_reg( REG_EAX, Rm );
nkeynes@991
   693
    load_reg( REG_ECX, Rn );
nkeynes@991
   694
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   695
    store_reg( REG_ECX, Rn );
nkeynes@417
   696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   697
:}
nkeynes@359
   698
ADD #imm, Rn {:  
nkeynes@671
   699
    COUNT_INST(I_ADDI);
nkeynes@991
   700
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   702
:}
nkeynes@359
   703
ADDC Rm, Rn {:
nkeynes@671
   704
    COUNT_INST(I_ADDC);
nkeynes@417
   705
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   706
        LDC_t();
nkeynes@417
   707
    }
nkeynes@991
   708
    load_reg( REG_EAX, Rm );
nkeynes@991
   709
    load_reg( REG_ECX, Rn );
nkeynes@991
   710
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   711
    store_reg( REG_ECX, Rn );
nkeynes@359
   712
    SETC_t();
nkeynes@417
   713
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   714
:}
nkeynes@359
   715
ADDV Rm, Rn {:
nkeynes@671
   716
    COUNT_INST(I_ADDV);
nkeynes@991
   717
    load_reg( REG_EAX, Rm );
nkeynes@991
   718
    load_reg( REG_ECX, Rn );
nkeynes@991
   719
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   720
    store_reg( REG_ECX, Rn );
nkeynes@359
   721
    SETO_t();
nkeynes@417
   722
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   723
:}
nkeynes@359
   724
AND Rm, Rn {:
nkeynes@671
   725
    COUNT_INST(I_AND);
nkeynes@991
   726
    load_reg( REG_EAX, Rm );
nkeynes@991
   727
    load_reg( REG_ECX, Rn );
nkeynes@991
   728
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   729
    store_reg( REG_ECX, Rn );
nkeynes@417
   730
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   731
:}
nkeynes@359
   732
AND #imm, R0 {:  
nkeynes@671
   733
    COUNT_INST(I_ANDI);
nkeynes@991
   734
    load_reg( REG_EAX, 0 );
nkeynes@991
   735
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   736
    store_reg( REG_EAX, 0 );
nkeynes@417
   737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   738
:}
nkeynes@359
   739
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   740
    COUNT_INST(I_ANDB);
nkeynes@991
   741
    load_reg( REG_EAX, 0 );
nkeynes@991
   742
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   743
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   744
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   745
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   746
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   747
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   749
:}
nkeynes@359
   750
CMP/EQ Rm, Rn {:  
nkeynes@671
   751
    COUNT_INST(I_CMPEQ);
nkeynes@991
   752
    load_reg( REG_EAX, Rm );
nkeynes@991
   753
    load_reg( REG_ECX, Rn );
nkeynes@991
   754
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   755
    SETE_t();
nkeynes@417
   756
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   757
:}
nkeynes@359
   758
CMP/EQ #imm, R0 {:  
nkeynes@671
   759
    COUNT_INST(I_CMPEQI);
nkeynes@991
   760
    load_reg( REG_EAX, 0 );
nkeynes@991
   761
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   762
    SETE_t();
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   764
:}
nkeynes@359
   765
CMP/GE Rm, Rn {:  
nkeynes@671
   766
    COUNT_INST(I_CMPGE);
nkeynes@991
   767
    load_reg( REG_EAX, Rm );
nkeynes@991
   768
    load_reg( REG_ECX, Rn );
nkeynes@991
   769
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   770
    SETGE_t();
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   772
:}
nkeynes@359
   773
CMP/GT Rm, Rn {: 
nkeynes@671
   774
    COUNT_INST(I_CMPGT);
nkeynes@991
   775
    load_reg( REG_EAX, Rm );
nkeynes@991
   776
    load_reg( REG_ECX, Rn );
nkeynes@991
   777
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   778
    SETG_t();
nkeynes@417
   779
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   780
:}
nkeynes@359
   781
CMP/HI Rm, Rn {:  
nkeynes@671
   782
    COUNT_INST(I_CMPHI);
nkeynes@991
   783
    load_reg( REG_EAX, Rm );
nkeynes@991
   784
    load_reg( REG_ECX, Rn );
nkeynes@991
   785
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   786
    SETA_t();
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   788
:}
nkeynes@359
   789
CMP/HS Rm, Rn {: 
nkeynes@671
   790
    COUNT_INST(I_CMPHS);
nkeynes@991
   791
    load_reg( REG_EAX, Rm );
nkeynes@991
   792
    load_reg( REG_ECX, Rn );
nkeynes@991
   793
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   794
    SETAE_t();
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   796
 :}
nkeynes@359
   797
CMP/PL Rn {: 
nkeynes@671
   798
    COUNT_INST(I_CMPPL);
nkeynes@991
   799
    load_reg( REG_EAX, Rn );
nkeynes@991
   800
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   801
    SETG_t();
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   803
:}
nkeynes@359
   804
CMP/PZ Rn {:  
nkeynes@671
   805
    COUNT_INST(I_CMPPZ);
nkeynes@991
   806
    load_reg( REG_EAX, Rn );
nkeynes@991
   807
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   808
    SETGE_t();
nkeynes@417
   809
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   810
:}
nkeynes@361
   811
CMP/STR Rm, Rn {:  
nkeynes@671
   812
    COUNT_INST(I_CMPSTR);
nkeynes@991
   813
    load_reg( REG_EAX, Rm );
nkeynes@991
   814
    load_reg( REG_ECX, Rn );
nkeynes@991
   815
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   816
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   817
    JE_label(target1);
nkeynes@991
   818
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   819
    JE_label(target2);
nkeynes@991
   820
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   821
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   822
    JE_label(target3);
nkeynes@991
   823
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   824
    JMP_TARGET(target1);
nkeynes@380
   825
    JMP_TARGET(target2);
nkeynes@380
   826
    JMP_TARGET(target3);
nkeynes@368
   827
    SETE_t();
nkeynes@417
   828
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   829
:}
nkeynes@361
   830
DIV0S Rm, Rn {:
nkeynes@671
   831
    COUNT_INST(I_DIV0S);
nkeynes@991
   832
    load_reg( REG_EAX, Rm );
nkeynes@991
   833
    load_reg( REG_ECX, Rn );
nkeynes@991
   834
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   835
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
   836
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   837
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   838
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   839
    SETNE_t();
nkeynes@417
   840
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   841
:}
nkeynes@361
   842
DIV0U {:  
nkeynes@671
   843
    COUNT_INST(I_DIV0U);
nkeynes@991
   844
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
   845
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
   846
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   847
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   848
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   849
:}
nkeynes@386
   850
DIV1 Rm, Rn {:
nkeynes@671
   851
    COUNT_INST(I_DIV1);
nkeynes@995
   852
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
   853
    load_reg( REG_EAX, Rn );
nkeynes@417
   854
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   855
	LDC_t();
nkeynes@417
   856
    }
nkeynes@991
   857
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   858
    SETC_r8( REG_DL ); // Q'
nkeynes@991
   859
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
   860
    JE_label(mqequal);
nkeynes@991
   861
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
   862
    JMP_label(end);
nkeynes@380
   863
    JMP_TARGET(mqequal);
nkeynes@991
   864
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
   865
    JMP_TARGET(end);
nkeynes@991
   866
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
   867
    SETC_r8(REG_AL); // tmp1
nkeynes@991
   868
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
   869
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
   870
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   871
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
   872
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
   873
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   874
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   875
:}
nkeynes@361
   876
DMULS.L Rm, Rn {:  
nkeynes@671
   877
    COUNT_INST(I_DMULS);
nkeynes@991
   878
    load_reg( REG_EAX, Rm );
nkeynes@991
   879
    load_reg( REG_ECX, Rn );
nkeynes@991
   880
    IMULL_r32(REG_ECX);
nkeynes@995
   881
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   882
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   884
:}
nkeynes@361
   885
DMULU.L Rm, Rn {:  
nkeynes@671
   886
    COUNT_INST(I_DMULU);
nkeynes@991
   887
    load_reg( REG_EAX, Rm );
nkeynes@991
   888
    load_reg( REG_ECX, Rn );
nkeynes@991
   889
    MULL_r32(REG_ECX);
nkeynes@995
   890
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   891
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
   892
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   893
:}
nkeynes@359
   894
DT Rn {:  
nkeynes@671
   895
    COUNT_INST(I_DT);
nkeynes@991
   896
    load_reg( REG_EAX, Rn );
nkeynes@991
   897
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
   898
    store_reg( REG_EAX, Rn );
nkeynes@359
   899
    SETE_t();
nkeynes@417
   900
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   901
:}
nkeynes@359
   902
EXTS.B Rm, Rn {:  
nkeynes@671
   903
    COUNT_INST(I_EXTSB);
nkeynes@991
   904
    load_reg( REG_EAX, Rm );
nkeynes@991
   905
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   906
    store_reg( REG_EAX, Rn );
nkeynes@359
   907
:}
nkeynes@361
   908
EXTS.W Rm, Rn {:  
nkeynes@671
   909
    COUNT_INST(I_EXTSW);
nkeynes@991
   910
    load_reg( REG_EAX, Rm );
nkeynes@991
   911
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   912
    store_reg( REG_EAX, Rn );
nkeynes@361
   913
:}
nkeynes@361
   914
EXTU.B Rm, Rn {:  
nkeynes@671
   915
    COUNT_INST(I_EXTUB);
nkeynes@991
   916
    load_reg( REG_EAX, Rm );
nkeynes@991
   917
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   918
    store_reg( REG_EAX, Rn );
nkeynes@361
   919
:}
nkeynes@361
   920
EXTU.W Rm, Rn {:  
nkeynes@671
   921
    COUNT_INST(I_EXTUW);
nkeynes@991
   922
    load_reg( REG_EAX, Rm );
nkeynes@991
   923
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   924
    store_reg( REG_EAX, Rn );
nkeynes@361
   925
:}
nkeynes@586
   926
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   927
    COUNT_INST(I_MACL);
nkeynes@586
   928
    if( Rm == Rn ) {
nkeynes@991
   929
	load_reg( REG_EAX, Rm );
nkeynes@991
   930
	check_ralign32( REG_EAX );
nkeynes@991
   931
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   932
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   933
	load_reg( REG_EAX, Rm );
nkeynes@991
   934
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
   935
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   936
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   937
    } else {
nkeynes@991
   938
	load_reg( REG_EAX, Rm );
nkeynes@991
   939
	check_ralign32( REG_EAX );
nkeynes@991
   940
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   941
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   942
	load_reg( REG_EAX, Rn );
nkeynes@991
   943
	check_ralign32( REG_EAX );
nkeynes@991
   944
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   945
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
   946
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   947
    }
nkeynes@939
   948
    
nkeynes@991
   949
    IMULL_rspdisp( 0 );
nkeynes@991
   950
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
   951
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
   952
nkeynes@995
   953
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   954
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
   955
    JE_label( nosat );
nkeynes@995
   956
    CALL_ptr( signsat48 );
nkeynes@386
   957
    JMP_TARGET( nosat );
nkeynes@417
   958
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   959
:}
nkeynes@386
   960
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   961
    COUNT_INST(I_MACW);
nkeynes@586
   962
    if( Rm == Rn ) {
nkeynes@991
   963
	load_reg( REG_EAX, Rm );
nkeynes@991
   964
	check_ralign16( REG_EAX );
nkeynes@991
   965
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   966
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   967
	load_reg( REG_EAX, Rm );
nkeynes@991
   968
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
   969
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   970
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   971
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   972
	// adding a page-boundary check to skip the second translation
nkeynes@586
   973
    } else {
nkeynes@991
   974
	load_reg( REG_EAX, Rm );
nkeynes@991
   975
	check_ralign16( REG_EAX );
nkeynes@991
   976
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   977
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   978
	load_reg( REG_EAX, Rn );
nkeynes@991
   979
	check_ralign16( REG_EAX );
nkeynes@991
   980
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   981
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
   982
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   983
    }
nkeynes@991
   984
    IMULL_rspdisp( 0 );
nkeynes@995
   985
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   986
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
   987
    JE_label( nosat );
nkeynes@386
   988
nkeynes@991
   989
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   990
    JNO_label( end );            // 2
nkeynes@995
   991
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
   992
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
   993
    JS_label( positive );        // 2
nkeynes@995
   994
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
   995
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
   996
    JMP_label(end2);           // 2
nkeynes@386
   997
nkeynes@386
   998
    JMP_TARGET(positive);
nkeynes@995
   999
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
  1000
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1001
    JMP_label(end3);            // 2
nkeynes@386
  1002
nkeynes@386
  1003
    JMP_TARGET(nosat);
nkeynes@991
  1004
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1005
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
  1006
    JMP_TARGET(end);
nkeynes@386
  1007
    JMP_TARGET(end2);
nkeynes@386
  1008
    JMP_TARGET(end3);
nkeynes@417
  1009
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1010
:}
nkeynes@359
  1011
MOVT Rn {:  
nkeynes@671
  1012
    COUNT_INST(I_MOVT);
nkeynes@995
  1013
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
  1014
    store_reg( REG_EAX, Rn );
nkeynes@359
  1015
:}
nkeynes@361
  1016
MUL.L Rm, Rn {:  
nkeynes@671
  1017
    COUNT_INST(I_MULL);
nkeynes@991
  1018
    load_reg( REG_EAX, Rm );
nkeynes@991
  1019
    load_reg( REG_ECX, Rn );
nkeynes@991
  1020
    MULL_r32( REG_ECX );
nkeynes@995
  1021
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1023
:}
nkeynes@374
  1024
MULS.W Rm, Rn {:
nkeynes@671
  1025
    COUNT_INST(I_MULSW);
nkeynes@995
  1026
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1027
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1028
    MULL_r32( REG_ECX );
nkeynes@995
  1029
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1030
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1031
:}
nkeynes@374
  1032
MULU.W Rm, Rn {:  
nkeynes@671
  1033
    COUNT_INST(I_MULUW);
nkeynes@995
  1034
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1035
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1036
    MULL_r32( REG_ECX );
nkeynes@995
  1037
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1038
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1039
:}
nkeynes@359
  1040
NEG Rm, Rn {:
nkeynes@671
  1041
    COUNT_INST(I_NEG);
nkeynes@991
  1042
    load_reg( REG_EAX, Rm );
nkeynes@991
  1043
    NEGL_r32( REG_EAX );
nkeynes@991
  1044
    store_reg( REG_EAX, Rn );
nkeynes@417
  1045
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1046
:}
nkeynes@359
  1047
NEGC Rm, Rn {:  
nkeynes@671
  1048
    COUNT_INST(I_NEGC);
nkeynes@991
  1049
    load_reg( REG_EAX, Rm );
nkeynes@991
  1050
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
  1051
    LDC_t();
nkeynes@991
  1052
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1053
    store_reg( REG_ECX, Rn );
nkeynes@359
  1054
    SETC_t();
nkeynes@417
  1055
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1056
:}
nkeynes@359
  1057
NOT Rm, Rn {:  
nkeynes@671
  1058
    COUNT_INST(I_NOT);
nkeynes@991
  1059
    load_reg( REG_EAX, Rm );
nkeynes@991
  1060
    NOTL_r32( REG_EAX );
nkeynes@991
  1061
    store_reg( REG_EAX, Rn );
nkeynes@417
  1062
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1063
:}
nkeynes@359
  1064
OR Rm, Rn {:  
nkeynes@671
  1065
    COUNT_INST(I_OR);
nkeynes@991
  1066
    load_reg( REG_EAX, Rm );
nkeynes@991
  1067
    load_reg( REG_ECX, Rn );
nkeynes@991
  1068
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1069
    store_reg( REG_ECX, Rn );
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
:}
nkeynes@359
  1072
OR #imm, R0 {:
nkeynes@671
  1073
    COUNT_INST(I_ORI);
nkeynes@991
  1074
    load_reg( REG_EAX, 0 );
nkeynes@991
  1075
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1076
    store_reg( REG_EAX, 0 );
nkeynes@417
  1077
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1078
:}
nkeynes@374
  1079
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1080
    COUNT_INST(I_ORB);
nkeynes@991
  1081
    load_reg( REG_EAX, 0 );
nkeynes@991
  1082
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1083
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1084
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1085
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1086
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1087
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1088
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1089
:}
nkeynes@359
  1090
ROTCL Rn {:
nkeynes@671
  1091
    COUNT_INST(I_ROTCL);
nkeynes@991
  1092
    load_reg( REG_EAX, Rn );
nkeynes@417
  1093
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1094
	LDC_t();
nkeynes@417
  1095
    }
nkeynes@991
  1096
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1097
    store_reg( REG_EAX, Rn );
nkeynes@359
  1098
    SETC_t();
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1100
:}
nkeynes@359
  1101
ROTCR Rn {:  
nkeynes@671
  1102
    COUNT_INST(I_ROTCR);
nkeynes@991
  1103
    load_reg( REG_EAX, Rn );
nkeynes@417
  1104
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1105
	LDC_t();
nkeynes@417
  1106
    }
nkeynes@991
  1107
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1108
    store_reg( REG_EAX, Rn );
nkeynes@359
  1109
    SETC_t();
nkeynes@417
  1110
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1111
:}
nkeynes@359
  1112
ROTL Rn {:  
nkeynes@671
  1113
    COUNT_INST(I_ROTL);
nkeynes@991
  1114
    load_reg( REG_EAX, Rn );
nkeynes@991
  1115
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1116
    store_reg( REG_EAX, Rn );
nkeynes@359
  1117
    SETC_t();
nkeynes@417
  1118
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1119
:}
nkeynes@359
  1120
ROTR Rn {:  
nkeynes@671
  1121
    COUNT_INST(I_ROTR);
nkeynes@991
  1122
    load_reg( REG_EAX, Rn );
nkeynes@991
  1123
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1124
    store_reg( REG_EAX, Rn );
nkeynes@359
  1125
    SETC_t();
nkeynes@417
  1126
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1127
:}
nkeynes@359
  1128
SHAD Rm, Rn {:
nkeynes@671
  1129
    COUNT_INST(I_SHAD);
nkeynes@359
  1130
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1131
    load_reg( REG_EAX, Rn );
nkeynes@991
  1132
    load_reg( REG_ECX, Rm );
nkeynes@991
  1133
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1134
    JGE_label(doshl);
nkeynes@361
  1135
                    
nkeynes@991
  1136
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1137
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1138
    JE_label(emptysar);     // 2
nkeynes@991
  1139
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1140
    JMP_label(end);          // 2
nkeynes@386
  1141
nkeynes@386
  1142
    JMP_TARGET(emptysar);
nkeynes@991
  1143
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1144
    JMP_label(end2);
nkeynes@382
  1145
nkeynes@380
  1146
    JMP_TARGET(doshl);
nkeynes@991
  1147
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1148
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1149
    JMP_TARGET(end);
nkeynes@386
  1150
    JMP_TARGET(end2);
nkeynes@991
  1151
    store_reg( REG_EAX, Rn );
nkeynes@417
  1152
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
:}
nkeynes@359
  1154
SHLD Rm, Rn {:  
nkeynes@671
  1155
    COUNT_INST(I_SHLD);
nkeynes@991
  1156
    load_reg( REG_EAX, Rn );
nkeynes@991
  1157
    load_reg( REG_ECX, Rm );
nkeynes@991
  1158
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1159
    JGE_label(doshl);
nkeynes@368
  1160
nkeynes@991
  1161
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1162
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1163
    JE_label(emptyshr );
nkeynes@991
  1164
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1165
    JMP_label(end);          // 2
nkeynes@386
  1166
nkeynes@386
  1167
    JMP_TARGET(emptyshr);
nkeynes@991
  1168
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1169
    JMP_label(end2);
nkeynes@382
  1170
nkeynes@382
  1171
    JMP_TARGET(doshl);
nkeynes@991
  1172
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1173
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1174
    JMP_TARGET(end);
nkeynes@386
  1175
    JMP_TARGET(end2);
nkeynes@991
  1176
    store_reg( REG_EAX, Rn );
nkeynes@417
  1177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1178
:}
nkeynes@359
  1179
SHAL Rn {: 
nkeynes@671
  1180
    COUNT_INST(I_SHAL);
nkeynes@991
  1181
    load_reg( REG_EAX, Rn );
nkeynes@991
  1182
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1183
    SETC_t();
nkeynes@991
  1184
    store_reg( REG_EAX, Rn );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1186
:}
nkeynes@359
  1187
SHAR Rn {:  
nkeynes@671
  1188
    COUNT_INST(I_SHAR);
nkeynes@991
  1189
    load_reg( REG_EAX, Rn );
nkeynes@991
  1190
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1191
    SETC_t();
nkeynes@991
  1192
    store_reg( REG_EAX, Rn );
nkeynes@417
  1193
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1194
:}
nkeynes@359
  1195
SHLL Rn {:  
nkeynes@671
  1196
    COUNT_INST(I_SHLL);
nkeynes@991
  1197
    load_reg( REG_EAX, Rn );
nkeynes@991
  1198
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1199
    SETC_t();
nkeynes@991
  1200
    store_reg( REG_EAX, Rn );
nkeynes@417
  1201
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1202
:}
nkeynes@359
  1203
SHLL2 Rn {:
nkeynes@671
  1204
    COUNT_INST(I_SHLL);
nkeynes@991
  1205
    load_reg( REG_EAX, Rn );
nkeynes@991
  1206
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1207
    store_reg( REG_EAX, Rn );
nkeynes@417
  1208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1209
:}
nkeynes@359
  1210
SHLL8 Rn {:  
nkeynes@671
  1211
    COUNT_INST(I_SHLL);
nkeynes@991
  1212
    load_reg( REG_EAX, Rn );
nkeynes@991
  1213
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1214
    store_reg( REG_EAX, Rn );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1216
:}
nkeynes@359
  1217
SHLL16 Rn {:  
nkeynes@671
  1218
    COUNT_INST(I_SHLL);
nkeynes@991
  1219
    load_reg( REG_EAX, Rn );
nkeynes@991
  1220
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1221
    store_reg( REG_EAX, Rn );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@359
  1224
SHLR Rn {:  
nkeynes@671
  1225
    COUNT_INST(I_SHLR);
nkeynes@991
  1226
    load_reg( REG_EAX, Rn );
nkeynes@991
  1227
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1228
    SETC_t();
nkeynes@991
  1229
    store_reg( REG_EAX, Rn );
nkeynes@417
  1230
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1231
:}
nkeynes@359
  1232
SHLR2 Rn {:  
nkeynes@671
  1233
    COUNT_INST(I_SHLR);
nkeynes@991
  1234
    load_reg( REG_EAX, Rn );
nkeynes@991
  1235
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1236
    store_reg( REG_EAX, Rn );
nkeynes@417
  1237
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1238
:}
nkeynes@359
  1239
SHLR8 Rn {:  
nkeynes@671
  1240
    COUNT_INST(I_SHLR);
nkeynes@991
  1241
    load_reg( REG_EAX, Rn );
nkeynes@991
  1242
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1243
    store_reg( REG_EAX, Rn );
nkeynes@417
  1244
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1245
:}
nkeynes@359
  1246
SHLR16 Rn {:  
nkeynes@671
  1247
    COUNT_INST(I_SHLR);
nkeynes@991
  1248
    load_reg( REG_EAX, Rn );
nkeynes@991
  1249
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1250
    store_reg( REG_EAX, Rn );
nkeynes@417
  1251
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1252
:}
nkeynes@359
  1253
SUB Rm, Rn {:  
nkeynes@671
  1254
    COUNT_INST(I_SUB);
nkeynes@991
  1255
    load_reg( REG_EAX, Rm );
nkeynes@991
  1256
    load_reg( REG_ECX, Rn );
nkeynes@991
  1257
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1258
    store_reg( REG_ECX, Rn );
nkeynes@417
  1259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1260
:}
nkeynes@359
  1261
SUBC Rm, Rn {:  
nkeynes@671
  1262
    COUNT_INST(I_SUBC);
nkeynes@991
  1263
    load_reg( REG_EAX, Rm );
nkeynes@991
  1264
    load_reg( REG_ECX, Rn );
nkeynes@417
  1265
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1266
	LDC_t();
nkeynes@417
  1267
    }
nkeynes@991
  1268
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1269
    store_reg( REG_ECX, Rn );
nkeynes@394
  1270
    SETC_t();
nkeynes@417
  1271
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1272
:}
nkeynes@359
  1273
SUBV Rm, Rn {:  
nkeynes@671
  1274
    COUNT_INST(I_SUBV);
nkeynes@991
  1275
    load_reg( REG_EAX, Rm );
nkeynes@991
  1276
    load_reg( REG_ECX, Rn );
nkeynes@991
  1277
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1278
    store_reg( REG_ECX, Rn );
nkeynes@359
  1279
    SETO_t();
nkeynes@417
  1280
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1281
:}
nkeynes@359
  1282
SWAP.B Rm, Rn {:  
nkeynes@671
  1283
    COUNT_INST(I_SWAPB);
nkeynes@991
  1284
    load_reg( REG_EAX, Rm );
nkeynes@991
  1285
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1286
    store_reg( REG_EAX, Rn );
nkeynes@359
  1287
:}
nkeynes@359
  1288
SWAP.W Rm, Rn {:  
nkeynes@671
  1289
    COUNT_INST(I_SWAPB);
nkeynes@991
  1290
    load_reg( REG_EAX, Rm );
nkeynes@991
  1291
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1292
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1293
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1294
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1295
    store_reg( REG_ECX, Rn );
nkeynes@417
  1296
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1297
:}
nkeynes@361
  1298
TAS.B @Rn {:  
nkeynes@671
  1299
    COUNT_INST(I_TASB);
nkeynes@991
  1300
    load_reg( REG_EAX, Rn );
nkeynes@991
  1301
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1302
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1303
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1304
    SETE_t();
nkeynes@991
  1305
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1306
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1307
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1308
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1309
:}
nkeynes@361
  1310
TST Rm, Rn {:  
nkeynes@671
  1311
    COUNT_INST(I_TST);
nkeynes@991
  1312
    load_reg( REG_EAX, Rm );
nkeynes@991
  1313
    load_reg( REG_ECX, Rn );
nkeynes@991
  1314
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1315
    SETE_t();
nkeynes@417
  1316
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1317
:}
nkeynes@368
  1318
TST #imm, R0 {:  
nkeynes@671
  1319
    COUNT_INST(I_TSTI);
nkeynes@991
  1320
    load_reg( REG_EAX, 0 );
nkeynes@991
  1321
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1322
    SETE_t();
nkeynes@417
  1323
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1324
:}
nkeynes@368
  1325
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1326
    COUNT_INST(I_TSTB);
nkeynes@991
  1327
    load_reg( REG_EAX, 0);
nkeynes@991
  1328
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1329
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1330
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1331
    SETE_t();
nkeynes@417
  1332
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1333
:}
nkeynes@359
  1334
XOR Rm, Rn {:  
nkeynes@671
  1335
    COUNT_INST(I_XOR);
nkeynes@991
  1336
    load_reg( REG_EAX, Rm );
nkeynes@991
  1337
    load_reg( REG_ECX, Rn );
nkeynes@991
  1338
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1339
    store_reg( REG_ECX, Rn );
nkeynes@417
  1340
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1341
:}
nkeynes@359
  1342
XOR #imm, R0 {:  
nkeynes@671
  1343
    COUNT_INST(I_XORI);
nkeynes@991
  1344
    load_reg( REG_EAX, 0 );
nkeynes@991
  1345
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1346
    store_reg( REG_EAX, 0 );
nkeynes@417
  1347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1348
:}
nkeynes@359
  1349
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1350
    COUNT_INST(I_XORB);
nkeynes@991
  1351
    load_reg( REG_EAX, 0 );
nkeynes@991
  1352
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1353
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1354
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1355
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1356
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1357
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1359
:}
nkeynes@361
  1360
XTRCT Rm, Rn {:
nkeynes@671
  1361
    COUNT_INST(I_XTRCT);
nkeynes@991
  1362
    load_reg( REG_EAX, Rm );
nkeynes@991
  1363
    load_reg( REG_ECX, Rn );
nkeynes@991
  1364
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1365
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1366
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1367
    store_reg( REG_ECX, Rn );
nkeynes@417
  1368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1369
:}
nkeynes@359
  1370
nkeynes@359
  1371
/* Data move instructions */
nkeynes@359
  1372
MOV Rm, Rn {:  
nkeynes@671
  1373
    COUNT_INST(I_MOV);
nkeynes@991
  1374
    load_reg( REG_EAX, Rm );
nkeynes@991
  1375
    store_reg( REG_EAX, Rn );
nkeynes@359
  1376
:}
nkeynes@359
  1377
MOV #imm, Rn {:  
nkeynes@671
  1378
    COUNT_INST(I_MOVI);
nkeynes@995
  1379
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1380
    store_reg( REG_EAX, Rn );
nkeynes@359
  1381
:}
nkeynes@359
  1382
MOV.B Rm, @Rn {:  
nkeynes@671
  1383
    COUNT_INST(I_MOVB);
nkeynes@991
  1384
    load_reg( REG_EAX, Rn );
nkeynes@991
  1385
    load_reg( REG_EDX, Rm );
nkeynes@991
  1386
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1388
:}
nkeynes@359
  1389
MOV.B Rm, @-Rn {:  
nkeynes@671
  1390
    COUNT_INST(I_MOVB);
nkeynes@991
  1391
    load_reg( REG_EAX, Rn );
nkeynes@991
  1392
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1393
    load_reg( REG_EDX, Rm );
nkeynes@991
  1394
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1395
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1396
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1397
:}
nkeynes@359
  1398
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1399
    COUNT_INST(I_MOVB);
nkeynes@991
  1400
    load_reg( REG_EAX, 0 );
nkeynes@991
  1401
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1402
    load_reg( REG_EDX, Rm );
nkeynes@991
  1403
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1405
:}
nkeynes@359
  1406
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1407
    COUNT_INST(I_MOVB);
nkeynes@995
  1408
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1409
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1410
    load_reg( REG_EDX, 0 );
nkeynes@991
  1411
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1413
:}
nkeynes@359
  1414
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1415
    COUNT_INST(I_MOVB);
nkeynes@991
  1416
    load_reg( REG_EAX, Rn );
nkeynes@991
  1417
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1418
    load_reg( REG_EDX, 0 );
nkeynes@991
  1419
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1421
:}
nkeynes@359
  1422
MOV.B @Rm, Rn {:  
nkeynes@671
  1423
    COUNT_INST(I_MOVB);
nkeynes@991
  1424
    load_reg( REG_EAX, Rm );
nkeynes@991
  1425
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1426
    store_reg( REG_EAX, Rn );
nkeynes@417
  1427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1428
:}
nkeynes@359
  1429
MOV.B @Rm+, Rn {:  
nkeynes@671
  1430
    COUNT_INST(I_MOVB);
nkeynes@991
  1431
    load_reg( REG_EAX, Rm );
nkeynes@991
  1432
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@939
  1433
    if( Rm != Rn ) {
nkeynes@991
  1434
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1435
    }
nkeynes@991
  1436
    store_reg( REG_EAX, Rn );
nkeynes@417
  1437
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1438
:}
nkeynes@359
  1439
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1440
    COUNT_INST(I_MOVB);
nkeynes@991
  1441
    load_reg( REG_EAX, 0 );
nkeynes@991
  1442
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1443
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1444
    store_reg( REG_EAX, Rn );
nkeynes@417
  1445
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1446
:}
nkeynes@359
  1447
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1448
    COUNT_INST(I_MOVB);
nkeynes@995
  1449
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1450
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1451
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1452
    store_reg( REG_EAX, 0 );
nkeynes@417
  1453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1454
:}
nkeynes@359
  1455
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1456
    COUNT_INST(I_MOVB);
nkeynes@991
  1457
    load_reg( REG_EAX, Rm );
nkeynes@991
  1458
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1459
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1460
    store_reg( REG_EAX, 0 );
nkeynes@417
  1461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1462
:}
nkeynes@374
  1463
MOV.L Rm, @Rn {:
nkeynes@671
  1464
    COUNT_INST(I_MOVL);
nkeynes@991
  1465
    load_reg( REG_EAX, Rn );
nkeynes@991
  1466
    check_walign32(REG_EAX);
nkeynes@991
  1467
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1468
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1469
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1470
    JNE_label( notsq );
nkeynes@991
  1471
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1472
    load_reg( REG_EDX, Rm );
nkeynes@991
  1473
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1474
    JMP_label(end);
nkeynes@930
  1475
    JMP_TARGET(notsq);
nkeynes@991
  1476
    load_reg( REG_EDX, Rm );
nkeynes@991
  1477
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1478
    JMP_TARGET(end);
nkeynes@417
  1479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1480
:}
nkeynes@361
  1481
MOV.L Rm, @-Rn {:  
nkeynes@671
  1482
    COUNT_INST(I_MOVL);
nkeynes@991
  1483
    load_reg( REG_EAX, Rn );
nkeynes@991
  1484
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1485
    check_walign32( REG_EAX );
nkeynes@991
  1486
    load_reg( REG_EDX, Rm );
nkeynes@991
  1487
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1488
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1489
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1490
:}
nkeynes@361
  1491
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1492
    COUNT_INST(I_MOVL);
nkeynes@991
  1493
    load_reg( REG_EAX, 0 );
nkeynes@991
  1494
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1495
    check_walign32( REG_EAX );
nkeynes@991
  1496
    load_reg( REG_EDX, Rm );
nkeynes@991
  1497
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1499
:}
nkeynes@361
  1500
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1501
    COUNT_INST(I_MOVL);
nkeynes@995
  1502
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1503
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1504
    check_walign32( REG_EAX );
nkeynes@991
  1505
    load_reg( REG_EDX, 0 );
nkeynes@991
  1506
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1507
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1508
:}
nkeynes@361
  1509
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1510
    COUNT_INST(I_MOVL);
nkeynes@991
  1511
    load_reg( REG_EAX, Rn );
nkeynes@991
  1512
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1513
    check_walign32( REG_EAX );
nkeynes@991
  1514
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1515
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1516
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1517
    JNE_label( notsq );
nkeynes@991
  1518
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1519
    load_reg( REG_EDX, Rm );
nkeynes@991
  1520
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1521
    JMP_label(end);
nkeynes@930
  1522
    JMP_TARGET(notsq);
nkeynes@991
  1523
    load_reg( REG_EDX, Rm );
nkeynes@991
  1524
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1525
    JMP_TARGET(end);
nkeynes@417
  1526
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1527
:}
nkeynes@361
  1528
MOV.L @Rm, Rn {:  
nkeynes@671
  1529
    COUNT_INST(I_MOVL);
nkeynes@991
  1530
    load_reg( REG_EAX, Rm );
nkeynes@991
  1531
    check_ralign32( REG_EAX );
nkeynes@991
  1532
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1533
    store_reg( REG_EAX, Rn );
nkeynes@417
  1534
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1535
:}
nkeynes@361
  1536
MOV.L @Rm+, Rn {:  
nkeynes@671
  1537
    COUNT_INST(I_MOVL);
nkeynes@991
  1538
    load_reg( REG_EAX, Rm );
nkeynes@991
  1539
    check_ralign32( REG_EAX );
nkeynes@991
  1540
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@939
  1541
    if( Rm != Rn ) {
nkeynes@991
  1542
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1543
    }
nkeynes@991
  1544
    store_reg( REG_EAX, Rn );
nkeynes@417
  1545
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1546
:}
nkeynes@361
  1547
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1548
    COUNT_INST(I_MOVL);
nkeynes@991
  1549
    load_reg( REG_EAX, 0 );
nkeynes@991
  1550
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1551
    check_ralign32( REG_EAX );
nkeynes@991
  1552
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1553
    store_reg( REG_EAX, Rn );
nkeynes@417
  1554
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1555
:}
nkeynes@361
  1556
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1557
    COUNT_INST(I_MOVL);
nkeynes@995
  1558
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1559
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1560
    check_ralign32( REG_EAX );
nkeynes@991
  1561
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1562
    store_reg( REG_EAX, 0 );
nkeynes@417
  1563
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1564
:}
nkeynes@361
  1565
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1566
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1567
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1568
	SLOTILLEGAL();
nkeynes@374
  1569
    } else {
nkeynes@388
  1570
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1571
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1572
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1573
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1574
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1575
nkeynes@586
  1576
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1577
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1578
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1579
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1580
	    // behaviour though.
nkeynes@586
  1581
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1582
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1583
	} else {
nkeynes@586
  1584
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1585
	    // different virtual address than the translation was done with,
nkeynes@586
  1586
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1587
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1588
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1589
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1590
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1591
	}
nkeynes@991
  1592
	store_reg( REG_EAX, Rn );
nkeynes@374
  1593
    }
nkeynes@361
  1594
:}
nkeynes@361
  1595
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1596
    COUNT_INST(I_MOVL);
nkeynes@991
  1597
    load_reg( REG_EAX, Rm );
nkeynes@991
  1598
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1599
    check_ralign32( REG_EAX );
nkeynes@991
  1600
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1601
    store_reg( REG_EAX, Rn );
nkeynes@417
  1602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1603
:}
nkeynes@361
  1604
MOV.W Rm, @Rn {:  
nkeynes@671
  1605
    COUNT_INST(I_MOVW);
nkeynes@991
  1606
    load_reg( REG_EAX, Rn );
nkeynes@991
  1607
    check_walign16( REG_EAX );
nkeynes@991
  1608
    load_reg( REG_EDX, Rm );
nkeynes@991
  1609
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1610
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1611
:}
nkeynes@361
  1612
MOV.W Rm, @-Rn {:  
nkeynes@671
  1613
    COUNT_INST(I_MOVW);
nkeynes@991
  1614
    load_reg( REG_EAX, Rn );
nkeynes@991
  1615
    check_walign16( REG_EAX );
nkeynes@991
  1616
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1617
    load_reg( REG_EDX, Rm );
nkeynes@991
  1618
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1619
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1620
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1621
:}
nkeynes@361
  1622
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1623
    COUNT_INST(I_MOVW);
nkeynes@991
  1624
    load_reg( REG_EAX, 0 );
nkeynes@991
  1625
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1626
    check_walign16( REG_EAX );
nkeynes@991
  1627
    load_reg( REG_EDX, Rm );
nkeynes@991
  1628
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1630
:}
nkeynes@361
  1631
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1632
    COUNT_INST(I_MOVW);
nkeynes@995
  1633
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1634
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1635
    check_walign16( REG_EAX );
nkeynes@991
  1636
    load_reg( REG_EDX, 0 );
nkeynes@991
  1637
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1638
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1639
:}
nkeynes@361
  1640
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1641
    COUNT_INST(I_MOVW);
nkeynes@991
  1642
    load_reg( REG_EAX, Rn );
nkeynes@991
  1643
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1644
    check_walign16( REG_EAX );
nkeynes@991
  1645
    load_reg( REG_EDX, 0 );
nkeynes@991
  1646
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1647
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1648
:}
nkeynes@361
  1649
MOV.W @Rm, Rn {:  
nkeynes@671
  1650
    COUNT_INST(I_MOVW);
nkeynes@991
  1651
    load_reg( REG_EAX, Rm );
nkeynes@991
  1652
    check_ralign16( REG_EAX );
nkeynes@991
  1653
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1654
    store_reg( REG_EAX, Rn );
nkeynes@417
  1655
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1656
:}
nkeynes@361
  1657
MOV.W @Rm+, Rn {:  
nkeynes@671
  1658
    COUNT_INST(I_MOVW);
nkeynes@991
  1659
    load_reg( REG_EAX, Rm );
nkeynes@991
  1660
    check_ralign16( REG_EAX );
nkeynes@991
  1661
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@939
  1662
    if( Rm != Rn ) {
nkeynes@991
  1663
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1664
    }
nkeynes@991
  1665
    store_reg( REG_EAX, Rn );
nkeynes@417
  1666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1667
:}
nkeynes@361
  1668
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1669
    COUNT_INST(I_MOVW);
nkeynes@991
  1670
    load_reg( REG_EAX, 0 );
nkeynes@991
  1671
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1672
    check_ralign16( REG_EAX );
nkeynes@991
  1673
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1674
    store_reg( REG_EAX, Rn );
nkeynes@417
  1675
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1676
:}
nkeynes@361
  1677
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1678
    COUNT_INST(I_MOVW);
nkeynes@995
  1679
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1680
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1681
    check_ralign16( REG_EAX );
nkeynes@991
  1682
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1683
    store_reg( REG_EAX, 0 );
nkeynes@417
  1684
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1685
:}
nkeynes@361
  1686
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1687
    COUNT_INST(I_MOVW);
nkeynes@374
  1688
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1689
	SLOTILLEGAL();
nkeynes@374
  1690
    } else {
nkeynes@586
  1691
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1692
	uint32_t target = pc + disp + 4;
nkeynes@586
  1693
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1694
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1695
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1696
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1697
	} else {
nkeynes@995
  1698
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1699
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1700
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1701
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1702
	}
nkeynes@991
  1703
	store_reg( REG_EAX, Rn );
nkeynes@374
  1704
    }
nkeynes@361
  1705
:}
nkeynes@361
  1706
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1707
    COUNT_INST(I_MOVW);
nkeynes@991
  1708
    load_reg( REG_EAX, Rm );
nkeynes@991
  1709
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1710
    check_ralign16( REG_EAX );
nkeynes@991
  1711
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1712
    store_reg( REG_EAX, 0 );
nkeynes@417
  1713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1714
:}
nkeynes@361
  1715
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1716
    COUNT_INST(I_MOVA);
nkeynes@374
  1717
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1718
	SLOTILLEGAL();
nkeynes@374
  1719
    } else {
nkeynes@995
  1720
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1721
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1722
	store_reg( REG_ECX, 0 );
nkeynes@586
  1723
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1724
    }
nkeynes@361
  1725
:}
nkeynes@361
  1726
MOVCA.L R0, @Rn {:  
nkeynes@671
  1727
    COUNT_INST(I_MOVCA);
nkeynes@991
  1728
    load_reg( REG_EAX, Rn );
nkeynes@991
  1729
    check_walign32( REG_EAX );
nkeynes@991
  1730
    load_reg( REG_EDX, 0 );
nkeynes@991
  1731
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1732
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1733
:}
nkeynes@359
  1734
nkeynes@359
  1735
/* Control transfer instructions */
nkeynes@374
  1736
BF disp {:
nkeynes@671
  1737
    COUNT_INST(I_BF);
nkeynes@374
  1738
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1739
	SLOTILLEGAL();
nkeynes@374
  1740
    } else {
nkeynes@586
  1741
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1742
	JT_label( nottaken );
nkeynes@586
  1743
	exit_block_rel(target, pc+2 );
nkeynes@380
  1744
	JMP_TARGET(nottaken);
nkeynes@408
  1745
	return 2;
nkeynes@374
  1746
    }
nkeynes@374
  1747
:}
nkeynes@374
  1748
BF/S disp {:
nkeynes@671
  1749
    COUNT_INST(I_BFS);
nkeynes@374
  1750
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1751
	SLOTILLEGAL();
nkeynes@374
  1752
    } else {
nkeynes@590
  1753
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1754
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1755
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1756
	    JT_label(nottaken);
nkeynes@991
  1757
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1758
	    JMP_TARGET(nottaken);
nkeynes@991
  1759
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1760
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1761
	    exit_block_emu(pc+2);
nkeynes@601
  1762
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1763
	    return 2;
nkeynes@601
  1764
	} else {
nkeynes@601
  1765
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1766
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1767
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1768
	    }
nkeynes@601
  1769
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1770
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1771
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1772
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1773
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1774
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1775
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1776
	    
nkeynes@601
  1777
	    // not taken
nkeynes@601
  1778
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1779
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1780
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1781
	    return 4;
nkeynes@417
  1782
	}
nkeynes@374
  1783
    }
nkeynes@374
  1784
:}
nkeynes@374
  1785
BRA disp {:  
nkeynes@671
  1786
    COUNT_INST(I_BRA);
nkeynes@374
  1787
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1788
	SLOTILLEGAL();
nkeynes@374
  1789
    } else {
nkeynes@590
  1790
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1791
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1792
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1793
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1794
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1795
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1796
	    exit_block_emu(pc+2);
nkeynes@601
  1797
	    return 2;
nkeynes@601
  1798
	} else {
nkeynes@601
  1799
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1800
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1801
	    return 4;
nkeynes@601
  1802
	}
nkeynes@374
  1803
    }
nkeynes@374
  1804
:}
nkeynes@374
  1805
BRAF Rn {:  
nkeynes@671
  1806
    COUNT_INST(I_BRAF);
nkeynes@374
  1807
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1808
	SLOTILLEGAL();
nkeynes@374
  1809
    } else {
nkeynes@995
  1810
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1811
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1812
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1813
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1814
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1815
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1816
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1817
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1818
	    exit_block_emu(pc+2);
nkeynes@601
  1819
	    return 2;
nkeynes@601
  1820
	} else {
nkeynes@601
  1821
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1822
	    exit_block_newpcset(pc+4);
nkeynes@601
  1823
	    return 4;
nkeynes@601
  1824
	}
nkeynes@374
  1825
    }
nkeynes@374
  1826
:}
nkeynes@374
  1827
BSR disp {:  
nkeynes@671
  1828
    COUNT_INST(I_BSR);
nkeynes@374
  1829
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1830
	SLOTILLEGAL();
nkeynes@374
  1831
    } else {
nkeynes@995
  1832
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1833
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1834
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  1835
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1836
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1837
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1838
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1839
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  1840
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1841
	    exit_block_emu(pc+2);
nkeynes@601
  1842
	    return 2;
nkeynes@601
  1843
	} else {
nkeynes@601
  1844
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1845
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1846
	    return 4;
nkeynes@601
  1847
	}
nkeynes@374
  1848
    }
nkeynes@374
  1849
:}
nkeynes@374
  1850
BSRF Rn {:  
nkeynes@671
  1851
    COUNT_INST(I_BSRF);
nkeynes@374
  1852
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1853
	SLOTILLEGAL();
nkeynes@374
  1854
    } else {
nkeynes@995
  1855
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1856
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1857
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1858
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1859
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1860
nkeynes@601
  1861
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1862
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1863
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1864
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1865
	    exit_block_emu(pc+2);
nkeynes@601
  1866
	    return 2;
nkeynes@601
  1867
	} else {
nkeynes@601
  1868
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1869
	    exit_block_newpcset(pc+4);
nkeynes@601
  1870
	    return 4;
nkeynes@601
  1871
	}
nkeynes@374
  1872
    }
nkeynes@374
  1873
:}
nkeynes@374
  1874
BT disp {:
nkeynes@671
  1875
    COUNT_INST(I_BT);
nkeynes@374
  1876
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1877
	SLOTILLEGAL();
nkeynes@374
  1878
    } else {
nkeynes@586
  1879
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1880
	JF_label( nottaken );
nkeynes@586
  1881
	exit_block_rel(target, pc+2 );
nkeynes@380
  1882
	JMP_TARGET(nottaken);
nkeynes@408
  1883
	return 2;
nkeynes@374
  1884
    }
nkeynes@374
  1885
:}
nkeynes@374
  1886
BT/S disp {:
nkeynes@671
  1887
    COUNT_INST(I_BTS);
nkeynes@374
  1888
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1889
	SLOTILLEGAL();
nkeynes@374
  1890
    } else {
nkeynes@590
  1891
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1892
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1893
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1894
	    JF_label(nottaken);
nkeynes@991
  1895
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1896
	    JMP_TARGET(nottaken);
nkeynes@991
  1897
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1898
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1899
	    exit_block_emu(pc+2);
nkeynes@601
  1900
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1901
	    return 2;
nkeynes@601
  1902
	} else {
nkeynes@601
  1903
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1904
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1905
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1906
	    }
nkeynes@991
  1907
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  1908
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  1909
nkeynes@879
  1910
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1911
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1912
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1913
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1914
	    // not taken
nkeynes@601
  1915
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1916
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1917
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1918
	    return 4;
nkeynes@417
  1919
	}
nkeynes@374
  1920
    }
nkeynes@374
  1921
:}
nkeynes@374
  1922
JMP @Rn {:  
nkeynes@671
  1923
    COUNT_INST(I_JMP);
nkeynes@374
  1924
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1925
	SLOTILLEGAL();
nkeynes@374
  1926
    } else {
nkeynes@991
  1927
	load_reg( REG_ECX, Rn );
nkeynes@995
  1928
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1929
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1930
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1931
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1932
	    exit_block_emu(pc+2);
nkeynes@601
  1933
	    return 2;
nkeynes@601
  1934
	} else {
nkeynes@601
  1935
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1936
	    exit_block_newpcset(pc+4);
nkeynes@601
  1937
	    return 4;
nkeynes@601
  1938
	}
nkeynes@374
  1939
    }
nkeynes@374
  1940
:}
nkeynes@374
  1941
JSR @Rn {:  
nkeynes@671
  1942
    COUNT_INST(I_JSR);
nkeynes@374
  1943
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1944
	SLOTILLEGAL();
nkeynes@374
  1945
    } else {
nkeynes@995
  1946
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1947
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1948
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1949
	load_reg( REG_ECX, Rn );
nkeynes@995
  1950
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  1951
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1952
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1953
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1954
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1955
	    exit_block_emu(pc+2);
nkeynes@601
  1956
	    return 2;
nkeynes@601
  1957
	} else {
nkeynes@601
  1958
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1959
	    exit_block_newpcset(pc+4);
nkeynes@601
  1960
	    return 4;
nkeynes@601
  1961
	}
nkeynes@374
  1962
    }
nkeynes@374
  1963
:}
nkeynes@374
  1964
RTE {:  
nkeynes@671
  1965
    COUNT_INST(I_RTE);
nkeynes@374
  1966
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1967
	SLOTILLEGAL();
nkeynes@374
  1968
    } else {
nkeynes@408
  1969
	check_priv();
nkeynes@995
  1970
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  1971
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  1972
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  1973
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  1974
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1975
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1976
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1977
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1978
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1979
	    exit_block_emu(pc+2);
nkeynes@601
  1980
	    return 2;
nkeynes@601
  1981
	} else {
nkeynes@601
  1982
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1983
	    exit_block_newpcset(pc+4);
nkeynes@601
  1984
	    return 4;
nkeynes@601
  1985
	}
nkeynes@374
  1986
    }
nkeynes@374
  1987
:}
nkeynes@374
  1988
RTS {:  
nkeynes@671
  1989
    COUNT_INST(I_RTS);
nkeynes@374
  1990
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1991
	SLOTILLEGAL();
nkeynes@374
  1992
    } else {
nkeynes@995
  1993
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  1994
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1995
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1996
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1997
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1998
	    exit_block_emu(pc+2);
nkeynes@601
  1999
	    return 2;
nkeynes@601
  2000
	} else {
nkeynes@601
  2001
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2002
	    exit_block_newpcset(pc+4);
nkeynes@601
  2003
	    return 4;
nkeynes@601
  2004
	}
nkeynes@374
  2005
    }
nkeynes@374
  2006
:}
nkeynes@374
  2007
TRAPA #imm {:  
nkeynes@671
  2008
    COUNT_INST(I_TRAPA);
nkeynes@374
  2009
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2010
	SLOTILLEGAL();
nkeynes@374
  2011
    } else {
nkeynes@995
  2012
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  2013
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  2014
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  2015
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  2016
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  2017
	exit_block_pcset(pc+2);
nkeynes@409
  2018
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2019
	return 2;
nkeynes@374
  2020
    }
nkeynes@374
  2021
:}
nkeynes@374
  2022
UNDEF {:  
nkeynes@671
  2023
    COUNT_INST(I_UNDEF);
nkeynes@374
  2024
    if( sh4_x86.in_delay_slot ) {
nkeynes@956
  2025
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
nkeynes@374
  2026
    } else {
nkeynes@956
  2027
	exit_block_exc(EXC_ILLEGAL, pc);    
nkeynes@408
  2028
	return 2;
nkeynes@374
  2029
    }
nkeynes@368
  2030
:}
nkeynes@374
  2031
nkeynes@374
  2032
CLRMAC {:  
nkeynes@671
  2033
    COUNT_INST(I_CLRMAC);
nkeynes@991
  2034
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  2035
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  2036
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2037
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2038
:}
nkeynes@374
  2039
CLRS {:
nkeynes@671
  2040
    COUNT_INST(I_CLRS);
nkeynes@374
  2041
    CLC();
nkeynes@991
  2042
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2043
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2044
:}
nkeynes@374
  2045
CLRT {:  
nkeynes@671
  2046
    COUNT_INST(I_CLRT);
nkeynes@374
  2047
    CLC();
nkeynes@374
  2048
    SETC_t();
nkeynes@417
  2049
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2050
:}
nkeynes@374
  2051
SETS {:  
nkeynes@671
  2052
    COUNT_INST(I_SETS);
nkeynes@374
  2053
    STC();
nkeynes@991
  2054
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2055
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2056
:}
nkeynes@374
  2057
SETT {:  
nkeynes@671
  2058
    COUNT_INST(I_SETT);
nkeynes@374
  2059
    STC();
nkeynes@374
  2060
    SETC_t();
nkeynes@417
  2061
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  2062
:}
nkeynes@359
  2063
nkeynes@375
  2064
/* Floating point moves */
nkeynes@375
  2065
FMOV FRm, FRn {:  
nkeynes@671
  2066
    COUNT_INST(I_FMOV1);
nkeynes@377
  2067
    check_fpuen();
nkeynes@901
  2068
    if( sh4_x86.double_size ) {
nkeynes@991
  2069
        load_dr0( REG_EAX, FRm );
nkeynes@991
  2070
        load_dr1( REG_ECX, FRm );
nkeynes@991
  2071
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2072
        store_dr1( REG_ECX, FRn );
nkeynes@901
  2073
    } else {
nkeynes@991
  2074
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  2075
        store_fr( REG_EAX, FRn );
nkeynes@901
  2076
    }
nkeynes@375
  2077
:}
nkeynes@416
  2078
FMOV FRm, @Rn {: 
nkeynes@671
  2079
    COUNT_INST(I_FMOV2);
nkeynes@586
  2080
    check_fpuen();
nkeynes@991
  2081
    load_reg( REG_EAX, Rn );
nkeynes@901
  2082
    if( sh4_x86.double_size ) {
nkeynes@991
  2083
        check_walign64( REG_EAX );
nkeynes@991
  2084
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2085
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2086
        load_reg( REG_EAX, Rn );
nkeynes@991
  2087
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2088
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2089
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2090
    } else {
nkeynes@991
  2091
        check_walign32( REG_EAX );
nkeynes@991
  2092
        load_fr( REG_EDX, FRm );
nkeynes@991
  2093
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2094
    }
nkeynes@417
  2095
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2096
:}
nkeynes@375
  2097
FMOV @Rm, FRn {:  
nkeynes@671
  2098
    COUNT_INST(I_FMOV5);
nkeynes@586
  2099
    check_fpuen();
nkeynes@991
  2100
    load_reg( REG_EAX, Rm );
nkeynes@901
  2101
    if( sh4_x86.double_size ) {
nkeynes@991
  2102
        check_ralign64( REG_EAX );
nkeynes@991
  2103
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2104
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2105
        load_reg( REG_EAX, Rm );
nkeynes@991
  2106
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2107
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2108
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2109
    } else {
nkeynes@991
  2110
        check_ralign32( REG_EAX );
nkeynes@991
  2111
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2112
        store_fr( REG_EAX, FRn );
nkeynes@901
  2113
    }
nkeynes@417
  2114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2115
:}
nkeynes@377
  2116
FMOV FRm, @-Rn {:  
nkeynes@671
  2117
    COUNT_INST(I_FMOV3);
nkeynes@586
  2118
    check_fpuen();
nkeynes@991
  2119
    load_reg( REG_EAX, Rn );
nkeynes@901
  2120
    if( sh4_x86.double_size ) {
nkeynes@991
  2121
        check_walign64( REG_EAX );
nkeynes@991
  2122
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2123
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2124
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2125
        load_reg( REG_EAX, Rn );
nkeynes@991
  2126
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2127
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2128
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2129
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2130
    } else {
nkeynes@991
  2131
        check_walign32( REG_EAX );
nkeynes@991
  2132
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2133
        load_fr( REG_EDX, FRm );
nkeynes@991
  2134
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2135
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2136
    }
nkeynes@417
  2137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2138
:}
nkeynes@416
  2139
FMOV @Rm+, FRn {:
nkeynes@671
  2140
    COUNT_INST(I_FMOV6);
nkeynes@586
  2141
    check_fpuen();
nkeynes@991
  2142
    load_reg( REG_EAX, Rm );
nkeynes@901
  2143
    if( sh4_x86.double_size ) {
nkeynes@991
  2144
        check_ralign64( REG_EAX );
nkeynes@991
  2145
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2146
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2147
        load_reg( REG_EAX, Rm );
nkeynes@991
  2148
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2149
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2150
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2151
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2152
    } else {
nkeynes@991
  2153
        check_ralign32( REG_EAX );
nkeynes@991
  2154
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2155
        store_fr( REG_EAX, FRn );
nkeynes@991
  2156
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2157
    }
nkeynes@417
  2158
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2159
:}
nkeynes@377
  2160
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2161
    COUNT_INST(I_FMOV4);
nkeynes@586
  2162
    check_fpuen();
nkeynes@991
  2163
    load_reg( REG_EAX, Rn );
nkeynes@991
  2164
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2165
    if( sh4_x86.double_size ) {
nkeynes@991
  2166
        check_walign64( REG_EAX );
nkeynes@991
  2167
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2168
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2169
        load_reg( REG_EAX, Rn );
nkeynes@991
  2170
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2171
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2172
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2173
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2174
    } else {
nkeynes@991
  2175
        check_walign32( REG_EAX );
nkeynes@991
  2176
        load_fr( REG_EDX, FRm );
nkeynes@991
  2177
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2178
    }
nkeynes@417
  2179
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2180
:}
nkeynes@377
  2181
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2182
    COUNT_INST(I_FMOV7);
nkeynes@586
  2183
    check_fpuen();
nkeynes@991
  2184
    load_reg( REG_EAX, Rm );
nkeynes@991
  2185
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2186
    if( sh4_x86.double_size ) {
nkeynes@991
  2187
        check_ralign64( REG_EAX );
nkeynes@991
  2188
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2189
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2190
        load_reg( REG_EAX, Rm );
nkeynes@991
  2191
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2192
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2193
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2194
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2195
    } else {
nkeynes@991
  2196
        check_ralign32( REG_EAX );
nkeynes@991
  2197
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2198
        store_fr( REG_EAX, FRn );
nkeynes@901
  2199
    }
nkeynes@417
  2200
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2201
:}
nkeynes@377
  2202
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2203
    COUNT_INST(I_FLDI0);
nkeynes@377
  2204
    check_fpuen();
nkeynes@901
  2205
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2206
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2207
        store_fr( REG_EAX, FRn );
nkeynes@901
  2208
    }
nkeynes@417
  2209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2210
:}
nkeynes@377
  2211
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2212
    COUNT_INST(I_FLDI1);
nkeynes@377
  2213
    check_fpuen();
nkeynes@901
  2214
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2215
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2216
        store_fr( REG_EAX, FRn );
nkeynes@901
  2217
    }
nkeynes@377
  2218
:}
nkeynes@377
  2219
nkeynes@377
  2220
FLOAT FPUL, FRn {:  
nkeynes@671
  2221
    COUNT_INST(I_FLOAT);
nkeynes@377
  2222
    check_fpuen();
nkeynes@991
  2223
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2224
    if( sh4_x86.double_prec ) {
nkeynes@901
  2225
        pop_dr( FRn );
nkeynes@901
  2226
    } else {
nkeynes@901
  2227
        pop_fr( FRn );
nkeynes@901
  2228
    }
nkeynes@377
  2229
:}
nkeynes@377
  2230
FTRC FRm, FPUL {:  
nkeynes@671
  2231
    COUNT_INST(I_FTRC);
nkeynes@377
  2232
    check_fpuen();
nkeynes@901
  2233
    if( sh4_x86.double_prec ) {
nkeynes@901
  2234
        push_dr( FRm );
nkeynes@901
  2235
    } else {
nkeynes@901
  2236
        push_fr( FRm );
nkeynes@901
  2237
    }
nkeynes@995
  2238
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2239
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2240
    FCOMIP_st(1);
nkeynes@991
  2241
    JNA_label( sat );
nkeynes@995
  2242
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@995
  2243
    FILD_r32disp( REG_ECX, 0 );
nkeynes@995
  2244
    FCOMIP_st(1);              
nkeynes@995
  2245
    JAE_label( sat2 );            
nkeynes@995
  2246
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2247
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2248
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2249
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2250
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2251
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2252
    JMP_label(end);             
nkeynes@388
  2253
nkeynes@388
  2254
    JMP_TARGET(sat);
nkeynes@388
  2255
    JMP_TARGET(sat2);
nkeynes@991
  2256
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2257
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2258
    FPOP_st();
nkeynes@388
  2259
    JMP_TARGET(end);
nkeynes@417
  2260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2261
:}
nkeynes@377
  2262
FLDS FRm, FPUL {:  
nkeynes@671
  2263
    COUNT_INST(I_FLDS);
nkeynes@377
  2264
    check_fpuen();
nkeynes@991
  2265
    load_fr( REG_EAX, FRm );
nkeynes@995
  2266
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2267
:}
nkeynes@377
  2268
FSTS FPUL, FRn {:  
nkeynes@671
  2269
    COUNT_INST(I_FSTS);
nkeynes@377
  2270
    check_fpuen();
nkeynes@995
  2271
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2272
    store_fr( REG_EAX, FRn );
nkeynes@377
  2273
:}
nkeynes@377
  2274
FCNVDS FRm, FPUL {:  
nkeynes@671
  2275
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2276
    check_fpuen();
nkeynes@901
  2277
    if( sh4_x86.double_prec ) {
nkeynes@901
  2278
        push_dr( FRm );
nkeynes@901
  2279
        pop_fpul();
nkeynes@901
  2280
    }
nkeynes@377
  2281
:}
nkeynes@377
  2282
FCNVSD FPUL, FRn {:  
nkeynes@671
  2283
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2284
    check_fpuen();
nkeynes@901
  2285
    if( sh4_x86.double_prec ) {
nkeynes@901
  2286
        push_fpul();
nkeynes@901
  2287
        pop_dr( FRn );
nkeynes@901
  2288
    }
nkeynes@377
  2289
:}
nkeynes@375
  2290
nkeynes@359
  2291
/* Floating point instructions */
nkeynes@374
  2292
FABS FRn {:  
nkeynes@671
  2293
    COUNT_INST(I_FABS);
nkeynes@377
  2294
    check_fpuen();
nkeynes@901
  2295
    if( sh4_x86.double_prec ) {
nkeynes@901
  2296
        push_dr(FRn);
nkeynes@901
  2297
        FABS_st0();
nkeynes@901
  2298
        pop_dr(FRn);
nkeynes@901
  2299
    } else {
nkeynes@901
  2300
        push_fr(FRn);
nkeynes@901
  2301
        FABS_st0();
nkeynes@901
  2302
        pop_fr(FRn);
nkeynes@901
  2303
    }
nkeynes@374
  2304
:}
nkeynes@377
  2305
FADD FRm, FRn {:  
nkeynes@671
  2306
    COUNT_INST(I_FADD);
nkeynes@377
  2307
    check_fpuen();
nkeynes@901
  2308
    if( sh4_x86.double_prec ) {
nkeynes@901
  2309
        push_dr(FRm);
nkeynes@901
  2310
        push_dr(FRn);
nkeynes@901
  2311
        FADDP_st(1);
nkeynes@901
  2312
        pop_dr(FRn);
nkeynes@901
  2313
    } else {
nkeynes@901
  2314
        push_fr(FRm);
nkeynes@901
  2315
        push_fr(FRn);
nkeynes@901
  2316
        FADDP_st(1);
nkeynes@901
  2317
        pop_fr(FRn);
nkeynes@901
  2318
    }
nkeynes@375
  2319
:}
nkeynes@377
  2320
FDIV FRm, FRn {:  
nkeynes@671
  2321
    COUNT_INST(I_FDIV);
nkeynes@377
  2322
    check_fpuen();
nkeynes@901
  2323
    if( sh4_x86.double_prec ) {
nkeynes@901
  2324
        push_dr(FRn);
nkeynes@901
  2325
        push_dr(FRm);
nkeynes@901
  2326
        FDIVP_st(1);
nkeynes@901
  2327
        pop_dr(FRn);
nkeynes@901
  2328
    } else {
nkeynes@901
  2329
        push_fr(FRn);
nkeynes@901
  2330
        push_fr(FRm);
nkeynes@901
  2331
        FDIVP_st(1);
nkeynes@901
  2332
        pop_fr(FRn);
nkeynes@901
  2333
    }
nkeynes@375
  2334
:}
nkeynes@375
  2335
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2336
    COUNT_INST(I_FMAC);
nkeynes@377
  2337
    check_fpuen();
nkeynes@901
  2338
    if( sh4_x86.double_prec ) {
nkeynes@901
  2339
        push_dr( 0 );
nkeynes@901
  2340
        push_dr( FRm );
nkeynes@901
  2341
        FMULP_st(1);
nkeynes@901
  2342
        push_dr( FRn );
nkeynes@901
  2343
        FADDP_st(1);
nkeynes@901
  2344
        pop_dr( FRn );
nkeynes@901
  2345
    } else {
nkeynes@901
  2346
        push_fr( 0 );
nkeynes@901
  2347
        push_fr( FRm );
nkeynes@901
  2348
        FMULP_st(1);
nkeynes@901
  2349
        push_fr( FRn );
nkeynes@901
  2350
        FADDP_st(1);
nkeynes@901
  2351
        pop_fr( FRn );
nkeynes@901
  2352
    }
nkeynes@375
  2353
:}
nkeynes@375
  2354
nkeynes@377
  2355
FMUL FRm, FRn {:  
nkeynes@671
  2356
    COUNT_INST(I_FMUL);
nkeynes@377
  2357
    check_fpuen();
nkeynes@901
  2358
    if( sh4_x86.double_prec ) {
nkeynes@901
  2359
        push_dr(FRm);
nkeynes@901
  2360
        push_dr(FRn);
nkeynes@901
  2361
        FMULP_st(1);
nkeynes@901
  2362
        pop_dr(FRn);
nkeynes@901
  2363
    } else {
nkeynes@901
  2364
        push_fr(FRm);
nkeynes@901
  2365
        push_fr(FRn);
nkeynes@901
  2366
        FMULP_st(1);
nkeynes@901
  2367
        pop_fr(FRn);
nkeynes@901
  2368
    }
nkeynes@377
  2369
:}
nkeynes@377
  2370
FNEG FRn {:  
nkeynes@671
  2371
    COUNT_INST(I_FNEG);
nkeynes@377
  2372
    check_fpuen();
nkeynes@901
  2373
    if( sh4_x86.double_prec ) {
nkeynes@901
  2374
        push_dr(FRn);
nkeynes@901
  2375
        FCHS_st0();
nkeynes@901
  2376
        pop_dr(FRn);
nkeynes@901
  2377
    } else {
nkeynes@901
  2378
        push_fr(FRn);
nkeynes@901
  2379
        FCHS_st0();
nkeynes@901
  2380
        pop_fr(FRn);
nkeynes@901
  2381
    }
nkeynes@377
  2382
:}
nkeynes@377
  2383
FSRRA FRn {:  
nkeynes@671
  2384
    COUNT_INST(I_FSRRA);
nkeynes@377
  2385
    check_fpuen();
nkeynes@901
  2386
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2387
        FLD1_st0();
nkeynes@901
  2388
        push_fr(FRn);
nkeynes@901
  2389
        FSQRT_st0();
nkeynes@901
  2390
        FDIVP_st(1);
nkeynes@901
  2391
        pop_fr(FRn);
nkeynes@901
  2392
    }
nkeynes@377
  2393
:}
nkeynes@377
  2394
FSQRT FRn {:  
nkeynes@671
  2395
    COUNT_INST(I_FSQRT);
nkeynes@377
  2396
    check_fpuen();
nkeynes@901
  2397
    if( sh4_x86.double_prec ) {
nkeynes@901
  2398
        push_dr(FRn);
nkeynes@901
  2399
        FSQRT_st0();
nkeynes@901
  2400
        pop_dr(FRn);
nkeynes@901
  2401
    } else {
nkeynes@901
  2402
        push_fr(FRn);
nkeynes@901
  2403
        FSQRT_st0();
nkeynes@901
  2404
        pop_fr(FRn);
nkeynes@901
  2405
    }
nkeynes@377
  2406
:}
nkeynes@377
  2407
FSUB FRm, FRn {:  
nkeynes@671
  2408
    COUNT_INST(I_FSUB);
nkeynes@377
  2409
    check_fpuen();
nkeynes@901
  2410
    if( sh4_x86.double_prec ) {
nkeynes@901
  2411
        push_dr(FRn);
nkeynes@901
  2412
        push_dr(FRm);
nkeynes@901
  2413
        FSUBP_st(1);
nkeynes@901
  2414
        pop_dr(FRn);
nkeynes@901
  2415
    } else {
nkeynes@901
  2416
        push_fr(FRn);
nkeynes@901
  2417
        push_fr(FRm);
nkeynes@901
  2418
        FSUBP_st(1);
nkeynes@901
  2419
        pop_fr(FRn);
nkeynes@901
  2420
    }
nkeynes@377
  2421
:}
nkeynes@377
  2422
nkeynes@377
  2423
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2424
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2425
    check_fpuen();
nkeynes@901
  2426
    if( sh4_x86.double_prec ) {
nkeynes@901
  2427
        push_dr(FRm);
nkeynes@901
  2428
        push_dr(FRn);
nkeynes@901
  2429
    } else {
nkeynes@901
  2430
        push_fr(FRm);
nkeynes@901
  2431
        push_fr(FRn);
nkeynes@901
  2432
    }
nkeynes@377
  2433
    FCOMIP_st(1);
nkeynes@377
  2434
    SETE_t();
nkeynes@377
  2435
    FPOP_st();
nkeynes@901
  2436
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2437
:}
nkeynes@377
  2438
FCMP/GT FRm, FRn {:  
nkeynes@671
  2439
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2440
    check_fpuen();
nkeynes@901
  2441
    if( sh4_x86.double_prec ) {
nkeynes@901
  2442
        push_dr(FRm);
nkeynes@901
  2443
        push_dr(FRn);
nkeynes@901
  2444
    } else {
nkeynes@901
  2445
        push_fr(FRm);
nkeynes@901
  2446
        push_fr(FRn);
nkeynes@901
  2447
    }
nkeynes@377
  2448
    FCOMIP_st(1);
nkeynes@377
  2449
    SETA_t();
nkeynes@377
  2450
    FPOP_st();
nkeynes@901
  2451
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2452
:}
nkeynes@377
  2453
nkeynes@377
  2454
FSCA FPUL, FRn {:  
nkeynes@671
  2455
    COUNT_INST(I_FSCA);
nkeynes@377
  2456
    check_fpuen();
nkeynes@901
  2457
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2458
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2459
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2460
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2461
    }
nkeynes@417
  2462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2463
:}
nkeynes@377
  2464
FIPR FVm, FVn {:  
nkeynes@671
  2465
    COUNT_INST(I_FIPR);
nkeynes@377
  2466
    check_fpuen();
nkeynes@901
  2467
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2468
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2469
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2470
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2471
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2472
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2473
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2474
        } else {
nkeynes@904
  2475
            push_fr( FVm<<2 );
nkeynes@903
  2476
            push_fr( FVn<<2 );
nkeynes@903
  2477
            FMULP_st(1);
nkeynes@903
  2478
            push_fr( (FVm<<2)+1);
nkeynes@903
  2479
            push_fr( (FVn<<2)+1);
nkeynes@903
  2480
            FMULP_st(1);
nkeynes@903
  2481
            FADDP_st(1);
nkeynes@903
  2482
            push_fr( (FVm<<2)+2);
nkeynes@903
  2483
            push_fr( (FVn<<2)+2);
nkeynes@903
  2484
            FMULP_st(1);
nkeynes@903
  2485
            FADDP_st(1);
nkeynes@903
  2486
            push_fr( (FVm<<2)+3);
nkeynes@903
  2487
            push_fr( (FVn<<2)+3);
nkeynes@903
  2488
            FMULP_st(1);
nkeynes@903
  2489
            FADDP_st(1);
nkeynes@903
  2490
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2491
        }
nkeynes@901
  2492
    }
nkeynes@377
  2493
:}
nkeynes@377
  2494
FTRV XMTRX, FVn {:  
nkeynes@671
  2495
    COUNT_INST(I_FTRV);
nkeynes@377
  2496
    check_fpuen();
nkeynes@901
  2497
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2498
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2499
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2500
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2501
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2502
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2503
nkeynes@991
  2504
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2505
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2506
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2507
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2508
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2509
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2510
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2511
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2512
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2513
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2514
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2515
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2516
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2517
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2518
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2519
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2520
        } else {
nkeynes@991
  2521
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@995
  2522
            CALL1_ptr_r32( sh4_ftrv, REG_EAX );
nkeynes@903
  2523
        }
nkeynes@901
  2524
    }
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2526
:}
nkeynes@377
  2527
nkeynes@377
  2528
FRCHG {:  
nkeynes@671
  2529
    COUNT_INST(I_FRCHG);
nkeynes@377
  2530
    check_fpuen();
nkeynes@991
  2531
    XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
nkeynes@995
  2532
    CALL_ptr( sh4_switch_fr_banks );
nkeynes@417
  2533
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2534
:}
nkeynes@377
  2535
FSCHG {:  
nkeynes@671
  2536
    COUNT_INST(I_FSCHG);
nkeynes@377
  2537
    check_fpuen();
nkeynes@991
  2538
    XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
nkeynes@991
  2539
    XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2540
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2541
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2542
:}
nkeynes@359
  2543
nkeynes@359
  2544
/* Processor control instructions */
nkeynes@368
  2545
LDC Rm, SR {:
nkeynes@671
  2546
    COUNT_INST(I_LDCSR);
nkeynes@386
  2547
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2548
	SLOTILLEGAL();
nkeynes@386
  2549
    } else {
nkeynes@386
  2550
	check_priv();
nkeynes@991
  2551
	load_reg( REG_EAX, Rm );
nkeynes@995
  2552
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2553
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2554
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2555
	return 2;
nkeynes@386
  2556
    }
nkeynes@368
  2557
:}
nkeynes@359
  2558
LDC Rm, GBR {: 
nkeynes@671
  2559
    COUNT_INST(I_LDC);
nkeynes@991
  2560
    load_reg( REG_EAX, Rm );
nkeynes@995
  2561
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@359
  2562
:}
nkeynes@359
  2563
LDC Rm, VBR {:  
nkeynes@671
  2564
    COUNT_INST(I_LDC);
nkeynes@386
  2565
    check_priv();
nkeynes@991
  2566
    load_reg( REG_EAX, Rm );
nkeynes@995
  2567
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2568
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2569
:}
nkeynes@359
  2570
LDC Rm, SSR {:  
nkeynes@671
  2571
    COUNT_INST(I_LDC);
nkeynes@386
  2572
    check_priv();
nkeynes@991
  2573
    load_reg( REG_EAX, Rm );
nkeynes@995
  2574
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2575
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2576
:}
nkeynes@359
  2577
LDC Rm, SGR {:  
nkeynes@671
  2578
    COUNT_INST(I_LDC);
nkeynes@386
  2579
    check_priv();
nkeynes@991
  2580
    load_reg( REG_EAX, Rm );
nkeynes@995
  2581
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2582
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2583
:}
nkeynes@359
  2584
LDC Rm, SPC {:  
nkeynes@671
  2585
    COUNT_INST(I_LDC);
nkeynes@386
  2586
    check_priv();
nkeynes@991
  2587
    load_reg( REG_EAX, Rm );
nkeynes@995
  2588
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2589
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2590
:}
nkeynes@359
  2591
LDC Rm, DBR {:  
nkeynes@671
  2592
    COUNT_INST(I_LDC);
nkeynes@386
  2593
    check_priv();
nkeynes@991
  2594
    load_reg( REG_EAX, Rm );
nkeynes@995
  2595
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2597
:}
nkeynes@374
  2598
LDC Rm, Rn_BANK {:  
nkeynes@671
  2599
    COUNT_INST(I_LDC);
nkeynes@386
  2600
    check_priv();
nkeynes@991
  2601
    load_reg( REG_EAX, Rm );
nkeynes@995
  2602
    MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2603
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2604
:}
nkeynes@359
  2605
LDC.L @Rm+, GBR {:  
nkeynes@671
  2606
    COUNT_INST(I_LDCM);
nkeynes@991
  2607
    load_reg( REG_EAX, Rm );
nkeynes@991
  2608
    check_ralign32( REG_EAX );
nkeynes@991
  2609
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2610
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2611
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@417
  2612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2613
:}
nkeynes@368
  2614
LDC.L @Rm+, SR {:
nkeynes@671
  2615
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2616
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2617
	SLOTILLEGAL();
nkeynes@386
  2618
    } else {
nkeynes@586
  2619
	check_priv();
nkeynes@991
  2620
	load_reg( REG_EAX, Rm );
nkeynes@991
  2621
	check_ralign32( REG_EAX );
nkeynes@991
  2622
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2623
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2624
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2625
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2626
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2627
	return 2;
nkeynes@386
  2628
    }
nkeynes@359
  2629
:}
nkeynes@359
  2630
LDC.L @Rm+, VBR {:  
nkeynes@671
  2631
    COUNT_INST(I_LDCM);
nkeynes@586
  2632
    check_priv();
nkeynes@991
  2633
    load_reg( REG_EAX, Rm );
nkeynes@991
  2634
    check_ralign32( REG_EAX );
nkeynes@991
  2635
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2636
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2637
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2638
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2639
:}
nkeynes@359
  2640
LDC.L @Rm+, SSR {:
nkeynes@671
  2641
    COUNT_INST(I_LDCM);
nkeynes@586
  2642
    check_priv();
nkeynes@991
  2643
    load_reg( REG_EAX, Rm );
nkeynes@991
  2644
    check_ralign32( REG_EAX );
nkeynes@991
  2645
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2646
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2647
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2648
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2649
:}
nkeynes@359
  2650
LDC.L @Rm+, SGR {:  
nkeynes@671
  2651
    COUNT_INST(I_LDCM);
nkeynes@586
  2652
    check_priv();
nkeynes@991
  2653
    load_reg( REG_EAX, Rm );
nkeynes@991
  2654
    check_ralign32( REG_EAX );
nkeynes@991
  2655
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2656
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2657
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2658
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2659
:}
nkeynes@359
  2660
LDC.L @Rm+, SPC {:  
nkeynes@671
  2661
    COUNT_INST(I_LDCM);
nkeynes@586
  2662
    check_priv();
nkeynes@991
  2663
    load_reg( REG_EAX, Rm );
nkeynes@991
  2664
    check_ralign32( REG_EAX );
nkeynes@991
  2665
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2666
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2667
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2668
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2669
:}
nkeynes@359
  2670
LDC.L @Rm+, DBR {:  
nkeynes@671
  2671
    COUNT_INST(I_LDCM);
nkeynes@586
  2672
    check_priv();
nkeynes@991
  2673
    load_reg( REG_EAX, Rm );
nkeynes@991
  2674
    check_ralign32( REG_EAX );
nkeynes@991
  2675
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2676
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2677
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2678
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2679
:}
nkeynes@359
  2680
LDC.L @Rm+, Rn_BANK {: