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lxdream.org :: lxdream/src/aica/armdasm.c
lxdream 0.9.1
released Jun 29
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filename src/aica/armdasm.c
changeset 4:7d6f596ce577
next7:976a16e92aab
author nkeynes
date Sat Oct 02 05:49:12 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change Add armdasm
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/*
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 * armdasm.c    21 Aug 2004  - ARM7tdmi (ARMv4) disassembler
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 *
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 * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted
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 * under the terms of the GNU General Public License version 2 or later.
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 */
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#include "armcore.h"
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#define COND(ir) (ir>>28)
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#define OPCODE(ir) ((ir>>20)&0x1F)
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#define GRP(ir) ((ir>>26)&0x03)
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#define IFLAG(ir) (ir&0x02000000)
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#define SFLAG(ir) (ir&0x00100000)
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#define PFLAG(ir) (ir&0x01000000)
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#define UFLAG(ir) (ir&0x00800000)
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#define BFLAG(ir) (ir&0x00400000)
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#define WFLAG(ir) (IR&0x00200000)
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#define LFLAG(ir) SFLAG(ir)
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#define RN(ir) ((ir>>16)&0x0F)
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#define RD(ir) ((ir>>12)&0x0F)
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#define RS(ir) ((ir>>8)&0x0F)
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#define RM(ir) (ir&0x0F)
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#define IMM8(ir) (ir&0xFF)
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#define IMM12(ir) (ir&0xFFF)
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#define SHIFTIMM(ir) ((ir>>7)0x1F)
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#define IMMROT(ir) ((ir>>7)&1E)
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#define SHIFT(ir) ((ir>>4)&0x07)
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#define DISP24(ir) ((ir&0x00FFFFFF))
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#define FSXC(ir) msrFieldMask[RN(ir)]
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#define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
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char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
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                           "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
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                         /* fsxc */
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char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
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	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
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#define UNIMP(ir) snprintf( buf, len, "???     " )
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int arm_disasm_instruction( int pc, char *buf, int len )
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{
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    uint32_t ir = arm_mem_read_long(pc);
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    if( COND(ir) == 0x0F ) {
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    	UNIMP(ir);
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    	return pc+4;
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    }
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    char *cond = conditionNames[COND(ir)];
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	switch( GRP(ir) ) {
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	case 0:
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		if( (ir & 0x0D900000) == 0x01000000 ) {
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			/* Instructions that aren't actual data processing */
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			switch( ir & 0x0FF000F0 ) {
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			case 0x01200010: /* BXcc */
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				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
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				break;
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			case 0x01000000: /* MRS Rd, CPSR */
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				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
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				break;
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			case 0x01400000: /* MRS Rd, SPSR */
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				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
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				break;
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			case 0x01200000: /* MSR CPSR, Rm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
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				break;
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			case 0x01600000: /* MSR SPSR, Rm */
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				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
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				break;
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			case 0x03200000: /* MSR CPSR, imm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
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				break;
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			case 0x03600000: /* MSR SPSR, imm */
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				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
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				break;
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			default:
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				UNIMP();
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			}
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		} else if( (ir & 0x0E000090) == 0x00000090 ) {
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			/* Neither are these */
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			switch( (ir>>5)&0x03 ) {
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			case 0:
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				/* Arithmetic extension area */
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				switch(OPCODE(ir)) {
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				case 0: /* MUL */
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					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
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					break;
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				case 1: /* MULS */
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					break;
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				case 2: /* MLA */
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					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
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					break;
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				case 3: /* MLAS */
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					break;
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				case 8: /* UMULL */
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					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 9: /* UMULLS */
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					break;
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				case 10: /* UMLAL */
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					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 11: /* UMLALS */
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					break;
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				case 12: /* SMULL */
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					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 13: /* SMULLS */
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					break;
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				case 14: /* SMLAL */
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					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 15: /* SMLALS */
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					break;
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				case 16: /* SWP */
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					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
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					break;
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				case 20: /* SWPB */
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					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
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					break;
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				default:
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					UNIMP(ir);
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				}
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				break;
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			case 1:
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				if( LFLAG(ir) ) {
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					/* LDRH */
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				} else {
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					/* STRH */
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				}
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				break;
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			case 2:
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				if( LFLAG(ir) ) {
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					/* LDRSB */
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				} else {
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					UNIMP(ir);
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				}
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				break;
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			case 3:
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				if( LFLAG(ir) ) {
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					/* LDRSH */
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				} else {
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					UNIMP(ir);
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				}
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				break;
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			}
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		} else {
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			/* Data processing */
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			switch(OPCODE(ir)) {
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			case 0: /* AND Rd, Rn, operand */
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				RD(ir) = RN(ir) & arm_get_shift_operand(ir);
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				break;
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			case 1: /* ANDS Rd, Rn, operand */
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				operand = arm_get_shift_operand_s(ir) & RN(ir);
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				RD(ir) = operand;
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				if( RDn(ir) == 15 ) {
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					arm_restore_cpsr();
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				} else {
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					armr.n = operand>>31;
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					armr.z = (operand == 0);
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					armr.c = armr.shift_c;
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				}
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				break;
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			case 2: /* EOR Rd, Rn, operand */
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				RD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
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				break;
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			case 3: /* EORS Rd, Rn, operand */
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				operand = arm_get_shift_operand_s(ir) ^ RN(ir);
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				RD(ir) = operand;
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				if( RDn(ir) == 15 ) {
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					arm_restore_cpsr();
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				} else {
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					armr.n = operand>>31;
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					armr.z = (operand == 0);
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					armr.c = armr.shift_c;
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				}
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				break;
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			case 4: /* SUB Rd, Rn, operand */
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				RD(ir) = RN(ir) - arm_get_shift_operand(ir);
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				break;
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			case 5: /* SUBS Rd, Rn, operand */
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			    operand = RN(ir);
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				operand2 = arm_get_shift_operand(ir)
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				tmp = operand - operand2;
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				RD(ir) = tmp;
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				if( RDn(ir) == 15 ) {
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					arm_restore_cpsr();
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				} else {
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					armr.n = tmp>>31;
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					armr.z = (tmp == 0);
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					armr.c = IS_NOTBORROW(tmp,operand,operand2);
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					armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
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				}
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				break;
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			case 6: /* RSB Rd, operand, Rn */
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				RD(ir) = arm_get_shift_operand(ir) - RN(ir);
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				break;
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			case 7: /* RSBS Rd, operand, Rn */
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				operand = arm_get_shift_operand(ir);
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			    operand2 = RN(ir);
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				tmp = operand - operand2;
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				RD(ir) = tmp;
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				if( RDn(ir) == 15 ) {
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					arm_restore_cpsr();
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				} else {
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					armr.n = tmp>>31;
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					armr.z = (tmp == 0);
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					armr.c = IS_NOTBORROW(tmp,operand,operand2);
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					armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
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				}
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				break;
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			case 8: /* ADD Rd, Rn, operand */
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				RD(ir) = RN(ir) + arm_get_shift_operand(ir);
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				break;
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			case 9: /* ADDS Rd, Rn, operand */
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				operand = arm_get_shift_operand(ir);
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			    operand2 = RN(ir);
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				tmp = operand + operand2
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				RD(ir) = tmp;
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				if( RDn(ir) == 15 ) {
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					arm_restore_cpsr();
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				} else {
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					armr.n = tmp>>31;
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					armr.z = (tmp == 0);
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					armr.c = IS_CARRY(tmp,operand,operand2);
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					armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
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				}
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				break;			
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			case 10: /* ADC */
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			case 11: /* ADCS */
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			case 12: /* SBC */
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			case 13: /* SBCS */
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			case 14: /* RSC */
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			case 15: /* RSCS */
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				break;
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			case 17: /* TST Rn, operand */
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				operand = arm_get_shift_operand_s(ir) & RN(ir);
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				armr.n = operand>>31;
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				armr.z = (operand == 0);
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				armr.c = armr.shift_c;
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				break;
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			case 19: /* TEQ Rn, operand */
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				operand = arm_get_shift_operand_s(ir) ^ RN(ir);
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				armr.n = operand>>31;
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				armr.z = (operand == 0);
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				armr.c = armr.shift_c;
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				break;				
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   253
			case 21: /* CMP Rn, operand */
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			    operand = RN(ir);
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				operand2 = arm_get_shift_operand(ir)
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				tmp = operand - operand2;
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				armr.n = tmp>>31;
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   258
				armr.z = (tmp == 0);
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   259
				armr.c = IS_NOTBORROW(tmp,operand,operand2);
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   260
				armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
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   261
				break;
nkeynes@4
   262
			case 23: /* CMN Rn, operand */
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   263
			    operand = RN(ir);
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   264
				operand2 = arm_get_shift_operand(ir)
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   265
				tmp = operand + operand2;
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   266
				armr.n = tmp>>31;
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   267
				armr.z = (tmp == 0);
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   268
				armr.c = IS_CARRY(tmp,operand,operand2);
nkeynes@4
   269
				armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
nkeynes@4
   270
				break;
nkeynes@4
   271
			case 24: /* ORR Rd, Rn, operand */
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   272
				RD(ir) = RN(ir) | arm_get_shift_operand(ir);
nkeynes@4
   273
				break;
nkeynes@4
   274
			case 25: /* ORRS Rd, Rn, operand */
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   275
				operand = arm_get_shift_operand_s(ir) | RN(ir);
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   276
				RD(ir) = operand;
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   277
				if( RDn(ir) == 15 ) {
nkeynes@4
   278
					arm_restore_cpsr();
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   279
				} else {
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   280
					armr.n = operand>>31;
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   281
					armr.z = (operand == 0);
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   282
					armr.c = armr.shift_c;
nkeynes@4
   283
				}
nkeynes@4
   284
				break;
nkeynes@4
   285
			case 26: /* MOV Rd, operand */
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   286
				RD(ir) = arm_get_shift_operand(ir);
nkeynes@4
   287
				break;
nkeynes@4
   288
			case 27: /* MOVS Rd, operand */
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   289
				operand = arm_get_shift_operand_s(ir);
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   290
				RD(ir) = operand;
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   291
				if( RDn(ir) == 15 ) {
nkeynes@4
   292
					arm_restore_cpsr();
nkeynes@4
   293
				} else {
nkeynes@4
   294
					armr.n = operand>>31;
nkeynes@4
   295
					armr.z = (operand == 0);
nkeynes@4
   296
					armr.c = armr.shift_c;
nkeynes@4
   297
				}
nkeynes@4
   298
				break;
nkeynes@4
   299
			case 28: /* BIC Rd, Rn, operand */
nkeynes@4
   300
				RD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
nkeynes@4
   301
				break;
nkeynes@4
   302
			case 29: /* BICS Rd, Rn, operand */
nkeynes@4
   303
				operand = RN(ir) & (~arm_get_shift_operand_s(ir));
nkeynes@4
   304
				RD(ir) = operand;
nkeynes@4
   305
				if( RDn(ir) == 15 ) {
nkeynes@4
   306
					arm_restore_cpsr();
nkeynes@4
   307
				} else {
nkeynes@4
   308
					armr.n = operand>>31;
nkeynes@4
   309
					armr.z = (operand == 0);
nkeynes@4
   310
					armr.c = armr.shift_c;
nkeynes@4
   311
				}
nkeynes@4
   312
				break;
nkeynes@4
   313
			case 30: /* MVN Rd, operand */
nkeynes@4
   314
				RD(ir) = ~arm_get_shift_operand(ir);
nkeynes@4
   315
				break;
nkeynes@4
   316
			case 31: /* MVNS Rd, operand */
nkeynes@4
   317
				operand = ~arm_get_shift_operand_s(ir);
nkeynes@4
   318
				RD(ir) = operand;
nkeynes@4
   319
				if( RDn(ir) == 15 ) {
nkeynes@4
   320
					arm_restore_cpsr();
nkeynes@4
   321
				} else {
nkeynes@4
   322
					armr.n = operand>>31;
nkeynes@4
   323
					armr.z = (operand == 0);
nkeynes@4
   324
					armr.c = armr.shift_c;
nkeynes@4
   325
				}
nkeynes@4
   326
				break;
nkeynes@4
   327
			default:
nkeynes@4
   328
				UNIMP(ir);
nkeynes@4
   329
			}
nkeynes@4
   330
		}
nkeynes@4
   331
		break;
nkeynes@4
   332
	case 1: /* Load/store */
nkeynes@4
   333
		break;
nkeynes@4
   334
	case 2: /* Load/store multiple, branch*/
nkeynes@4
   335
		break;
nkeynes@4
   336
	case 3: /* Copro */
nkeynes@4
   337
		break;
nkeynes@4
   338
	}
nkeynes@4
   339
	
nkeynes@4
   340
	
nkeynes@4
   341
	
nkeynes@4
   342
	return pc+4;
nkeynes@4
   343
}
.