Search
lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/pvr2/pvr2.c
changeset 284:808617ee7135
prev282:01e53698ff38
next295:6637664291a8
author nkeynes
date Mon Jan 15 08:32:09 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Break vram routines out into pvr2mem.c
Initial (untested) implementation of stride textures
Hookup YUV converter code in pvr2.c
file annotate diff log raw
nkeynes@31
     1
/**
nkeynes@284
     2
 * $Id: pvr2.c,v 1.39 2007-01-15 08:32:09 nkeynes Exp $
nkeynes@31
     3
 *
nkeynes@133
     4
 * PVR2 (Video) Core module implementation and MMIO registers.
nkeynes@31
     5
 *
nkeynes@31
     6
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@31
     7
 *
nkeynes@31
     8
 * This program is free software; you can redistribute it and/or modify
nkeynes@31
     9
 * it under the terms of the GNU General Public License as published by
nkeynes@31
    10
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@31
    11
 * (at your option) any later version.
nkeynes@31
    12
 *
nkeynes@31
    13
 * This program is distributed in the hope that it will be useful,
nkeynes@31
    14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@31
    15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@31
    16
 * GNU General Public License for more details.
nkeynes@31
    17
 */
nkeynes@35
    18
#define MODULE pvr2_module
nkeynes@31
    19
nkeynes@1
    20
#include "dream.h"
nkeynes@265
    21
#include "eventq.h"
nkeynes@144
    22
#include "display.h"
nkeynes@1
    23
#include "mem.h"
nkeynes@1
    24
#include "asic.h"
nkeynes@261
    25
#include "clock.h"
nkeynes@103
    26
#include "pvr2/pvr2.h"
nkeynes@56
    27
#include "sh4/sh4core.h"
nkeynes@1
    28
#define MMIO_IMPL
nkeynes@103
    29
#include "pvr2/pvr2mmio.h"
nkeynes@1
    30
nkeynes@1
    31
char *video_base;
nkeynes@1
    32
nkeynes@133
    33
static void pvr2_init( void );
nkeynes@133
    34
static void pvr2_reset( void );
nkeynes@133
    35
static uint32_t pvr2_run_slice( uint32_t );
nkeynes@133
    36
static void pvr2_save_state( FILE *f );
nkeynes@133
    37
static int pvr2_load_state( FILE *f );
nkeynes@265
    38
static void pvr2_update_raster_posn( uint32_t nanosecs );
nkeynes@265
    39
static void pvr2_schedule_line_event( int eventid, int line );
nkeynes@274
    40
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines );
nkeynes@265
    41
uint32_t pvr2_get_sync_status();
nkeynes@133
    42
nkeynes@94
    43
void pvr2_display_frame( void );
nkeynes@94
    44
nkeynes@161
    45
int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
nkeynes@161
    46
nkeynes@133
    47
struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
nkeynes@133
    48
					pvr2_run_slice, NULL,
nkeynes@133
    49
					pvr2_save_state, pvr2_load_state };
nkeynes@133
    50
nkeynes@103
    51
nkeynes@144
    52
display_driver_t display_driver = NULL;
nkeynes@15
    53
nkeynes@103
    54
struct video_timing {
nkeynes@103
    55
    int fields_per_second;
nkeynes@103
    56
    int total_lines;
nkeynes@108
    57
    int retrace_lines;
nkeynes@103
    58
    int line_time_ns;
nkeynes@103
    59
};
nkeynes@103
    60
nkeynes@261
    61
struct video_timing pal_timing = { 50, 625, 65, 31945 };
nkeynes@108
    62
struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
nkeynes@103
    63
nkeynes@133
    64
struct pvr2_state {
nkeynes@133
    65
    uint32_t frame_count;
nkeynes@133
    66
    uint32_t line_count;
nkeynes@133
    67
    uint32_t line_remainder;
nkeynes@265
    68
    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
nkeynes@133
    69
    uint32_t irq_vpos1;
nkeynes@133
    70
    uint32_t irq_vpos2;
nkeynes@261
    71
    uint32_t odd_even_field; /* 1 = odd, 0 = even */
nkeynes@261
    72
nkeynes@261
    73
    /* timing */
nkeynes@261
    74
    uint32_t dot_clock;
nkeynes@261
    75
    uint32_t total_lines;
nkeynes@261
    76
    uint32_t line_size;
nkeynes@261
    77
    uint32_t line_time_ns;
nkeynes@261
    78
    uint32_t vsync_lines;
nkeynes@261
    79
    uint32_t hsync_width_ns;
nkeynes@261
    80
    uint32_t front_porch_ns;
nkeynes@261
    81
    uint32_t back_porch_ns;
nkeynes@265
    82
    uint32_t retrace_start_line;
nkeynes@265
    83
    uint32_t retrace_end_line;
nkeynes@261
    84
    gboolean interlaced;
nkeynes@133
    85
    struct video_timing timing;
nkeynes@133
    86
} pvr2_state;
nkeynes@15
    87
nkeynes@133
    88
struct video_buffer video_buffer[2];
nkeynes@133
    89
int video_buffer_idx = 0;
nkeynes@133
    90
nkeynes@265
    91
/**
nkeynes@265
    92
 * Event handler for the retrace callback (fires on line 0 normally)
nkeynes@265
    93
 */
nkeynes@265
    94
static void pvr2_retrace_callback( int eventid ) {
nkeynes@265
    95
    asic_event( eventid );
nkeynes@265
    96
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
    97
    pvr2_schedule_line_event( EVENT_RETRACE, 0 );
nkeynes@265
    98
}
nkeynes@265
    99
nkeynes@265
   100
/**
nkeynes@265
   101
 * Event handler for the scanline callbacks. Fires the corresponding
nkeynes@265
   102
 * ASIC event, and resets the timer for the next field.
nkeynes@265
   103
 */
nkeynes@265
   104
static void pvr2_scanline_callback( int eventid ) {
nkeynes@265
   105
    asic_event( eventid );
nkeynes@265
   106
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   107
    if( eventid == EVENT_SCANLINE1 ) {
nkeynes@274
   108
	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 );
nkeynes@265
   109
    } else {
nkeynes@274
   110
	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 );
nkeynes@265
   111
    }
nkeynes@265
   112
}
nkeynes@265
   113
nkeynes@133
   114
static void pvr2_init( void )
nkeynes@1
   115
{
nkeynes@1
   116
    register_io_region( &mmio_region_PVR2 );
nkeynes@85
   117
    register_io_region( &mmio_region_PVR2PAL );
nkeynes@56
   118
    register_io_region( &mmio_region_PVR2TA );
nkeynes@265
   119
    register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
nkeynes@265
   120
    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
nkeynes@265
   121
    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
nkeynes@1
   122
    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
nkeynes@133
   123
    texcache_init();
nkeynes@133
   124
    pvr2_reset();
nkeynes@214
   125
    pvr2_ta_reset();
nkeynes@133
   126
}
nkeynes@133
   127
nkeynes@133
   128
static void pvr2_reset( void )
nkeynes@133
   129
{
nkeynes@133
   130
    pvr2_state.line_count = 0;
nkeynes@133
   131
    pvr2_state.line_remainder = 0;
nkeynes@265
   132
    pvr2_state.cycles_run = 0;
nkeynes@133
   133
    pvr2_state.irq_vpos1 = 0;
nkeynes@133
   134
    pvr2_state.irq_vpos2 = 0;
nkeynes@133
   135
    pvr2_state.timing = ntsc_timing;
nkeynes@265
   136
    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
nkeynes@265
   137
    pvr2_state.back_porch_ns = 4000;
nkeynes@265
   138
    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
nkeynes@265
   139
    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
nkeynes@284
   140
    mmio_region_PVR2_write( YUV_ADDR, 0 );
nkeynes@284
   141
    mmio_region_PVR2_write( YUV_CFG, 0 );
nkeynes@133
   142
    video_buffer_idx = 0;
nkeynes@133
   143
    
nkeynes@133
   144
    pvr2_ta_init();
nkeynes@107
   145
    pvr2_render_init();
nkeynes@133
   146
    texcache_flush();
nkeynes@133
   147
}
nkeynes@133
   148
nkeynes@133
   149
static void pvr2_save_state( FILE *f )
nkeynes@133
   150
{
nkeynes@133
   151
    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
nkeynes@193
   152
    pvr2_ta_save_state( f );
nkeynes@133
   153
}
nkeynes@133
   154
nkeynes@133
   155
static int pvr2_load_state( FILE *f )
nkeynes@133
   156
{
nkeynes@153
   157
    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
nkeynes@153
   158
	return 1;
nkeynes@193
   159
    return pvr2_ta_load_state(f);
nkeynes@133
   160
}
nkeynes@133
   161
nkeynes@265
   162
/**
nkeynes@265
   163
 * Update the current raster position to the given number of nanoseconds,
nkeynes@265
   164
 * relative to the last time slice. (ie the raster will be adjusted forward
nkeynes@265
   165
 * by nanosecs - nanosecs_already_run_this_timeslice)
nkeynes@265
   166
 */
nkeynes@265
   167
static void pvr2_update_raster_posn( uint32_t nanosecs )
nkeynes@265
   168
{
nkeynes@265
   169
    uint32_t old_line_count = pvr2_state.line_count;
nkeynes@265
   170
    if( pvr2_state.line_time_ns == 0 ) {
nkeynes@265
   171
	return; /* do nothing */
nkeynes@265
   172
    }
nkeynes@265
   173
    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
nkeynes@265
   174
    pvr2_state.cycles_run = nanosecs;
nkeynes@265
   175
    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
nkeynes@265
   176
	pvr2_state.line_count ++;
nkeynes@265
   177
	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
nkeynes@265
   178
    }
nkeynes@265
   179
nkeynes@265
   180
    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
nkeynes@265
   181
	pvr2_state.line_count -= pvr2_state.total_lines;
nkeynes@265
   182
	if( pvr2_state.interlaced ) {
nkeynes@265
   183
	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
nkeynes@265
   184
	}
nkeynes@265
   185
    }
nkeynes@265
   186
    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
nkeynes@265
   187
	(old_line_count < pvr2_state.retrace_end_line ||
nkeynes@265
   188
	 old_line_count > pvr2_state.line_count) ) {
nkeynes@265
   189
	pvr2_display_frame();
nkeynes@265
   190
    }
nkeynes@265
   191
}
nkeynes@265
   192
nkeynes@133
   193
static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
nkeynes@133
   194
{
nkeynes@265
   195
    pvr2_update_raster_posn( nanosecs );
nkeynes@265
   196
    pvr2_state.cycles_run = 0;
nkeynes@133
   197
    return nanosecs;
nkeynes@133
   198
}
nkeynes@133
   199
nkeynes@133
   200
int pvr2_get_frame_count() 
nkeynes@133
   201
{
nkeynes@133
   202
    return pvr2_state.frame_count;
nkeynes@106
   203
}
nkeynes@106
   204
nkeynes@103
   205
/**
nkeynes@1
   206
 * Display the next frame, copying the current contents of video ram to
nkeynes@1
   207
 * the window. If the video configuration has changed, first recompute the
nkeynes@1
   208
 * new frame size/depth.
nkeynes@1
   209
 */
nkeynes@94
   210
void pvr2_display_frame( void )
nkeynes@1
   211
{
nkeynes@197
   212
    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@103
   213
    
nkeynes@197
   214
    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
nkeynes@197
   215
    int dispmode = MMIO_READ( PVR2, DISP_MODE );
nkeynes@261
   216
    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
nkeynes@94
   217
    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
nkeynes@94
   218
    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
nkeynes@94
   219
    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
nkeynes@103
   220
    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
nkeynes@103
   221
    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
nkeynes@161
   222
    video_buffer_t buffer = &video_buffer[video_buffer_idx];
nkeynes@161
   223
    video_buffer_idx = !video_buffer_idx;
nkeynes@161
   224
    video_buffer_t last = &video_buffer[video_buffer_idx];
nkeynes@161
   225
    buffer->rowstride = (vid_ppl + vid_stride) << 2;
nkeynes@197
   226
    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@161
   227
    buffer->vres = vid_lpf;
nkeynes@161
   228
    if( interlaced ) buffer->vres <<= 1;
nkeynes@161
   229
    switch( (dispmode & DISPMODE_COL) >> 2 ) {
nkeynes@161
   230
    case 0: 
nkeynes@161
   231
	buffer->colour_format = COLFMT_ARGB1555;
nkeynes@161
   232
	buffer->hres = vid_ppl << 1; 
nkeynes@161
   233
	break;
nkeynes@161
   234
    case 1: 
nkeynes@161
   235
	buffer->colour_format = COLFMT_RGB565;
nkeynes@161
   236
	buffer->hres = vid_ppl << 1; 
nkeynes@161
   237
	break;
nkeynes@161
   238
    case 2:
nkeynes@161
   239
	buffer->colour_format = COLFMT_RGB888;
nkeynes@161
   240
	buffer->hres = (vid_ppl << 2) / 3; 
nkeynes@161
   241
	break;
nkeynes@161
   242
    case 3: 
nkeynes@161
   243
	buffer->colour_format = COLFMT_ARGB8888;
nkeynes@161
   244
	buffer->hres = vid_ppl; 
nkeynes@161
   245
	break;
nkeynes@161
   246
    }
nkeynes@161
   247
	
nkeynes@161
   248
    if( buffer->hres <=8 )
nkeynes@161
   249
	buffer->hres = 640;
nkeynes@161
   250
    if( buffer->vres <=8 )
nkeynes@161
   251
	buffer->vres = 480;
nkeynes@161
   252
    if( display_driver != NULL ) {
nkeynes@161
   253
	if( buffer->hres != last->hres ||
nkeynes@161
   254
	    buffer->vres != last->vres ||
nkeynes@161
   255
	    buffer->colour_format != last->colour_format) {
nkeynes@161
   256
	    display_driver->set_display_format( buffer->hres, buffer->vres,
nkeynes@161
   257
						buffer->colour_format );
nkeynes@94
   258
	}
nkeynes@161
   259
	if( !bEnabled ) {
nkeynes@161
   260
	    display_driver->display_blank_frame( 0 );
nkeynes@197
   261
	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
nkeynes@197
   262
	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
nkeynes@161
   263
	    display_driver->display_blank_frame( colour );
nkeynes@161
   264
	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
nkeynes@161
   265
	    display_driver->display_frame( buffer );
nkeynes@65
   266
	}
nkeynes@1
   267
    }
nkeynes@133
   268
    pvr2_state.frame_count++;
nkeynes@1
   269
}
nkeynes@1
   270
nkeynes@197
   271
/**
nkeynes@197
   272
 * This has to handle every single register individually as they all get masked 
nkeynes@197
   273
 * off differently (and its easier to do it at write time)
nkeynes@197
   274
 */
nkeynes@1
   275
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
nkeynes@1
   276
{
nkeynes@1
   277
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   278
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   279
        return;
nkeynes@1
   280
    }
nkeynes@1
   281
    
nkeynes@1
   282
    switch(reg) {
nkeynes@189
   283
    case PVRID:
nkeynes@189
   284
    case PVRVER:
nkeynes@261
   285
    case GUNPOS: /* Read only registers */
nkeynes@189
   286
	break;
nkeynes@197
   287
    case PVRRESET:
nkeynes@197
   288
	val &= 0x00000007; /* Do stuff? */
nkeynes@197
   289
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   290
	break;
nkeynes@191
   291
    case RENDER_START:
nkeynes@261
   292
	if( val == 0xFFFFFFFF || val == 0x00000001 )
nkeynes@189
   293
	    pvr2_render_scene();
nkeynes@189
   294
	break;
nkeynes@191
   295
    case RENDER_POLYBASE:
nkeynes@191
   296
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   297
    	break;
nkeynes@191
   298
    case RENDER_TSPCFG:
nkeynes@191
   299
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   300
    	break;
nkeynes@197
   301
    case DISP_BORDER:
nkeynes@191
   302
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   303
    	break;
nkeynes@197
   304
    case DISP_MODE:
nkeynes@191
   305
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   306
    	break;
nkeynes@191
   307
    case RENDER_MODE:
nkeynes@191
   308
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   309
    	break;
nkeynes@191
   310
    case RENDER_SIZE:
nkeynes@191
   311
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   312
    	break;
nkeynes@197
   313
    case DISP_ADDR1:
nkeynes@189
   314
	val &= 0x00FFFFFC;
nkeynes@189
   315
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   316
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   317
	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
nkeynes@265
   318
	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
nkeynes@108
   319
	    pvr2_display_frame();
nkeynes@108
   320
	}
nkeynes@108
   321
	break;
nkeynes@197
   322
    case DISP_ADDR2:
nkeynes@191
   323
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@191
   324
    	break;
nkeynes@197
   325
    case DISP_SIZE:
nkeynes@191
   326
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   327
    	break;
nkeynes@191
   328
    case RENDER_ADDR1:
nkeynes@191
   329
    case RENDER_ADDR2:
nkeynes@191
   330
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   331
    	break;
nkeynes@191
   332
    case RENDER_HCLIP:
nkeynes@191
   333
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   334
	break;
nkeynes@191
   335
    case RENDER_VCLIP:
nkeynes@191
   336
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   337
	break;
nkeynes@197
   338
    case DISP_HPOSIRQ:
nkeynes@191
   339
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   340
	break;
nkeynes@197
   341
    case DISP_VPOSIRQ:
nkeynes@189
   342
	val = val & 0x03FF03FF;
nkeynes@189
   343
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   344
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   345
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@274
   346
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
nkeynes@274
   347
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
nkeynes@189
   348
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   349
	break;
nkeynes@197
   350
    case RENDER_NEARCLIP:
nkeynes@197
   351
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   352
	break;
nkeynes@191
   353
    case RENDER_SHADOW:
nkeynes@191
   354
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   355
	break;
nkeynes@191
   356
    case RENDER_OBJCFG:
nkeynes@191
   357
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   358
    	break;
nkeynes@191
   359
    case RENDER_TSPCLIP:
nkeynes@191
   360
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   361
    	break;
nkeynes@197
   362
    case RENDER_FARCLIP:
nkeynes@197
   363
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   364
	break;
nkeynes@191
   365
    case RENDER_BGPLANE:
nkeynes@191
   366
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   367
    	break;
nkeynes@191
   368
    case RENDER_ISPCFG:
nkeynes@191
   369
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   370
    	break;
nkeynes@197
   371
    case VRAM_CFG1:
nkeynes@197
   372
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   373
	break;
nkeynes@197
   374
    case VRAM_CFG2:
nkeynes@197
   375
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   376
	break;
nkeynes@197
   377
    case VRAM_CFG3:
nkeynes@197
   378
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   379
	break;
nkeynes@197
   380
    case RENDER_FOGTBLCOL:
nkeynes@197
   381
    case RENDER_FOGVRTCOL:
nkeynes@197
   382
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   383
	break;
nkeynes@197
   384
    case RENDER_FOGCOEFF:
nkeynes@197
   385
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   386
	break;
nkeynes@197
   387
    case RENDER_CLAMPHI:
nkeynes@197
   388
    case RENDER_CLAMPLO:
nkeynes@197
   389
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   390
	break;
nkeynes@261
   391
    case RENDER_TEXSIZE:
nkeynes@261
   392
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   393
	break;
nkeynes@261
   394
    case RENDER_PALETTE:
nkeynes@261
   395
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   396
	break;
nkeynes@261
   397
nkeynes@261
   398
	/********** CRTC registers *************/
nkeynes@197
   399
    case DISP_HBORDER:
nkeynes@197
   400
    case DISP_VBORDER:
nkeynes@197
   401
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   402
	break;
nkeynes@261
   403
    case DISP_TOTAL:
nkeynes@261
   404
	val = val & 0x03FF03FF;
nkeynes@261
   405
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   406
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   407
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   408
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   409
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   410
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   411
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@265
   412
	pvr2_schedule_line_event( EVENT_RETRACE, 0 );
nkeynes@274
   413
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
nkeynes@274
   414
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
nkeynes@261
   415
	break;
nkeynes@261
   416
    case DISP_SYNCCFG:
nkeynes@261
   417
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   418
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   419
	break;
nkeynes@261
   420
    case DISP_SYNCTIME:
nkeynes@261
   421
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   422
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   423
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   424
	break;
nkeynes@197
   425
    case DISP_CFG2:
nkeynes@197
   426
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   427
	break;
nkeynes@197
   428
    case DISP_HPOS:
nkeynes@261
   429
	val = val & 0x03FF;
nkeynes@261
   430
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   431
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   432
	break;
nkeynes@197
   433
    case DISP_VPOS:
nkeynes@197
   434
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   435
	break;
nkeynes@261
   436
nkeynes@261
   437
	/*********** Tile accelerator registers ***********/
nkeynes@261
   438
    case TA_POLYPOS:
nkeynes@261
   439
    case TA_LISTPOS:
nkeynes@261
   440
	/* Readonly registers */
nkeynes@197
   441
	break;
nkeynes@189
   442
    case TA_TILEBASE:
nkeynes@193
   443
    case TA_LISTEND:
nkeynes@189
   444
    case TA_LISTBASE:
nkeynes@191
   445
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   446
	break;
nkeynes@191
   447
    case RENDER_TILEBASE:
nkeynes@189
   448
    case TA_POLYBASE:
nkeynes@189
   449
    case TA_POLYEND:
nkeynes@191
   450
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   451
	break;
nkeynes@189
   452
    case TA_TILESIZE:
nkeynes@191
   453
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   454
	break;
nkeynes@189
   455
    case TA_TILECFG:
nkeynes@191
   456
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   457
	break;
nkeynes@261
   458
    case TA_INIT:
nkeynes@261
   459
	if( val & 0x80000000 )
nkeynes@261
   460
	    pvr2_ta_init();
nkeynes@261
   461
	break;
nkeynes@261
   462
    case TA_REINIT:
nkeynes@261
   463
	break;
nkeynes@261
   464
	/**************** Scaler registers? ****************/
nkeynes@261
   465
    case SCALERCFG:
nkeynes@269
   466
	/* KOS suggests bits as follows:
nkeynes@269
   467
	 *   0: enable vertical scaling
nkeynes@269
   468
	 *  10: ???
nkeynes@269
   469
	 *  16: enable FSAA
nkeynes@269
   470
	 */
nkeynes@261
   471
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   472
	break;
nkeynes@261
   473
nkeynes@197
   474
    case YUV_ADDR:
nkeynes@284
   475
	val = val & 0x00FFFFF8;
nkeynes@284
   476
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   477
	pvr2_yuv_init( val );
nkeynes@197
   478
	break;
nkeynes@197
   479
    case YUV_CFG:
nkeynes@197
   480
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   481
	pvr2_yuv_set_config(val);
nkeynes@197
   482
	break;
nkeynes@261
   483
nkeynes@261
   484
	/**************** Unknowns ***************/
nkeynes@261
   485
    case PVRUNK1:
nkeynes@261
   486
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   487
    	break;
nkeynes@261
   488
    case PVRUNK2:
nkeynes@261
   489
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   490
	break;
nkeynes@261
   491
    case PVRUNK3:
nkeynes@261
   492
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   493
	break;
nkeynes@261
   494
    case PVRUNK5:
nkeynes@261
   495
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   496
	break;
nkeynes@261
   497
    case PVRUNK6:
nkeynes@261
   498
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   499
	break;
nkeynes@197
   500
    case PVRUNK7:
nkeynes@197
   501
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   502
	break;
nkeynes@1
   503
    }
nkeynes@1
   504
}
nkeynes@1
   505
nkeynes@261
   506
/**
nkeynes@261
   507
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   508
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   509
 * The register reads (LSB to MSB) as:
nkeynes@261
   510
 *     0..9  Current scan line
nkeynes@261
   511
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   512
 *     11    Display active (including border and overscan)
nkeynes@261
   513
 *     12    Horizontal sync off
nkeynes@261
   514
 *     13    Vertical sync off
nkeynes@261
   515
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   516
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   517
 */
nkeynes@261
   518
uint32_t pvr2_get_sync_status()
nkeynes@261
   519
{
nkeynes@265
   520
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   521
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   522
nkeynes@265
   523
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   524
	result |= 0x0400;
nkeynes@261
   525
    }
nkeynes@265
   526
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   527
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   528
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   529
	}
nkeynes@265
   530
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   531
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   532
		result |= 0x2800; /* Display active */
nkeynes@261
   533
	    } else {
nkeynes@261
   534
		result |= 0x2000; /* Front porch */
nkeynes@261
   535
	    }
nkeynes@261
   536
	}
nkeynes@261
   537
    } else {
nkeynes@269
   538
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   539
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   540
		result |= 0x3800; /* Display active */
nkeynes@269
   541
	    } else {
nkeynes@269
   542
		result |= 0x3000;
nkeynes@269
   543
	    }
nkeynes@261
   544
	} else {
nkeynes@261
   545
	    result |= 0x1000; /* Back porch */
nkeynes@261
   546
	}
nkeynes@261
   547
    }
nkeynes@261
   548
    return result;
nkeynes@261
   549
}
nkeynes@261
   550
nkeynes@265
   551
/**
nkeynes@265
   552
 * Schedule an event for the start of the given line. If the line is actually
nkeynes@265
   553
 * the current line, schedules it for the next field. 
nkeynes@265
   554
 * The raster position should be updated before calling this method.
nkeynes@265
   555
 */
nkeynes@265
   556
static void pvr2_schedule_line_event( int eventid, int line )
nkeynes@265
   557
{
nkeynes@265
   558
    uint32_t time;
nkeynes@265
   559
    if( line <= pvr2_state.line_count ) {
nkeynes@265
   560
	time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
nkeynes@265
   561
	    - pvr2_state.line_remainder;
nkeynes@265
   562
    } else {
nkeynes@265
   563
	time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
nkeynes@265
   564
    }
nkeynes@265
   565
nkeynes@265
   566
    if( line < pvr2_state.total_lines ) {
nkeynes@265
   567
	event_schedule( eventid, time );
nkeynes@265
   568
    } else {
nkeynes@265
   569
	event_cancel( eventid );
nkeynes@265
   570
    }
nkeynes@265
   571
}
nkeynes@265
   572
nkeynes@265
   573
/**
nkeynes@265
   574
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   575
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   576
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   577
 * The raster position should be updated before calling this
nkeynes@265
   578
 * method.
nkeynes@265
   579
 */
nkeynes@274
   580
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines )
nkeynes@265
   581
{
nkeynes@265
   582
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   583
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   584
	field = !field;
nkeynes@265
   585
    }
nkeynes@265
   586
nkeynes@265
   587
    line <<= 1;
nkeynes@265
   588
    if( field ) {
nkeynes@265
   589
	line += 1;
nkeynes@265
   590
    }
nkeynes@274
   591
    
nkeynes@274
   592
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   593
	uint32_t lines;
nkeynes@274
   594
	uint32_t time;
nkeynes@274
   595
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   596
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   597
	} else {
nkeynes@274
   598
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   599
	}
nkeynes@274
   600
	if( lines <= minimum_lines ) {
nkeynes@274
   601
	    lines += pvr2_state.total_lines;
nkeynes@274
   602
	}
nkeynes@274
   603
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder;
nkeynes@274
   604
	event_schedule( eventid, time );
nkeynes@274
   605
    } else {
nkeynes@274
   606
	event_cancel( eventid );
nkeynes@274
   607
    }
nkeynes@265
   608
}
nkeynes@265
   609
nkeynes@1
   610
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   611
{
nkeynes@1
   612
    switch( reg ) {
nkeynes@261
   613
        case DISP_SYNCSTAT:
nkeynes@261
   614
            return pvr2_get_sync_status();
nkeynes@1
   615
        default:
nkeynes@1
   616
            return MMIO_READ( PVR2, reg );
nkeynes@1
   617
    }
nkeynes@1
   618
}
nkeynes@19
   619
nkeynes@85
   620
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   621
nkeynes@19
   622
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   623
{
nkeynes@197
   624
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   625
}
nkeynes@56
   626
nkeynes@56
   627
nkeynes@65
   628
nkeynes@98
   629
nkeynes@56
   630
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   631
{
nkeynes@56
   632
    return 0xFFFFFFFF;
nkeynes@56
   633
}
nkeynes@56
   634
nkeynes@56
   635
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   636
{
nkeynes@189
   637
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   638
}
nkeynes@56
   639
.