nkeynes@931 | 1 | /**
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nkeynes@931 | 2 | * $Id$
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nkeynes@931 | 3 | * Implements the on-chip operand cache and instruction caches
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nkeynes@931 | 4 | *
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nkeynes@931 | 5 | * Copyright (c) 2008 Nathan Keynes.
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nkeynes@931 | 6 | *
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nkeynes@931 | 7 | * This program is free software; you can redistribute it and/or modify
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nkeynes@931 | 8 | * it under the terms of the GNU General Public License as published by
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nkeynes@931 | 9 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@931 | 10 | * (at your option) any later version.
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nkeynes@931 | 11 | *
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nkeynes@931 | 12 | * This program is distributed in the hope that it will be useful,
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nkeynes@931 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@931 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@931 | 15 | * GNU General Public License for more details.
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nkeynes@931 | 16 | */
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nkeynes@931 | 17 |
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nkeynes@931 | 18 | #define MODULE sh4_module
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nkeynes@931 | 19 |
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nkeynes@931 | 20 | #include <string.h>
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nkeynes@931 | 21 | #include "dream.h"
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nkeynes@931 | 22 | #include "mem.h"
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nkeynes@931 | 23 | #include "mmio.h"
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nkeynes@931 | 24 | #include "sh4/sh4core.h"
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nkeynes@931 | 25 | #include "sh4/sh4mmio.h"
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nkeynes@931 | 26 | #include "sh4/xltcache.h"
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nkeynes@931 | 27 |
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nkeynes@931 | 28 | #define OCRAM_START (0x7C000000>>LXDREAM_PAGE_BITS)
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nkeynes@931 | 29 | #define OCRAM_MID (0x7E000000>>LXDREAM_PAGE_BITS)
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nkeynes@931 | 30 | #define OCRAM_END (0x80000000>>LXDREAM_PAGE_BITS)
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nkeynes@931 | 31 |
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nkeynes@931 | 32 | #define CACHE_VALID 1
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nkeynes@931 | 33 | #define CACHE_DIRTY 2
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nkeynes@931 | 34 |
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nkeynes@931 | 35 | #define ICACHE_ENTRY_COUNT 256
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nkeynes@931 | 36 | #define OCACHE_ENTRY_COUNT 512
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nkeynes@931 | 37 |
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nkeynes@931 | 38 | struct cache_line {
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nkeynes@931 | 39 | uint32_t key; // Fast address match - bits 5..28 for valid entry, -1 for invalid entry
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nkeynes@931 | 40 | uint32_t tag; // tag + flags value from the address field
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nkeynes@931 | 41 | };
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nkeynes@931 | 42 |
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nkeynes@931 | 43 |
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nkeynes@931 | 44 | static struct cache_line ccn_icache[ICACHE_ENTRY_COUNT];
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nkeynes@931 | 45 | static struct cache_line ccn_ocache[OCACHE_ENTRY_COUNT];
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nkeynes@931 | 46 | static unsigned char ccn_icache_data[ICACHE_ENTRY_COUNT*32];
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nkeynes@931 | 47 | static unsigned char ccn_ocache_data[OCACHE_ENTRY_COUNT*32];
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nkeynes@931 | 48 |
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nkeynes@931 | 49 |
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nkeynes@931 | 50 | /*********************** General module requirements ********************/
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nkeynes@931 | 51 |
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nkeynes@931 | 52 | void CCN_save_state( FILE *f )
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nkeynes@931 | 53 | {
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nkeynes@931 | 54 | fwrite( &ccn_icache, sizeof(ccn_icache), 1, f );
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nkeynes@931 | 55 | fwrite( &ccn_icache_data, sizeof(ccn_icache_data), 1, f );
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nkeynes@931 | 56 | fwrite( &ccn_ocache, sizeof(ccn_ocache), 1, f);
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nkeynes@931 | 57 | fwrite( &ccn_ocache_data, sizeof(ccn_ocache_data), 1, f);
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nkeynes@931 | 58 | }
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nkeynes@931 | 59 |
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nkeynes@931 | 60 | int CCN_load_state( FILE *f )
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nkeynes@931 | 61 | {
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nkeynes@931 | 62 | /* Setup the cache mode according to the saved register value
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nkeynes@931 | 63 | * (mem_load runs before this point to load all MMIO data)
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nkeynes@931 | 64 | */
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nkeynes@931 | 65 | mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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nkeynes@931 | 66 |
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nkeynes@931 | 67 | if( fread( &ccn_icache, sizeof(ccn_icache), 1, f ) != 1 ) {
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nkeynes@931 | 68 | return 1;
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nkeynes@931 | 69 | }
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nkeynes@931 | 70 | if( fread( &ccn_icache_data, sizeof(ccn_icache_data), 1, f ) != 1 ) {
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nkeynes@931 | 71 | return 1;
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nkeynes@931 | 72 | }
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nkeynes@931 | 73 | if( fread( &ccn_ocache, sizeof(ccn_ocache), 1, f ) != 1 ) {
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nkeynes@931 | 74 | return 1;
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nkeynes@931 | 75 | }
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nkeynes@931 | 76 | if( fread( &ccn_ocache_data, sizeof(ccn_ocache_data), 1, f ) != 1 ) {
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nkeynes@931 | 77 | return 1;
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nkeynes@931 | 78 | }
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nkeynes@931 | 79 | return 0;
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nkeynes@931 | 80 | }
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nkeynes@931 | 81 |
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nkeynes@931 | 82 |
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nkeynes@931 | 83 | /************************* OCRAM memory address space ************************/
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nkeynes@931 | 84 |
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nkeynes@931 | 85 | #define OCRAMPAGE0 (&ccn_ocache_data[4096]) /* Lines 128-255 */
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nkeynes@931 | 86 | #define OCRAMPAGE1 (&ccn_ocache_data[12288]) /* Lines 384-511 */
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nkeynes@931 | 87 |
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nkeynes@931 | 88 | static int32_t FASTCALL ocram_page0_read_long( sh4addr_t addr )
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nkeynes@931 | 89 | {
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nkeynes@931 | 90 | return *((int32_t *)(OCRAMPAGE0 + (addr&0x00000FFF)));
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nkeynes@931 | 91 | }
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nkeynes@931 | 92 | static int32_t FASTCALL ocram_page0_read_word( sh4addr_t addr )
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nkeynes@931 | 93 | {
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nkeynes@931 | 94 | return SIGNEXT16(*((int16_t *)(OCRAMPAGE0 + (addr&0x00000FFF))));
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nkeynes@931 | 95 | }
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nkeynes@931 | 96 | static int32_t FASTCALL ocram_page0_read_byte( sh4addr_t addr )
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nkeynes@931 | 97 | {
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nkeynes@931 | 98 | return SIGNEXT8(*((int16_t *)(OCRAMPAGE0 + (addr&0x00000FFF))));
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nkeynes@931 | 99 | }
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nkeynes@931 | 100 | static void FASTCALL ocram_page0_write_long( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 101 | {
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nkeynes@931 | 102 | *(uint32_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = val;
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nkeynes@931 | 103 | }
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nkeynes@931 | 104 | static void FASTCALL ocram_page0_write_word( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 105 | {
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nkeynes@931 | 106 | *(uint16_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = (uint16_t)val;
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nkeynes@931 | 107 | }
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nkeynes@931 | 108 | static void FASTCALL ocram_page0_write_byte( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 109 | {
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nkeynes@931 | 110 | *(uint8_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = (uint8_t)val;
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nkeynes@931 | 111 | }
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nkeynes@931 | 112 | static void FASTCALL ocram_page0_read_burst( unsigned char *dest, sh4addr_t addr )
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nkeynes@931 | 113 | {
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nkeynes@931 | 114 | memcpy( dest, OCRAMPAGE0+(addr&0x00000FFF), 32 );
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nkeynes@931 | 115 | }
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nkeynes@931 | 116 | static void FASTCALL ocram_page0_write_burst( sh4addr_t addr, unsigned char *src )
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nkeynes@931 | 117 | {
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nkeynes@931 | 118 | memcpy( OCRAMPAGE0+(addr&0x00000FFF), src, 32 );
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nkeynes@931 | 119 | }
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nkeynes@931 | 120 |
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nkeynes@931 | 121 | struct mem_region_fn mem_region_ocram_page0 = {
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nkeynes@931 | 122 | ocram_page0_read_long, ocram_page0_write_long,
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nkeynes@931 | 123 | ocram_page0_read_word, ocram_page0_write_word,
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nkeynes@931 | 124 | ocram_page0_read_byte, ocram_page0_write_byte,
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nkeynes@931 | 125 | ocram_page0_read_burst, ocram_page0_write_burst };
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nkeynes@931 | 126 |
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nkeynes@931 | 127 | static int32_t FASTCALL ocram_page1_read_long( sh4addr_t addr )
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nkeynes@931 | 128 | {
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nkeynes@931 | 129 | return *((int32_t *)(OCRAMPAGE1 + (addr&0x00000FFF)));
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nkeynes@931 | 130 | }
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nkeynes@931 | 131 | static int32_t FASTCALL ocram_page1_read_word( sh4addr_t addr )
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nkeynes@931 | 132 | {
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nkeynes@931 | 133 | return SIGNEXT16(*((int16_t *)(OCRAMPAGE1 + (addr&0x00000FFF))));
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nkeynes@931 | 134 | }
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nkeynes@931 | 135 | static int32_t FASTCALL ocram_page1_read_byte( sh4addr_t addr )
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nkeynes@931 | 136 | {
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nkeynes@931 | 137 | return SIGNEXT8(*((int16_t *)(OCRAMPAGE1 + (addr&0x00000FFF))));
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nkeynes@931 | 138 | }
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nkeynes@931 | 139 | static void FASTCALL ocram_page1_write_long( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 140 | {
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nkeynes@931 | 141 | *(uint32_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = val;
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nkeynes@931 | 142 | }
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nkeynes@931 | 143 | static void FASTCALL ocram_page1_write_word( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 144 | {
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nkeynes@931 | 145 | *(uint16_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = (uint16_t)val;
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nkeynes@931 | 146 | }
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nkeynes@931 | 147 | static void FASTCALL ocram_page1_write_byte( sh4addr_t addr, uint32_t val )
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nkeynes@931 | 148 | {
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nkeynes@931 | 149 | *(uint8_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = (uint8_t)val;
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nkeynes@931 | 150 | }
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nkeynes@931 | 151 | static void FASTCALL ocram_page1_read_burst( unsigned char *dest, sh4addr_t addr )
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nkeynes@931 | 152 | {
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nkeynes@931 | 153 | memcpy( dest, OCRAMPAGE1+(addr&0x00000FFF), 32 );
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nkeynes@931 | 154 | }
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nkeynes@931 | 155 | static void FASTCALL ocram_page1_write_burst( sh4addr_t addr, unsigned char *src )
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nkeynes@931 | 156 | {
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nkeynes@931 | 157 | memcpy( OCRAMPAGE1+(addr&0x00000FFF), src, 32 );
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nkeynes@931 | 158 | }
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nkeynes@931 | 159 |
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nkeynes@931 | 160 | struct mem_region_fn mem_region_ocram_page1 = {
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nkeynes@931 | 161 | ocram_page1_read_long, ocram_page1_write_long,
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nkeynes@931 | 162 | ocram_page1_read_word, ocram_page1_write_word,
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nkeynes@931 | 163 | ocram_page1_read_byte, ocram_page1_write_byte,
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nkeynes@931 | 164 | ocram_page1_read_burst, ocram_page1_write_burst };
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nkeynes@931 | 165 |
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nkeynes@933 | 166 | /************************** Cache direct access ******************************/
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nkeynes@933 | 167 |
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nkeynes@933 | 168 | static int32_t ccn_icache_addr_read( sh4addr_t addr )
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nkeynes@933 | 169 | {
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nkeynes@933 | 170 | int entry = (addr & 0x00001FE0);
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nkeynes@933 | 171 | return ccn_icache[entry>>5].tag;
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nkeynes@933 | 172 | }
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nkeynes@933 | 173 |
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nkeynes@933 | 174 | static void ccn_icache_addr_write( sh4addr_t addr, uint32_t val )
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nkeynes@933 | 175 | {
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nkeynes@933 | 176 | int entry = (addr & 0x00003FE0);
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nkeynes@933 | 177 | struct cache_line *line = &ccn_ocache[entry>>5];
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nkeynes@933 | 178 | if( addr & 0x08 ) { // Associative
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nkeynes@933 | 179 | /* FIXME: implement this - requires ITLB lookups, with exception in case of multi-hit */
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nkeynes@933 | 180 | } else {
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nkeynes@933 | 181 | line->tag = val & 0x1FFFFC01;
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nkeynes@933 | 182 | line->key = (val & 0x1FFFFC00)|(entry & 0x000003E0);
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nkeynes@933 | 183 | }
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nkeynes@933 | 184 | }
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nkeynes@933 | 185 |
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nkeynes@933 | 186 | struct mem_region_fn p4_region_icache_addr = {
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nkeynes@933 | 187 | ccn_icache_addr_read, ccn_icache_addr_write,
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nkeynes@933 | 188 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 189 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 190 | unmapped_read_burst, unmapped_write_burst };
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nkeynes@933 | 191 |
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nkeynes@933 | 192 |
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nkeynes@933 | 193 | static int32_t ccn_icache_data_read( sh4addr_t addr )
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nkeynes@933 | 194 | {
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nkeynes@933 | 195 | int entry = (addr & 0x00001FFC);
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nkeynes@933 | 196 | return *(uint32_t *)&ccn_icache_data[entry];
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nkeynes@933 | 197 | }
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nkeynes@933 | 198 |
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nkeynes@933 | 199 | static void ccn_icache_data_write( sh4addr_t addr, uint32_t val )
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nkeynes@933 | 200 | {
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nkeynes@933 | 201 | int entry = (addr & 0x00001FFC);
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nkeynes@933 | 202 | *(uint32_t *)&ccn_icache_data[entry] = val;
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nkeynes@933 | 203 | }
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nkeynes@933 | 204 |
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nkeynes@933 | 205 | struct mem_region_fn p4_region_icache_data = {
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nkeynes@933 | 206 | ccn_icache_data_read, ccn_icache_data_write,
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nkeynes@933 | 207 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 208 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 209 | unmapped_read_burst, unmapped_write_burst };
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nkeynes@933 | 210 |
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nkeynes@933 | 211 |
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nkeynes@933 | 212 | static int32_t ccn_ocache_addr_read( sh4addr_t addr )
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nkeynes@933 | 213 | {
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nkeynes@933 | 214 | int entry = (addr & 0x00003FE0);
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nkeynes@933 | 215 | return ccn_ocache[entry>>5].tag;
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nkeynes@933 | 216 | }
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nkeynes@933 | 217 |
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nkeynes@933 | 218 | static void ccn_ocache_addr_write( sh4addr_t addr, uint32_t val )
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nkeynes@933 | 219 | {
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nkeynes@933 | 220 | int entry = (addr & 0x00003FE0);
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nkeynes@933 | 221 | struct cache_line *line = &ccn_ocache[entry>>5];
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nkeynes@933 | 222 | if( addr & 0x08 ) { // Associative
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nkeynes@933 | 223 | } else {
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nkeynes@933 | 224 | if( (line->tag & (CACHE_VALID|CACHE_DIRTY)) == (CACHE_VALID|CACHE_DIRTY) ) {
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nkeynes@933 | 225 | char *cache_data = &ccn_ocache_data[entry&0x00003FE0];
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nkeynes@933 | 226 | // Cache line is dirty - writeback.
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nkeynes@933 | 227 | ext_address_space[line->tag>>12]->write_burst(line->key, cache_data);
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nkeynes@933 | 228 | }
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nkeynes@933 | 229 | line->tag = val & 0x1FFFFC03;
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nkeynes@933 | 230 | line->key = (val & 0x1FFFFC00)|(entry & 0x000003E0);
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nkeynes@933 | 231 | }
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nkeynes@933 | 232 | }
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nkeynes@933 | 233 |
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nkeynes@933 | 234 | struct mem_region_fn p4_region_ocache_addr = {
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nkeynes@933 | 235 | ccn_ocache_addr_read, ccn_ocache_addr_write,
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nkeynes@933 | 236 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 237 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 238 | unmapped_read_burst, unmapped_write_burst };
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nkeynes@933 | 239 |
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nkeynes@933 | 240 |
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nkeynes@933 | 241 | static int32_t ccn_ocache_data_read( sh4addr_t addr )
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nkeynes@933 | 242 | {
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nkeynes@933 | 243 | int entry = (addr & 0x00003FFC);
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nkeynes@933 | 244 | return *(uint32_t *)&ccn_ocache_data[entry];
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nkeynes@933 | 245 | }
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nkeynes@933 | 246 |
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nkeynes@933 | 247 | static void ccn_ocache_data_write( sh4addr_t addr, uint32_t val )
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nkeynes@933 | 248 | {
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nkeynes@933 | 249 | int entry = (addr & 0x00003FFC);
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nkeynes@933 | 250 | *(uint32_t *)&ccn_ocache_data[entry] = val;
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nkeynes@933 | 251 | }
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nkeynes@933 | 252 |
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nkeynes@933 | 253 | struct mem_region_fn p4_region_ocache_data = {
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nkeynes@933 | 254 | ccn_ocache_data_read, ccn_ocache_data_write,
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nkeynes@933 | 255 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 256 | unmapped_read_long, unmapped_write_long,
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nkeynes@933 | 257 | unmapped_read_burst, unmapped_write_burst };
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nkeynes@933 | 258 |
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nkeynes@933 | 259 |
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nkeynes@931 | 260 | /****************** Cache control *********************/
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nkeynes@931 | 261 |
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nkeynes@931 | 262 | void CCN_set_cache_control( int reg )
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nkeynes@931 | 263 | {
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nkeynes@931 | 264 | uint32_t i;
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nkeynes@933 | 265 |
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nkeynes@933 | 266 | if( reg & CCR_ICI ) { /* icache invalidate */
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nkeynes@933 | 267 | for( i=0; i<ICACHE_ENTRY_COUNT; i++ ) {
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nkeynes@933 | 268 | ccn_icache[i].tag &= ~CACHE_VALID;
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nkeynes@933 | 269 | }
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nkeynes@933 | 270 | }
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nkeynes@933 | 271 |
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nkeynes@933 | 272 | if( reg & CCR_OCI ) { /* ocache invalidate */
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nkeynes@933 | 273 | for( i=0; i<OCACHE_ENTRY_COUNT; i++ ) {
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nkeynes@933 | 274 | ccn_ocache[i].tag &= ~(CACHE_VALID|CACHE_DIRTY);
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nkeynes@933 | 275 | }
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nkeynes@933 | 276 | }
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nkeynes@933 | 277 |
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nkeynes@931 | 278 | switch( reg & (CCR_OIX|CCR_ORA|CCR_OCE) ) {
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nkeynes@931 | 279 | case MEM_OC_INDEX0: /* OIX=0 */
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nkeynes@931 | 280 | for( i=OCRAM_START; i<OCRAM_END; i+=4 ) {
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nkeynes@931 | 281 | sh4_address_space[i] = &mem_region_ocram_page0;
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nkeynes@931 | 282 | sh4_address_space[i+1] = &mem_region_ocram_page0;
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nkeynes@931 | 283 | sh4_address_space[i+2] = &mem_region_ocram_page1;
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nkeynes@931 | 284 | sh4_address_space[i+3] = &mem_region_ocram_page1;
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nkeynes@931 | 285 | }
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nkeynes@931 | 286 | break;
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nkeynes@931 | 287 | case MEM_OC_INDEX1: /* OIX=1 */
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nkeynes@931 | 288 | for( i=OCRAM_START; i<OCRAM_MID; i++ )
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nkeynes@931 | 289 | sh4_address_space[i] = &mem_region_ocram_page0;
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nkeynes@931 | 290 | for( i=OCRAM_MID; i<OCRAM_END; i++ )
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nkeynes@931 | 291 | sh4_address_space[i] = &mem_region_ocram_page1;
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nkeynes@931 | 292 | break;
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nkeynes@931 | 293 | default: /* disabled */
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nkeynes@931 | 294 | for( i=OCRAM_START; i<OCRAM_END; i++ )
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nkeynes@931 | 295 | sh4_address_space[i] = &mem_region_unmapped;
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nkeynes@931 | 296 | break;
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nkeynes@931 | 297 | }
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nkeynes@931 | 298 | } |