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lxdream.org :: lxdream/test/testide.c
lxdream 0.9.1
released Jun 29
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filename test/testide.c
changeset 258:8864fae65928
prev252:cfd0ec3bfeec
next263:6f641270b2aa
author nkeynes
date Fri Dec 29 00:23:16 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix byte-count handling in accordance with the actual DC chip
file annotate diff log raw
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/**
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 * $Id: testide.c,v 1.5 2006-12-29 00:23:16 nkeynes Exp $
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 *
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 * IDE interface test cases. Covers all (known) IDE registers in the 
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 * 5F7000 - 5F74FF range including DMA, but does not cover any GD-Rom
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 * device behaviour (ie packet comands).
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 *
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 * These tests should be run with the drive empty.
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 *
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 * Copyright (c) 2006 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <stdlib.h>
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#include <stdio.h>
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#include "lib.h"
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#include "ide.h"
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#include "asic.h"
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unsigned int test_count = 0, test_failures = 0;
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#define IDE_BASE 0xA05F7000
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#define IDE_ALTSTATUS IDE_BASE+0x018
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#define IDE_UNKNOWN   IDE_BASE+0x01C
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#define IDE_DATA      IDE_BASE+0x080 /* 16 bits */
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#define IDE_FEATURE   IDE_BASE+0x084
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#define IDE_COUNT     IDE_BASE+0x088
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#define IDE_LBA0      IDE_BASE+0x08C
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#define IDE_LBA1      IDE_BASE+0x090
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#define IDE_LBA2      IDE_BASE+0x094
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#define IDE_DEVICE    IDE_BASE+0x098
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#define IDE_COMMAND   IDE_BASE+0x09C
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#define IDE_ACTIVATE  IDE_BASE+0x4E4
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#define IDE_DISC       IDE_LBA0
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#define IDE_DEVCONTROL IDE_ALTSTATUS
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#define IDE_ERROR      IDE_FEATURE
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#define IDE_STATUS     IDE_COMMAND
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#define IDE_DMA_ADDR   IDE_BASE+0x404
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#define IDE_DMA_SIZE   IDE_BASE+0x408
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#define IDE_DMA_DIR    IDE_BASE+0x40C
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#define IDE_DMA_CTL1   IDE_BASE+0x414
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#define IDE_DMA_CTL2   IDE_BASE+0x418
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#define IDE_DMA_MAGIC  IDE_BASE+0x4B8
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#define IDE_DMA_STATUS IDE_BASE+0x4F8
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#define CHECK_REG_EQUALS( a, b, c ) if( b != c ) { fprintf(stderr, "Assertion failed at %s:%d %s(): expected %08X from register %08X, but was %08X\n", __FILE__, __LINE__, __func__, b, a, c ); return -1; }
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/* Wait for the standard timeout for an INTRQ. If none is received, print an
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 * error and return -1
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 */
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#define EXPECT_INTRQ() if( ide_wait_irq() != 0 ) { fprintf(stderr, "Timeout at %s:%d %s(): waiting for INTRQ\n", __FILE__, __LINE__, __func__ ); return -1; }
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/* Check if the INTRQ line is currently cleared (ie inactive) */
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#define CHECK_INTRQ_CLEAR() if ( (long_read( ASIC_STATUS1 ) & 1) != 0 ) { fprintf(stderr, "Assertion failed at %s:%d %s(): expected INTRQ to be cleared, but was raised.\n", __FILE__, __LINE__, __func__ ); return -1; }
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#define EXPECT_READY() if( ide_wait_ready() != 0 ) { fprintf(stderr, "Timeout at %s:%d %s(): waiting for BSY flag to clear\n", __FILE__, __LINE__, __func__ ); return -1; }
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int check_regs( uint32_t *regs,const char *file, int line, const char *fn ) 
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{
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    int i;
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    int rv = 0;
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    for( i=0; regs[i] != 0; i+=2 ) {
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	uint32_t addr = regs[i];
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	uint32_t val = regs[i+1];
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	uint32_t actual;
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	if( addr == IDE_DATA ) {
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	    actual = (uint32_t)word_read(addr);
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	    if( val != actual ) { 
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		fprintf(stderr, "Assertion failed at %s:%d %s(): expected %04X from register %08X, but was %04X\n", file, line, fn, val, addr, actual ); 
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		rv = -1;
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	    }
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	} else if( addr <= IDE_COMMAND ) {
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	    actual = (uint32_t)byte_read(addr);
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	    if( val != actual ) { 
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		fprintf(stderr, "Assertion failed at %s:%d %s(): expected %02X from register %08X, but was %02X\n", file, line, fn, val, addr, actual ); 
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		rv = -1;
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	    }
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	} else {
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	    actual = long_read(addr);
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	    if( val != actual ) { 
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		fprintf(stderr, "Assertion failed at %s:%d %s(): expected %08X from register %08X, but was %08X\n", file, line, fn, val, addr, actual ); 
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		rv = -1;
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	    }
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	}
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    }
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    return rv;
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}
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#define CHECK_REGS( r ) if( check_regs(r, __FILE__, __LINE__, __func__) != 0 ) { return -1; }
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uint32_t post_packet_ready_regs[] = 
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    { IDE_ALTSTATUS, 0x58,
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      IDE_COUNT, 0x01,
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      IDE_LBA1, 8,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0x58, 0, 0 };
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uint32_t post_packet_cmd_regs[] = 
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    { IDE_ALTSTATUS, 0xD0,
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      IDE_ERROR, 0x00,
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      IDE_COUNT, 0x01,
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      IDE_LBA1, 8,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0xD0, 0, 0 };
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uint32_t packet_cmd_error6_regs[] = 
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    { IDE_ALTSTATUS, 0x51,
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      IDE_ERROR, 0x60,
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      IDE_COUNT, 0x03,
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      IDE_LBA1, 8,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0x51, 0, 0 };
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uint32_t packet_data_ready_regs[] = 
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    { IDE_ALTSTATUS, 0x58,
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      IDE_ERROR, 0x00,
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      IDE_COUNT, 0x02,
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      IDE_LBA1, 0x0C,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0x58, 0, 0 };
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uint32_t post_packet_data_regs[] = 
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    { IDE_ALTSTATUS, 0xD0,
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      IDE_ERROR, 0x00,
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      IDE_COUNT, 0x02,
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      IDE_LBA1, 0x0C,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0xD0, 0, 0 };
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uint32_t packet_complete_regs[] = 
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    { IDE_ALTSTATUS, 0x50,
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      IDE_ERROR, 0x00,
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      IDE_COUNT, 0x03,
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      IDE_LBA1, 0x0C,
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      IDE_LBA2, 0,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0x50, 0, 0 };
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int send_packet_command( const char *cmd )
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{
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    unsigned short *spkt = (unsigned short *)cmd;
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    int i;
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    EXPECT_READY();
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    byte_write( IDE_FEATURE, 0 );
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    byte_write( IDE_COUNT, 0 );
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    byte_write( IDE_LBA0, 0 );
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    byte_write( IDE_LBA1, 8 );
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    byte_write( IDE_LBA2, 0 );
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    byte_write( IDE_DEVICE, 0 );
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    byte_write( IDE_COMMAND, 0xA0 );
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    byte_read(IDE_ALTSTATUS); /* delay 1 PIO cycle */
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    EXPECT_READY(); /* Wait until device is ready to accept command (usually immediate) */
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    CHECK_INTRQ_CLEAR();
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    CHECK_REGS( post_packet_ready_regs );
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    /* Write the command */
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    for( i=0; i<6; i++ ) {
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        word_write( IDE_DATA, spkt[i] );
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    }
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    byte_read(IDE_ALTSTATUS); 
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    // CHECK_REGS( post_packet_cmd_regs );
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    EXPECT_INTRQ();
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    EXPECT_READY();
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    return 0;
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}
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int read_pio( char *buf, int expected_length ) {
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    uint32_t ready_regs[] = {
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	IDE_ALTSTATUS, 0x58,
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	IDE_ERROR, 0x00,
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	IDE_COUNT, 0x02,
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	IDE_LBA1, expected_length & 0xFF,
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	IDE_LBA2, (expected_length >> 8),
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	IDE_DEVICE, 0,
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	IDE_STATUS, 0x58, 
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	0, 0 };    
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    int i;
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    unsigned short *bufptr = (unsigned short *)buf;
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    unsigned int length = 0, avail;
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    int status;
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    CHECK_REGS( ready_regs );
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    for( i=0; i<expected_length; i+=2 ) {
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	*bufptr++ = word_read(IDE_DATA);
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    }
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    EXPECT_INTRQ();
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    EXPECT_READY();
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    ready_regs[1] = 0x50;
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    ready_regs[5] = 0x03;
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    ready_regs[13] = 0x50;
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    CHECK_REGS( ready_regs );
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    return 0;
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}
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#define IDE_TEST_PACKET_OK( c,e,l ) if( ide_test_packet_ok( __FILE__, __LINE__, __func__, c, e, l ) != 0 ) { return -1; }
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int ide_test_packet_ok( const char *file, int line, const char *func, 
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			const char *cmd, char *expect, int expect_len ) 
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{
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    char buf[expect_len];
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    int status = send_packet_command(cmd);
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    if( status != 0 ) {
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	return status;
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    }
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    status = byte_read( IDE_ALTSTATUS );
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    if( status & 1 ) { /* Error */
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	status = ide_get_sense_code();
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	fprintf( stderr, "Assertion failed at %s:%d %s(): Unexpected error %04X\n",
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		 file, line, func, status );
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	return -1;
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    }
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    status = read_pio( buf, expect_len );
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    if( status != 0 ) {
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	return status;
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    }
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    if( expect != NULL && memcmp( expect, buf, expect_len ) != 0 ) {
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	fprintf(stderr, "Assertion failed at %s:%d %s(): Results differ from expected:\n",file,line,func );
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	fwrite_diff( stderr, expect, expect_len, buf, expect_len );
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	return -1;
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    }
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    return 0;
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}
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#define IDE_TEST_PACKET_ERROR( c,e ) if( ide_test_packet_error( __FILE__, __LINE__, __func__, c, e ) != 0 ) { return -1; }
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int ide_test_packet_error( char *file, int line, char *func,
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			   char *cmd, int expect_error )
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{
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    uint32_t error_regs[] = 
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    { IDE_ALTSTATUS, 0x51,
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      IDE_ERROR, (expect_error & 0x0F)<<4,
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      IDE_COUNT, 0x03,
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      IDE_DEVICE, 0,
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      IDE_STATUS, 0x51, 0, 0 };
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    uint32_t error_code;
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    int status = send_packet_command(cmd);
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    if( status != 0 ) {
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	return status;
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    }
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    CHECK_REGS(error_regs);
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    error_code = ide_get_sense_code();
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    CHECK_IEQUALS( expect_error, error_code );
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    return 0;
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}
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uint32_t abort_regs[] = {
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    IDE_ALTSTATUS, 0x51,
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    IDE_ERROR, 0x04,
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    IDE_COUNT, 0x02,
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    IDE_LBA1, 0x00,
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    IDE_LBA2, 0x50,
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    IDE_DEVICE, 0,
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    IDE_DATA, 0x0000,
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    IDE_STATUS, 0x51, 
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    0, 0 };
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uint32_t post_reset_regs[] = {
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    IDE_ALTSTATUS, 0x00,
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    IDE_ERROR, 0x01,
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    IDE_COUNT, 0x01,
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    IDE_LBA1, 0x14,
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    IDE_LBA2, 0xEB,
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    IDE_DEVICE, 0,
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    IDE_DATA, 0xFFFF,
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    IDE_STATUS, 0x00, 
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    0, 0 };
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uint32_t post_set_feature_regs[] = {
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    IDE_ALTSTATUS, 0x50,
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    IDE_ERROR, 0x00,
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    IDE_COUNT, 0x0B,
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    IDE_LBA1, 0x00,
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    IDE_LBA2, 0x00,
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    IDE_DEVICE, 0,
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    IDE_DATA, 0xFFFF,
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    IDE_STATUS, 0x50, 
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    0, 0 };    
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uint32_t post_set_feature2_regs[] = {
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    IDE_ALTSTATUS, 0x50,
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    IDE_ERROR, 0x00,
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    IDE_COUNT, 0x22,
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    IDE_LBA1, 0x00,
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    IDE_LBA2, 0x00,
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    IDE_DEVICE, 0,
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    IDE_DATA, 0xFFFF,
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    IDE_STATUS, 0x50, 
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    0, 0 };    
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/************************** Interface Tests *******************************/
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/**
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 * Test enable/disable of the IDE interface via port
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 * 0x4E4. 
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 */
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int test_enable()
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{
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    int i;
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    int failed = 0;
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    /* ensure deactivated */
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    long_write( IDE_ACTIVATE, 0x00042FE );
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    /* test registers to ensure all return 0xFF (need to wait a few cycles?) */
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    for( i= IDE_BASE; i< IDE_BASE+0x400; i+= 4 ) {
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	CHECK_REG_EQUALS( i, 0xFFFFFFFF, long_read( i ) );
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    }
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    /* enable interface */
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    ide_activate();
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    /* test registers have default settings */
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    //    CHECK_REGS( post_reset_regs );
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    /* disable interface and re-test */
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    long_write( IDE_ACTIVATE, 0x00042FE );
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    /* Test registers all 0xFF */
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    for( i= IDE_BASE; i< IDE_BASE+0x400; i+= 4 ) {
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	CHECK_REG_EQUALS( i, 0xFFFFFFFF, long_read( i ) );
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    }
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    /* Finally leave the interface in an enabled state */
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    ide_activate();
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    return 0;
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}
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uint32_t drive_ready_regs[] = {
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    IDE_ALTSTATUS, 0x50,
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    IDE_ERROR, 0x00,
nkeynes@251
   357
    IDE_COUNT, 0x03,
nkeynes@251
   358
    IDE_LBA1, 0x08,
nkeynes@251
   359
    IDE_LBA2, 0x00,
nkeynes@251
   360
    IDE_DEVICE, 0,
nkeynes@251
   361
    IDE_DATA, 0xFFFF,
nkeynes@251
   362
    IDE_STATUS, 0x50, 
nkeynes@251
   363
    0, 0 };    
nkeynes@251
   364
nkeynes@248
   365
/**
nkeynes@248
   366
 * Test the reset command
nkeynes@248
   367
 */
nkeynes@248
   368
int test_reset()
nkeynes@248
   369
{
nkeynes@248
   370
    byte_write( IDE_COMMAND, 0x08 );
nkeynes@248
   371
    EXPECT_READY();
nkeynes@248
   372
    CHECK_INTRQ_CLEAR();
nkeynes@248
   373
    CHECK_REGS( post_reset_regs );
nkeynes@248
   374
    
nkeynes@248
   375
    /** Set Default PIO mode */
nkeynes@248
   376
    byte_write( IDE_FEATURE, 0x03 );
nkeynes@248
   377
    byte_write( IDE_COUNT, 0x0B );
nkeynes@248
   378
    byte_write( IDE_COMMAND, 0xEF );
nkeynes@248
   379
    EXPECT_READY();
nkeynes@248
   380
    CHECK_REGS( post_set_feature_regs );
nkeynes@248
   381
    
nkeynes@248
   382
    /** Set Multi-word DMA mode 2 */
nkeynes@248
   383
    long_write( 0xA05F7490, 0x222 );
nkeynes@248
   384
    long_write( 0xA05F7494, 0x222 );
nkeynes@248
   385
    byte_write( IDE_FEATURE, 0x03 );
nkeynes@248
   386
    byte_write( IDE_COUNT, 0x22 );
nkeynes@248
   387
    byte_write( IDE_COMMAND, 0xEF );
nkeynes@248
   388
    EXPECT_READY();
nkeynes@248
   389
    CHECK_INTRQ_CLEAR();
nkeynes@248
   390
    CHECK_REGS( post_set_feature2_regs );
nkeynes@185
   391
nkeynes@251
   392
    char test_ready_cmd[12] = { 0,0,0,0, 0,0,0,0, 0,0,0,0 };
nkeynes@251
   393
    if( send_packet_command(test_ready_cmd) != 0 ) {
nkeynes@251
   394
	return -1;
nkeynes@251
   395
    }
nkeynes@251
   396
nkeynes@251
   397
    CHECK_REGS( packet_cmd_error6_regs );
nkeynes@251
   398
    int sense = ide_get_sense_code();
nkeynes@251
   399
    CHECK_IEQUALS( 0x2906, sense );
nkeynes@251
   400
nkeynes@251
   401
    if( send_packet_command(test_ready_cmd) != 0 ) {
nkeynes@251
   402
	return -1;
nkeynes@251
   403
    }
nkeynes@251
   404
    CHECK_REGS( drive_ready_regs );
nkeynes@248
   405
    return 0;
nkeynes@248
   406
}
nkeynes@248
   407
nkeynes@248
   408
char expect_ident[] = { 0x00, 0xb4, 0x19, 0x00,
nkeynes@248
   409
			0x00, 0x08, 0x53, 0x45, 0x20, 0x20, 0x20, 0x20 };
nkeynes@251
   410
nkeynes@248
   411
/**
nkeynes@248
   412
 * Test the PACKET command (using the Inquiry command)
nkeynes@248
   413
 */
nkeynes@248
   414
int test_packet()
nkeynes@185
   415
{
nkeynes@248
   416
    int i;
nkeynes@248
   417
    char cmd[12] = { 0x11, 0, 4, 0,  12, 0, 0, 0,  0, 0, 0, 0 };
nkeynes@248
   418
    // char cmd[12] = { 0x00,0,0,0, 0,0,0,0, 0,0,0,0 };
nkeynes@251
   419
    unsigned short *spkt;
nkeynes@248
   420
    char result[12];
nkeynes@248
   421
nkeynes@251
   422
    send_packet_command( cmd );
nkeynes@248
   423
    CHECK_REGS( packet_data_ready_regs );
nkeynes@248
   424
    spkt = (unsigned short *)result;
nkeynes@248
   425
    *spkt++ = word_read(IDE_DATA);
nkeynes@248
   426
    *spkt++ = word_read(IDE_DATA);
nkeynes@248
   427
    *spkt++ = word_read(IDE_DATA);
nkeynes@248
   428
    *spkt++ = word_read(IDE_DATA);
nkeynes@248
   429
    CHECK_REGS( packet_data_ready_regs );
nkeynes@248
   430
    *spkt++ = word_read(IDE_DATA);
nkeynes@248
   431
    *spkt++ = word_read(IDE_DATA);
nkeynes@252
   432
//    CHECK_REGS( post_packet_data_regs );
nkeynes@248
   433
    EXPECT_READY();
nkeynes@251
   434
    EXPECT_INTRQ();
nkeynes@248
   435
    CHECK_REGS( packet_complete_regs );
nkeynes@251
   436
nkeynes@248
   437
    if( memcmp( result, expect_ident, 12 ) != 0 ) {
nkeynes@248
   438
	fwrite_diff( stderr, expect_ident, 12, result, 12 );
nkeynes@252
   439
	return -1;
nkeynes@248
   440
    }
nkeynes@248
   441
    return 0;
nkeynes@185
   442
}
nkeynes@248
   443
nkeynes@248
   444
/**
nkeynes@248
   445
 * Test the SET FEATURE command
nkeynes@248
   446
 */
nkeynes@248
   447
int test_set_feature()
nkeynes@248
   448
{
nkeynes@248
   449
    return 0;
nkeynes@248
   450
}
nkeynes@248
   451
nkeynes@258
   452
nkeynes@258
   453
nkeynes@248
   454
/**
nkeynes@248
   455
 * Test DMA transfer (using the Inquiry packet comand)
nkeynes@248
   456
 */
nkeynes@248
   457
int test_dma()
nkeynes@248
   458
{
nkeynes@248
   459
    return 0;
nkeynes@248
   460
}
nkeynes@248
   461
nkeynes@248
   462
/**
nkeynes@248
   463
 * Test DMA abort
nkeynes@248
   464
 */
nkeynes@248
   465
int test_dma_abort()
nkeynes@248
   466
{
nkeynes@248
   467
    return 0;
nkeynes@248
   468
}
nkeynes@248
   469
nkeynes@252
   470
/***************************** GD-Rom Tests **********************************/
nkeynes@252
   471
nkeynes@252
   472
int test_read_toc()
nkeynes@252
   473
{
nkeynes@252
   474
    char cmd[12] = { 0x14,0,0,0x00, 0x0C,0,0,0, 0,0,0,0 };
nkeynes@252
   475
    char expect[12] = { 0x41, 0,0, 0x96, 0x41, 0, 0x2E, 0x4C, 0xFF, 0xFF, 0xFF, 0xFF };
nkeynes@252
   476
    
nkeynes@252
   477
    IDE_TEST_PACKET_OK( cmd, expect, 12 );
nkeynes@252
   478
    return 0;
nkeynes@252
   479
}
nkeynes@252
   480
nkeynes@258
   481
int test_read_pio()
nkeynes@258
   482
{
nkeynes@258
   483
    int i,j;
nkeynes@258
   484
    char cmd[12] = {0x30, 0x28, 0, 0x2E,  0x4C, 0, 0, 0,  0, 0, 7, 0 };
nkeynes@258
   485
    uint32_t read_pio_ready_regs[] = 
nkeynes@258
   486
	{ IDE_ALTSTATUS, 0x58,
nkeynes@258
   487
	  IDE_ERROR, 0x00,
nkeynes@258
   488
	  IDE_COUNT, 0x02,
nkeynes@258
   489
	  IDE_LBA1, 0x00,
nkeynes@258
   490
	  IDE_LBA2, 0x08,
nkeynes@258
   491
	  IDE_DEVICE, 0,
nkeynes@258
   492
	  IDE_STATUS, 0x58, 0, 0 };
nkeynes@258
   493
nkeynes@258
   494
    if( send_packet_command(cmd) != 0 ) {
nkeynes@258
   495
	return -1;
nkeynes@258
   496
    }
nkeynes@258
   497
nkeynes@258
   498
    for( j=0; j<7; j++ ) {
nkeynes@258
   499
	CHECK_REGS(read_pio_ready_regs);
nkeynes@258
   500
	CHECK_INTRQ_CLEAR();
nkeynes@258
   501
	for( i=0; i<0x0800; i+=2 ) {
nkeynes@258
   502
	    word_read(IDE_DATA); // throw away for now.
nkeynes@258
   503
	}
nkeynes@258
   504
	
nkeynes@258
   505
	EXPECT_INTRQ();
nkeynes@258
   506
	EXPECT_READY();
nkeynes@258
   507
    }
nkeynes@258
   508
nkeynes@258
   509
    read_pio_ready_regs[1] = 0x50;
nkeynes@258
   510
    read_pio_ready_regs[5] = 0x03;
nkeynes@258
   511
    read_pio_ready_regs[13] = 0x50;
nkeynes@258
   512
    CHECK_REGS( read_pio_ready_regs );
nkeynes@258
   513
    return 0;
nkeynes@258
   514
}
nkeynes@258
   515
nkeynes@252
   516
/**
nkeynes@252
   517
 * Test interaction of Read CD (0x30) with Status (0x40,1)
nkeynes@252
   518
 */
nkeynes@252
   519
int test_status1() 
nkeynes@252
   520
{
nkeynes@252
   521
    char cmd[12] = { 0x40, 0x01, 0, 0, 16,0,0,0, 0,0,0,0 };
nkeynes@252
   522
    char read1cmd[12] = { 0x30, 0x28, 0, 0x2E, 0x4C, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   523
    char expect1[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0,1,0,0, 0x2E,0x4D,0,0 };
nkeynes@252
   524
    char read2cmd[12] = { 0x30, 0x28, 0, 0x2E, 0x4D, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   525
    char expect2[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0,4,0,0, 0x2E,0x50,0,0 };
nkeynes@252
   526
    char read3cmd[12] = { 0x30, 0x28, 0, 0x2E, 0x4E, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   527
    char expect3[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0,5,0,0, 0x2E,0x51,0,0 };
nkeynes@252
   528
    char expect4[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0,2,0,0, 0x2E,0x4E,0,0 };
nkeynes@252
   529
    char read5cmd[12] = { 0x30, 0x28, 0, 0x2F, 0x01, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   530
    char expect5[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0,0xB6,0,0, 0x2F,0x02,0,0 };
nkeynes@252
   531
    char read6cmd[12] = { 0x30, 0x28, 0, 0x2F, 0x50, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   532
    char expect6[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0x01,0x05,0,0, 0x2F,0x51,0,0 };
nkeynes@252
   533
    char read7cmd[12] = { 0x30, 0x28, 0, 0x2F, 0x51, 0, 0, 0, 0, 0,1,0 };
nkeynes@252
   534
    char expect7[16] = { 0,0x15,0,0x0E, 0x41,2,1,0, 0x01,0x06,0,0, 0x2F,0x52,0,0 };
nkeynes@252
   535
    
nkeynes@252
   536
nkeynes@252
   537
    IDE_TEST_PACKET_OK(read1cmd, NULL, 2048);
nkeynes@252
   538
    IDE_TEST_PACKET_OK(cmd, expect1, 14 );
nkeynes@252
   539
    IDE_TEST_PACKET_OK(read2cmd, NULL, 2048);
nkeynes@252
   540
    IDE_TEST_PACKET_OK(cmd, expect2, 14 );
nkeynes@252
   541
    IDE_TEST_PACKET_OK(read3cmd, NULL, 2048);
nkeynes@252
   542
    IDE_TEST_PACKET_OK(cmd, expect3, 14 );
nkeynes@252
   543
    IDE_TEST_PACKET_OK(read2cmd, NULL, 2048);
nkeynes@252
   544
    IDE_TEST_PACKET_OK(cmd, expect4, 14 );
nkeynes@252
   545
    IDE_TEST_PACKET_OK(read5cmd, NULL, 2048);
nkeynes@252
   546
    IDE_TEST_PACKET_OK(cmd, expect5, 14 );
nkeynes@252
   547
    IDE_TEST_PACKET_OK(read6cmd, NULL, 2048);
nkeynes@252
   548
    IDE_TEST_PACKET_OK(cmd, expect6, 14 );
nkeynes@252
   549
nkeynes@252
   550
    return 0;
nkeynes@252
   551
}
nkeynes@252
   552
nkeynes@252
   553
/********************************* Main **************************************/
nkeynes@252
   554
nkeynes@248
   555
typedef int (*test_func_t)();
nkeynes@248
   556
nkeynes@251
   557
test_func_t test_fns[] = { test_enable, test_reset, test_packet,
nkeynes@258
   558
			   test_dma, test_dma_abort, test_read_pio,
nkeynes@252
   559
			   test_read_toc,
nkeynes@252
   560
			   test_status1, NULL };
nkeynes@248
   561
nkeynes@248
   562
int main() 
nkeynes@248
   563
{
nkeynes@248
   564
    int i;
nkeynes@248
   565
    ide_init();
nkeynes@248
   566
nkeynes@248
   567
    /* run tests */
nkeynes@248
   568
    for( i=0; test_fns[i] != NULL; i++ ) {
nkeynes@248
   569
	test_count++;
nkeynes@248
   570
	if( test_fns[i]() != 0 ) {
nkeynes@252
   571
	    fprintf( stderr, "Test %d failed\n", i+1 );
nkeynes@248
   572
	    test_failures++;
nkeynes@248
   573
	}
nkeynes@248
   574
    }
nkeynes@248
   575
nkeynes@248
   576
    /* report */
nkeynes@248
   577
    fprintf( stderr, "%d/%d tests passed!\n", test_count - test_failures, test_count );
nkeynes@248
   578
    return test_failures;
nkeynes@248
   579
}
.