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lxdream.org :: lxdream/src/aica/armcore.h
lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.h
changeset 30:89b30313d757
prev14:fc481a638848
next35:21a4be098304
author nkeynes
date Sun Dec 25 05:57:00 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Change timeslice to nanoseconds (was microseconds)
Generize single step (now steps through active CPU)
Add lots of header blocks
file annotate diff log raw
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/**
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 * $Id: armcore.h,v 1.6 2005-12-25 05:57:00 nkeynes Exp $
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 * 
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 * Interface definitions for the ARM CPU emulation core proper.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef dream_armcore_H
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#define dream_armcore_H 1
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#include "dream.h"
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#include <stdint.h>
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#define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
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struct arm_registers {
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    uint32_t r[16]; /* Current register bank */
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    uint32_t cpsr;
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    uint32_t spsr;
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    /* Various banked versions of the registers. */
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    uint32_t fiq_r[7]; /* FIQ bank 8..14 */
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    uint32_t irq_r[2]; /* IRQ bank 13..14 */
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    uint32_t und_r[2]; /* UND bank 13..14 */
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    uint32_t abt_r[2]; /* ABT bank 13..14 */
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    uint32_t svc_r[2]; /* SVC bank 13..14 */
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    uint32_t user_r[7]; /* User/System bank 8..14 */
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    uint32_t c,n,z,v,t;
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    /* "fake" registers */
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    uint32_t shift_c;  /* used for temporary storage of shifter results */
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    uint32_t icount; /* Instruction counter */
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};
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#define CPSR_N 0x80000000 /* Negative flag */
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#define CPSR_Z 0x40000000 /* Zero flag */
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#define CPSR_C 0x20000000 /* Carry flag */
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#define CPSR_V 0x10000000 /* Overflow flag */
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#define CPSR_I 0x00000080 /* Interrupt disable bit */ 
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#define CPSR_F 0x00000040 /* Fast interrupt disable bit */
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#define CPSR_T 0x00000020 /* Thumb mode */
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#define CPSR_MODE 0x0000001F /* Current execution mode */
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#define MODE_USER 0x00 /* User mode */
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#define MODE_FIQ   0x01 /* Fast IRQ mode */
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#define MODE_IRQ  0x02 /* IRQ mode */
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#define MODE_SV   0x03 /* Supervisor mode */
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#define MODE_ABT 0x07 /* Abort mode */
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#define MODE_UND 0x0B /* Undefined mode */
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#define MODE_SYS 0x0F /* System mode */
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extern struct arm_registers armr;
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#define CARRY_FLAG (armr.cpsr&CPSR_C)
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/* ARM Memory */
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int32_t arm_read_long( uint32_t addr );
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int32_t arm_read_word( uint32_t addr );
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int32_t arm_read_byte( uint32_t addr );
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void arm_write_long( uint32_t addr, uint32_t val );
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void arm_write_word( uint32_t addr, uint32_t val );
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void arm_write_byte( uint32_t addr, uint32_t val );
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int32_t arm_read_phys_word( uint32_t addr );
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int arm_has_page( uint32_t addr );
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gboolean arm_execute_instruction( void );
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#endif /* !dream_armcore_H */
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